Diversion of Byte Enable as Clock Enable for Power Saving

Abstract

A system, apparatus, and method for efficient data transmission in a computing system are disclosed. A source generates a packet to be transmitted to a destination over a communications fabric (or fabrics). The source generates partition enable signals for partitions of payload data. If the source determines that the type of packet indicates that a particular partition should have an associated asserted enable signal in the packet, the source negates the enable signal for the particular partition; however, the source determines that the particular partition contains a particular data pattern. A routing component of the fabric disables clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern into the particular partition of the payload data.

Description

Background Art

[0001] (Description of Related Art) Various computing devices utilize heterogeneous integration to integrate multiple types of processing devices to provide system functionality. The multiple functions include audio / video (A / V) data processing, other high-data parallel applications for the medical and commercial fields, processing instructions for general-purpose instruction set architectures (ISAs), and digital, analog, mixed-signal, and radio frequency (RF) functions, among others. To integrate multiple types of processing devices, there are various options for system packaging. In some computing devices, a system-on-chip (SoC) is used, while in other computing devices, smaller and higher-yield chips are packaged as large chips within a multi-chip module (MCM). Some computing devices stack two or more dies vertically within a system-in-package (SiP) and utilize die-stacking techniques, as well as three-dimensional integrated circuits (3D ICs) using silicon interposers, through-silicon vias (TSVs), and other mechanisms to electrically connect them.

[0002] In addition to input / output devices, each of these processing devices is a source of a computing system capable of generating read and write requests for data. In addition to system memory, each source can be a target destination for requests. Regardless of the selected system package, data access requests and corresponding data, coherence probes, interrupts, and other communication messages generated by the source of the target destination are typically transferred via a communication fabric (or fabric). The fabric reduces latency by enabling the use of a relatively large number of physical wires to transfer packets between the source and the destination. Packet data transfer via the fabric wires and switching of internal nodes such as storage elements, queues, control logic, etc. within the fabric increases the power consumption of the computing system.

[0003] Due to the power consumption of today's integrated circuits, design problems have become even more significant in each generation of semiconductor chips. As power consumption increases, more expensive cooling systems such as larger fans and heat sinks must be utilized to remove excess heat and prevent circuit failures. However, the cooling system increases the cost of the system. Circuit power loss constraints are a problem not only for portable computers and mobile communication devices, but also for desktop computers and servers utilizing high-performance microprocessors.

[0004] In view of the above, a method for efficient data transmission in a computing system is desired.

[0005] The advantages of the methods and mechanisms described herein can be well understood by referring to the following description in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0006]

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[0007] The present invention accepts various modifications and alternative forms. Specific embodiments are shown by way of example in the drawings and are described in detail herein. However, the drawings and the detailed description thereof are not intended to limit the present invention to the specific forms disclosed, but on the contrary, the present invention should be understood to encompass all modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims.

[0008] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the methods and mechanisms presented herein. However, one of ordinary skill in the art should recognize that the various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the methods described herein. It should be understood that the elements shown in the drawings are not necessarily drawn to scale for simplicity and clarity of illustration. For example, the dimensions of some elements may be exaggerated relative to other elements.

[0009] Disclosed are various systems, apparatuses, methods, and computer-readable media for arbitrating threads in a computing system. In various embodiments, a computing system includes one or more clients for processing applications. Examples of clients include general-purpose central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), input / output (I / O) devices, and the like. Each client can generate a data access request. A client is referred to as a "source" when it generates and transmits a packet including a data access request, payload data, a probe request, a coherence command, or other communication to be sent to a target destination. A client and system memory are referred to as "destinations" when they are the targets of a packet generated by a source.

[0010] The source transmits packets to a destination via a communication fabric (or fabric). Examples of interconnections within the fabric include a bus architecture, a crossbar-based architecture, a network on chip (NoC) communication subsystem, an inter-die communication channel, a router switch with arbitration logic, a repeater, a silicon interposer used to stack chips, through-silicon vias (TSVs) used to vertically stack special-purpose dies on top of a processor die, etc.

[0011] In some embodiments, the source divides the payload data into partitions such as bytes, words, double words, etc. Further, in various embodiments, a partition enable signal for partitioning the payload data is generated. For example, the partition enable signal for field 156 is a byte enable signal. In some embodiments, the source generates a partition enable signal (or enable signal) to indicate which partitions contain valid data of the payload data. For example, each partition contains valid data of a read response packet. Thus, the source asserts each of the enable signals corresponding to the multiple partitions of the payload data. Similarly, each partition contains valid data of a full-light data packet and a cache victim packet used to transmit previously cached data to the system memory. In other embodiments, the source negates one or more enable signals to indicate which partitions contain invalid data of the payload data. For example, one or more partitions contain invalid data of a partial write data packet.

[0012] In other embodiments, when the source determines that a particular packet type indicates that a particular partition has an associated asserted enable signal within the packet, the source negates the enable signal for the particular partition, but the source determines that the particular partition contains a particular data pattern. For example, a particular partition of the read response payload data contains a particular pattern. In a read response data packet, typically each of a plurality of enable signals is asserted, but the source disables the enable signal for the particular partition. The negated enable signal indicates that rather than transferring the particular data pattern across the fabric, the particular partition should store the particular pattern without actually transferring it across the fabric.

[0013] The destination receives the read response data packet, and the destination determines that both the packet type and the particular partition have an associated negated (negative) enable signal within the packet. In this example, the packet type of the read response data packet indicates that a particular partition should contain an associated asserted enable signal in the packet. Thus, the destination interprets the negated enable signal as indicating that the particular partition should contain a particular data pattern. Thus, when storing the read response payload data, the destination inserts the particular data pattern into the particular partition.

[0014] While transferring packets between a source and a destination, one or more routing components send and receive packets within the fabric. Examples of routing components include router switches, repeater blocks, etc. In various embodiments, when a routing component receives a packet and determines that one or more partitions of the payload data have an associated negated enable signal, the routing component disables the storage element of the routing component allocated to store the data of the partition of the payload data associated with the negated enable signal. Later, when the routing component sends the packet to the next routing component or the destination, the routing component sends the negated enable signal and the previous values stored in each storage element allocated to store the data of the partition of the payload data associated with the negated enable signal. Since the clock signal is disabled, these storage elements do not load new values. The previous values continue to be stored in these storage elements. Further, these storage elements do not consume power associated with loading new values, and the conditional clock signal does not toggle. In some embodiments, the clock gating logic of the routing component directly uses the partition enable signal as a conditional clock gating control signal.

[0015] Referring to FIG. 1, a general block diagram of one embodiment of a computing system 100 is shown. As shown, source 110 transmits packet 150 to destination 140 via routing component 120. Source 110 is a client within computing system 100 such as a general-purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a multimedia engine, an input / output (I / O) device, etc. Destination 140 is a system memory or an exemplary client within computing system 100. Examples of routing component 120 are repeater blocks, network switches, or other components of a communication fabric. Although a single source 110, a single routing component 120, and a single destination 140 are shown, computing system 100 may include any number of these blocks in other implementations. In some embodiments, blocks 110-140 of computing system 100 are individual dies on an integrated circuit (IC) such as a system-on-chip (SOC). In other embodiments, blocks 110-140 are individual dies within a system-in-package (SiP) or a multi-chip module (MCM). Other blocks such as a power controller or power management unit, a clock generation source, a link interface for communicating with any other processing nodes, and a memory controller for interfacing with system memory are not shown for simplicity of explanation.

[0016] Source 110 generates and transmits packets. Source 110 and destination 140 use packets to communicate data access requests, payload data, probe requests, coherence commands, etc. Packet generation logic 112 (or logic 112) generates packet 150. Packet 150 includes a plurality of fields 152-158. Although fields 152-158 are shown in a particular sequential order, in other embodiments, packet 150 uses a different storage arrangement. In other embodiments, packet 150 includes one or more other fields not shown.

[0017] The header 152 stores one or more commands, source and destination identifiers, process and thread identifiers, timestamps, parity and checksum and other data integrity information, priority levels and / or quality of service parameters, and the like. In other embodiments, one or more of these fields are separated from the header 152 and placed elsewhere within the packet 150. Examples of other fields not shown in the packet 150 are virtual channel identifiers, response types of response packets, indicators of transaction offsets used when a read response to a large read request is split into multiple data packets, indicators of response packets indicating whether a single response or multiple responses are included in the response packet, and indicators of multiple credits, request packets, and response packets of data packets. Other examples of fields stored in the packet 150 are possible and are contemplated in other embodiments.

[0018] Address 154 stores an indicator of the target address associated with the command in header 152. Field 156 stores an enable signal associated with the partition of the payload data stored in field 158. In the case of a data packet, source 110 divides the payload data into partitions. Examples of partition sizes include bytes, words (4 bytes), double words (8 bytes), and the like. Partition enable logic 114 (or logic 114) generates a partition enable signal stored in field 156. When the partition size is a byte, the partition enable signal in field 156 is a byte enable signal. In some embodiments, logic 114 generates a partition enable signal (or enable signal) to indicate which partitions contain valid data of the payload data stored in field 158. For example, each partition contains valid data of a read response packet. The command and / or packet type is stored in header 152. Accordingly, logic 114 asserts each of the enable signals in field 156 corresponding to the multiple partitions of the payload data in field 158. Similarly, each partition contains valid data of a full-light data packet and a cache victim packet used to send previously cached data to system memory.

[0019] In other embodiments, logic 114 negates one or more enable signals of field 156 to indicate which partitions contain invalid data of the payload data of field 158. For example, one or more partitions contain invalid data of a partial write data packet. As used herein, a signal is considered “asserted” if it has a value used to enable logic, turn on a transistor, and cause current to flow through the transistor. In some logic, the asserted value is the high value of boolean logic or the high level of boolean logic. For example, when an n-type metal oxide semiconductor (NMOS) transistor receives a high level of boolean logic at its gate terminal, the NMOS transistor becomes enabled or turns on. Thus, the NMOS transistor can conduct current. In the case of other logic, the asserted value is the low level of boolean logic. When a p-type MOS (PMOS) transistor receives a low level of boolean logic at its gate terminal, the PMOS transistor becomes enabled or turns on, and the PMOS transistor can conduct current. In contrast, a signal is considered “negated” if it has a value used to disable logic and turn off a transistor.

[0020] In some embodiments, logic 114 negates the enable signal in field 156 of a particular partition within field 158 when logic 114 determines that the packet type indicates that a particular partition has an asserted enable signal associated therewith within the packet. However, logic 114 determines that a particular partition contains a particular data pattern. For example, a particular partition of read response payload data contains a particular pattern. An example of a particular pattern is that all are zeros in a particular partition. If the partition size is 1 byte, the particular partition contains eight zeros. Other data patterns are possible and contemplated. Read response data packets typically have each of a plurality of enable signals asserted, but logic 114 negates the enable signal of field 156 of a particular partition of field 158. The negated enable signal indicates that the routing component 120 should transfer the packet 150 without the actual value of the particular partition rather than transfer a particular data pattern via the routing component 120.

[0021] In various embodiments, interface 122 of routing component 120 receives packet 150. In some embodiments, interface 122 includes storage element 134 for receiving and storing packet 150. In other embodiments, interface 122 includes an impedance matching circuit when the distance from source 110 is clear. In still other embodiments, interface 122 includes a wire for transferring the received packet to storage element 134. Packet 124 generally represents a packet received by routing component 120 such as packet 150. Thus, packet 124 includes the same fields as described above for packet 150. Routing component 120 includes clock gating logic 132 (or logic 132) for enabling and disabling clock signal 130 to one or more storage elements 134. Storage element 134 includes one or more registers, flip - flops, circuits, content - addressable memories (CAMs), random - access memories (RAMs), etc. Logic 132 conditionally enables and disables clock signal 130 to one or more storage elements 134 using partition enable signal 126 from packet 124. For example, logic 132 is assigned to store the data of the partition of the payload data associated with the negated enable signal of partition enable signal 126 and disables clock signal 130 for each of storage elements 134. Thus, logic 132 uses partition enable signal 126 as a clock enable signal. When the size of the partition is in bytes, logic 132 uses byte enable signal 126 as a clock enable signal.

[0022] Subsequently, when the routing component 120 transmits the packet 124 to the next routing component (not shown) or the destination 140, the interface 136 transmits the packet information stored in the storage element 134. The interface 136 simply includes a wire, one or more logic gate buffers, or other circuitry for transmitting data. The interface 136 transmits the negated enable signal of the partition enable signal 126 and the previous value stored in each storage element assigned to store the data of the partition of the payload data associated with the negated enable signal. Since the logic 132 disabled a particular one of the clock signals 130 of the storage element 134, these particular storage elements did not load new values. The previous values from the previous clock cycle are still stored in these particular storage elements, and the interface 136 transmits these previous values to the destination 140. The original value transmitted by the source 110 of the particular partition of the payload data associated with the negated partition enables the signal of the signal 126 and is not stored or transported by the routing component 120. Further, these storage elements do not consume power associated with loading new values, and the conditional clock signal does not toggle. In contrast, the other of the storage elements 134 store the header 152, the address 154, and the partition enable signal 156 of the packet 124. These storage elements receive a version of the clock signal 130 that is not qualified by the partition enable signal 126.

[0023] The destination 140 receives packet information, and the destination 140 determines both the type of the packet and whether a particular partition of the payload data has a related negated enable signal within the packet. If the packet type indicates that each partition of the payload data should have an asserted enable signal within the packet, but one or more partition enable signals are negated, the destination 140 determines that it is necessary to insert a specific data pattern into one or more partitions. As described above, when the packet type is a full - size write packet, a read response packet, or a cache victim packet, typically each partition enable signal is asserted. Therefore, the destination 140 interprets the negated enable signal as indicating that a specific data pattern should be included in a specific partition. Accordingly, the payload data assembler 142 (or assembler 142) inserts a specific data pattern into a specific partition when storing read response payload data.

[0024] Note that each of the source 110, the destination 140, the routing component 120, the logics 112, 114, 132, and the assembler 142 is implemented by either a hardware circuit, software, or a combination of hardware and software. Although not shown, in other embodiments, the routing component includes multiple stages of storage elements in addition to multiple types of queues for storing packets based on the packet type. For example, the routing component 120 uses multiple queues to store read response data, write data, read access requests, write access requests, probe requests, etc. Further, in some embodiments, the routing component 120 uses arbitration logic to determine an order for transmitting packets to the destination 140 via the interface 136.

[0025] Moving on to FIG. 2, a generalized block diagram of one embodiment of computing system 200 is shown. The same reference numerals are used for the circuits and logic described above. The storage element 234 of routing component 120 is shown as a flip-flop circuit, but other storage elements are possible and contemplated. Packet 224 generally represents a packet received by routing component 120 such as packet 150. Thus, packet 224 includes the same fields as described above for packet 150. Clock gating logic 232 (or logic 232) conditionally enables and disables clock signal 130 to one or more storage elements 234 using the partition enable signal from packet 224. For example, logic 232 disables the clock signal 130 of each of the storage elements 234 assigned to store the data of the partition of the payload data associated with the negated enable signal of the partition enable signal. When the size of the partition is in bytes, logic 232 uses the byte enable signal as the clock enable signal.

[0026] As shown, packet 224 includes N partitions where N is a positive integer other than zero. Each partition includes M bits where M is a positive integer other than zero. Examples of partition sizes as described above include bytes, words, double words, etc. For each of the M bits of partition N, logic 232 conditionally enables the clock signal 130 of the associated one of storage elements 234 using the signal that enables partition N. When the size of the partition is in bytes, the enabling of partition N is the byte enable signal of the M bits of partition N. Logic 232 uses the enable signal of partition N as the clock enable signal for the payload data from bit 0 of partition N to bit M of partition N.

[0027] Referring to FIG. 3, an embodiment of a method 300 for efficient data transfer in a computing system by a routing component is shown. For purposes of explanation, the steps in this embodiment (and the steps in FIGS. 4-6) are shown in order. However, it should be noted that in various embodiments of the method being described, one or more of the elements being described may be executed simultaneously, may be executed in an order different from the order shown, or may be omitted entirely. Other additional elements may also be executed as needed. Any of the various systems or devices described herein are configured to implement methods 300 and 400-600.

[0028] The source generates a packet and transmits the packet to a destination via the communication fabric of the computing system. The communication fabric includes one or more routing components. The interface of a particular routing component receives the packet (block 302). The control logic of the routing component is implemented by a hardware circuit, software, or a combination of hardware and software. The control logic analyzes the received packet. For example, the control logic decodes the commands in the header. If the packet is a data packet storing payload data, the control logic examines in detail the partition enable signal corresponding to the partition of the payload data.

[0029] If there is no partition that negates the enable signal (conditional block 304: "No"), the control logic maintains the clock signal of the storage element allocated to store the partition data (block 306). However, if any of the partitions have a negated enable signal (conditional block 304: "Yes"), the control logic disables the clock signal of the storage element allocated to store the data of these partitions (block 308). Therefore, the control logic uses the partition enable signal as the clock enable signal. Thereafter, the control logic transmits the packet to the destination via an interconnect such as a communication fabric (block 310).

[0030] Referring to FIG. 4, an embodiment of a method 400 for efficient data transfer in a computing system by a source is shown. Any one of one or more sources in the computing system generates a packet within the computing system (block 402). Examples of sources include a general-purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a multimedia engine, an input / output (I / O) device, and the like.

[0031] The source determines the type of the packet (block 404). Examples of packet types include read request packets, read response packets, full-size write request packets, partial-size write request packets, write data packets, cache victim packets, probe request packets, coherence command packets, and the like. In some embodiments, the source splits a write request into a write control packet and a write data packet. The source inserts the write command into the write control packet and inserts the write data into a separate write data packet corresponding to the write command. In an embodiment, the source inserts a read request command into a read control packet. Then, the destination receives the read control packet and inserts a read response command into the read control packet. The destination also inserts the response data into a separate read data packet.

[0032] A partial-size write request packet is an example of a packet type having a sparsely asserted enable signal for partitioning payload data. For example, if the source desires to update 2 words (8 bytes) of a 64-byte cache line, the partial-size write request packet includes 8 asserted partition enable signals for the 8 bytes to be updated. The other 56 partition enable signals are negated. In another example, the source wishes to update all of a 64-byte cache line except the last word (4 bytes). Thus, the partial-size write request packet includes 60 asserted partition enable signals for the 60 bytes to be updated. The remaining 4 partition enable signals are negated. For other packet types such as read response packets, cache victim packets, full-size write packets, etc., each partition enable signal is asserted. These packet types do not have negated partition enable signals.

[0033] If the packet type indicates an enable signal that is sparsely asserted for a partition of the payload data (conditional block 406: "Yes"), the source maintains the value of the partition enable signal (block 408). However, if the packet type does not indicate an enable signal that is sparsely asserted for a partition of the payload data (conditional block 406: "No"), the source determines whether any partition contains a specific data pattern. An example of a specific data pattern is that all within the partition are zeros. Other examples of specific data patterns are possible and contemplated.

[0034] If the source determines that there is no partition containing a specific data pattern (conditional block 410: "No"), the control flow of method 400 moves to block 408 and the source maintains the value of the partition enable signal. If the source determines that any partition contains a specific data pattern (conditional block 410: "Yes"), the source negates the enable signal for the partition containing the specific data pattern (block 412). In some embodiments, the source asserts an indicator within the packet header that indicates that the packet has a packet type not associated with an enable signal sparsely asserted for a partition of the payload data. Later, instead of decoding the commands of the header packet, the destination uses the indicator to determine whether the packet type is associated with an enable signal sparsely asserted for a partition of the payload data. The source transmits the packet to the destination via an interconnect such as a communication fabric (block 414).

[0035] Moving on to FIG. 5, an embodiment of a method 500 for identifying packet types for efficient data transfer in a computing system is shown. Control logic receives a packet. The control logic is internal to a source or destination of the computing system. The control logic is implemented by a hardware circuit, software, or a combination of hardware and software. The control logic examines the packet in detail (block 502). The control logic analyzes the header of the packet to determine the packet type. If the control logic determines that the packet type is a read response type (conditional block 504: "yes"), a full-size write request type (conditional block 506: "yes"), or a cache victim type (conditional block 508: "yes"), then the control logic determines that the packet does not contain a sparse enable signal for partitioning of the packet (block 510). Otherwise, the control logic determines that the packet contains a sparse enable signal for partitioning of the packet (block 512). These results are later used by control logic to determine whether to update the partition enable signal, as described above in method 400.

[0036] Moving on to FIG. 6, an embodiment of a method 600 for identifying packet types for efficient data transfer in a computing system by a destination is shown. Any one of one or more destinations within the computing system receives a packet within the computing system (block 602). Examples of destinations include system memory, a general-purpose central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a multimedia engine, an input / output (I / O) device, and the like. The destination determines the type of the packet (block 604). As described above, examples of packet types include a read request packet, a read response packet, a full-size write request packet, a partial-size write request packet, a write data packet, a cache victim packet, a probe request packet, a coherence command packet, and the like.

[0037] If the packet type indicates an enable signal asserted sparsely for a partition of the payload data (conditional block 606: "Yes"), the destination maintains the received data for the partition of the packet (block 608). However, if the packet type does not indicate an enable signal asserted sparsely for a partition of the payload data (conditional block 606: "No"), the destination determines whether any partition has a related enable signal that is negated. If there is no negated partition enable signal for the payload data (conditional block 610: "No"), the control flow of method 600 moves to block 608 where the destination maintains the received data for the partition of the packet.

[0038] If the destination determines that there is any negated partition enable signal for the payload data (conditional block 610: "Yes"), the destination replaces these partitions with a specific data pattern and asserts the corresponding enable signal (block 612). An example of a pattern of specific data is that all within the partition is zero. Other examples of specific data patterns are possible and contemplated. The destination processes the packet using the data within the valid partitions (block 614). For example, the destination performs a write operation on the partition using the asserted partition enable signal. The data of these partitions updates the data stored at the memory location of the destination pointed to by the address stored in the packet. In some embodiments, a specific data pattern is used, but this specific data pattern is not transferred by the communication fabric between the source and the destination.

[0039] Moving on to FIG. 7, a generalized block diagram of one embodiment of a computing system 700 is shown. The computing system 700 includes a communication fabric 710 between a memory controller 770 and clients 790. The memory controller 770 is used for interfacing with a memory 780. Three clients 792 - 796 are shown as clients 790, but the computing system 700 can include any number of clients. The communication fabric 710 (or fabric 710) includes multiple types of blocks for routing control and data packets. For example, the fabric 710 includes multiple routing components 720, 762, 764, 766 in addition to a routing component 750 and a routing network 760. Each of the sources and destinations of the computing system 700 and the fabric 710 supports a specific interconnection protocol. Packets carried on the fabric 710 include the same fields as described above for packet 150 (of FIG. 1). One or more blocks within the fabric 710 include clock gating logic that uses a partition enable signal as a clock enable signal to disable storage elements used to store partitions of payload data. For example, the routing component 720 is shown as including clock gating logic 742 that receives a partition enable signal 744. When the size of the partition is in bytes, the partition enable signal 744 is a byte enable signal. The clock gating logic 742 reduces the power consumption of the computing system 700 by disabling the clock signal. In various embodiments, the clock gating logic 742 has a function equivalent to that of the clock gating logic 132 (of FIG. 1) and the clock gating logic 232 (of FIG. 2).

[0040] In some embodiments, client 790 is an individual die on an integrated circuit (IC) such as a system-on-chip (SOC). In other embodiments, client 790 is an individual die within a system-in-package (SiP) or a multi-chip module (MCM). In yet other embodiments, client 790 is an individual die or chip on a printed circuit board. In various embodiments, client 790 is used in smartphones, tablet computers, gaming consoles, smartwatches, desktop computers, and the like. Each of clients 792, 794, 796 is a functional block or unit, a processor core, or a processor. For example, in an embodiment, computing system 700 includes a general-purpose central processing unit (CPU) 792, a highly parallel data architecture processor such as a graphics processing unit (GPU) 794, and a multimedia engine 796. As described above, other examples of clients are possible, such as a display unit, one or more input / output (I / O) peripheral devices, a multimedia player, one or more hubs used for an interface with a display unit, and the like. In such a case, the hub is a client in computing system 700.

[0041] Memory controller 770 includes queues for storing requests and responses. Further, memory controller 770 groups requests to be sent to memory 780, sends requests based on the timing specifications of memory 780, and includes control logic for supporting any burst mode. Also, memory controller 770 includes status and control registers for storing control parameters. In various embodiments, each of routing component 720 and memory controller 770 reorders received memory access requests for efficient out-of-order service. The reordering is based on one or more of priority levels, quality of service (QoS) parameters, elapsed time of packets of memory access requests, etc. Although a single memory controller 770 is shown, in other embodiments, computing system 700 includes multiple memory controllers each supporting one or more memory channels.

[0042] In various embodiments, memory 780 includes row buffers for storing the contents of rows of accessed dynamic random access memory (DRAM). In an embodiment, access to memory 780 includes a first activation or opening stage, followed by a stage of copying the contents of the entire row to the corresponding row buffer. Thereafter, in addition to updating relevant status information, there is access to read or write columns. In some embodiments, memory 780 includes multiple banks. Each bank includes its own row buffer. The accessed row is identified by an address such as a DRAM page address in a memory access request received from one client 790. In various embodiments, the row buffer stores a page of data. In some embodiments, a page is a 4 kilobyte (KB) continuous storage of data. However, other page sizes are possible and contemplated.

[0043] In one embodiment, the memory 780 includes a plurality of three-dimensional (3D) memory dies stacked on top of each other. Die stacking technology is a manufacturing process that enables physically stacking multiple separate silicon dies (integrated chips) within the same package with high-bandwidth and low-latency interconnects. In some embodiments, the dies are arranged on a silicon interposer or directly stacked vertically on top of each other. One configuration of a SiP is to stack one or more memory chips adjacent to and / or on top of a processing unit.

[0044] In various embodiments, a copy of updated (latest) data is supplied from the memory 780 to one or more levels of the cache memory subsystem of one of the clients 790. Based on the instructions being processed by the client, the client updates a copy of the data and now includes a copy of the updated (latest) data. Alternatively, the client does not modify the data retrieved from the memory 780 and uses it to process the instructions of one or more applications and updates other data. Later, when the client processes the instructions of another application and deletes specific data stored at a specified memory address, the cache memory subsystem is filled with other data. A copy of the data is returned from the corresponding one of the clients 790 to the memory 780 by a write access request to update the copy stored in the memory 780.

[0045] In various embodiments, fabric 710 transfers data among clients 790 and between memory 780 and clients 790. Each of routing components 762, 764, 766 supports a communication protocol with clients 792, 794, 796. In some embodiments, each of routing components 720, 750, 762, 764, 766 communicates with a single client as illustrated. In other embodiments, one or more of routing components 720, 750, 762, 764, 766 communicate with multiple clients and track packets by client identifier. In some embodiments, routing components 720, 750, 762, 764, 766 include at least a queue for storing request packets and response packets, selection logic for arbitrating among received packets before transmitting the packets to network 760, and logic for constructing packets, decrypting packets, and supporting a communication protocol with routing network 760. In an embodiment, routing components 720, 750, 762, 764, 766 have an updated mapping between the address space and the memory channel. In various embodiments, routing components 720, 750, 762, 764, 766 and memory controller 770 include hardware circuits and / or software for implementing an algorithm for providing their desired functionality.

[0046] In various embodiments, fabric 710 includes control logic, status and control registers, other storage elements for queuing requests and responses, storing control parameters, and efficiently routing traffic between sources and destinations of one or more buses according to one or more communication and network protocols. In an embodiment, routing network 760 utilizes a plurality of switches in a point-to-point (P2P) ring topology. In other embodiments, routing network 760 utilizes network switches with programmable routing tables in a cluster topology. In yet other embodiments, routing network 760 utilizes a combination of topologies.

[0047] As illustrated, arbitration unit 730 includes a read queue 732, a write queue 736, and selection logic 740. Although two queues are shown, in various embodiments, arbitration unit 730 includes any number of queues for storing memory access responses. Selection logic 740 selects between a selected read response 734 and a selected write response 738 and transmits the selected response 742 to each of clients 790 via fabric 710. In one embodiment, arbitration unit 730 receives memory access responses from memory controller 770 via interface 722. In some embodiments, arbitration unit 730 stores received read responses in read queue 732 and stores received write responses in write queue 736. In other embodiments, received read responses and received write responses are stored in the same queue. In some embodiments, arbitration unit 730 rearranges received memory access responses for efficient out-of-order service. The rearrangement is based on one or more of a priority level, a quality of service (QoS) parameter, the elapsed time of packets of a memory access request, or other considerations. The rearrangement algorithm is used by logic (not shown) disposed within or adjacent to read queue 732 and write queue 736, similar to selection logic 740.

[0048] In various embodiments, the arbitration unit 730 includes programmable control registers and / or control logic for adapting the algorithms used for response selection and rearrangement based on the characteristics of the fabric 710. In some embodiments, each of the interfaces 722, 724 includes a storage element for storing received packets. The clock gating logic 742 receives a partition enable signal 744 of a data packet that stores payload data partitioned into partitions. The clock gating logic 742 reduces the power consumption of the computing system 700 by disabling the clock signal to at least the storage elements of the interfaces 722, 724. When a plurality of components and routing components 720, 750, 762, 764, 766 within the routing network 760 use clock gating logic that depends on the partition enable signal associated with the partition of the payload data, the computing system 700 reduces the power consumption to process the application.

[0049] In various embodiments, the program instructions of the software application are used to implement the methods and / or mechanisms described herein. The program instructions describe the behavior of the hardware in a high-level programming language such as the C language. Alternatively, a hardware design language (HDL) such as Verilog is used. The program instructions are stored in a non-transitory computer-readable storage medium. Many types of storage media are available. The storage medium is accessible by the computing system during use and provides the program instructions and associated data to the computing system for program execution. The computing system includes at least one or more memories and one or more processors that execute the program instructions.

[0050] It should be emphasized that the above-described embodiments are merely non-limiting examples of embodiments. Many variations and modifications will be apparent to those skilled in the art upon a sufficient understanding of the above disclosure. The following claims are intended to be construed so as to embrace all such variations and modifications.

Claims

1. A computing system, comprising: a routing component configured to be coupled to each of a source and a destination; wherein the routing component: receives a data packet from the source, the data packet including a plurality of partitions of a data payload and a plurality of partition enable signals, each of the plurality of partition enable signals indicating whether a related one of the plurality of partitions contains valid data; in response to determining that a partition enable signal corresponding to a predetermined partition indicates that the predetermined partition does not store valid data, disables a clock signal to a plurality of storage elements assigned to store data of the predetermined partition among the plurality of partitions; includes a circuit configured to perform the above; A computing system.

2. The routing component of claim 1, further configured to: transmit the partition enable signal and a previous value stored in each storage element assigned to store data of the predetermined partition to the destination. The computing system of claim 1.

3. The routing component of claim 1, further configured to: in response to determining that the predetermined partition has a related partition enable signal in the data packet indicating that the predetermined partition stores valid data, enable a clock signal to each storage element of the routing component assigned to store data of the predetermined partition. The computing system of claim 1.

4. The source of claim 1, further configured to: in response to determining that the predetermined partition includes a predetermined data pattern, set the partition enable signal for the predetermined partition to a value indicating that the predetermined partition does not store valid data. The computing system of claim 1.

5. The data packet of claim 4 is a read response type data packet. The computing system of claim 4.

6. The source of claim 1, Further configured to insert an indicator of a predetermined data pattern into the predetermined partition of the data packet. The computing system of claim 1. **Claim 7** The routing component further comprises either a switch or a repeater of the communication fabric between the source and the destination. The computing system of claim 1. **Claim 8** The source comprises one or more of a central processing unit, a graphics processing unit, and a multimedia engine. The computing system of claim 1. **Claim 9** A method comprising: a source generating a packet including a plurality of partitions of a data payload and a plurality of enable signals respectively associated with the plurality of partitions; a destination processing the packet; a routing component receiving a data packet, the data packet including a plurality of partitions of a data payload and a plurality of partition enable signals, each of the plurality of partition enable signals indicating whether an associated partition of the plurality of partitions contains valid data; the routing component disabling a clock signal to a plurality of storage elements assigned to store data of the predetermined partition among the plurality of partitions in response to determining that a partition enable signal corresponding to the predetermined partition indicates that the predetermined partition does not store valid data. A method. **Claim 10** Further comprising transmitting to the destination the partition enable signal of the predetermined partition and a previous value stored in each storage element assigned to store data of the predetermined partition. The method of claim 9. **Claim 11** Further comprising enabling a clock signal to each storage element of the routing component assigned to store data of the predetermined partition in response to determining that the predetermined partition has an associated partition enable signal indicating that the predetermined partition stores valid data. The method of claim 9. ​ According to claim 12, further comprising setting the partition enable signal for the predetermined partition to indicate that the predetermined partition does not store valid data in response to determining that the predetermined partition includes a predetermined data pattern. The method of claim 9.

13. The data packet is a cache victim type data packet. The method of claim 12.

14. The data packet is a full-size write type data packet. The method of claim 12.

15. Further comprising inserting an indicator of a predetermined data pattern into the predetermined partition of the data packet by a source of the data packet. The method of claim 12.

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