Memory device

Abstract

To provide a storage device in which power consumption is reduced.SOLUTION: A storage device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of applying a precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. Preferably, the precharge voltage and either a low power supply voltage or a high power supply voltage are supplied to the latch circuit in a standby state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, and more particularly to a memory device.

[0002] Another aspect of the present invention relates to an object, a method, or a manufacturing method. The term "process, machine, manufacture, or composition" is used interchangeably. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. The memory devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices are The device may include a semiconductor device. [Background technology]

[0004] There is a growing emphasis on reducing the power consumption of electronic devices. Power consumption is a major issue in circuit design. The power consumption of an IC can be broadly divided into Power consumption when in operation (dynamic power) and when not in operation (standby power) When the operating frequency is increased to improve performance, the dynamic Most of the static power is consumed by transistor leakage current. The leakage current includes subthreshold leakage current, gate leakage current, Channel leakage current, Gate-induced drain leakage (GIDL) There are two types of leakage current: drain leakage current and junction tunnel leakage current. These leakage currents increase as transistors become smaller, leading to increased power consumption. This is a major obstacle to improving the performance and integration of ICs.

[0005] To reduce the power consumption of semiconductor devices, power gating and clock gating are used. Power gating is a technique for shutting down circuits that do not need to be operated. This has the effect of eliminating standby power because it stops the power supply. To enable this, the contents of registers and caches must be backed up to non-volatile memory. It will be necessary to do so.

[0006] The active layer is made of oxide semiconductor. transistor (hereinafter referred to as an "oxide semiconductor transistor" or "OS transistor"). ) has an extremely small off-state current, which allows data to be retained even when the power is off. For example, Non-Patent Document 1 proposes a memory circuit that can OS-SRAM (Static Random Access Memory) with a backup circuit using a Non-patent document 1 discloses a microcomputer equipped with OS-SRAM. The processor can be power gated with a short break-even time (BET) without affecting normal operation. It is disclosed that it is possible to [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] T. Ishizu et al., Int. Memory Workshop, 2014, pp.106-103.

[0008] [Non-patent document 2] S. Bartling et al., ISSCC Dig.Tech.Papers, pp.432‐434, 2013. [Non-patent document 3] N. Sakimura et al., ISSCC Dig.Tech.Papers, pp.184‐185, 2014. [Non-patent document 4] VK. Singhal et al., ISSCC Dig.Tech.Papers, pp.148‐149, 2015. Summary of the Invention [Problem to be solved by the invention]

[0009] SRAM is a high-speed memory, so it is used for storing data stored in logic circuits such as CPUs. It is used in memory and cache memory. However, as the capacity of SRAM increases, Low voltage operation, standby current (current when not accessed), and cell size are issues. do.

[0010] An object of one embodiment of the present invention is to provide a memory device with reduced power consumption. Another object of one embodiment of the present invention is to provide a memory device with a small circuit area. An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with a small circuit area. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] It should be noted that the description of multiple problems does not preclude the existence of each problem. It is not necessary to solve all of the problems exemplified above. Furthermore, problems other than those listed may be solved by the present specification, etc. This problem is also one of the problems of the present invention. It could be. [Means for solving the problem]

[0012] One aspect of the present invention is a memory cell including a plurality of memory cells, a precharge circuit, a latch circuit, and a first bit a bit line pair consisting of a first local bit line and a second local bit line; a local bit line pair consisting of a first transistor and a second transistor; The first transistor is connected to the first bit line and the first local bit line. The second transistor has a function of controlling the second bit line and the second local bit line. The plurality of memory cells each have a function of controlling a conduction state. The third transistor has a first capacitance element and a second capacitance element. The fourth transistor has a function of controlling the conduction state between the local bit line and the first capacitance element. The capacitor has a function of controlling the conduction state between the second local bit line and the second capacitance element. The charge circuit has the function of supplying a precharge voltage to the local bit line pair. The path is electrically connected to the local bit line pair. The latch circuit includes a first transistor, a second transistor, and a When the transistor, the third transistor, and the fourth transistor are non-conductive, Preferably, the power supply is supplied with a power supply voltage and one of a low power supply voltage or a high power supply voltage.

[0013] In the above embodiment, the third transistor has an oxide semiconductor in a channel formation region, and the fourth transistor The transistor preferably has an oxide semiconductor in a channel formation region.

[0014] In the above embodiment, the plurality of memory cells are provided on the precharge circuit or the latch circuit. It is preferable that

[0015] One aspect of the present invention is a memory cell including a plurality of memory cells, a precharge circuit, a latch circuit, and a first bit a bit line pair consisting of a first local bit line and a second local bit line; a local bit line pair consisting of a first transistor and a second transistor; The first transistor is connected to the first bit line and the first local bit line. The second transistor has a function of controlling the second bit line and the second local bit line. The plurality of memory cells each have a function of controlling the conduction state. are classified as second memory cells. The first memory cells are classified as third transistors and The second memory cells each have a fourth transistor and a second capacitor. The third transistor controls the conduction state between the first local bit line and the first capacitance element. The fourth transistor has a function of controlling the conduction between the second local bit line and the second capacitance element. The precharge circuit has a function of controlling the on-state of the local bit line pair. The latch circuit has a function of supplying a voltage to the local bit line pair. The latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. When the transistor is non-conducting, the precharge voltage and either the low or high supply voltage are connected. , is preferably supplied.

[0016] In the above embodiment, the third transistor has an oxide semiconductor in a channel formation region, and the fourth transistor The transistor preferably has an oxide semiconductor in a channel formation region.

[0017] In the above embodiment, the plurality of memory cells are provided on the precharge circuit or the latch circuit. It is preferable that

[0018] One aspect of the present invention is a semiconductor wafer having a plurality of the memory devices according to the above aspects and having an isolation region. It's Ha.

[0019] One embodiment of the present invention is an electronic device including the storage device according to any one of the above embodiments and a battery. . [Effects of the Invention]

[0020] According to one embodiment of the present invention, a memory device with reduced power consumption can be provided. According to one embodiment of the present invention, a memory device with a small circuit area can be provided. By adopting this configuration, a semiconductor device with reduced power consumption can be provided. According to one embodiment, a semiconductor device with a small circuit area can be provided. The embodiment can provide a novel semiconductor device.

[0021] It should be noted that the description of multiple effects does not preclude the existence of other effects. The embodiment does not necessarily have all the effects exemplified. Other problems, effects, and novel features will be apparent from the description of this specification, etc. This is what happens. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a storage device. [Figure 2] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 3] 4 is a timing chart showing an example of the operation of the storage device. [Figure 4] FIG. 1 is a circuit diagram showing a configuration example of a memory cell. [Figure 5] FIG. 1 is a block diagram showing an example of the structure of a memory cell array. [Figure 6] FIG. 1 is a circuit diagram showing an example of the structure of a memory cell. [Figure 7] FIG. 1 is a circuit diagram showing an example of the structure of a memory cell. [Figure 8] FIG. 1 is a circuit diagram showing an example of the structure of a memory cell. [Figure 9] FIG. 1 is a circuit diagram showing an example of the structure of a memory cell. [Figure 10] FIG. 2 is a circuit diagram showing a memory cell, a voltage holding circuit, and a voltage generating circuit. [Figure 11] FIG. 2 is a circuit diagram showing a configuration example of a voltage generating circuit. [Figure 12] FIG. 1 is a cross-sectional view showing a configuration example of a storage device. [Figure 13] FIG. 1 is a cross-sectional view showing a configuration example of a storage device. [Figure 14] FIG. 1 is a cross-sectional view illustrating a structural example of a transistor. [Figure 15] A diagram explaining the InMZnO4 crystal. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a transistor. [Figure 20] FIG. 2 is a block diagram showing an example of the configuration of a processor (CPU). [Figure 21] FIG. 1 is a block diagram showing an example of the configuration of a processor (RFIC). [Figure 22] Top view of a semiconductor wafer. [Figure 23] 1A and 1B are a flowchart and a perspective view illustrating a manufacturing process of a semiconductor device. [Figure 24] FIG. 1 is a perspective view showing an example of an electronic device. [Figure 25] FIG. 1 is a block diagram showing an example of the configuration of a prototype chip. [Figure 26] Block diagram showing an example of the configuration of a prototype DOSRAM. [Figure 27] Schematic diagram showing an example of the configuration of DOSRAM. [Figure 28]Figure showing the calculation results of the active energy of DODRAM. [Figure 29] Layout of the prototype DODRAM. [Figure 30] Circuit diagram of the prototype OS flip-flop. [Figure 31] Optical microscope image of the prototype chip. [Figure 32] FIG. 10 is a graph showing the retention characteristics of a prototype chip. [Figure 33] A diagram showing the backup-recovery waveforms of the prototype chip. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. The present invention is not to be construed as being limited to the embodiments and the contents of the examples.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are designated by the same reference numerals. The same reference numerals are used in common among different drawings, and the repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be added.

[0025] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0026] In this specification, unless otherwise specified, the on-current is the current when a transistor is in the on-state. The on-state refers to the drain current when the transistor is in the on-state, unless otherwise specified. In a transistor, the voltage between the gate and source (V G ) is the threshold voltage (V th ) or more states, p In a channel transistor, V G V th For example, the following state is shown: The on-current of a transistor is V G V th This refers to the drain current when The on-state current of a transistor is determined by the voltage between the drain and source (V D ) may depend on

[0027] In this specification, unless otherwise specified, the off-state current refers to the current when a transistor is in an off state. The off state refers to the drain current when the transistor is in the off state unless otherwise specified. At the stadium, V G V th For p-channel transistors, V G V th For example, the off-state current of an n-channel transistor is higher than V G V th The off-state current of a transistor is the drain current when the voltage is lower than V G Depends on Therefore, the off-state current of the transistor may be -21 Less than A means that The off-state current of the transistor is 10 -21 V less than A G It may be said that there exists a value of

[0028] The off-state current of the transistor is V D In this specification, Currents are V unless otherwise specified. D The absolute value of is 0.1V, 0.8V, 1V, 1.2V, 1 0.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V Alternatively, it may refer to a semiconductor device that includes the transistor. Used V D The term may refer to the off-state current at

[0029] In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc. depending on the situation. It can be done.

[0030] In this specification, the high power supply voltage is referred to as the H level (or V DD ), low power supply voltage is L level This is sometimes called the ground (or GND).

[0031] In addition, in this specification, the following embodiment modes and examples can be combined as appropriate. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined with each other as appropriate. It is possible to match.

[0032] (Embodiment 1) In this embodiment, a memory device will be described as an example of a semiconductor device.

[0033] The storage device of this embodiment is a nonvolatile memory section A capable of high-speed processing, and a power-on It has a memory section B that can retain data for a long time even in a power-off state.

[0034] The memory section A corresponds to the working memory and is used for data exchange between the host device and the storage device. Memory section B corresponds to the storage section of long-term memory, and the information written in memory section A is Memory section B has a slower processing speed than memory section A, but it retains the data for a long time. The memory section B has a large capacity. In addition, the memory section B can retain data for a long time even when the power is off. It is Noh.

[0035] <<Storage device 100>> 1 is a block diagram showing an example of the configuration of a storage device. A cell array 110, a peripheral circuit 111, a control circuit 112, a voltage generating circuit 127, It has power switches (PSW) 141 and 142.

[0036] In the storage device 100, each circuit, each signal, and each voltage may be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals. The signal RDA is an output signal to the outside. The signal CLK is a clock signal. CE, GW, and BW are control signals. CE is a chip enable signal. , signal GW is the global write enable signal, and signal BW is the byte write enable signal. The signal ADDR is the address signal. The signal WDA is the write data. The signal RDA is the read data. The signals PON1 and PON2 are the power gates. The signals PON1 and PON2 are used for controlling the transmission of the data. It may be done.

[0037] The control circuit 112 is a logic circuit having a function of controlling the overall operation of the storage device 100. For example, the control circuit performs a logical operation on the signals CE, GW, and BW. The operation mode of the storage device 100 (for example, write operation, read operation) is determined by calculating the Alternatively, the control circuit 112 may control the peripheral circuits so that this operation mode is executed. 111 control signals.

[0038] The memory cell array 110 includes a plurality of memory cells (MC) 130, a plurality of wirings WL, The memory cells 130 are arranged in rows and columns, and have NWL, BL, and BLB.

[0039] The memory cells 130 in the same row are electrically connected to the wirings WL and NWL in that row. L and NWL are word lines, and lines BL and BLB are for transmitting complementary data. The wiring BLB is a bit line to which data with the logic of BL reversed is input. These are sometimes called complementary bit lines or inverted bit lines. The memory circuit 10 (hereinafter referred to as "SMC 10") has the following memory circuits 10 and 20. The memory circuit 20 (hereinafter referred to as the memory circuit 20) is a memory circuit capable of storing one bit of complementary data. Hereinafter referred to as "NVM20", the NVM20 stores n-bit (n is an integer greater than 1) complementary data. It is a memory circuit that can store data and retain it for a long period of time even when the power is off. In other words, the SMC 10 constitutes the memory section A (working memory) mentioned above. The NVM 20 is a memory cell that constitutes the memory section B (long-term memory storage section) described above. It is a cell.

[0040] The voltage generating circuit 127 generates a negative voltage (V BG ) has the function of generating V BG is NVM20 The WAKE signal is applied to the transistors used. For example, when a high-level signal is given to WAKE, the signal C LK is input to the voltage generating circuit 127, and the voltage generating circuit 127 outputs V BG Generates the following. The voltage generating circuit 127 will be described in detail later with reference to FIGS.

[0041] The SMC 10 and NVM 20 are electrically connected by a local bit line pair (lines LBL and LBLB). The line LBLB is a local bit line for the line BL, and the line L BLB is a local bit line for the line BLB. The SMC 10 and the NVM 20 are electrically connected. (hereinafter referred to as "LPC30"). LPC30 has wiring LBL and wiring LB This is a local precharge circuit for precharging LB. Control signal of LPC30 is generated in the peripheral circuit 111.

[0042] The peripheral circuit 111 writes and reads data to and from the memory cell array 110. The peripheral circuit 111 is a circuit for driving the wirings WL, NWL, BL, and BLB. The peripheral circuit 111 includes a row decoder 121, a column decoder 122, a row driver 1 23, a column driver 124, an input circuit 125, and an output circuit 126.

[0043] The row decoder 121 and the column decoder 122 have the function of decoding the signal ADDR. The row decoder 121 is a circuit for specifying the row to be accessed, and the column decoder 122 is a circuit for specifying a column to be accessed. The row driver 1 has the function of selecting the wiring WL and NWL of the row specified by the row driver 1. The column driver 23 has a function of generating a signal for selecting the wirings WL and NWL. 24 is a function for writing data to the memory cell array 110, and The function to read data, the function to hold the read data, the wiring BL and the wiring BLB It has functions such as precharging.

[0044] The input circuit 125 has a function of holding the signal WDA. The output data of the input circuit 125 is output to the column driver 124. The column driver 124 reads data from the memory cell array 110. The output data (Dout) is output to the output circuit 126. The output circuit 126 has a function of storing the stored data. The output data is the signal RDA.

[0045] The PSW 141 supplies VDD to circuits other than the memory cell array 110 (peripheral circuit 115). The PSW 142 controls the supply of VHM to the row driver 123. Here, the high power supply voltage of the storage device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is used to set the wiring NWL to a high level. The high power supply voltage is higher than VDD. The signal PON1 turns on the PSW141. The ON / OFF of PSW142 is controlled by signal PON2. In the peripheral circuit 115, the number of power domains to which VDD is supplied is set to 1. In this case, a power switch is provided for each power domain. That's fine.

[0046] <<Memory Cell 130>> FIG. 2 shows an example of the circuit configuration of the memory cell 130.

[0047] <smc10> SMC10 includes wiring BL, wiring BLB, wiring LBL, wiring LBLB, wiring VHH, and It is electrically connected to the wiring VLL.

[0048] SMC10 has the same circuit configuration as a CMOS type (6-transistor type) SRAM cell. , having transistors Tld1, Tld2, Tdr1, Tdr2, Tac1, and Tac2 Transistors Tld1 and Tld2 are load transistors (pull-up transistors) Transistors Tdr1 and Tdr2 are drive transistors (pull-down transistors) The transistors Tac1 and Tac2 are access transistors (transfer transistors). (Zista).

[0049] The transistor Tac1 controls the conduction state between the wiring BL and the wiring LBL. The conduction state between the wiring BLB and the wiring LBLB is controlled by the transistor Tac2. The on / off of the transistors Tac1 and Tac2 is controlled by the potential of the wiring WL. The transistors Tld1 and Tdr1 form an inverter, and the transistors Tld2 and Tdr The inverter is composed of 2. The input terminals of these two inverters are The other output terminal is electrically connected to the other output terminal, forming a latch circuit. The power supply voltage is supplied to the capacitor through wiring VHH and VLL.

[0050] <nvm20> The NVM 20 shown in FIG. 2 has n NMCs (n is an integer of 1 or more). The n NMCs are electrically connected to different wirings NWL. It is electrically connected to CS. To distinguish n NMCs, symbols such as [0] and [1] are used. In order to distinguish between the n wirings NWL, symbols such as _0, _1, etc. are used. .

[0051] NMC is a memory circuit (called a memory cell) that can store one bit of complementary data. MC1 is written to the wiring LBL. MC2 is a memory cell for storing the data written to the wiring LBLB. MC1 and MC2 are memory cells that store the data stored in the memory cells. Circuitry similar to that of a dynamic random access memory (DRAM) memory cell MC1 has a transistor Tr1 and a capacitance element C1. MC2 has a transistor The capacitor C1 functions as a storage capacitor for MC1. The capacitance element C2 functions as a storage capacitor for MC2. This is the power supply line for the storage capacitor 2, and GND is input here.

[0052] The gates (first gates) of the transistors Tr1 and Tr2 are electrically connected to the wiring NWL. One of the source and drain of the transistor Tr1 is electrically connected to the wiring LBL. One of the source and drain of the transistor Tr2 is electrically connected to the wiring LBLB. The first terminal of the capacitance element C1 is connected to the source or drain of the transistor Tr1. The second terminal of the capacitance element C1 is electrically connected to VCS. The first terminal of the capacitance element C2 is electrically connected to the other of the source and drain of the transistor Tr2. The second terminal is electrically connected to the VCS.

[0053] The transistors Tr1 and Tr2 each have a second gate. The second gates of the transistors 2 are electrically connected to the wiring BGL. A signal line to which a signal for controlling the potential of the second gate of the transistors Tr1 and Tr2 is input, The potential of the wiring BGL is the power supply line to which a constant potential is input. The threshold voltages of the transistors Tr1 and Tr2 can be controlled. This prevents Tr2 from becoming normally on.

[0054] By reducing the off-current of transistors Tr1 and Tr2, the NMC hold time is extended. An extremely small off-state current is, for example, The lower the off-state current, the better. It is preferable that the normalized off-state current is 10 zA / μm or less, or 1 zA / μm It is preferable that the current density is 10 yA (yoctoampere) / μm or less, and more preferable that the current density is 10 yA (yoctoampere) / μm or less. 1zA is 1×10 -21 A, and 1yA is 1 x 10 -24 It's A.

[0055] To make the off-state current extremely small, the channel formation region of the transistor must be band-coupled. The gate electrode may be formed from a semiconductor having a wide gap. An example of such a semiconductor is an oxide semiconductor. Since the band gap of oxide semiconductors is 3.0 eV or more, The OS transistor has a small leakage current due to thermal excitation and an extremely small off-state current. The details of the transistor and the oxide semiconductor will be described in Embodiment 3 below.

[0056] By using OS transistors for transistors Tr1 and Tr2, the NMC hold time is extended. Therefore, the NMC can be used as a nonvolatile memory circuit. In OS transistors, the temperature dependence of the off-state current characteristics is small. Even at temperatures above 100°C, the normalized off-state current of the OS transistor is 100µA or less. Therefore, by applying OS transistors to NMC, NMC can be Even in high temperature environments, data can be retained without being lost. Therefore, a storage device 100 having high reliability can be obtained even under such circumstances.

[0057] The NMC has a pair of memory cells (MC1, MC2) that can store complementary data. In addition, by using OS transistors for transistors Tr1 and Tr2, a complementary The NMC can store complementary data for a long time. When reading out the complementary data held in the SMC10, the SMC10 functions as a differential amplifier circuit. Therefore, the voltage held by the capacitance element C1 of MC1 and the capacitance of MC2 Even if the voltage difference with the voltage held by element C2 is small, a highly reliable read operation can be performed. In addition, like DRAM memory cells, NMCs are capable of high-speed read operations and high-speed A write operation is possible.

[0058] The transistors Tr1 and Tr2 included in the NVM 20 may be The second gate may be omitted. By not having a port, the manufacturing process of the storage device 100 can be simplified. The voltage generating circuit 127 shown in FIG. 1 can also be omitted.

[0059] <lpc30> The LPC30 is electrically connected to the wiring PCL and the wiring VPC. This is a signal line for supplying a signal for controlling the precharge operation of the lines LBL and LBLB. The wiring VPC is a power supply line for supplying the precharge voltage. Transistors Teq1, Tpc1, and Tpc2 are included. The gate of transistor Teq1 is electrically connected to wiring PCL. The transistor Tpc1 controls the conduction state between the wiring LBL and the wiring VPC The transistor Tpc2 controls the conduction state between the wiring LBLB and the wiring VPC. Controls the normal state.

[0060] In the example of Figure 2, transistors Teq1, Tpc1, and Tpc2 are n-channel transistors. However, these may be p-channel transistors. eq1 may not be provided. In this case, the transistors Tpc1 and Tpc2 are n-channel Either a n-channel transistor or a p-channel transistor may be used. It can also be configured with only the transistor Teq1. In this case, the transistor Teq1 is also n The transistor Teq may be either a n-channel transistor or a p-channel transistor. The LPC30 consisting of 1 smoothes the potential between the wiring LBL and the wiring LBLB. Precharges BL and wiring LBLB.

[0061] The peripheral circuit 111 is connected to various power supply lines (wirings VHH, V It has the function of supplying potential to the power supplies (LL, VPC). Therefore, when the supply of VDD to the peripheral circuit 111 is stopped, the supply of potential to these power supply lines is also stopped. This will be done.

[0062] In the standby state, the memory cell 130 of FIG. 2 has a leakage current flowing through the SMC 10. In order to reduce static power, the wiring V However, if a new voltage is to be supplied to the wiring VHH, In this case, a new circuit (voltage generation circuit) must be provided to generate the voltage, which increases the area. This will cause an increase in overhead. All word lines (wiring WL and wiring NWL_0 to NWL_[n -1]) is in a non-selected state.

[0063] In order to solve the above problem, in the standby state of the memory cell 130, It is preferable to supply GND and a precharge voltage to the wiring VHH. The precharge voltage is lower than VDD. Also, the precharge voltage is used for LPC30, There is no need to provide a new voltage generating circuit. Alternatively, VDD may be supplied to the wiring VHH. By supplying a voltage to the storage device 100, the storage device 100 can reduce static power consumption. .

[0064] <<Example of Operation of Storage Device 100>> An example of the operation of the storage device 100 will be described using the timing chart of FIG. While the host device is processing a task, the only object of access is the SMC 10. When this is complete, transfer the data from SMC10 to NVM20 (store operation), and then If you want to perform another task, write the data to one of the NMCs. is transferred from one of the NMCs in the NVM 20 to the SMC 10 (load operation). Assuming that the data transfer destination and transfer source are NMC[1], the operation example of the storage device 100 is as follows: explain.

[0065] The times t1 to t8 shown in FIG. 3 represent the timing of each operation. DM is a power supply line for supplying VDD provided in the storage device 100. The supply of VDD to the wiring VDDM is controlled by the The waveform shown by the dotted line indicates that the potential is uncertain. The low level (L level) of M, etc. is GND. The high level (H level) of wiring PCL, WL is VDD, and the high level of the wirings NWL_0 to NWL_[n-1] is VHM.

[0066] The high level of the wirings NWL_0 to NWL_[n-1] is VHM because the transistor The threshold voltages of transistors Tr1 and Tr2 are higher than those of other transistors such as transistor Tac1. This is because we are assuming a high voltage. If data can be written and read from the NVM 20 by applying The high level of WL_0 to NWL_[n-1] can be set to VDD. The storage device 100 does not necessarily have to be provided with the PSW 142 (see FIG. 1).

[0067] <Power gating> First, the power gating operation of the storage device 100 will be described. At time t1, the storage device 100 is in a power-off state where the supply of VDD is cut off. From this point on, the storage device 100 is in a power-on state with VDD being supplied.

[0068] Before time t1, the storage device 100 turns off the PSW 141 and enters a power-off state. The wiring VDDM is set to GND. Also, when PSW141 is turned off, the surrounding Since the supply of VDD to the side circuit 111 is also cut off, the wirings WL, NWL_0 to NWL_[ n-1], PCL, and VPC are also GND.

[0069] When PSW141 turns on at time t1, the wiring VDDM is charged, and then The potential rises to VDD. The time from t1 to t2 is the time required for the power supply to return to normal. In the timing chart of 3, PSW142 is linked to the on / off of PSW141. Just turn it on and off.

[0070] <Initialization, Load> When the power is on from t2 to t4, an initialization operation is performed to set the storage device 100 to its initial state. During the operation from t2 to t3, the bit line pair and the local bit line pair are precharged. Specifically, the wiring VPC, wiring VHH, and wiring VLL are set to VDD / 2. The line pair (lines BL, BLB) and the local bit line pair (lines LBL, LBLB) are The bit line pair is precharged to VDD / 2. The precharging of the local bit line pair is performed by LPC30. By setting the line PCL to a high level (H level), the transistors Teq1, Tpc1, and Tp c2 is turned on, and the wirings LBL and LBLB are precharged and the potential is smoothed.

[0071] Between t3 and t4, the storage device 100 is performing a load operation. Load data from NMC[1] of 0. Here, NMC[1] stores data DB1. The wiring PCL is set to the L level, and the wiring LBL and LBLB are set to the floating state. Next, the wiring NWL_1 is set to H level, and the transistor Tr1 of MC1[1] The transistor Tr2 of MC2[1] is turned on. The data lines LBL and LBLB are connected to the After setting the wiring NWL_1 to the H level, set the wiring VHH to VDD. Then, connect the wiring VLL to GND and activate SMC10. The data DB1 written to the lines LBL and BLBL is amplified and held. MC1[1] When the value is "1", the line LBL is set to VDD and the line LBLB is set to GND. After setting the wiring NWL_1 to H level for a certain period of time, the load operation is completed by setting it to L level. Complete.

[0072] <Write> Between times t4 and t5, the storage device 100 performs a data write operation. The data to be written to SMC10 is data DB2. When there is a write access, the column driver The data DB2 is written to the bit line pair by the driver 124. If the row address is DD, the line BLB is GND. The row driver 123 sets the wiring WL of the row specified by the row address to H level. This turns on the transistors Tac1 and Tac2, and the local bit line pair Data DB2 is written. After the wiring WL is set to the H level for a certain period of time, it is set to the L level. After the line WL is set to the L level, the column driver 124 precharges the bit line pair to VDD / 2. Then, the write operation is completed.

[0073] <Read> Between times t5 and t6, the storage device 100 performs a data read operation. When an access occurs, the row address is decoded by the row decoder 121 and sent to the row driver 12 The wiring WL of the row specified by the row address becomes H level by 3. The data lines Tac1 and Tac2 are turned on, and the data line DB2 of the local bit line pair is connected to the bit line The data DB2 written to the bit line pair is written by the column driver 124. The line WL is set to H level for a certain period of time, and then set to L level. After the bit line pair is set to the VDD / 2 level, the bit line pair is precharged to VDD / 2 by the column driver 124. After that, the data read operation is completed.

[0074] <Standby> Between times t6 and t7, the storage device 100 is in a standby state where there is no access request from the host device. At this time, by keeping the SMC 10 active, the storage device 100 In addition, the wiring VHH can be connected to VD By lowering the power consumption from D to VDD / 2, the storage device 100 reduces the static power consumption of the SMC 10. In FIG. 3, the storage device 100 has a wiring VHH set to VDD / 2 and a wiring V By connecting LL to GND, static power is reduced, but the wiring VHH is connected to VDD, Static power can be reduced by setting VLL to VDD / 2.

[0075] In this embodiment, the precharge voltage is set to VDD / 2, but is not limited to this. The precharge voltage can be selected in the range greater than GND and less than VDD. .

[0076] The above-described operation for reducing static power consumption may be performed for each memory cell 130. That is, in the storage device 100, the memory cell 130 for which an access request is made and the memory cell 130 in the standby state are When memory cells 130 in the standby state are mixed, Only then may the above-described static power reduction operation be performed.

[0077] <Store> Between times t7 and t8, the storage device 100 performs a data transfer (store) operation. The storage device 100 receives a command from the host device to execute another task or to end a task. Upon receiving the command, the memory device 100 performs a store operation. First, the line VHH is returned to VDD. , the line NWL_1 is set to the H level. The data DB written to the local bit line pair is 2 is written to NMC[1]. If the line LBL is VDD, then MC1[1 ] will hold "1" and MC2[1] will hold "0".

[0078] After setting the wire NWL_1 to H level for a certain period of time, it is set to L level. This completes the store operation. Next, the storage device 100 sets the line VHH to VDD / 2 to receive commands from the host device. After that, the storage device 100 reads data in response to an access request from the host device. operation or data write operation.

[0079] <<Modification of memory cell>> The NVM 21 shown in FIG. 4 is a memory circuit having n NMC2s. MC3 is a modification of MC1, and instead of transistor Tr1, A transistor Tr3 is provided. MC4 is a modification of MC2, and a transistor T Instead of r2, a transistor Tr4 is provided.

[0080] The transistor Tr3 is provided with a second gate, and the second gate and the first gate are electrically connected. Similarly, the transistor Tr4 is provided with a second gate, and the second gate and the first gate are connected to each other. The first gate is electrically connected to the second gate. This can improve the on-current of the transistors Tr3 and Tr4.

[0081] <<Device structure of memory cell array>> In the memory device 100, the transistors Tr1 and Tr2 of the NVM 20 are OS transistors. The other transistors may be, for example, Si transistors. The memory cell array 110 is formed by connecting an OS transistor to a circuit made up of Si transistors. The device structure can be a stack of circuits made up of memory cells. 1A and 1B show schematic diagrams of an example of the device structure of a cell array 110.

[0082] <Memory cell array> In the example of FIG. 5, a memory cell array 110B is stacked on a memory cell array 110A. The memory cell array 110A has SMCs 10 and LPCs 30 arranged in a matrix. The memory cell array 110B has NVMs 20 arranged in a matrix. The memory cell array 110A constitutes a memory section A having a high response speed, and the memory cell array 1 10B constitutes a memory section B for long-term storage of data. By stacking the memory cell array 110A, the memory device 100 can be effectively made larger in capacity and smaller in size. It can be done.

[0083] <Twin cell type> Focusing on one of the memory cells 130, the area where the SMC 10 and the LPC 30 are formed is The NVM 20 is formed on the region. 6 is a circuit diagram showing the circuit in which the NVM 20 stores 8-bit complementary data. Therefore, the NVM 20 has NMC[0] to NMC[7]. On the area where SMC10 and LPC30 are formed, NMC[0] to NMC[ 7] is provided. Note that the configuration of the memory cell 130 described above (one wiring Two complementary memory cells (MC1 and MC2) are connected to the NWL. This will be called the cell type.

[0084] In the memory cell 130, the number of NMCs is preferably a multiple of 8. That is, it is preferable that the number of bits of data that the NVM 20 can hold is a multiple of 8. By setting C to a multiple of 8, the memory cell 130 can store, for example, 1 byte (8 bits) or 1 word. Data is handled in units such as word (32 bits) and half word (16 bits). It is possible to do so.

[0085] It is possible to stack an OS transistor on an OS transistor. The cell array 110B can have a device structure in which two or more layers of circuits are stacked. FIG. 7 shows a device of the memory cell 130 when the memory cell array 110B has a two-layer structure. Here, the NVM 20 also has NMC[0] to NMC[7]. NMC[0] to NMC[3] are laminated on the area where 10 and LPC30 are formed. NMC[4] to NMC[5] are formed on the area where NMC[0] to NMC[3] are formed. 7] are stacked.

[0086] By stacking the memory cell array 110B on the memory cell array 110A, For example, if the memory cell 130 is the device shown in FIG. In the case of a memory cell array 110 having a 32-bit structure, the area per bit of the memory cell array 110 is the area of one NMC. In other words, the area per bit is the area where two transistors and two capacitance elements are provided. In addition, when the memory cell 130 has the device structure shown in FIG. The area per bit of the re-cell array 110 is half that of the example in FIG. By stacking NVM20 on MC10, the memory cell capacity is increased compared to that of CMOS-type SRAM. In comparison, the area per bit of the memory cell 130 is smaller.

[0087] The memory cell array 110B configured with the NVM 20 is a flash memory, an MRAM (magnetic random access memory), Others such as resistive random access memory (RRAM) and PRAM (phase change random access memory) Compared to non-volatile memory, flash memory has excellent compatibility with CMOS circuits. MRAM and PRAM are current-driven memories, so they require high voltage to operate. Current drive elements and circuits are required. In contrast, the NVM20 uses transistors 1, Tr2 on and off control. In other words, NVM20 is a CMOS circuit It is a circuit that consists of voltage-driven transistors, and is driven at low voltage. Therefore, it is possible to incorporate the processor and the storage device 100 into one chip. Furthermore, the memory device 100 can easily reduce the area per bit without reducing performance. The storage device 100 can also reduce power consumption. Since the storage device 100 can store data even when the power is off, 100 power gating is possible.

[0088] Because of its speed, SRAM is used as on-chip cache memory in standard processors. SRAM consumes power even when in standby mode, and it is difficult to increase the capacity. For example, processors for mobile devices have on-chip caches. The standby power consumption of memory accounts for 80% of the average power consumption of the entire processor. In contrast, the storage device 100 is said to have fast read and write speeds. It is a RAM that takes advantage of the advantages of SRAM while eliminating its disadvantages. Therefore, applying the storage device 100 to an on-chip cache memory can reduce the overall processor load. It is useful for reducing the body's power consumption.

[0089] <Folding type> Other memory cell layout methods include folded and open types. This is an example in which a folded type is applied to the cell 130. The twin-cell type memory cell 13 shown in FIG. In 0, the NMC is composed of two transistors and two capacitive elements, but in Fig. In the folded memory cell 130, the NMC is composed of one transistor and one capacitance element. In the folded memory cell 130, the NMC is connected to the wiring LBL. The two types are classified as those connected to the wiring LBLB and those connected to the wiring LBLB. In the memory cell 130, the potential of the line NWL changes depending on whether the line LBL or the line LB The noise output to the LB can be reduced.

[0090] <Open type> 9 shows an example in which an open-type memory cell 130 is applied. In 30, the NMC consists of one transistor and one capacitance element. In this case, it appears that two NMCs are connected to one wiring NWL, but two NMs One of the C's is connected to the adjacent memory cell 130. In 130, the NMC is connected to the wiring LBL and the NMC is connected to the wiring LBLB. The open type allows for high integration of NMC, and the twin cell type and folded type In comparison with the conventional type, the storage device 100 can store a larger amount of data.

[0091] The twin-cell memory cell 130 stores complementary data stored in two capacitance elements in one bit. However, the folded and open memory cells 130 are held in one capacitance element. The data entered is treated as 1 bit. Otherwise, the loopback and open-type operation is The explanation of the in-cell type operation can be taken into consideration.

[0092] In the folded and open types, as in the twin cell type, in the standby state, the wiring V GND is supplied to LL and a precharge voltage is supplied to the wiring VHH (or the wiring VLL) It is preferable to supply a precharge voltage to the line VHH and supply VDD to the line VHH. This allows the storage device 100 to reduce static power consumption.

[0093] <<Voltage holding circuits, voltage generation circuits>>

[0094] Next, the voltage holding circuit 128 and the voltage generating circuit 127 will be explained with reference to FIGS. 10 and 11. Give an explanation.

[0095] FIG. 10 shows the NVM 20, the voltage holding circuit 128 connected to the NVM 20, and the voltage holding circuit 128. A voltage generating circuit 127 connected to 128 is shown.

[0096] The voltage holding circuit 128 includes a transistor OS1 and a capacitance element C0. The first terminal of OS1 is connected to the first gate of the transistor OS1, the second gate of the transistor OS1, and the The transistor O is electrically connected to the first terminal of the capacitor C0 and the wiring BGL. The second terminal of S1 is electrically connected to the voltage generating circuit 127 and supplies the voltage V BG Furthermore, In the following description, the transistor OS1 will be described as an n-channel transistor. cormorant.

[0097] The voltage holding circuit 128 writes a potential to the second gates of the transistors Tr1 and Tr2, and For example, the voltage holding circuit 128 has a function of holding the transistor Tr1. When a negative potential is written to the second gate of Tr2, the second gates of the transistors Tr1 and Tr2 While the negative potential of the transistor Tr1 is maintained, the transistors Tr1 and Tr2 are connected to V th To keep the Transistors Tr1 and Tr2 are V th Maintaining a high level prevents normally-on This allows the power consumption of the storage device 100 to be reduced.

[0098] In the transistor OS1, the first gate and the second gate are connected to each other via a semiconductor layer. It is preferable that the transistor OS1 has an area overlapping the above-mentioned OS transistor. It is preferable to use an OS transistor for the transistor OS1. GS The drain current at 0V (hereafter referred to as cutoff current) must be sufficiently small. Therefore, the voltage holding circuit 128 can hold the negative potential applied to the wiring BGL for a long period of time. can.

[0099] The channel length of the transistor OS1 is the same as that of the transistors Tr1 and Tr2. For example, the length of the transistor Tr1 and the transistor T If the channel length of r2 is less than 1 μm, the channel length of transistor OS1 is 1 μm or more. More preferably, the thickness is 3 μm or more, more preferably 5 μm or more, and even more preferably 10 μm or more. μm or more.

[0100] By increasing the channel length of the transistor OS1, the transistor OS1 achieves short channel efficiency. The cut-off current can be kept low without being affected by the effect of the transistor OS. 1 can increase the breakdown voltage between the source and drain. When the withstand voltage between the drains is high, the voltage generating circuit 127 that generates a high voltage and the transistor OS This is preferable because it makes it easier to connect to 1.

[0101] The transistor OS1 is used in circuits that require high integration, such as memory cells. Therefore, it is preferable that the channel lengths of the transistors Tr1 and Tr2 are short. On the other hand, since the voltage holding circuit 128 is formed outside the memory cell, the channel of the transistor OS1 The channel length of the transistor can be long without any problem. Although the on-state current of the transistor OS1 decreases, the transistor OS1 is mainly used in the off state. Therefore, a high on-state current is not required.

[0102] The voltage generating circuit 127 generates a negative potential (V BG ) The circuit diagram shown in Figure 11 1 shows an example of the voltage generating circuit 127. These circuits are step-down charge pumps, GND is input to the input terminal IN, and V is output from the output terminal OUT. BG is output. Here, As an example, the number of stages in the basic circuit of the charge pump circuit is set to four, but it is not limited to this. The charge pump circuit may be configured with any number of stages.

[0103] The voltage generating circuit 127a shown in FIG. 11A includes transistors M21 to M24 and a capacitor Hereinafter, the transistors M21 to M24 are n-channel The explanation will be given as a transistor.

[0104] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT. The gate and the first electrode of each are connected to function as a diode. The gates of the transistors M21 to M24 are connected to the capacitors C21 to C24, respectively. It has been done.

[0105] CLK is input to the first electrodes of the odd-numbered capacitors C21 and C23, and CLKB is input to the first electrodes of C22 and C24. CLKB has the opposite phase to CLK. It is an inverted clock signal.

[0106] The voltage generating circuit 127a reduces the GND input to the input terminal IN and generates V BG Generate The voltage generating circuit 127a generates a negative potential only by supplying CLK and CLKB. It is possible.

[0107] The above-described transistors M21 to M24 may be formed of OS transistors. By using a transistor, the reverse direction of the diode-connected transistors M21 to M24 This is preferable because it can reduce the directional current.

[0108] The voltage generating circuit 127b shown in FIG. 11B is a p-channel transistor. The other components are the voltage generation circuit 1 The explanation in 27a is cited.

[0109] As described above, the storage device 100 according to one embodiment of the present invention can reduce power consumption by using the above-described configuration. This reduces the number of inputs and the circuit area.

[0110] (Embodiment 2) In this embodiment, a configuration example of the storage device 100 shown in the first embodiment will be described. .

[0111] FIG. 12 shows an example of a cross-sectional view of the storage device 100. The storage device 100 shown in FIG. , has a layer L1, a layer L2, a layer L3, and a layer L4 stacked in this order from the bottom.

[0112] The layer L1 includes a transistor M1, a substrate 300, an isolation layer 301, an insulator 302, and The connector 300 includes a plug 310 and the like.

[0113] The layer L2 includes an insulator 303, a wiring 320, an insulator 304, a plug 311, etc. .

[0114] The layer L3 includes an insulator 214, an insulator 216, a transistor Tr1, a plug 312, and The first gate of the transistor Tr1 is connected to the wiring NW The second gate of the transistor Tr1 functions as the wiring BGL. do.

[0115] The layer L4 includes a capacitance element C1, a plug 313, and a wiring LBL. It consists of a conductor 322 , a conductor 323 , and an insulator 305 .

[0116] Next, the transistor M1 will be described in detail with reference to FIG. 14. FIG. 14(A) shows the transistor M1. 14(A) is a cross-sectional view of the channel length direction of the transistor M1, and FIG. 14(B) is a cross-sectional view of the channel length direction of the transistor M1. 1 shows a cross-sectional view in the width direction of the tube.

[0117] The transistor M1 is provided on a substrate 300 and is isolated from other adjacent transistors by an element isolation layer 301. The element isolation layer 301 is made of silicon oxide or silicon oxynitride. Silicon nitride, silicon oxide, silicon nitride, etc. can be used. Oxynitrides are compounds that contain more oxygen than nitrogen, and nitride oxides are compounds that contain more oxygen than nitrogen. It refers to a compound that contains more nitrogen than

[0118] The substrate 300 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor Substrates, compound semiconductor substrates made of silicon germanium, and SOI (Silicon O In addition, as the substrate 300, for example, For example, glass substrates, quartz substrates, plastic substrates, metal substrates, laminated films, fibers Paper or a base film containing such a material may also be used. The conductive elements may be formed and then the semiconductor elements may be transferred to another substrate.

[0119] A flexible substrate may be used as the substrate 300. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to a flexible substrate 300. A peeling layer may be provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil made of woven fibers may be used. The substrate 300 may be stretchable. Also, the substrate 300 may be designed to retain its original shape when the bending or pulling is stopped. Alternatively, the substrate 3 may have a property of not returning to its original shape. The thickness of 00 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is 15 μm or more and 300 μm or less. The weight of the semiconductor device can be reduced. In addition, by making the substrate 300 thinner, it is possible to reduce the weight of the substrate 300 by using a material such as glass. Even when using a material with elasticity, it may be possible for the material to return to its original shape when bending or pulling is stopped. Therefore, if the semiconductor device on the substrate 300 is dropped, It is possible to mitigate the impacts and the like that are applied to the semiconductor device. The substrate 300, which is a flexible substrate, may be made of, for example, metal, alloy, resin, or glass. The substrate 300, which is a flexible substrate, can be made of wire or fiber. The lower the expansion coefficient, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1 × 10 -3 / K or less, 5×10 -5 / K or less, or 1 x10 -5 The resin may be, for example, polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Aramid, acrylic, polytetrafluoroethylene (PTFE), etc. Since the linear expansion coefficient is low, it is suitable for the substrate 300, which is a flexible substrate.

[0120] In this embodiment, an example is shown in which a single crystal silicon wafer is used as the substrate 300.

[0121] The transistor M1 shown in FIGS. 14A and 14B is a channel-type transistor provided in a well 351. A region 352, an impurity region 353, and an impurity region 354 are provided in contact with the impurity regions. The conductive region 355 and the conductive region 356 are formed on the channel forming region 352. A gate insulator 358 and a gate electrode 357 provided on the gate insulator 358 are included. The conductive regions 355 and 356 may be made of metal silicide or the like.

[0122] The transistor M1 has a channel forming region 352 that has a convex shape, and the side and top surfaces of the channel forming region 352 are A gate insulator 358 and a gate electrode 357 are provided (see FIG. 14(B)). A transistor having such a shape is called a FIN transistor. Although the case where a convex portion is formed by processing a part of a conductor substrate has been shown, it is also possible to process an SOI substrate to form a convex shape. Alternatively, a semiconductor layer having the following structure may be formed.

[0123] In this embodiment, as an example, a Si transistor is used as the transistor M1. The transistor M1 is an n-channel transistor or a p-channel transistor. Any transistor may be used, and an appropriate transistor may be used depending on the circuit.

[0124] Note that a planar transistor may be used as the transistor M1. 14(C) and (D) show examples of the above. FIG. 14(C) shows the channel length direction of the transistor M1. 14(D) is a cross-sectional view of the transistor M1 in the channel width direction. do.

[0125] The transistor M1 shown in FIGS. 14C and 14D is a channel-type transistor provided in a well 361. formation region 362, low concentration impurity region 371, low concentration impurity region 372, and high concentration impurity region a region 363 and a high-concentration impurity region 364, and a conductive layer provided in contact with the high-concentration impurity region; A gate insulating layer is formed on the region 365 and the conductive region 366, and the channel forming region 362. a gate electrode 367 provided on the gate insulator 368; The conductive region has a sidewall insulating layer 369 and a sidewall insulating layer 370 provided on the sidewall of the conductive region. The layers 365 and 366 may be made of metal silicide or the like.

[0126] Returning to FIG. 12 again, the insulator 302 functions as an interlayer insulator. When a Si transistor is used for the insulator 302, it is preferable that the insulator 302 contains hydrogen. The hydrogen contained in 302 terminates the dangling bonds of silicon, and the transistor M1 The insulator 302 is preferably made of silicon oxide or silicon oxynitride. It is preferable to use silicon nitride, silicon oxide nitride, silicon nitride, or the like.

[0127] The insulator 303 is provided with a substrate 300 or a transistor M1, etc., from which the transistor Tr1 It is preferable to use a barrier film that prevents diffusion of hydrogen and impurities in the region where the barrier film is to be provided. For example, silicon nitride formed by CVD can be used. When hydrogen diffuses into an oxide semiconductor having a metal oxide layer, the characteristics of the oxide semiconductor may be degraded. Therefore, the diffusion of hydrogen is suppressed between the transistor M1 and the transistor Tr1. It is preferred to use a membrane.

[0128] A film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen. For example, thermal desorption spectroscopy (TDS) For example, the water in the insulator 324 can be analyzed by using a microscope. The amount of desorption of hydrogen atoms was measured by TDS analysis in the range of 50 to 500°C. The calculated amount of desorption is converted into 10×10 per area of the insulator 303. 15 atoms / c m 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0129] The insulators 304, 214, 282 also serve to inhibit copper diffusion or to protect against oxygen and water. It is preferable to use an insulator that has barrier properties against elements. For example, An example of a film that can be used is silicon nitride. Metal oxides may also be used.

[0130] The insulator 216 may be, for example, a silicon oxide film or a silicon oxynitride film. do.

[0131] The insulator 280 and the transistor Tr1 will be described in detail in the third embodiment below.

[0132] The insulator 305 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, aluminum nitride Hafnium, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc. Just use

[0133] The insulator 305 may have a stacked structure of the above insulators. For example, silicon oxynitride Which materials have high dielectric breakdown resistance and which high-k materials, such as aluminum oxide, With this configuration, the capacitance element C1 can ensure a sufficient capacitance, In addition, electrostatic breakdown can be suppressed.

[0134] The conductors, wirings and plugs shown in FIG. 12 are made of copper (Cu), tungsten (W), molybdenum (Mo), and the like. Density (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti) , Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir) , strontium (Sr) low resistance material, its alloy, or its main component It is preferable to use a single layer or a multilayer of a conductor containing a compound having the above properties. It is preferable to use a compatible high melting point material such as tungsten or molybdenum. It is preferably made of a low resistance conductive material such as aluminum or copper.

[0135] In the memory device 100 of FIG. 12, the transistor Tr1 may be formed on the capacitive element C1. The cross-sectional view in this case is shown in Fig. 13. In the cross-sectional view shown in Fig. 13, the layer L3 and the layer L4 are the same as those in Fig. 12. The views are different.

[0136] In FIG. 13, the layer L3 includes a wiring 341 and a capacitance element C1.

[0137] In FIG. 13, the layer L4 includes plugs 331, 332, 333, and 334. , wiring 342, wiring 343, wiring LBL, insulator 214, insulator 216, insulator 280, The insulator 282 includes a transistor Tr1.

[0138] By providing the capacitance element C1 under the transistor Tr1, the capacitance generated when forming the capacitance element C1 is reduced. This can protect the transistor Tr1 from the effects of process damage or hydrogen that may occur.

[0139] In Figures 12 and 13, areas without symbols or hatching patterns are The insulators include aluminum oxide, aluminum nitride oxide, and oxide. magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide, tantalum oxide, etc. Insulators can be used. In addition, polyimide resin, polyamide resin, Organic resins such as acrylic resin, siloxane resin, epoxy resin, and phenol resin can be used. It can also be done as follows.

[0140] (Embodiment 3) In this embodiment, a structure of the OS transistor used in the above embodiment will be described. .

[0141] <Oxide semiconductor> First, an oxide semiconductor that can be used for an OS transistor will be described.

[0142] The oxide semiconductor preferably contains at least indium or zinc. Preferably, the oxide semiconductor contains indium, element M, and zinc. Consider the case with zinc.

[0143] As the element M, for example, gallium (Ga) is preferable. Other elements applicable to the element M include: The elements are aluminum (Al), boron (B), silicon (Si), and titanium (Ti). , Zirconium (Zr), Lanthanum (La), Cerium (Ce), Yttrium (Y), Hafnium (Hf), tantalum (Ta), niobium (Nb), scandium (Sc), etc. Examples include:

[0144] First, with reference to FIGS. 15(A), 15(B), and 15(C), the oxide according to the present invention will be described. A preferred range of the atomic ratio of indium, element M, and zinc contained in the semiconductor will be explained. Note that the atomic ratio of oxygen is not shown in FIG. 15. The atomic ratios of indium, element M, and zinc are [In], [M], and Let it be [Zn].

[0145] In Figures 15(A), 15(B), and 15(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (α is between -1 and 1) The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2 , the line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):3, The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):4, and and the line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 Represents.

[0146] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents the

[0147] The dashed double-dashed line indicates the atomic number of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The ratio (γ is between -1 and 1) represents the line where [In]:[M] shown in FIG. Oxide semiconductors with an atomic ratio of Zn:[Zn]=0:2:1 or close to it are spinel-type. It is easy to form a crystalline structure.

[0148] In some oxide semiconductors, multiple phases coexist (two-phase coexistence, three-phase coexistence, etc.). For example, At atomic ratios close to [In]:[M]:[Zn]=0:2:1, the spin Two phases, a flanking crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of [Zn]=1:0:0, bixbyite-type Two phases, a crystalline structure and a layered crystalline structure, tend to coexist. When different crystal structures are present, grain boundaries are formed between them. This may be the case.

[0149] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor can be improved. This is because the oxide semiconductor containing indium, element M, and zinc can be In the body, the s orbitals of heavy metals mainly contribute to carrier conduction, and the indium content This is because by increasing the height, the area where the s orbitals overlap becomes larger.

[0150] In the region A in FIG. 15A, the carrier mobility of the oxide semiconductor is high, and This represents a region that is likely to have a layered structure with few grain boundaries.

[0151] Region B shown in FIG. 15(B) is [In]:[M]:[Zn]=4:2:3 to 4.1, and The neighboring values are shown as follows. For example, the atomic ratio is [In]:[M]:[Z n]=5:3:4. The oxide semiconductor having the atomic ratio shown in region B is particularly , is an excellent oxide semiconductor with high crystallinity and high carrier mobility.

[0152] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and its In the atomic ratio having a value close to 0 (for example, region C shown in FIG. 15(C)), the insulating property becomes high.

[0153] <Transistor structure 1> 16A to 16C are a top view and a cross-sectional view of the transistor 200a. 16(A) is a top view, and FIG. 16(B) is a view of the cross section of the dashed line X1-X2 shown in FIG. 16(A) and the cross section of FIG. 6(C) is a cross-sectional view corresponding to the dashed line Y1-Y2. In the figure, some elements are omitted for clarity.

[0154] 16B and 16C show a case where a transistor 200a is provided on an insulator 214 and an insulator 216. This shows an example of a case where

[0155] The transistor 200a includes a conductor 205 (conductor 205a) and a and conductor 205b) and conductor 260, and insulator 220 which functions as a gate insulating layer. , the insulator 222, the insulator 224, and the insulator 250, and the oxide semiconductor 230 (oxide semiconductor conductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c) and a source or Conductor 240a functions as one of the drains, and conductive material 240b functions as the other of the source or drain. The conductor 240b functions as a protective layer, and the insulator 241 protects the conductor 260. and an insulator 280 (containing oxygen in excess of the stoichiometric composition).

[0156] In the transistor 200a, the conductor 260 is the top gate and the conductor 205 is the bottom gate. Alternatively, the conductor 260 may be referred to as the first gate, and the conductor 205 may be referred to as the second gate. It is sometimes called a to.

[0157] The oxide semiconductor 230 is made up of an oxide semiconductor 230a and an oxide layer on the oxide semiconductor 230a. The oxide semiconductor 230b is an oxide semiconductor 230c on the oxide semiconductor 230b. When the transistor 200a is turned on, a current flows mainly through the oxide semiconductor 230b. Therefore, the oxide semiconductor 230b functions as a channel formation region. The compound semiconductor 230a and the oxide semiconductor 230c are formed in the vicinity of the interface with the oxide semiconductor 230b. Although current may flow in the mixed region, other regions may act as an insulator.

[0158] The conductor 205 may be made of molybdenum, titanium, tantalum, tungsten, aluminum, copper, or chromium. A metal film containing an element selected from the group consisting of chromium, neodymium, and scandium, or a metal film containing the above elements. metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) Or, indium tin oxide, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide, indium zinc oxide, indium stannate with silicon oxide Conductive materials such as carbides can also be applied.

[0159] For example, titanium nitride is used as the conductor 205a as a conductor having a barrier property against hydrogen. It is preferable to use tungsten or the like as the conductor 205b, and to stack tungsten, which has high conductivity. By using this combination, the oxide semiconductor 230 can be formed while maintaining the conductivity as a wiring. In FIG. 16B, the conductor 205a and Although a two-layer structure of the conductive material 205b and the conductive material 205c is shown, the present invention is not limited to this configuration, and may be a single layer or a three or more layer structure. A laminated structure may also be used.

[0160] The insulators 220 and 224 are made of an oxide film such as a silicon oxide film or a silicon oxynitride film. In particular, the insulator 224 is preferably an insulator containing excess oxygen. It is preferable to use such an insulator containing excess oxygen as the transistor 200a. By providing it in contact with the constituent oxide, oxygen deficiency in the oxide can be compensated for. The insulators 220 and 224 do not necessarily have to be made of the same material. stomach.

[0161] The insulator 222 may be, for example, silicon nitride, silicon oxynitride, aluminum oxide, or halogen oxide. Insulators containing materials such as tantalum oxide, zirconium oxide, and other materials are used in single or multilayer configurations. It is preferable to use

[0162] In addition, by appropriately adjusting the film thickness of the insulators 220, 222, and 224, V th Alternatively, it is possible to provide a transistor with a small leakage current when it is not conducting. The thickness of each of the insulators 220, 222, and 224 can be reduced. Therefore, V th This is preferable because it is easy to control. The thickness of the insulators 222 and 224 is preferably 50 nm or less. 30 nm or less, more preferably 10 nm or less, and even more preferably 5 nm or less. It should be less than m.

[0163] The oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are In- The oxide semiconductor 230 is formed of a metal oxide such as In-Mn-Zn oxide. Ga oxide and In-Zn oxide may also be used.

[0164] The oxide semiconductor 230a and the oxide semiconductor 230c have a conduction band lower than that of the oxide semiconductor 230b. The energy level of the conduction band minimum of the oxide semiconductor 230b is close to the vacuum level. and the energy levels of the oxide semiconductor 230a and the oxide semiconductor 230c at the bottom of the conduction band. The difference between the energy level and the That is, the oxide semiconductor 230a and the oxide semiconductor 230b are preferably 1 eV or less. The difference between the electron affinity of 30c and the electron affinity of the oxide semiconductor 230b is 0.15 eV or more. , or 0.5 eV or more and 2 eV or less, or 1 eV or less is preferable.

[0165] In the oxide semiconductor 230b, the energy gap is preferably 2 eV or more, and more preferably 2.5 e V or more and 3.0 eV or less is more preferable. In 230c, the energy gap is preferably 2 eV or more, more preferably 2.5 eV or more. Preferably, the oxide semiconductor 230 has a conductivity of 2.7 eV or more and 3.5 eV or less. The energy gap of the oxide semiconductor 230a and the oxide semiconductor 230c is For example, the oxide semiconductor 230a and the oxide The energy gap of the semiconductor 230c is the same as that of the oxide semiconductor 230b. Compared to 0.15 eV or more, or 0.5 eV or more, or 1.0 eV or more, and 2 eV It is preferably 1 eV or less, or 1 eV or less.

[0166] In addition, the thicknesses of the oxide semiconductors 230a, 230b, and 230c is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably is 3 nm or more and 60 nm or less.

[0167] By reducing the carrier density in the oxide semiconductor film, the threshold voltage of the transistor can be reduced. This is preferable because the phase shift or the off-state current of the transistor can be reduced.

[0168] Factors that affect the carrier density in oxide semiconductors include oxygen vacancies in the oxide semiconductor ( Vo) or impurities in the oxide semiconductor. When the oxygen vacancy is increased, hydrogen bonds to the oxygen vacancy (this state is also called VoH), and the defect level Alternatively, when the amount of impurities in the oxide semiconductor increases, defects due to the impurities increase. Therefore, by controlling the defect state density in the oxide semiconductor, The carrier density of the compound semiconductor can be controlled.

[0169] A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a small number of carrier generation sources. Therefore, the carrier density can be reduced.

[0170] The oxide semiconductor 230a and the oxide semiconductor 230c are preferably high-purity intrinsic or substantially high-purity oxide. It is preferable to use an oxide semiconductor having intrinsic purity. The carrier density of the oxide semiconductor 230c is 8×10 15 cm -3 Less than 1 x10 11 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 That's all there is to it.

[0171] On the other hand, the improvement of the on-state current of the transistor or the field-effect mobility of the transistor In this case, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly increased. Alternatively, the defect state density of the oxide semiconductor may be increased slightly. It is desirable to make the band gap of the semiconductor smaller. For example, the I D -V G In the range where the on / off ratio of the characteristics can be obtained, the impurity concentration is slightly high or the defect level Oxide semiconductors with slightly higher densities can be considered essentially intrinsic. As a result, the band gap becomes smaller, and as a result, the thermally excited electrons (capacitors) The oxide semiconductor with increased electron affinity can be considered essentially intrinsic. When an oxide semiconductor with high conductivity is used, the threshold voltage of the transistor is lowered. .

[0172] The carrier density of the oxide semiconductor 230b is The carrier density of the oxide semiconductor 230b is preferably higher than that of the oxide semiconductor 230c. 5 cm -3 More than 1×10 18 cm -3 Less than 1 x 10 is preferable. 7 cm -3 More than 1×10 17 cm -3 Less than 1×10 is preferable. 9 cm -3 5x10 or more 16 cm -3 The following is More preferably, 1 × 10 10 cm -3 More than 1×10 16 cm -3 The following is even more preferable: , 1×10 11 cm -3 More than 1×10 15 cm -3 The following is even more preferred:

[0173] The interface between the oxide semiconductor 230a and the oxide semiconductor 230b, or the interface between the oxide semiconductor 230b and the oxide semiconductor 230a To reduce the defect level density of the mixed layer formed at the interface with the oxide semiconductor 230c. is preferred.

[0174] Specifically, the oxide semiconductor 230a and the oxide semiconductor 230b, the oxide semiconductor 230b and the oxide semiconductor 230c are The compound semiconductor 230c has a common element other than oxygen (as a main component), so that the defect level For example, when the oxide semiconductor 230b is an In-G In the case of a-Zn oxide semiconductor, I It is preferable to use n-Ga-Zn oxide semiconductor, Ga-Zn oxide semiconductor, gallium oxide, etc. stomach.

[0175] At this time, the main carrier path is the oxide semiconductor 230b. and the oxide semiconductor 230b, and the oxide semiconductor 230b and the oxide semiconductor 230c. The defect level density at the interface with the silicon can be reduced, which reduces the carrier transport due to interface scattering. The effect on conductivity is small, and a high on-current can be obtained.

[0176] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the V th The oxide semiconductor 230a and the oxide By providing the oxide semiconductor 230c, the trap level is located farther from the oxide semiconductor 230b. By using this configuration, the V th shifts in the positive direction This can prevent the following from happening.

[0177] The oxide semiconductors 230a and 230c are more conductive than the oxide semiconductor 230b. A material with a sufficiently low dielectric constant is used. and the interface between the oxide semiconductor 230b and the oxide semiconductor 230a. The interface between the oxide semiconductor 230a and the oxide semiconductor 230c mainly functions as a channel region. The compound semiconductor 230c has an atomic ratio shown in region C in FIG. 15(C) where the insulating property is high. Note that a region C shown in FIG. 15C is an oxide semiconductor having a structure of [In]:[M]. :[Zn]=0:1:0 or a value close to that.

[0178] In particular, the oxide semiconductor 230b contains an oxide semiconductor having an atomic ratio shown in region A in FIG. 15(A). When a conductor is used, the oxide semiconductor 230a and the oxide semiconductor 230c have a [M] / [ It is preferable to use an oxide semiconductor in which In is 1 or more, preferably 2 or more. [M] / ([Zn] It is preferable to use an oxide semiconductor in which +[In]) is 1 or more.

[0179] The oxide semiconductor 230c may have lower crystallinity than the oxide semiconductor 230b. The oxide semiconductor 230b preferably includes a CAAC-OS, which will be described later. By reducing the crystallinity of the oxide semiconductor 230c, the oxygen permeability of the oxide semiconductor 230c is increased. This allows oxygen to be transferred from the insulator located above the oxide semiconductor 230c to the oxide semiconductor 230b. Here, the oxide semiconductor 230c may be amorphous or -like(amorphous-like oxide semiconductor ) may also be used.

[0180] The oxide semiconductor 230a may include a CAAC-OS. It is preferable that the crystallinity of the oxide semiconductor 230c is higher than that of the oxide semiconductor 230c.

[0181] The insulator 250 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3( Insulators including materials such as BST can be used in single or multilayer configurations. Insulators such as aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, Silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide are added. Alternatively, these insulators may be nitrided. Silicon oxide nitride or silicon nitride may be stacked.

[0182] In addition, the insulator 250, like the insulator 224, contains more oxygen than the stoichiometric composition. It is preferable to use an oxide insulator containing a large amount of oxygen. By providing the oxide semiconductor 230 in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be reduced. It can be reduced.

[0183] The insulator 250 may be aluminum oxide, aluminum oxynitride, hafnium oxide, or oxide. It uses insulating films with barrier properties against oxygen and hydrogen, such as hafnium nitride and silicon nitride. When such a material is used, the oxide semiconductor 230 can be easily formed. It functions as a layer that prevents the release of elements and the intrusion of impurities such as hydrogen from the outside.

[0184] The conductors 240a and 240b may be made of aluminum, titanium, chromium, nickel, copper, yttria, or the like. metals such as aluminum, zirconium, molybdenum, silver, tantalum, or tungsten, or In addition, although the figure shows a single layer structure, it is possible to use an alloy containing this as the main component. A laminated structure of more than one layer may also be used.

[0185] For example, a titanium film and an aluminum film may be stacked. a two-layer structure in which a magnesium film is laminated on a copper-magnesium-aluminum alloy film; a two-layer structure with a copper film laminated on a titanium film; a two-layer structure with a copper film laminated on a tungsten film; A two-layer structure may also be used.

[0186] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A titanium film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed on the aluminum film or a copper film. Three-layer structure: a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the molybdenum film, and then a molybdenum film or There are three-layer structures in which a molybdenum nitride film is formed. A transparent conductive material containing zinc oxide may also be used.

[0187] The conductor 260 having the function of a gate electrode is made of, for example, aluminum, chromium, or copper. , tantalum, titanium, molybdenum, tungsten, or any of the above metals. It can be formed using an alloy containing the above metals as a component, or an alloy combining the above metals. In addition, it is also possible to use one or more metals selected from manganese and zirconium. In addition, semiconductors such as polycrystalline silicon doped with impurity elements such as phosphorus, Silicides such as nickel silicide may also be used.

[0188] For example, a two-layer structure in which a titanium film is laminated on aluminum is preferable. Two-layer structure in which a titanium film is laminated on a titanium nitride film, and two-layer structure in which a tungsten film is laminated on a titanium nitride film. The structure is a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. You may do so.

[0189] In addition, a titanium film is laminated on the titanium film, and an aluminum film is laminated on the titanium film. There are also three-layer structures that form aluminium, titanium, tantalum, tungsten, etc. , molybdenum, chromium, neodymium, and scandium. A combined alloy film or nitride film may also be used.

[0190] The conductor 260 may be made of indium tin oxide or indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal may also be used.

[0191] By using a conductive material with a high work function as the conductor 260, the transistor 200a V th The work function of the conductor 260 can be increased to lower the cutoff current. Preferably, it is 4.8 eV or more, more preferably 5.0 eV or more, and even more preferably 5. Conductivity of 2 eV or more, more preferably 5.4 eV or more, and even more preferably 5.6 eV or more Conductive materials with a large work function include, for example, molybdenum and oxide. Molybdenum, Pt, Pt silicide, Ni silicide, Indium tin oxide, Nitrogen doped Examples include In-Ga-Zn oxide.

[0192] An insulator 241 is provided to cover the conductor 260. The insulator 241 is made of aluminum oxide, Oxides such as aluminum oxide nitride, hafnium oxide, hafnium oxide nitride, and silicon nitride An insulating film that has barrier properties against silicon and hydrogen can be used. When formed, the conductor 260 can be prevented from being oxidized by the heat treatment process. The insulator 241 can be omitted by using a material that is difficult to oxidize for the conductor 260. can.

[0193] An insulator 280 is provided above the transistor 200a. The insulator 280 contains excess oxygen. In particular, it is preferable to provide an interlayer film or the like near the transistor 200a that contains excess oxygen. By providing an insulator, oxygen vacancies in the transistor 200a can be reduced, thereby improving reliability. It can be improved.

[0194] As an insulator having excess oxygen, specifically, an oxide material from which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. The amount of oxygen released in terms of elementary atoms is 1.0 × 10 18 atoms / cm 3 Above, preferably is 3.0 x 10 20 atoms / cm 3 The oxide film has the above TDS content. The surface temperature of the film during deposition is 100°C or higher and 700°C or lower, or 100°C or higher and 50°C or lower. A range of 0°C or less is preferred.

[0195] For example, a material containing silicon oxide or silicon oxynitride is used as such a material. Alternatively, a metal oxide can also be used.

[0196] The insulator 280 covering the transistor 200a is a flat surface that covers the uneven shape underneath. It may also function as a protective film.

[0197] <Transistor structure 2> 17A to 17C are a top view and a cross-sectional view of the transistor 200b. 17(A) is a top view, and FIG. 17(B) is a view of the cross section of the dashed line X1-X2 shown in FIG. 17(A) and the cross section of FIG. 17(C) is a cross-sectional view corresponding to the dashed line Y1-Y2. In the figure, some elements are omitted for clarity.

[0198] The transistor 200b includes an oxide semiconductor 230c, a The transistor 200 differs from the transistor 200a in that an insulator 250 and a conductor 260 are formed.

[0199] The transistor 200b includes the conductors 240a and 240b and the conductor 260. The parasitic capacitance on the conductor 260 is reduced due to the structure that has almost no overlap. That is, a transistor with a high operating frequency can be provided.

[0200] For further details regarding the transistor 200b, please refer to the description of the transistor 200a. That's fine.

[0201] <Transistor structure 3> 18A to 18C are a top view and a cross-sectional view of the transistor 200c. 18(A) is a top view, and FIG. 18(B) is a view of the cross section of the dashed line X1-X2 shown in FIG. 18(A) and the cross section of FIG. 18(C) is a cross-sectional view corresponding to the dashed line Y1-Y2. In the figure, some elements are omitted for clarity.

[0202] In the transistor 200c of FIG. 18, the central portions of the oxide semiconductors 230a and 230b are etched. The transistor 200 differs from the transistor 200a in that it is gated (see FIG. 18B).

[0203] In the transistor 200a, a channel is formed in the oxide semiconductor 230b. The transistor 200c has a channel formed in the oxide semiconductor 230c. The oxide semiconductor 230c has a lower electron mobility and a wider band gap than the oxide semiconductor 230b. The transistor 200c has a smaller on-state current than the transistor 200a, but also a smaller off-state current. The transistor 200c is suitable for transistors that prioritize off-current over on-current. is.

[0204] Transistor 200c can be formed simultaneously with transistor 200a. For example, Transistors Tr1 and Tr2 in Figure 2 require a high on-state current. The transistor 200a is used, and a low off-state current is required, such as the transistor OS1 in FIG. It is preferable to use the transistor 200c as the transistor.

[0205] For further details regarding the transistor 200b, please refer to the description of the transistor 200a. That's fine.

[0206] <Transistor structure 4> 19A to 19C are a top view and a cross-sectional view of the transistor 200d. 19(A) is a top view, and FIG. 19(B) is a view of the cross section of the dashed line X1-X2 shown in FIG. 19(A) and the cross section of FIG. 19(B) is a cross-sectional view corresponding to the dashed line Y1-Y2. In the figure, some elements are omitted for clarity.

[0207] The transistor 200d has a structure in which the central portions of the oxide semiconductors 230a and 230b are etched. The transistor 200 differs from the transistor 200b in that it has a structure similar to that of the transistor 200a (see FIG. 19B).

[0208] In the transistor 200b, a channel is formed in the oxide semiconductor 230b. The transistor 200d has a channel formed in the oxide semiconductor 230c. The oxide semiconductor 230c has a lower electron mobility and a wider band gap than the oxide semiconductor 230b. The transistor 200d has a smaller on-current than the transistor 200b, but also a smaller off-current. The transistor 200d is suitable for transistors that prioritize off-current over on-current. is.

[0209] Transistor 200d can be formed simultaneously with transistor 200b. For example, Transistors Tr1 and Tr2 in Figure 2 require a high on-state current. The transistor 200b is used, and a low off-state current is required, such as the transistor OS1 in Figure 10. It is preferable to use the transistor 200d as the transistor.

[0210] For further details regarding the transistor 200d, please refer to the description of the transistor 200b. That's fine.

[0211] (Fourth embodiment) In this embodiment, a structure of an oxide semiconductor that can be used for the OS transistor will be described. and explain.

[0212] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0213] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0214] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0215] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned oxide semiconductor (CAAC-OS) crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0216] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0217] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0218] That is, the stable oxide semiconductor is completely amorphous. ) and cannot be called an oxide semiconductor. On the other hand, a-li oxide semiconductors cannot be called completely amorphous oxide semiconductors. The ke OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0219] CAAC-OS First, let me explain about CAAC-OS.

[0220] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0221] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. A peak appears at a diffraction angle (2θ) of approximately 31°. Since the crystal orientation is attributed to the (009) plane of the CAAC-OS, the crystal has a c-axis orientation. The c-axis is approximately perpendicular to the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed) or to the upper surface. It can be confirmed that the peak is perpendicular to the 2θ. The peak at 2θ around 36° may also appear. The peak at 2θ around 36° is in the space group Fd This is due to the crystal structure classified as -3m. Therefore, CAAC-OS does not show this peak. It is preferable that there is no

[0222] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). On the other hand, when 2θ is adjusted to 56 for single crystal InGaZnO4, no clear peak appears. When φ is fixed around ° and scanned, a peak is attributed to the crystal plane equivalent to the (110) plane. Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has a It can be seen that the orientation of the b axis is irregular.

[0223] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, the electrons are generated on the (009) plane of the InGaZnO4 crystal. Therefore, electron diffraction also reveals spots due to C. The pellets contained in the AAC-OS have a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the film is formed or the upper surface. On the other hand, for the same sample, the probe diameter is perpendicular to the sample surface. When a 300 nm electron beam is incident on the CAAC, a ring-shaped diffraction pattern is observed. It can be seen that the a-axis and b-axis of the pellets contained in the -OS do not have any orientation.

[0224] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0225] High-resolution TEM images reveal pellets, which are regions where metal atoms are arranged in layers. The size of each pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are also called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC- It reflects the unevenness of the surface on which the OS is formed or the top surface of the CAAC-OS. is parallel to

[0226] It has also been confirmed that the pellets are hexagonal in shape. It is not limited to a regular hexagonal shape, and is often a non-regular hexagonal shape.

[0227] In CAAC-OS, no clear grain boundaries can be identified. , the formation of grain boundaries is suppressed by distorting the lattice arrangement. The OS is characterized by the fact that the arrangement of oxygen atoms in the ab plane direction is not dense, and that metal elements are substituted. This allows for distortion by changing the bond distance between atoms. It is thought that...

[0228] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0229] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects ( It can also be said to be an oxide semiconductor with few oxygen vacancies.

[0230] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0231] nc-OS Next, we will explain nc-OS.

[0232] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0233] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed in the region, a ring A diffraction pattern (nanobeam electron diffraction pattern) of the same sample was observed. When an electron beam with a probe diameter of 1 nm is incident, multiple spots are observed within the ring-shaped area. Therefore, the nc-OS is not able to be fabricated by irradiating it with an electron beam having a probe diameter of 50 nm. However, order was confirmed by irradiating an electron beam with a probe diameter of 1 nm. will be done.

[0234] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, An electron diffraction pattern in which the spots are arranged in a roughly regular hexagonal pattern may be observed. In the range of thickness less than 10 nm, the nc-OS has highly ordered regions, i.e., crystals. It can be seen that the crystals are oriented in various directions, so regular electron diffraction patterns are not observed. There are also areas where no turbulence is observed.

[0235] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be identified. The size is between 1 nm and 10 nm, and especially between 1 nm and 3 nm. In addition, oxide semiconductors with crystal sizes greater than 10 nm and less than 100 nm are often used. Microcrystalline oxide semiconductor In high-resolution TEM images, for example, the nc-OS is The grain boundaries may not be clearly visible. Therefore, in the following, we will refer to the crystalline part of nc-OS as pellets. It may be called a let.

[0236] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0237] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0238] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0239] a-like OS The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0240] The a-like OS is an unstable structure with porosity.

[0241] For example, in the a-like OS, the growth of crystalline portions can be observed due to electron irradiation. On the other hand, the nc-OS and CAAC-OS hardly show any growth of crystals due to electron irradiation. In other words, a-like OS is less likely to cause anxiety than nc-OS and CAAC-OS. It can be seen that it has a stable structure.

[0242] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0243] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0244] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0245] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0246] (Embodiment 5) In this embodiment, a semiconductor device including a memory device will be described.

[0247] For example, the storage device may be incorporated into a processor (also called a "processing unit"). The processor stores data (including instructions) necessary for processing. PU, GPU (Graphics Processing Unit), PLD (Pro grammable Logic Device), DSP(Digital Sign al Processor), MCU (Microcontroller Unit), These include custom LSI and RFIC.

[0248] < <cpu>> 20 is a block diagram showing an example of the configuration of a CPU. U-core 1330, power management unit (PMU) 1331 and peripheral circuits 13 It has 32.

[0249] The CPU core 1330 includes a control unit 1307, a program counter (PC) 1308, and a processor. A pipeline register 1309, a pipeline register 1310, an arithmetic logic unit (ALU) rithmetic logic unit) 1311, and register file 131 2, and a data bus 1333. Data transfer occurs via a data bus 1333 .

[0250] The PMU 1331 includes a power controller 1302 and a power switch 1303. The peripheral circuit 1332 includes a cache memory 1304, a bus interface (BUS I / F) 1305 and Debug I / F 1306. do.

[0251] The storage device of the first embodiment can be applied to the cache memory 1304. This makes it possible to suppress increases in area and power consumption and increase the capacity of the cache memory 1304. In addition, the standby power consumption of the cache memory 1304 can be reduced, resulting in a compact This makes it possible to provide a CPU 1300 with low power consumption.

[0252] The control unit 1307 includes a program counter 1308, a pipeline register 1309, and a program counter 1309a. Pipeline register 1310, ALU 1311, register file 1312, cache memory 1304, bus interface 1305, debug interface 1306, and the operation of the power controller 1302 are controlled in an integrated manner, It has the function of decoding and executing instructions contained in programs such as applications.

[0253] The ALU 1311 has the function of performing various arithmetic operations such as arithmetic operations and logical operations. The flash memory 1304 has a function of temporarily storing frequently used data. The program counter 1308 is a register that stores the address of the next instruction to be executed. Although not shown in FIG. 20, the cache memory 1304 contains A control circuit is provided to control the operation of the flash memory 1304 .

[0254] The pipeline register 1309 has the function of temporarily storing instruction data. The data file 1312 has a plurality of registers including general-purpose registers, and is connected to the main memory. It stores data read from the ALU1311 or data obtained as a result of ALU1311 arithmetic processing. The pipeline register 1310 is used for the arithmetic processing of the ALU 1311. It temporarily stores data to be used or data obtained as a result of ALU1311 calculations. It has the function of storing information.

[0255] The bus interface 1305 is a communication interface between the CPU 1300 and various devices external to the CPU 1300. The debug interface 130 functions as a data path between the device and the 6 is a signal path for inputting instructions for controlling debugging to the CPU 1300; It has the function of

[0256] The power switch 1303 is a power supply that the CPU 1300 has other than the power controller 1302. It has the function of controlling the supply of power supply voltage to various circuits. The power-gated circuit has one power domain. The circuits belonging to the same power domain are connected by the power switch 1303. The power controller 1302 controls the supply of the power supply voltage. By having such a power management system, the CPU1 300 is capable of performing power gating. An example will be given below.

[0257] First, the CPU core 1330 determines the timing to stop the supply of power voltage by the power controller. Then, the CPU core 1330 sends the power Then, the CPU 1300 sends a command to start power gating to the CPU 1302. The various registers and cache memory 1304 included in the memory start to save data. The power supply voltage to the various circuits other than the power controller 1302 of the CPU 1300 is The supply of power is stopped by the power switch 1303. Then, an interrupt signal is sent to the power The power supply voltage to the various circuits in the CPU 1300 is controlled by inputting the power supply voltage to the controller 1302. The power supply starts. A counter is provided in the power controller 1302. The timing at which the supply of power voltage starts is determined using a counter, regardless of whether an interrupt signal is input. Then, various registers start to restore data. In the cache memory 1304, for example, when operating in a write-back mode, the NVM 20 data is loaded into the SMC 10. Then, the instruction is executed in the control unit 1307. will resume.

[0258] < <rfic>> As an example of a processor, we will explain RFIC. RFIC is a processor that is used for RF tags, wireless chips, etc. RFICs are also called RFID chips, wireless ID chips, etc. RFICs have internal memory circuits. The necessary information is stored in the device, and information is exchanged with the outside world using a non-contact means, such as wireless communication. Due to these characteristics, RFIC can read individual information of items, etc. It can be used in an individual authentication system for identifying items.

[0259] 21 is a block diagram showing an example of the configuration of an RFIC. 404, rectifier circuit 1405, constant voltage circuit 1406, demodulation circuit 1407, modulation circuit 1408 , logic circuit 1409, RAM 1410, ROM (read-only memory) 1411, battery These circuits can be omitted as needed. For example, The RFIC 1400 is an active type, but the passive type does not have a battery 1412. Here, the RFIC 1400 may be configured as an antenna 1404. A semiconductor device that does not include an antenna 1404 is called an RFIC 1400. It is also possible.

[0260] The storage device of the first embodiment can be applied to the RAM 1410. Since memory devices have a high affinity with CMOS circuits, the RFIC1400 is manufactured It is possible to incorporate circuits other than the antenna 1404 into one chip without increasing the complexity of the system. The chip is equipped with an antenna 1404 with performance according to the communication band. The transmission method is an electromagnetic coupling method in which a pair of coils are placed opposite each other and communicate through mutual induction. There are various methods, such as the electromagnetic induction method, which uses electromagnetic fields to communicate, and the radio wave method, which uses radio waves to communicate. The RFIC 1400 shown in the embodiment can be used in either system.

[0261] The antenna 1404 transmits a radio signal to an antenna 1421 connected to a communication device 1420. The rectifier circuit 1405 is for transmitting and receiving the antenna 1404. The input AC signal generated by receiving a radio signal is rectified, for example, by half-wave double voltage rectification. The rectified signal is smoothed by the capacitive element installed in the subsequent stage, The rectifier circuit 1405 is a circuit for generating a limiting A limiter circuit is a circuit that limits the amplitude of the input AC signal to the internally generated voltage. When the voltage is high, it controls the power so that it does not exceed a certain level. It is a circuit.

[0262] The constant voltage circuit 1406 generates a stable power supply voltage from the input voltage and supplies it to each circuit. The constant voltage circuit 1406 has a reset signal generating circuit inside. The reset signal generation circuit may utilize the rising edge of the stable power supply voltage to reset the logic circuit. This is a circuit for generating a reset signal for 1409.

[0263] The demodulation circuit 1407 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 1408 is a circuit for modulating the data output from the antenna 1404. This is a circuit for performing modulation according to the data.

[0264] The logic circuit 1409 is a circuit for decoding and processing the demodulated signal. , a circuit that holds input information, row decoder, column decoder, driver, memory area The ROM 1411 stores a unique number (ID) and other information, and This is a circuit for outputting.

[0265] (Sixth embodiment) In this embodiment mode, a semiconductor wafer including the memory device or the semiconductor device described in the above embodiment mode is Examples of wafers, IC chips, and electronic components will be described with reference to FIGS.

[0266] [Semiconductor wafers, chips] FIG. 22(A) shows a top view of the substrate 611 before the dicing process is performed. The plate 611 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 612 are provided on the substrate 611. The semiconductor device or the like described in the above embodiment mode can be provided.

[0267] The plurality of circuit regions 612 are each surrounded by an isolation region 613. A separation line (also called a "dicing line") 614 is set at the overlapping position. By cutting the substrate 611 along the 14, chips 615 including circuit regions 612 are separated from the substrate 6 22(B) shows an enlarged view of the chip 615.

[0268] A conductive layer or a semiconductor layer may be provided in the separation region 613. By providing a conductive layer, ESD that may occur during the dicing process is mitigated, and This prevents a decrease in yield. In addition, the dicing process generally requires cooling the substrate, grinding, and Pure water that has been treated with carbon dioxide gas to reduce its resistivity for the purposes of removing dust and preventing static electricity. By providing a conductive layer or a semiconductor layer in the separation region 613, The amount of pure water used can be reduced, thereby reducing the production cost of semiconductor devices. Furthermore, the productivity of semiconductor devices can be improved.

[0269] The semiconductor layer provided in the separation region 613 has a band gap of 2.5 eV or more and 4.2 eV or less. It is preferable to use a material with a specific energy of 2.7 eV or more and 3.5 eV or less. Such materials are more resistant to ESD because they allow the accumulated charge to slowly discharge. This suppresses the sudden movement of charges due to static electricity, making it less likely that electrostatic breakdown will occur.

[0270] [Electronic Components] An example of applying the chip 615 to an electronic component will be described with reference to FIG. The product is also called a semiconductor package or IC package. There are multiple standards and names depending on the direction and terminal shape.

[0271] The electronic component is a semiconductor device according to the above embodiment that is used in an assembly process (post-process). The device is completed by combining components other than the semiconductor device.

[0272] The post-process will be explained using the flowchart shown in Figure 23(A). After the element substrate having the semiconductor device shown in the above embodiment is completed, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step S1). By thinning the element substrate through grinding, warping of the element substrate can be reduced, and electronic components can be It is possible to reduce the size of the device.

[0273] Next, a "dicing step" is carried out to separate the element substrate into a plurality of chips (step S2). Then, the separated chips are individually picked up and bonded onto the lead frame. The die bonding process is then carried out (step S3). The joining to the frame is done by resin joining, tape joining, etc., depending on the product. In addition, instead of a lead frame, the chip is bonded to an interposer substrate. You may do so.

[0274] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. The wire bonding process is then carried out to connect the wires to the substrate (step S4). Silver wire or gold wire can be used. Wire bonding is also called ball bonding. Alternatively, wedge bonding can be used.

[0275] The wire-bonded chip is sealed with epoxy resin in the "sealing process (module)". The electronic components are then sealed in a resin (step S5). The circuitry built into the chip and the wires connecting the chip and the leads are mechanically It can protect from external forces and reduce deterioration of characteristics (reduced reliability) due to moisture and dust. It is possible.

[0276] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step The plating process prevents the leads from rusting and prevents soldering when later attached to the printed circuit board. Next, the leads are cut and shaped. Then, the "process" is carried out (step S7).

[0277] Next, a "marking process" is carried out, in which printing (marking) is applied to the surface of the package. (Step S8) Then, the "inspection process" ( After step S9), the electronic component is completed.

[0278] A perspective view of the completed electronic component is shown in FIG. 23(B). As an example of a product, a perspective view of a QFP (Quad Flat Package) is shown below. The electronic component 650 shown in FIG. 23(B) includes leads 655 and a semiconductor device 653. The semiconductor device 653 may be the memory device or semiconductor device shown in the above embodiment modes. Placement etc. can be used.

[0279] The electronic component 650 shown in FIG. 23(B) is provided on, for example, a printed circuit board 652. A plurality of such electronic components 650 are combined and each is electrically connected on a printed circuit board 652. By connecting the components together, a substrate 654 is completed. Used in electronic devices, etc.

[0280] (Embodiment 7) The memory device or the semiconductor device described in the above embodiment is used in an electronic device having a built-in battery. It is preferable that the storage device or the like described in the above embodiment is used in an electronic device having a built-in battery. By using the semiconductor device, the power consumption of the electronic device can be reduced and the battery power can be saved. A specific example is shown in Figure 24.

[0281] FIG. 24(A) shows a wristwatch-type terminal 700. The wristwatch-type terminal 700 includes a housing 701, a crown, a The housing 701 includes a lens 702, a display unit 703, a belt 704, a detection unit 705, and the like. The display unit 703 has a battery, a memory device, or a semiconductor device. The user can input information by using a finger that touches the touch panel as a pointer. can.

[0282] The detection unit 705 has a function of detecting the surrounding conditions and acquiring information. For example, Acceleration sensor, direction sensor, pressure sensor, temperature sensor, humidity sensor, illuminance sensor or G Detects PS (Global Positioning System) signal receiving circuits, etc. It can be used in part 705.

[0283] For example, the ambient brightness detected by the illuminance sensor of the detection unit 705 is input to the calculation unit inside the housing 701. However, when it is determined that the illuminance is sufficiently bright compared with a predetermined illuminance, the luminance of the display unit 703 is reduced. Alternatively, if it is determined that the light is dim, the luminance of the display unit 703 is increased. Reduced electronics can be provided.

[0284] FIG. 24B shows a mobile phone 710. The mobile phone 710 includes a housing 711, a display unit 7 16, operation buttons 714, external connection port 713, speaker 717, microphone 712, etc. The housing 711 has a battery, a memory device, or a semiconductor device therein. 710 allows information to be input by touching the display unit 716 with a finger or the like. Any operation such as making a call or entering text can be performed by touching the display unit 716 with a finger or the like. Also, by operating the operation button 714, the power can be turned on, It is possible to switch the OFF operation and the type of image displayed on the display unit 716. For example, You can switch from the email creation screen to the main menu screen.

[0285] FIG. 24C shows a notebook personal computer 720, which includes a housing 721, a display unit 72 2, a keyboard 723, a pointing device 724, etc. The housing 711 has It has a battery, a memory device or a semiconductor device.

[0286] FIG. 24(D) shows a goggle-type display 730. The goggle-type display 730 is , a mounting portion 731, a housing 732, a cable 735, a battery 736, and a display portion 737. The battery 736 is housed in the mounting portion 731. The display portion 737 is provided in the housing 732. The housing 732 houses various electronic components such as a semiconductor device, a wireless communication device, and a memory device. A display unit 737 and a display unit 738 are connected to a battery 736 via a cable 735. Power is supplied to the electronic components. The display unit 737 displays various images, such as images transmitted wirelessly. The information is displayed.

[0287] The goggle-type display 730 may have a camera in the housing 732. By detecting and knowing the movements of the eyeballs and eyelids, the user can operate the goggle-type display 730. The goggle-type display 730 can also be equipped with a temperature sensor in the mounting section 731. Various sensors such as a pressure sensor, an acceleration sensor, a biosensor, etc. may be provided. The display 730 acquires biometric information of the user by a biometric sensor, and displays the biometric information on the housing 73 2. The goggle-type display 730 receives the image data by wireless signal. The acquired biometric information may be transmitted to another information terminal.

[0288] 24(E) shows a video camera 740. The video camera 740 is made up of a first housing 741, a second housing 742, a 2. The device has a housing 742, a display unit 743, operation keys 744, a lens 745, a connection unit 746, etc. The operation keys 744 and the lens 745 are provided on the first housing 741, and the display unit 743 The first housing 741 is provided with a battery, a storage device, and The battery may be provided outside the first housing 741. The housing 741 and the second housing 742 are connected by a connection part 746. The angle between the display unit 743 and the second housing 742 can be changed by the connector 746. The image at the first housing 741 is projected in accordance with the angle between the first housing 741 and the second housing 742 at the connection portion 746. It may be configured to switch between them.

[0289] FIG. 24(F) shows an automobile 750. The automobile 750 comprises a body 751, wheels 752, a dash The vehicle body 751 has a battery, a storage device, and a has a semiconductor device.

[0290] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the constituent elements. Therefore, it does not limit the number of components. The order of the components is not limited. In this case, a component referred to as "first" may be used in other embodiments or in the claims. In addition, for example, in the implementation of this specification, The elements referred to as "first" in one embodiment may be used in other embodiments or in the claims. It may be omitted within the scope of the request.

[0291] In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode or the first terminal), and the source The other of the source and drain is called the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the operating conditions, etc. Regarding the names of the source and drain of a transistor, In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. It can be replaced.

[0292] In this specification, the terms "electrode" and "wiring" are used to define these components functionally. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" are used to refer to a plurality of "electrodes" and "wirings." This also includes cases where they are formed integrally.

[0293] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. For example, the reference potential is the ground potential (earth potential). If we use the term "ground potential" (potential), we can translate voltage into potential. Note that the potential is relative, and the distribution may differ depending on the reference potential. The potential applied to the wires may be changed.

[0294] In this specification, the terms "film" and "layer" may be used in some cases or depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive layer" It may be possible to change the term to "conductive film." Alternatively, for example, In some cases, it may be possible to change the term to "insulating layer."

[0295] In this specification, a switch refers to a device that is in a conducting state (ON) or a non-conducting state (OFF). It is a device that has the function of controlling whether or not current flows. refers to a device that has the function of selecting and switching the path through which current flows. The switch may be a static or mechanical switch. Anything that can control the above is acceptable, and is not limited to a specific one.

[0296] An example of an electrical switch is a transistor (e.g., a bipolar transistor, M OS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) diode MIS (Metal Insulator Semiconductor) diodes diode-connected transistors), or logic circuits that combine these. be.

[0297] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically short-circuited. The "non-conducting state" of a transistor means that the source and drain of the transistor are electrically isolated. In addition, when a transistor is operated simply as a switch, In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0298] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode Thus, the device operates by controlling conduction and non-conduction.

[0299] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y may be electrically connected or may be directly connected. , which are deemed to be disclosed herein.

[0300] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0301] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When X and Y are connected without an intermediate element (electrode, display element, light-emitting element, load, etc.) is.

[0302] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. The switch can be in a conducting state (ON state) or a non-conducting state (OFF state). ) and has the function of controlling whether or not current flows. It has the function of selecting and switching the path through which current flows. X and Y are electrically connected. When X and Y are connected to each other, this includes the case where X and Y are directly connected. [Example]

[0303] In this embodiment, the storage device 100 shown in the first embodiment and an MCU (microcontroller) having a CPU core are used. We have developed a prototype chip (microcontroller unit) and confirmed that the prototype chip operates with low power consumption. I confirmed that.

[0304] In this embodiment, the storage device 100 is a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). It is called Microconductor Random Access Memory.

[0305] Figure 25 shows the block diagram of the prototype chip. The chip is an 8KB (byte) DOSRA M, CPU core, PMU (power management unit), AHB-Lite Bus The DOSRAM and the flip-flops in the CPU core are made of Si transistors, It consists of an OS transistor formed on a Si transistor. A transistor having the same structure as the transistor 200a shown in FIG. The power supply to the AM and CPU cores is controlled by the PMU. The data is read and written via a 32-bit bus.

[0306] Figure 26 shows the block diagram of 8KB DOSRAM. 8KB DOSRAM consists of four 2K Each subarray consists of 16 1Kb (bit) local arrays. The 1Kb local array consists of a cell array with 8 word lines and 256 bit lines. The structure in which the ray is stacked on 128 sense amplifiers (SA) and multiplexers (MUX) This stacked structure reduces the area that is active during memory access. It is possible.

[0307] The 1 Kb local array of FIG. 26 was tested using the folded memory cell 130 shown in FIG. The sense amplifier in Figure 26 corresponds to SMC10 in Figure 8. The area of the cell (NMC in Figure 8) is 2.9 μm 2 The capacitance was set to 3.5 fF.

[0308] 27(A) and (B) are schematic diagrams showing the structure of DOSRAM. This is the case when the array, sense amplifiers, and multiplexers are formed on the same layer. 7(A) needs to drive 256 long bit lines. The stacked structure allows for a bipolar cell array to be formed on the chip and multiplexer. The bit lines are 256 local bit lines (short bit lines) and 64 global bit lines. (long bit lines). A multiplexer divides the 64 of the bit lines are connected to the global bit lines. Therefore, the number of long bit lines can be reduced, and the bit line capacitance can be reduced. Furthermore, the storage capacitance can be reduced, and the load when driving the DOSRAM is reduced.

[0309] Figure 28 shows the simulation results of the active energy of a 2KB DODRAM. In FIG. 28, (a) shows a cell array, a sense amplifier, and a multiplexer. 27(A) shows the case where the sense amplifier and This shows the case where a cell array is stacked on a multiplexer (as shown in FIG. 27(B)). From the results of Figure 28, it can be seen that the laminated structure (b) exhibits a higher dynamic range than the non-laminated structure (a). It was confirmed that the production energy was reduced by more than 70%.

[0310] Figure 29 shows a part of the layout of the prototype DOSRAM. 10A and 10B show the amplifier, multiplexer, cell array, and global bit line, respectively.

[0311] FIG. 30 shows a flip-flop (hereinafter referred to as The circuit diagram of the OS-FF is shown. Three OS transistors and one capacitor are used for the scan flip-flop. The backup signal BK and recovery signal BK are sent from the PMU. The RE provides backup and recovery for the OS-FF.

[0312] An optical microscope photograph of the prototype chip is shown in Figure 31. The power supply voltage for the logic circuit was 1.1 V. The power supply voltage for the circuits using OS transistors and the I / O was set to 3.3V. The technology node for the OS transistor is 60nm. be.

[0313] Figure 32 shows the retention characteristics of the prototype DOSRAM at 85°C. It was confirmed that 99.95% of the data was retained. This means that data can be retained for a long time without refreshing the data. SRAM has been shown to be capable of long-term power gating.

[0314] Figure 33 shows the backup-recovery waveform of the prototype chip. In F, the backup time is 1 clock (33 ns) and the recovery time is 3 clocks ( 99ns). In addition, DOSRAM can retain data without power supply, No backup / recovery operation is required; simply turning the power on and off is sufficient.

[0315] Table 1 shows a summary of the operating modes and power consumption of the chip. Active power is the power consumption when DOSRAM is running for 9 clocks (7 reads and 2 writes). As shown in Table 1, both the DOSRAM and the CPU core It was confirmed that power gating reduces standby power consumption.

[0316] [Table 1]

[0317] Table 2 shows a comparison of the prototype chip in this example with other low-power MCUs that have been reported so far. In Table 2, A is the MCU described in Non-Patent Document 2, and B is the MCU described in Non-Patent Document 3. , C represents the MCU described in Non-Patent Document 4, and D represents the data of the prototype chip in this experiment. The prototype chips are: It was confirmed that the prototype chip is superior to other chips. It was confirmed that the lowest power consumption could be achieved regardless of the standby ratio.

[0318] [Table 2] [Explanation of symbols]

[0319] ADDR signal, BGL wiring, BL wiring, BLB wiring, BW signal, C 0 capacitance element, C1 capacitance element, C2 capacitance element, C21 capacitance element, C23 Capacitor element, C22 capacitor element, C24 capacitor element, CE signal, CLK signal , DB1 data, DB2 data, GW signal, L1 layer, L2 layer, L3 Layer, L4 layer, LBL wiring, LBLB wiring, M1 transistor, M2 1 transistor, M24 transistor, M31 transistor, M34 transistor Transistor, NWL wiring, NWL_0 wiring, NWL_1 wiring, OS1 wiring Transistor, PCL wiring, PON1 signal, PON2 signal, RDA signal, VCS wiring, VDDM wiring, VHH wiring, VLL wiring, VPC wiring , WDA signal, WL wiring, t1 time, t2 time, t3 time, t4 Time, t5 time, t6 time, t7 time, t8 time, Tac1 time transistor, Tac2 transistor, Tdr1 transistor, Teq1 transistor transistor, Tld1 transistor, Tld2 transistor, Tpc1 transistor transistor, Tpc2 transistor, Tr1 transistor, Tr2 transistor, Tr3 transistor, Tr4 transistor, 10 SMC, 20 NVM, 21 NVM, 30 LPC, 100 storage device, 110 memory cell array, 110A memory cell array, 110B memory cell array, 111 peripheral circuit, 112 control circuit, 115 peripheral circuit, 121 row decoder, 122 Column decoder, 123 row driver, 124 column driver, 125 input circuit, 12 6 output circuit, 127 voltage generating circuit, 127a voltage generating circuit, 127b voltage voltage generating circuit, 128 voltage holding circuit, 130 memory cell, 141 PSW, 14 2 PSW, 200a transistor, 200b transistor, 200c transistor Transistor, 200d Transistor, 205 Conductor, 205a Conductor, 20 5b Conductors, 214 Insulators, 216 Insulators, 220 Insulators, 222 Insulators, 224 Insulators, 230 Oxide semiconductors, 230a Oxide semiconductors, 23 0b Oxide semiconductor, 230c Oxide semiconductor, 240a Conductor, 240b Conductors, 241 Insulators, 250 Insulators, 260 Conductors, 280 Insulators, 282 insulator, 300 substrate, 301 element isolation layer, 302 insulator, 303 Insulator, 304 Insulator, 305 Insulator, 310 Plug, 311 Plug Plug, 312 Plug, 313 Plug, 320 Wiring, 321 Wiring, 322 Conductors, 323 Conductors, 324 Insulators, 331 Plugs, 332 Plugs , 333 plug, 334 plug, 341 wiring, 342 wiring, 343 Wiring, 351 well, 352 channel formation region, 353 impurity region, 354 Impurity region, 355 conductive region, 356 conductive region, 357 gate electrode , 358 Gate insulator, 361 Well, 362 Channel forming region, 363 High concentration impurity region, 364 High concentration impurity region, 365 Conductive region, 366 conductive region, 367 gate electrode, 368 gate insulator, 369 sidewall insulating layer; 370 sidewall insulating layer, 371 low-concentration impurity region, 372 low-concentration impurity region, 6 11 board, 612 circuit area, 613 separation area, 614 separation line, 615 Chips, 650 Electronic components, 652 Printed circuit boards, 653 Semiconductor devices, 65 4. Board, 655. Lead, 700. Wristwatch-type terminal, 701. Housing, 702. Crown, 703 Display, 704 Belt, 705 Detection, 710 Mobile phone Handset, 711 housing, 712 microphone, 713 external connection port, 714 operation Buttons, 716 Display, 717 Speaker, 720 Notebook personal computer Computer, 721 housing, 722 display unit, 723 keyboard, 724 point goggle-type display, 731, and attachment portion, 732 Housing, 735 Cable, 736 Battery, 737 Display, 740 Video Camera, 741 housing, 742 housing, 743 display unit, 744 operation keys, 7 45 Lenses, 746 Connections, 750 Automobiles, 751 Car bodies, 752 Cars Wheel, 753 Dashboard, 754 Light, 1300 CPU, 1302 Power controller, 1303 Power switch, 1304 Cache memory, 1 305 Bus Interface, 1306 Debug Interface, 1307 Control unit, 1308 program counter, 1309 pipeline register, 1 310 Pipeline register, 1311 ALU, 1312 Register file ,1330 CPU core, 1331 PMU, 1332 Peripheral circuit, 1333 Data bus, 1400 RFIC, 1404 antenna, 1405 rectifier circuit, 1 406 Constant voltage circuit, 1407 Demodulation circuit, 1408 Modulation circuit, 1409 Theory logic circuit, 1410 RAM, 1411 ROM, 1412 battery, 1420 Communication equipment, 1421 antenna, 1422 radio signal< / rfic> < / cpu>

Claims

【Claim 1】 A plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair having a first bit line and a second bit line, a local bit line pair having a first local bit line and a second local bit line, a first transistor, a second transistor, and the first transistor has a function of controlling a conduction state between the first bit line and the first local bit line, the second transistor has a function of controlling a conduction state between the second bit line and the second local bit line, each of the plurality of memory cells has a third transistor, a fourth transistor, a first insulating layer, a second insulating layer, a first capacitor element, and a second capacitor element, the third transistor has a first oxide semiconductor layer having a region located above the first insulating layer, a first conductor having a region located above the first oxide semiconductor layer, a second conductor having a region located above the first oxide semiconductor layer, and a third conductor overlapping with a channel region of the third transistor included in the first oxide semiconductor layer, the fourth transistor has a second oxide semiconductor layer having a region located above the first insulating layer, a fourth conductor having a region located above the second oxide semiconductor layer, a fifth conductor having a region located above the second oxide semiconductor layer, and a sixth conductor overlapping with a channel region of the fourth transistor included in the second oxide semiconductor layer, a third oxide semiconductor layer has a region in contact with an upper surface of the first conductor, a region in contact with an upper surface of the second conductor, a region in contact with an upper surface of the fourth conductor, a region in contact with an upper surface of the fifth conductor, a region in contact with a side surface of the first oxide semiconductor layer, a region in contact with a side surface of the second oxide semiconductor layer, and a region in contact with a side surface of the first insulating layer, the second insulating layer has a region in contact with an upper surface of the third oxide semiconductor layer, a region facing a side surface of the first oxide semiconductor layer via the third oxide semiconductor layer, and a region facing a side surface of the second oxide semiconductor layer via the third oxide semiconductor layer, the third transistor has a function of controlling a conduction state between the first local bit line and the first capacitor element, the fourth transistor has a function of controlling a conduction state between the second local bit line and the second capacitor element, The precharge circuit has a function of supplying a precharge voltage to the local bit line pair, The latch circuit is electrically connected to the local bit line pair, A memory device in which when the first transistor, the second transistor, the third transistor, and the fourth transistor are non-conductive, the precharge voltage and one of a low power supply voltage or a high power supply voltage are supplied to the latch circuit.

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