Semiconductor device

Abstract

To reduce variation in electric characteristics by using an oxide semiconductor film that thoroughly eliminates hydrogen for an inverted staggered thin film transistor because, in an active matrix display device, electric characteristics of a thin film transistor which constitutes a circuit are important and the electric characteristics influence performance of the display device.SOLUTION: In a semiconductor device, continuous deposition of three layers of a gate insulation film, an oxide semiconductor layer and a channel protective film is performed by sputtering without being exposed to atmospheric air. Deposition of the oxide semiconductor layer is performed in an atmosphere where oxygen is contained at a flow ratio of not less than 50% and not more than 100%. An upper layer and a lower layer of a channel formation region of the oxide semiconductor layer are silicon oxynitride films with a nitrogen content of not less than 3 atom% and not more than 30 atom%.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) using an oxide semiconductor film in a channel formation region, and a method for manufacturing the same. For example, it relates to an electronic device incorporating, as components, an electro-optical device typified by a liquid crystal display panel and a light-emitting display device having an organic light-emitting element. Note that, in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

[0002]

Background Art

[0003] Metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

[0004] Some metal oxides exhibit semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors having such metal oxides exhibiting semiconductor characteristics in a channel formation region are already known (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] By the way, metal oxides are known not only as single-component oxides but also as multi-component oxides. For example, InGaO (ZnO) 3 (m: natural number) is known as a multi-component oxide semiconductor containing In, Ga, and Zn (Non-Patent Documents 2 to 4). m

[0006] ​​​​​​​​​​​And it has been confirmed that an oxide semiconductor composed of an In-Ga-Zn-based oxide as described above can be applied as a channel layer of a thin film transistor (Patent Document 5, Non-Patent Documents 5 and 6).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0009] A thin-film transistor having a channel formation region provided with an oxide semiconductor uses amorphous silicon A higher field-effect mobility than that of the thin-film transistor used is obtained.

[0010] Using such an oxide semiconductor, thin-film transistors are formed on a glass substrate, a plastic substrate, etc., and applications to display devices such as liquid crystal displays, electroluminescence displays, or electronic paper are expected.

[0011] In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin-film transistor, the threshold voltage (Vth) is important. Of course, it is better to have a higher field-effect mobility, but even if the field-effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin-film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as a TFT cannot be performed in a state where the driving voltage is low, and there is a risk of becoming a load. Also, if the threshold voltage value is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0V, which is so-called normally on.

[0012] In the case of an n-channel type thin-film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin-film transistor used in a circuit.

[0013] The gate voltage of a thin film transistor using an oxide semiconductor film is set to a positive threshold as close as possible to 0V. One object of the present invention is to provide a structure in which a channel is formed at a low voltage.

[0014] In addition, it is also possible to reduce variations in electrical characteristics of thin film transistors using an oxide semiconductor film. In particular, there is a large variation between individual elements in a liquid crystal display device. In this case, there is a risk of display unevenness occurring due to variations in the TFT characteristics.

[0015] In addition, in a display device having a light-emitting element, the pixel electrodes are arranged so that a constant current flows through them. The on-chip TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) Current (I on If the variation in the brightness of the display screen is large, the brightness of the display screen may vary. There is a problem.

[0016] An object of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor.

[0017] One embodiment of the invention disclosed in this specification achieves at least one of the above objects. [Means for solving the problem]

[0018] In order to improve the characteristics of the oxide semiconductor layer and reduce the variation in the characteristics, It is important to reduce the hydrogen concentration in the layer.

[0019] Therefore, by using oxide semiconductors with thoroughly reduced hydrogen content, This improves the electrical properties of the transistor and also reduces the variation in properties, resulting in a highly reliable thin film transistor. To realize a transistor.

[0020] The characteristics of a thin film transistor having a channel formation region provided in an oxide semiconductor are determined by the interfaces, that is, the interface between the oxide semiconductor layer and the gate insulating film, the interface between the oxide semiconductor layer and the protective insulating film , or the interface between the oxide semiconductor layer and the electrode. However, the characteristics of the oxide semiconductor layer itself also have a significant influence.

[0021] To form these interfaces in a clean state, the gate insulating film, the oxide semiconductor layer, and the channel protection film are continuously formed without being exposed to the atmosphere. Preferably, by continuously forming these three layers under reduced pressure, an oxide semiconductor layer with good interfaces can be realized, and a thin film transistor with a low leakage current when the TFT is off and a high current driving ability can be realized. In particular, by forming the oxide semiconductor layer by sputtering in an atmosphere containing oxygen at a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, hydrogen incorporation into the oxide semiconductor layer can be prevented. In addition, as the oxide semiconductor film, one or more of impurity elements such as Group 1 elements (e.g., lithium (Li), sodium (Na ), potassium (K), rubidium (Rb), cesium (Cs)), Group 13 elements (e.g., boron (B), gallium (Ga), indium (In), thallium (Tl)), Group 14

[0022] elements (e.g., carbon (C), silicon (Si), germanium (Ge), tin (Sn), lead (Pb)), Group 15 elements (e.g., nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi)) or Group 17 elements (e.g., fluorine (F), chlorine (Cl ), bromine (Br), iodine (I)) are added, and the amorphous, polycrystalline, or amorphous and polycrystalline states of zinc oxide (ZnO) are used. An oxide semiconductor in a microcrystalline state (also called microcrystal) with a mixed crystal state can be used. Alternatively, an amorphous state of zinc oxide without any impurity element added , a polycrystalline state, or an oxide semiconductor in a microcrystalline state in which an amorphous state and a polycrystalline state are mixed can be used .

[0023] As a specific example, magnesium zinc oxide (Mg x Zn (1-x) O), cadmium zinc oxide (Cd Zn x Zn (1-x) O), an oxide semiconductor such as cadmium oxide (CdO), or an oxide semiconductor represented by InGaO (ZnO) 3 (ZnO) 5 -based In-Ga-Zn-O oxide semiconductor (a-IGZO), an In-Sn-Zn-O-based oxide semiconductor, a Ga-Sn-Zn- O-based oxide semiconductor, an In-Zn-O-based oxide semiconductor, an Sn-Zn-O-based oxide semiconductor , an In-Sn-O-based oxide semiconductor, or a Ga-Zn-O-based oxide semiconductor can be used. Among them, the In-Ga-Zn-O-based oxide semiconductor has a wide energy gap (Eg), so even if two gate electrodes are provided above and below the oxide semiconductor film, an increase in the off-current can be suppressed, which is preferable. Moreover, as the oxide semiconductor film, an oxide semiconductor film containing silicon oxide obtained by sputtering using an oxide semiconductor target containing SiOx may be used. Typically, SiO is contained in an amount of 0.1% by weight or more and 20% by weight or less, preferably 1% by weight or more and 6% by weight or less. A film is formed using an oxide semiconductor target, and SiOx (X >

[0024] inhibiting crystallization in the oxide semiconductor film can also be used. Typically, an oxide semiconductor film containing silicon oxide obtained by sputtering using an oxide semiconductor target containing SiOx is used. Specifically, SiO 2 is contained in an amount of 0.1% by weight or more and 20% by weight or less, preferably 1% by weight or more and 6% by weight or less. A film is formed using an oxide semiconductor target, and SiOx (X > inhibiting crystallization in the oxide semiconductor film By including (0), a thin-film transistor can be realized in which a channel is formed at a positive threshold voltage at which the gate voltage of the thin-film transistor can be as close as possible to 0V. The thin-film transistor can be realized with a channel formed at a threshold voltage close to 0V so that the gate voltage of the thin-film transistor is as close to 0V as possible.

[0025] The oxide semiconductor layer can be formed using a vapor phase method such as pulsed laser deposition (PLD method) and electron beam evaporation method. However, from the perspective of hydrogen reduction, sputtering performed in an atmosphere of only oxygen is suitable. Generally, in the sputtering method, it is often performed in an atmosphere containing a noble gas such as Ar or Kr. However, since these noble gas elements have a larger mass compared to oxygen, there is a risk of promoting the desorption of hydrogen-containing gases such as moisture and hydrocarbons adhering to the inner wall of the film formation chamber and the jig during sputtering. By making the atmosphere during sputtering only oxygen, it is possible to prevent the desorption of the gas adhering to the inner wall of the film formation chamber and the jig. However, in order to increase the film formation rate, oxygen and a noble gas may be mixed and used within a range that does not affect the desorption of the gas from the inner wall of the film formation chamber, etc. Specifically, it may be performed in an atmosphere where oxygen is 50% or more and 100% or less, preferably 70% or more and 100% or less, by flow rate ratio. It may be performed in an atmosphere where oxygen is 50% or more and 100% or less, preferably 70% or more and 100% or less, by flow rate ratio.

[0026] By making the atmosphere during sputtering only oxygen, it is possible to prevent the desorption of the gas adhering to the inner wall of the film formation chamber and the jig. However, in order to increase the film formation rate, oxygen and a noble gas may be mixed and used within a range that does not affect the desorption of the gas from the inner wall of the film formation chamber, etc. Specifically, it may be performed in an atmosphere where oxygen is 50% or more and 100% or less, preferably 70% or more and 100% or less, by flow rate ratio. One aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, and form a first insulating film on the gate electrode. An oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen at a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, is formed on the first insulating film. A second insulating film is laminated on the oxide semiconductor layer without exposing it to the atmosphere, and the second insulating film is selectively etched to form a protective film at a position overlapping the gate electrode.

[0027] One aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, and form a first insulating film on the gate electrode. An oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen at a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, is formed on the first insulating film. A second insulating film is laminated on the oxide semiconductor layer without exposing it to the atmosphere, and the second insulating film is selectively etched to form a protective film at a position overlapping the gate electrode. One aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, and form a first insulating film on the gate electrode. An oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen at a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, is formed on the first insulating film. A conductive film is formed on a layer and a protective film, and the conductive film and the oxide semiconductor layer are selectively etched. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device.

[0028] In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. Form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. Selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device. In addition, one aspect of the invention disclosed in this specification is to form a gate electrode on a substrate having an insulating surface, form a first insulating film on the gate electrode, form a conductive film on the first insulating film, selectively etch the conductive film to form a source electrode or a drain electrode, and stack, without exposing to the atmosphere, a second insulating film and an oxide semiconductor layer formed by sputtering in an atmosphere containing oxygen in a flow rate ratio of 50% or more and 100% or less, preferably 70% or more and 100% or less, on the first insulating film and the source electrode or the drain electrode, and selectively etch the second insulating film and the oxide semiconductor layer to form a protective film and an island-shaped semiconductor layer, and then form a third insulating film covering the protective film and the island-shaped semiconductor layer. This is a method for manufacturing a semiconductor device.

[0029] The present invention solves at least one of the above problems.

[0030] In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases. In the above manufacturing process, it is also one of the features to use a silicon oxynitride film for the first insulating film and the second insulating film. By forming a structure in which the oxide semiconductor layer is sandwiched between silicon oxynitride films, it is possible to prevent the intrusion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer. The silicon oxynitride film can be formed, for example, by a sputtering method using silicon or silicon oxide, etc. as a sputtering target in an atmosphere containing oxygen and nitrogen, or by a so-called CVD method such as high-density plasma CVD. When forming the film by the CVD method, for example, silane, nitrous oxide, and nitrogen can be appropriately mixed and used as reaction gases.

[0031] The sputtering method includes the RF sputtering method using a high-frequency power supply as the sputtering power supply and the DC sputtering method. There is also a pulsed DC sputtering method in which bias is applied pulsedly. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film .

[0032] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can laminate and deposit different material films in the same chamber, or can also discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0033] There is also a sputtering apparatus using the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and a sputtering apparatus using the ECR sputtering method that uses plasma generated using microwaves without using glow discharge.

[0034] An insulating film such as a silicon oxide film or a silicon nitride film may be used for the first insulating film or the second insulating film, but by using a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less, invasion or diffusion of hydrogen, moisture, etc. into the oxide semiconductor layer can be prevented. The formation of the insulating film is preferably performed under conditions that do not cause hysteresis or charge-up in the thin-film transistor.

[0035] In the formation of an oxide semiconductor by the sputtering method, an oxide semiconductor target containing at least In, Ga, and Zn is used, but it is necessary to reduce the hydrogen concentration contained in the target as much as possible. In a general oxide semiconductor target, in the analysis by SIMS analysis, 10 or more and 10 2 0 or more and 10 21 atoms / cm3 Although it contains hydrogen below, this is 10 19 atoms / cm 3 It is desirable to be as follows.

[0036] The target is generally configured by bonding a target material to a metal plate called a backing plate. The target material of the oxide semiconductor is, for example, an oxide containing In (indium), Ga (gallium), and Zn (zinc) is sintered at a high temperature of 800 °C or higher after being mixed at the same ratio (In O 2 O 3 :Ga 2 O 3 : ZnO = 1:1:1 [mol ratio]). By performing sintering in an inert gas atmosphere (nitrogen or noble gas atmosphere), it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from mixing into the target material. Sintering may be performed in a vacuum or a high-pressure atmosphere, or may be performed while applying mechanical pressure. It should be noted that the target material may be amorphous or crystalline. As described above, SiO may be contained in the target material in an amount of 0.1% by weight or more and 20% by weight or less, preferably 1% by weight or more and 6% by weight or less. In this specification, unless otherwise specified, this of the target material may be referred to as the target. The backing plate generally has the role of cooling the target material and serving as a sputtering electrode, so copper with excellent thermal conductivity and electrical conductivity is often used. By forming a cooling path inside or on the back surface of the backing plate and circulating water, oil, or the like as a coolant through the cooling path, the target can be cooled.

[0037] It should be noted that the target material may be amorphous or crystalline. As described above, SiO SiO 2 is contained in an amount of 0.1% by weight or more and 20% by weight or less, preferably 1% by weight or more and 6% by weight or less. In this specification, unless otherwise specified, this of the target material may be referred to as the target. The backing plate generally has the role of cooling the target material and serving as a sputtering electrode, so copper with excellent thermal conductivity and electrical conductivity is often used. By forming a cooling path inside or on the back surface of the backing plate and circulating water, oil, or the like as a coolant through the cooling path, the target can be cooled.

[0038] The backing plate generally has the role of cooling the target material and serving as a sputtering electrode, so copper with excellent thermal conductivity and electrical conductivity is often used. A cooling path is formed inside or on the back surface of the backing plate, and water, oil, or the like is circulated through the cooling path as a coolant, so that the target can be cooled. The backing plate generally has the role of cooling the target material and serving as a sputtering electrode, so copper with excellent thermal conductivity and electrical conductivity is often used. By forming a cooling path inside or on the back surface of the backing plate and circulating water, oil, or the like as a coolant through the cooling path, the target The cooling efficiency of the target can be enhanced. However, since the vaporization temperature of water is 100 °C, if it is desired to keep the target at 100 °C or higher, it is advisable to use a grease or the like instead of water. When it is desired to keep the target at 100 °C or higher, it is advisable to use a grease or the like instead of water.

[0039] The bonding of the target material and the backing plate may be carried out, for example, by electron beam welding. Electron beam welding is a technique in which electrons generated in a vacuum atmosphere are accelerated and converged, and irradiated onto an object, thereby melting only the portion to be welded and welding it without impairing the material properties of the portions other than the welded portion. It is possible to control the shape of the welded portion and the penetration depth, and since welding is performed in a vacuum, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target material. When irradiating an object, only the part to be welded is melted and welded without damaging the material properties of the parts other than the welded part. It is a method that can control the shape of the welded part and the penetration depth, and since welding is performed in a vacuum, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target material. Since welding is performed in a vacuum, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target material. Since welding is performed in a vacuum, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target material.

[0040] When transferring the fabricated target, it is carried out while keeping the target in a vacuum atmosphere or an inert gas atmosphere (nitrogen or noble gas atmosphere). By doing so, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target. By doing so, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target. By doing so, it is possible to prevent hydrogen, moisture, hydrocarbons, etc. from adhering to the target.

[0041] When attaching the target to the sputtering apparatus, it is also carried out in an inert gas atmosphere (nitrogen or noble gas atmosphere) without exposing it to the atmosphere, thereby preventing hydrogen, moisture, hydrocarbons, etc. from adhering to the target. When attaching the target to the sputtering apparatus, it is also carried out in an inert gas atmosphere (nitrogen or noble gas atmosphere) without exposing it to the atmosphere, thereby preventing hydrogen, moisture, hydrocarbons, etc. from adhering to the target. When attaching the target to the sputtering apparatus, it is also carried out in an inert gas atmosphere (nitrogen or noble gas atmosphere) without exposing it to the atmosphere, thereby preventing hydrogen, moisture, hydrocarbons, etc. from adhering to the target.

[0042] After attaching the target to the sputtering apparatus, it is advisable to perform a dehydrogenation treatment to remove the hydrogen remaining on the surface and inside of the target material. As the dehydrogenation treatment, there are methods such as heating the inside of the film formation chamber under reduced pressure to 200 °C or higher and 600 °C or lower, or repeating the introduction and exhaust of nitrogen or an inert gas while heating. In this case, the target coolant is not water but a grease or the like. After attaching the target to the sputtering apparatus, it is advisable to perform a dehydrogenation treatment to remove the hydrogen remaining on the surface and inside of the target material. As the dehydrogenation treatment, there are methods such as heating the inside of the film formation chamber under reduced pressure to 200 °C or higher and 600 °C or lower, or repeating the introduction and exhaust of nitrogen or an inert gas while heating. In this case, the target coolant is not water but a grease or the like. It may be used. Although a certain effect can be obtained by repeating the introduction and exhaust of nitrogen without heating, it is better to perform while heating. Also, oxygen or an inert gas, or both oxygen and an inert gas are introduced into the film formation chamber, and plasma of the inert gas or oxygen is generated using high frequency or microwave. Although a certain effect can be obtained even without heating, it is better to perform while heating.

[0043] In addition, as the vacuum pump used in a vacuum device such as a sputtering apparatus, for example, a cryopump may be used. A cryopump is a pump that installs an extremely low temperature surface in a vacuum chamber, condenses or adsorbs gas molecules in the vacuum chamber to capture them, and exhausts them, and has a high exhaust capacity for hydrogen and moisture.

[0044] In particular, the formation of the first insulating film, the oxide semiconductor, and the second insulating film is performed after sufficiently reducing hydrogen, moisture, and hydrocarbon in the atmosphere by appropriately using the heating and other methods described above.

[0045] It is desirable to use a high-purity gas with extremely low concentrations of hydrogen, moisture, hydrocarbon, etc. as the gas used during the production of the thin film transistor. By providing a purification device between the gas supply source and each device, it becomes possible to further improve the gas purity. It is advisable to use a gas with a purity of 99.9999% or more. Also, to prevent gas mixing from the inner wall of the gas pipe, it is advisable to use a gas pipe that is mirror-polished on the inner surface and passivated with Cr O or Al O. For the pipe joints and valves, it is advisable to use all-metal valves that do not use resin for the sealing part. 2 O 3 or 2 Al 3 O

[0046] In this specification, continuous film formation means that during a series of processes from the first film formation step to the second film formation step , the atmosphere in which the substrate to be processed is placed is always in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without being exposed to a contaminated atmosphere such as air. . By performing continuous film formation, it is possible to avoid reattachment of hydrogen, moisture, hydrocarbons, etc. to the cleaned substrate to be processed and perform film formation.

[0047] Further, the conductive film functions as a source electrode or a drain electrode. The conductive film is made of a single layer or a laminate of aluminum, or an aluminum alloy to which a heat resistance improving element or a hillock preventing element such as copper, silicon, titanium, neodymium, scandium, molybdenum, etc. is added. Alternatively, a structure in which a high melting point metal layer such as titanium, molybdenum, or tungsten is laminated on one or both of the lower side or the upper side of a single layer or a laminate of aluminum or an aluminum alloy may be used. Among them, titanium is mentioned as a material having excellent interface characteristics with the oxide semiconductor layer. In particular, when a laminate of a titanium film, an aluminum film, and a titanium film is used as the conductive film, it has low resistance, and since the aluminum film is sandwiched between the titanium films, hillocks caused by the aluminum film are less likely to occur, and it is suitable as a source electrode or a drain electrode.

[0048] Further, a structure having a silicon nitride film or a silicon oxide film between the gate electrode and the first insulating film may be used. That is, the gate insulating film may be a laminate of two or more layers, and as the first insulating film which is the uppermost layer in contact with the oxide semiconductor layer, a silicon oxynitride film is preferable, but the insulating film provided under that may be a silicon nitride film or a silicon oxide film. By providing a silicon film, it acts as an etching stopper to prevent the substrate surface from being etched in the manufacturing process of the TFT. A silicon nitride film or a silicon oxide film can also prevent mobile ions such as sodium from entering the semiconductor region from a glass substrate containing an alkali metal such as sodium, thereby suppressing the change in the electrical characteristics of the TFT. It acts as an etching stopper to prevent the substrate surface from being etched in the manufacturing process of the TFT. A silicon nitride film or a silicon oxide film can also prevent mobile ions such as sodium from entering the semiconductor region from a glass substrate containing an alkali metal such as sodium, thereby suppressing the change in the electrical characteristics of the TFT. It can prevent mobile ions such as sodium from entering the semiconductor region from a glass substrate containing an alkali metal such as sodium, thereby suppressing the change in the electrical characteristics of the TFT. It can prevent mobile ions such as sodium from entering the semiconductor region from a glass substrate containing an alkali metal such as sodium, thereby suppressing the change in the electrical characteristics of the TFT.

Advantages of the Invention

[0049] It is possible to realize a structure in which a channel is formed at a positive threshold voltage as close to 0 V as possible for the gate voltage of a thin film transistor using an oxide semiconductor film. In addition, it is possible to reduce the variation in the threshold value, prevent the deterioration of the electrical characteristics, and reduce, preferably eliminate, the shift of the TFT to the normally-on side. It is possible to realize a structure in which a channel is formed at a positive threshold voltage as close to 0 V as possible for the gate voltage of a thin film transistor using an oxide semiconductor film. In addition, it is possible to reduce the variation in the threshold value, prevent the deterioration of the electrical characteristics, and reduce, preferably eliminate, the shift of the TFT to the normally-on side. It is possible to reduce the variation in the threshold value, prevent the deterioration of the electrical characteristics, and reduce, preferably eliminate, the shift of the TFT to the normally-on side. It is possible to reduce the variation in the threshold value, prevent the deterioration of the electrical characteristics, and reduce, preferably eliminate, the shift of the TFT to the normally-on side.

Brief Description of the Drawings

[0050]

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Mode for Carrying Out the Invention

[0051] Embodiments of the present invention will be described below.

[0052] (Embodiment 1) In this embodiment, a thin film transistor and its manufacturing process will be described with reference to FIG. 1 .

[0053] First, a gate electrode 101 is formed on a substrate 100 (see Fig. 1(A)).

[0054] The substrate 100 is an alkali-free glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminum nosilicate glass, etc., a ceramic substrate, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process , etc. can be used. Further, a substrate provided with an insulating film on the surface of a metal substrate such as a stainless alloy may be applied. The size of the substrate 100 can be 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 m m, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 m m, 1150 mm × 1300 mm, 1500 mm × 1800 mm, 1900 mm × 220 0 mm, 2160 mm × 2460 mm, 2400 mm × 2800 mm, or 2850 m m × 3050 mm, etc. can be used.

[0055] Further, a base insulating film may be formed on the substrate 100 before forming the gate electrode 101. As the base insulating film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film may be formed using a CVD method, a sputtering method, etc. A small amount of a halogen element, such as fluorine or chlorine, may be added to the base insulating film to immobilize mobile ions such as sodium. The concentration of the halogen element contained in the insulating film is such that the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometer) is 1 × 10 15 cm -3 or more and 1 × 10 20 ​cm -3 It is preferably within the following range.

[0056] The gate electrode 101 is formed using a metal material such as titanium, molybdenum, chromium, tantalum, tungsten, aluminum or an alloy material thereof. The gate electrode 101 can be formed by forming a conductive film on the substrate 100 by sputtering ring method or vacuum evaporation method, forming a mask on the conductive film by photolithography technology or inkjet method, and etching the conductive film using the mask. Further, a conductive nanopaste such as silver, gold, or copper can be ejected and fired by the inkjet method to form the gate electrode 101. In addition, a nitride film of the above metal material may be provided between the substrate 100 and the gate electrode 101 as a barrier metal to improve the adhesion of the gate electrode 101 and prevent diffusion into the substrate and the underlying film. The gate electrode 101 may have a single-layer structure or a laminated structure. For example, from the side of the substrate 10 0, a laminate of a molybdenum film and an aluminum film, a laminate of a molybdenum film, an aluminum film, and an alloy film of aluminum and neodymium can be used, a laminate of a titanium film and an aluminum film, a laminate of a titanium film, an aluminum film and a titanium film, etc. Here, a laminated film of an aluminum film and a molybdenum film is formed using the sputtering method, and selective etching is performed using photolithography

[0057] technology. Here, a first photomask is used. Since a semiconductor film and wiring are formed on the gate electrode 101, it is desirable to process the end portion to be tapered in order to prevent step discontinuity. Next, a first insulating film 102 serving as a gate insulating film, a semiconductor film 103, and a second insulating film 1

[0058] 03 ​​04 is continuously formed without being exposed to the atmosphere (see Fig. 1(B)). Without being exposed to the atmosphere When continuously forming without exposure to the atmosphere, productivity is high and the reliability of the thin film interface is stable. Also, in the atmosphere each deposition interface can be formed without being contaminated by moisture, hydrocarbons, and other contaminant impurity elements contained in the atmosphere, and hydrogen can be prevented from being incorporated into the semiconductor film .

[0059] The first insulating film 102 and the second insulating film 104 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film using a CVD method, a sputtering method, or the like . Here, as the first insulating film 102 and the second insulating film 104, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less is formed by an RF sputtering method. By using a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less, intrusion or diffusion of hydrogen, moisture, etc. into the semiconductor film 103 can be prevented. The formation of the insulating film is preferably performed under conditions that do not cause hysteresis or charge-up in the thin film transistor .

[0060] Also, the first insulating film 102 can be a laminate of two layers or more. As the uppermost layer film in contact with the oxide semiconductor layer, a silicon oxynitride film is preferable, but the insulating film provided in the lower layer may be a silicon nitride film or a silicon oxide film. This lower layer film also has an effect of preventing hillock generation when a material that may cause hillock generation is used for the material of the gate electrode 101 .

[0061] Here, as the semiconductor film 103, a film of an oxide semiconductor layer (IGZO semiconductor layer) is formed by a DC magnetron sputtering method . In this specification, an oxide semiconductor The semiconductor layer formed using the solid film is also referred to as the "IGZO semiconductor layer." In this case, the composition ratio of the metal elements has a high degree of freedom, and the layer functions as a semiconductor over a wide range of mixture ratios. For example, indium oxide containing 10% by weight of zinc oxide, indium oxide and gallium oxide The ratio of the metal elements in the film is In:Ga:Z As an example, an oxide that exists in a ratio of n=2.2:2.2:1.0 [atom ratio] is In order to reduce the variation in the electrical characteristics of thin-film transistors, The layer is preferably in an amorphous state.

[0062] The semiconductor film 103 is formed in an atmosphere containing only oxygen. This is often done in an atmosphere containing rare gases such as r, but these rare gas elements are more toxic than oxygen. Because of its large mass, moisture and halide that adhered to the inner walls of the deposition chamber and jigs during sputtering However, it accelerates the deposition rate and promotes the desorption of gases that contain hydrogen, such as hydrocarbons. In order to prevent this, oxygen and rare gases are mixed in the chamber as long as they do not affect the desorption of gas from the inner walls of the chamber. Specifically, the oxygen flow rate is 50% or more and 100% or less, preferably 7 The semiconductor film 103 may be formed in an atmosphere having a concentration of 0% or more and 100% or less. The substrate temperature is preferably set to be equal to or higher than room temperature (25°C) and lower than 200°C.

[0063] Next, in order to pattern the semiconductor film 103, the second insulating film 104 is selectively etched. Then, the semiconductor film 103 is selectively etched to form an insulator 106. The semiconductor layer 105 is formed by dry etching using chlorine gas. Well. The insulator 106 functions as a channel protection film. At this stage, the semiconductor film 103 is removed. In the region where the semiconductor film 103 has been removed, the surface of the gate insulating film is exposed. Here, the second photomask is used. The mask formed on the second insulating film 104 during patterning is removed by an ashing process in an oxygen atmosphere. The cross-sectional structure of the substrate at this stage corresponds to the cross-sectional view of the substrate shown in FIG. 1(C). (See FIG. 1(C).) In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, washing with water may not be performed after this. (See FIG. 1(C).). In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, washing with water may not be performed after this. (See FIG. 1(C).). In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, washing with water may not be performed after this. (See FIG. 1(C).). In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, washing with water may not be performed after this.

[0064] Next, it is preferable to perform a heat treatment at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the IGZO semiconductor layer 105 is performed. Next, it is preferable to perform a heat treatment at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the IGZO semiconductor layer 105 is performed. Next, it is preferable to perform a heat treatment at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the IGZO semiconductor layer 105 is performed. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released. Also, the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 103. In the present embodiment, since the IGZO semiconductor layer 105 is covered with the insulator 106, it is suitable because deterioration of the IGZO semiconductor layer 105 after the heat treatment can be reduced. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released. Also, the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 103. In the present embodiment, since the IGZO semiconductor layer 105 is covered with the insulator 106, it is suitable because deterioration of the IGZO semiconductor layer 105 after the heat treatment can be reduced. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released. Also, the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 103. In the present embodiment, since the IGZO semiconductor layer 105 is covered with the insulator 106, it is suitable because deterioration of the IGZO semiconductor layer 105 after the heat treatment can be reduced. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released. Also, the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 103. In the present embodiment, since the IGZO semiconductor layer 105 is covered with the insulator 106, it is suitable because deterioration of the IGZO semiconductor layer 105 after the heat treatment can be reduced. .

[0065] Next, a part of the insulator 106 is further removed, and a contact hole (opening) 107 for connecting the source electrode 108 or the drain electrode 109 to be formed later and the IGZO semiconductor layer 105 is formed. Photolithography technology is used to form a contact hole (opening) 107 that selectively etches to expose a part of the IGZO semiconductor layer 105. Here, the third photomask is used. The etching is dry etching using chlorine gas. Next, a part of the insulator 106 is further removed, and a contact hole (opening) 107 for connecting the source electrode 108 or the drain electrode 109 to be formed later and the IGZO semiconductor layer 105 is formed. Photolithography technology is used to form a contact hole (opening) 107 that selectively etches to expose a part of the IGZO semiconductor layer 105. Here, the third photomask is used. The etching is dry etching using chlorine gas. Next, a part of the insulator 106 is further removed, and a contact hole (opening) 107 for connecting the source electrode 108 or the drain electrode 109 to be formed later and the IGZO semiconductor layer 105 is formed. Photolithography technology is used to form a contact hole (opening) 107 that selectively etches to expose a part of the IGZO semiconductor layer 105. Here, the third photomask is used. The etching is dry etching using chlorine gas. Next, a part of the insulator 106 is further removed, and a contact hole (opening) 107 for connecting the source electrode 108 or the drain electrode 109 to be formed later and the IGZO semiconductor layer 105 is formed. Photolithography technology is used to form a contact hole (opening) 107 that selectively etches to expose a part of the IGZO semiconductor layer 105. Here, the third photomask is used. The etching is dry etching using chlorine gas. Next, a part of the insulator 106 is further removed, and a contact hole (opening) 107 for connecting the source electrode 108 or the drain electrode 109 to be formed later and the IGZO semiconductor layer 105 is formed. Photolithography technology is used to form a contact hole (opening) 107 that selectively etches to expose a part of the IGZO semiconductor layer 105. Here, the third photomask is used. The etching is dry etching using chlorine gas. It is carried out by the G method. For the etching for forming the contact hole (opening) 107 here, I conditions with a sufficiently different etching rate from the IGZO semiconductor layer 105 are used. Also, by laser irradiation, only the insulator 106 may be selectively removed to form the contact hole (opening) 107 .

[0066] The contact hole (opening) 107 should be formed as small as possible in order to eliminate the influence of hydrogen, moisture, hydrocarbons, etc. given to the IGZO semiconductor layer 105 during its formation. However , if it is too small, the characteristics of the completed thin film transistor cannot be fully extracted . Therefore, it may be made as small as possible within a range where there is no influence .

[0067] Next, a metal multilayer film to be a source electrode or a drain electrode is formed. Here, a DC magnetron sputtering method is used to laminate an aluminum film on a titanium film, and further laminate a titanium film on the aluminum film. Both a titanium target and an aluminum target are installed in the sputtering chamber, and they are sequentially laminated using a shutter to perform continuous film formation . In this way, continuous lamination can be performed in the same chamber. At this time, it may be carried out in an atmosphere of only a rare gas such as Ar or Kr . This is because the IGZO semiconductor layer 105 is already sandwiched between the first insulating film 102 and the second insulating film 104, and in particular, the channel formation region in the IGZO semiconductor layer 105 is not affected by hydrogen, moisture, hydrocarbons, etc. due to gas desorption from the chamber inner wall . .

[0068] Also, before forming the metal multilayer film, the IGZO semiconductor layer in the contact hole (opening) 107 is reversed By performing sputtering, etching of about 10 nm may be performed. - No voltage is applied to the target side, and a voltage is applied to the substrate side in an inert gas or oxygen atmosphere. This is a method of etching the surface by forming plasma on the substrate side using reverse sputtering. A good interface state can be achieved between the ZO semiconductor layer and the metal multilayer film, and the contact resistance can be reduced.

[0069] In addition, an oxide semiconductor film was formed as a buffer layer between the IGZO semiconductor layer and the metal multilayer film. For example, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, etc. Stainless oxide, magnesium oxide, calcium oxide, tin oxide, etc. can be used. Al-Zn-O based non-single crystal film or Al-Zn-O based non-single crystal film containing nitrogen, i.e., A A l-Zn-ON type non-single crystal film may be used. The aluminum content of the l-Zn-ON oxide semiconductor is 1% by weight or more and 10% by weight or less. It is preferable that the temperature is lower than the above range.

[0070] Note that the Al-Zn-ON oxide semiconductor film referred to here is an oxide semiconductor film having a stoichiometric ratio of Al:Zn: This does not mean that O:N=1:1:1:1, but is written simply for ease of notation. The composition ratio of these elements can be appropriately adjusted by the film formation conditions.

[0071] The buffer layer may contain impurities that impart n-type or p-type conductivity. The elements that can be used include indium, gallium, aluminum, zinc, tin, and the like.

[0072] The carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer and has excellent conductivity. Compared with the case where the source or drain electrode is directly joined to the IGZO semiconductor layer, the contact resistance can be reduced. This can be achieved.

[0073] The buffer layer can also be referred to as the drain region or the source region.

[0074] Next, the metal multilayer film is selectively etched to form the source electrode 108 or the drain electrode 109. Here, a fourth photomask is used. The conductive film having a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order can be etched by a dry etching method using chlorine gas. Even when a buffer layer is formed between the IGZO semiconductor layer and the metal multilayer film, the buffer layer can be etched simultaneously with the etching of the metal multilayer film. This is possible. The cross-sectional structure of the substrate at this stage corresponds to the cross-sectional view of the substrate shown in FIG. 1(E) (see FIG. 1( E)). ).

[0075] In the channel formation region in the present embodiment, in the IGZO semiconductor layer 105, it is the region where the gate electrode 101 overlaps with the IGZO semiconductor layer 105, from the end of the contact hole (opening) 107 for connecting the source electrode 108 to the IGZO semiconductor layer 105 to the end of the contact hole (opening) 107 for connecting the drain electrode 109 to the IGZO semiconductor layer 105, and L1 in FIG. 1(D) corresponds to the channel length.

[0076] By sandwiching the channel formation region of the IGZO semiconductor layer 105 with a silicon oxynitride film having a nitrogen content of 3 atomic% or more and 30 atomic% or less, the intrusion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented. The silicon oxynitride film is formed to cause hysteresis and in the thin film transistor. It is preferably performed under conditions that do not cause charge-up.

[0077] (Embodiment 2) In this embodiment, the thin-film transistor and its manufacturing process will be described with reference to FIG. 2. . Note that the description of the same parts or parts having similar functions as those in Embodiment 1, and the repetition of processes will be omitted.

[0078] First, a gate electrode 201 is formed on a substrate 200. Here, the first photomask is used (see FIG. 2(A)). (See FIG. 2(A).)

[0079] Next, a first insulating film 202 serving as a gate insulating film, a first semiconductor film 203, and a second insulating film 204 are continuously formed without being exposed to the air (see FIG. 2(B)). Here, as the first insulating film 202 and the second insulating film 204, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less is formed by RF sputtering, and as the first semiconductor film 203, a DC magnetron sputtering method is used with an oxide semiconductor target containing 0. 1 wt% or more and 20 wt% or less of SiO in an oxide semiconductor (ZnO) containing Zn (zinc). 2 The film is formed. As described in Embodiment 1, the film formation of the oxide semiconductor layer is performed in an atmosphere of only oxygen, but it may be performed in an atmosphere in which oxygen is 50% or more and 100% or less, preferably 70% or more and 10 0% or less in terms of flow rate ratio and a rare gas is mixed. Note that the film formation of the first semiconductor film 203 is preferably performed with the substrate temperature being room temperature (25°C) or more and less than 200°C.

[0080] Next, the second insulating film 204 is etched leaving only the portion overlapping with the position where the gate electrode overlaps and the portion overlapping with the channel formation region of the first semiconductor film 203 to form an insulator 206. ​ Do this. The insulator 206 functions as a channel protection film. Selective etching is performed to form the insulator 206, and photolithography technology is used. Here, the second photomask is used. The etching for forming the insulator 206 here is performed by the dry etching method and conditions with a sufficiently different etching rate from the first semiconductor film 203 are used (see Fig. 2( C)). The mask formed on the second insulating film 204 during patterning is removed by ashing treatment in an oxygen atmosphere below. In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, subsequent washing with water may not be performed.

[0081] Also, when forming the insulator 206, a mask can be selectively formed at a position overlapping the gate electrode by self-alignment using backside exposure without using a photomask. In particular, the first semiconductor film 203 is an oxide semiconductor film, has high light transmittance, and is suitable for backside exposure. However, when performing backside exposure, it is necessary that the first insulating film 202 and the second insulating film 204 are made of materials having sufficient light transmittance.

[0082] Next, it is preferable to perform heat treatment at 200 °C or higher and 600 °C or lower, typically 300 °C or higher and 500 °C or lower. Here, it is placed in a furnace and heat-treated at 350 °C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the first semiconductor film 203 is performed. By this heat treatment (including photo annealing), strain that inhibits carrier movement is released. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the first semiconductor film 203. In the present embodiment, the first semiconductor film 203 is covered with the insulator 206. Therefore, it is suitable because deterioration of the first semiconductor film 203 after the heat treatment can be reduced. .

[0083] Next, a second semiconductor film 212 serving as a buffer layer and a metal multilayer film that becomes a source electrode or a drain electrode are formed. Here, using the DC magnetron sputtering method, a titanium oxide film is formed as the second semiconductor film 212, and a titanium film is laminated on the second semiconductor film 212 as the metal multilayer film 211, an aluminum film is laminated on the titanium film, and further a titanium film is laminated on the aluminum film (see Fig. 2(D)).

[0084] The carrier concentration of the second semiconductor film 212 serving as the buffer layer is higher than that of the oxide semiconductor layer and is superior in conductivity compared to the case where the source electrode or the drain electrode is directly joined to the semiconductor layer. Therefore, providing a buffer layer can reduce the contact resistance.

[0085] After forming the second semiconductor film 212 serving as the buffer layer, it is preferable to perform a heat treatment at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the second semiconductor film 212 is performed. By this heat treatment (including photo annealing), strain that inhibits carrier movement is released.

[0086] Next, selective etching of the metal laminated film is performed to form the source electrode 208 or the drain electrode 209. Here, a third photomask is used. The etching is performed by the dry etching method. At this time, the metal multilayer film 211, the second semiconductor film 212, and the first semiconductor film 203 By performing etching under conditions that allow any of them to be etched, the source electrode 208, the drain electrode 209, the source-side buffer layer 213, the drain-side buffer layer 214, and the formation of the semiconductor layer 205 can be carried out in the same etching process. The insulator 206 functions as a channel protection film and prevents the semiconductor layer 205 in the channel formation region from being etched (see Fig. 2(E)).

[0087] In the present embodiment, the channel formation region is a region in the semiconductor layer 205 where the gate electrode 201 overlaps with the semiconductor layer 205 and the insulator 206, and the width L2 of the insulator 206 corresponds to the channel length.

[0088] An oxynitride film with a nitrogen content of 3 atomic % or more and 30 atomic % or less is formed on the upper and lower layers of the channel formation region of the semiconductor layer 205, and the channel formation region is sandwiched between the oxynitride films, so that the intrusion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented.

[0089] In addition, in order to prevent the intrusion or diffusion of hydrogen, moisture, etc. from the side surface of the semiconductor layer, a third insulating film 210 may be formed so as to cover the thin film transistor. The third insulating film 210 can be formed of a silicon oxide film, a silicon nitride film, an oxynitride film, or a silicon oxynitride film. For example, an oxynitride film with a nitrogen content of 3 atomic % or more and 30 atomic % or less may be formed by sputtering. By using an oxynitride film with a nitrogen content of 3 to 30 atomic %, the intrusion or diffusion of hydrogen, moisture, hydrocarbons, etc. into the thin film transistor can be prevented. The formation of the oxynitride film is preferably carried out under conditions that do not cause hysteresis or charge-up in the thin film transistor. ​

[0090] (Embodiment 3) In this embodiment, a thin film transistor and its manufacturing process will be described with reference to FIG. 3 . Note that the description of the same parts or parts having similar functions as those in Embodiment 1, and the repeated description of the processes are omitted.

[0091] First, a gate electrode 301 is formed on a substrate 300. Here, the first photomask is used .

[0092] Next, a first insulating film 302 serving as a gate insulating film and a metal multilayer film 311 serving as a source electrode or a drain electrode are formed .

[0093] The first insulating film 302 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film by using a CVD method, a sputtering method, or the like. Here, as the first insulating film 302, a silicon oxynitride film having a nitrogen content of 3 atomic% or more and 30 atomic% or less is formed by an RF sputtering method . .

[0094] The metal multilayer film 311 serving as a source electrode or a drain electrode is formed by laminating an aluminum film on a titanium film and further laminating a titanium film on the aluminum film by using a DC magnetron sputtering method (see FIG. 3(A)). (See FIG. 3(A).)

[0095] Next, the metal multilayer film is selectively etched to form a source electrode 308 or a drain electrode 309. Here, the second photomask is used (see FIG. 3(B)). (See FIG. 3(B).)

[0096] Next, a semiconductor film 303 and a second insulating film 304 are continuously formed without exposing them to the atmosphere ​​Do (see Fig. 3(C)). As the semiconductor film 303, an oxide semiconductor layer (ZnO -SiO formed by DC magnetron sputtering using a target containing 10 wt% of silicon oxide in zinc oxide -SiO X (X>0) semiconductor layer) is used. As described in Embodiment 1, the formation of the oxide semiconductor layer is performed in an atmosphere of only oxygen, but it may be performed in an atmosphere mixed with a rare gas with oxygen being 50% or more and 100% or less, preferably 70% or more and 100% or less in terms of flow rate ratio. Note that the formation of the semiconductor film 303 is preferably performed with the substrate temperature being room temperature (25°C) or higher and lower than 200°C .

[0097] Here, the results of evaluating the crystallinity of the oxide semiconductor layer (ZnO-SiO semiconductor layer) by XRD measurement are shown . The measurement is performed on three types of oxide semiconductor layers (ZnO-SiO semiconductor layer) formed using targets containing 7.5 wt%, 10 wt%, and 12 .5 wt% of silicon oxide in zinc oxide, respectively.

[0098] Fig. 26 shows the XRD measurement results. The horizontal axis is the rotation angle degree (2θ) of the measurement sample with respect to the incident X-ray, and the vertical axis is the X-ray diffraction intensity. In the figure, the measurement results 601 of the silicon oxide content of 7.5 wt%, the measurement results 602 of the silicon oxide content of 10 wt%, and the measurement results 603 of the silicon oxide content of 12 .5 wt% are shown.

[0099] According to the measurement results in Fig. 26, a peak 60 4 indicating crystallinity is detected when the silicon oxide content is 7.5 wt%, but no peak indicating crystallinity is detected when the silicon oxide content is 10 wt% or more, indicating that the film is amorphous. Note that ZnO-SiO (X>0) X (X>0) If the silicon oxide content of the semiconductor layer is 10% by weight or more, it can maintain an amorphous state even in heat treatment at 700 °C. It can maintain an amorphous state even in heat treatment at 700 °C.

[0100] Before forming the semiconductor film 303, the surfaces of the first insulating film 302, the source electrode 308, and the drain electrode 309 may be etched by about 10 nm by reverse sputtering. By performing reverse sputtering, hydrogen, moisture, hydrocarbons, etc. attached to the surfaces of the first insulating film 302, the source electrode 308, and the drain electrode 309 can be removed. By performing reverse sputtering, hydrogen, moisture, hydrocarbons, etc. attached to the surfaces of the first insulating film 302, the source electrode 308, and the drain electrode 309 can be removed. By performing reverse sputtering, hydrogen, moisture, hydrocarbons, etc. attached to the surfaces of the first insulating film 302, the source electrode 308, and the drain electrode 309 can be removed.

[0101] Next, in order to pattern the semiconductor film 303, the second insulating film 304 is selectively etched to form an insulator 306, and then the semiconductor film 303 is selectively etched to form a ZnO-SiO(X>0) semiconductor layer 305. Here, a third photomask is used. Next, in order to pattern the semiconductor film 303, the second insulating film 304 is selectively etched to form an insulator 306, and then the semiconductor film 303 is selectively etched to form a ZnO-SiO(X>0) semiconductor layer 305. Here, a third photomask is used. -SiO X (X>0) semiconductor layer 305 is formed. Here, a third photomask is used. The mask formed on the second insulating film 304 during patterning is removed by ashing treatment in an oxygen atmosphere. The insulator 306 functions as a channel protection film. The etching is performed by a dry etching method. In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, The mask formed on the second insulating film 304 during patterning is removed by ashing treatment in an oxygen atmosphere. The insulator 306 functions as a channel protection film. The etching is performed by a dry etching method. In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, The mask formed on the second insulating film 304 during patterning is removed by ashing treatment in an oxygen atmosphere. The insulator 306 functions as a channel protection film. The etching is performed by a dry etching method. In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, subsequent washing with water may not be performed.

[0102] Next, heat treatment at 200 °C or higher and 600 °C or lower, typically 300 °C or higher and 500 °C or lower, is preferably performed. Here, it is placed in a furnace and heat treatment is performed at 350 °C for 1 hour in a nitrogen atmosphere containing oxygen. Next, heat treatment at 200 °C or higher and 600 °C or lower, typically 300 °C or higher and 500 °C or lower, is preferably performed. Here, it is placed in a furnace and heat treatment is performed at 350 °C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the semiconductor layer 305 is performed. By this heat treatment (including photo annealing), strain that inhibits carrier movement is released. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 303. In this embodiment By this heat treatment (including photo annealing), strain that inhibits carrier movement is released. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 303. In this embodiment By this heat treatment (including photo annealing), strain that inhibits carrier movement is released. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 303. In this embodiment In this state, since the semiconductor layer 305 is covered with the insulator 306, it is suitable because deterioration of the semiconductor layer 305 after heat treatment can be reduced. It is suitable because deterioration of the semiconductor layer 305 can be reduced.

[0103] The channel formation region in this embodiment is a region where the gate electrode 301 overlaps with the ZnO—SiO X (X>0) semiconductor layer 305 and is sandwiched between the source electrode 308 and the drain electrode 309. The distance L3 between the source electrode 308 and the X drain electrode 309 corresponds to the channel length. By forming silicon oxynitride films having a nitrogen content of 3 atomic % or more and 30 atomic % or less on the upper layer and the lower layer of the channel formation region of the semiconductor layer 305 and sandwiching the channel formation region with the silicon oxynitride films, invasion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented. The silicon oxynitride films are preferably formed under conditions that do not cause hysteresis or charge-up in the thin film transistor.

[0104] Note that, in order to prevent invasion or diffusion of hydrogen, moisture, etc. from the side surface portion of the ZnO—SiO (X>0) semiconductor layer, a third insulating film 310 may be formed so as to cover the thin film transistor. The third insulating film 310 is preferably formed under conditions that do not cause hysteresis or charge-up in the thin film transistor. The third insulating film 310 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. For example, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less may be formed by an RF sputtering method. Invasion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented. The silicon oxynitride films are preferably formed under conditions that do not cause hysteresis or charge-up in the thin film transistor.

[0105] Note that, in order to prevent invasion or diffusion of hydrogen, moisture, etc. from the side surface portion of the ZnO—SiO X (X>0) semiconductor layer, a third insulating film 310 may be formed so as to cover the thin film transistor. The third insulating film 310 is preferably formed under conditions that do not cause hysteresis or charge-up in the thin film transistor. The third insulating film 310 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. For example, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less may be formed by an RF sputtering method. By using a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less, the thin film transistor can prevent the intrusion or diffusion of hydrogen, moisture, etc. into the resistor.

[0106] Further, if necessary, a buffer X oxide semiconductor film serving as a layer may be formed between the ZnO—SiO (X>0) semiconductor layer and the metal multilayer film.

[0107] (Embodiment 4) In this embodiment, the thin film transistor and its manufacturing process will be described with reference to FIG. 4. Note that the same parts or parts having similar functions as those in Embodiment 1, and repeated descriptions of the processes are omitted.

[0108] First, a gate electrode 401 is formed on a substrate 400. Here, the first photomask is used (see FIG. 4(A)).

[0109] Next, a first insulating film 402 serving as a gate insulating film, a first semiconductor film 403, and a second semiconductor film 412 are continuously formed without exposing them to the air (see FIG. 4(B)). Here, as the first insulating film 402, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 3 0 atomic % or less is formed by an RF sputtering method, as the first semiconductor film 403, an IGZO semiconductor layer is formed by a DC magnetron sputtering method, and as the second semiconductor film 412, an Al—Zn—O —N-based oxide semiconductor film is formed. Note that for the formation of the oxide semiconductor film, the substrate temperature is preferably set to be room temperature (2 5° C.) or higher and lower than 200° C. Note that the Al—Zn—O—N-based oxide semiconductor film mentioned here does not mean that the stoichiometric ratio is Al:Zn: O:N = 1:1:1:1, but is merely described for ease of notation.

[0110] not. No. The composition ratios of these elements can be appropriately adjusted according to the film formation conditions.

[0111] Next, heat treatment is preferably performed at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the IGZO semiconductor layer and the Al-Zn-O-N-based oxide semiconductor film is carried out. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released. Note that the timing of the heat treatment is not particularly limited as long as it is after the formation of the first semiconductor film 403 and the second semiconductor film 412.

[0112] Next, in order to pattern the first semiconductor film 403, the second semiconductor film 412 is selectively etched, and then the first semiconductor film 403 is selectively etched to form the IGZO semiconductor layer 405. The etching is performed by a dry etching method using chlorine gas. The second semiconductor film 412 functions as a buffer layer. At this stage, the surface of the gate insulating film is exposed in the region where the first semiconductor film 403 is removed. Here, the second photomask is used. The mask formed on the second semiconductor film 412 during patterning is removed by an ashing process in an oxygen atmosphere. The cross-sectional structure of the substrate at this stage corresponds to the cross-sectional view of the substrate shown in FIG. 4(C) (see FIG. 4(C)). In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, washing with water may not be performed thereafter.

[0113] Since the carrier concentration of the second semiconductor film 412 serving as the buffer layer is higher than that of the IGZO semiconductor layer and it has excellent conductivity, the source electrode or the drain electrode is directly joined to the IGZO semiconductor layer. ​ Compared with the case without it, providing a buffer layer can reduce the contact resistance.

[0114] Next, a metal multilayer film serving as a source electrode or a drain electrode is formed. Here, DC Using a magnetron sputtering method, an aluminum film is laminated on a titanium film, and then a titanium film is laminated on the aluminum film. Both a titanium target and an aluminum target are installed in the sputtering chamber, and sequential lamination is performed using a shutter to form a continuous film. In this way, continuous lamination can be performed within the same chamber.

[0115] Next, the metal multilayer film is selectively etched to form a source electrode 408 or a drain electrode 409. Here, a third photomask is used. The etching is performed by a dry etching method. At this time, the metal multilayer film and the second semiconductor film 412 can be etched, and conditions where the etching rate is sufficiently different from that of the IGZO semiconductor layer 405 are used. As a result, the source electrode 408, the drain electrode 409, the source-side buffer layer 413, and the drain-side buffer layer 414 can be formed in the same etching process (see Fig. 4(D)).

[0116] Next, in order to prevent the intrusion or diffusion of hydrogen, moisture, etc. from the outside, a third insulating film 410 is formed so as to cover the thin film transistor. The formation of the third insulating film 410 is preferably performed under conditions that do not cause hysteresis or charge-up in the thin film transistor. The third insulating film 410 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. For example, by an RF sputtering method, the nitrogen content is 3 atomic% or more and 30 atomic % or less. % or less. % or less. % You may form the following silicon oxynitride film. By using a silicon oxynitride film with a nitrogen content of 3 atomic % or more and 30 atomic % or less, invasion or diffusion of hydrogen, moisture, etc. into the thin film transistor can be prevented.

[0117] Before forming the third insulating film 410, the surfaces of the IGZO semiconductor layer 405, the source electrode 408, and the drain electrode 409 may be etched by reverse sputtering by about 10 nm. By performing reverse sputtering, hydrogen, moisture, hydrocarbons, etc. adhering to the surfaces of the source electrode 408 and the drain electrode 409 can be removed.

[0118] In the present embodiment, the channel formation region is a region in the IGZO semiconductor layer 405 where the gate electrode 401 overlaps the IGZO semiconductor layer 405 and is sandwiched between the source side buffer layer 413 and the drain side buffer layer 414. The distance L4 up to the source side buffer layer 413 and the drain side buffer layer 414 corresponds to the channel length (see Fig. 4(E)). .

[0119] On the upper and lower layers of the channel formation region of the IGZO semiconductor layer 405, a silicon oxynitride film with a nitrogen content of 3 atomic % or more and 30 atomic % or less is formed, and the channel formation region is sandwiched between the silicon oxynitride films, so that invasion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented.

[0120] (Embodiment 5) In the present embodiment, the thin film transistor and its manufacturing process will be described with reference to Fig. 24. Note that descriptions of the same parts or parts having the same functions as those in Embodiment 1, and repeated descriptions of the processes are omitted.

[0121] First, a gate electrode 701 is formed on a substrate 700. (See FIG. 24(A)).

[0122] Next, the first insulating film 702 which will become the gate insulating film and the semiconductor film 703 are exposed to the air. The first insulating film 702 is formed in succession (see FIG. 24(B)). Silicon oxynitride film with nitrogen content of 3 atomic % to 30 atomic % by RF sputtering method As the semiconductor film 703, In (indium), Ga (gallium), and Zn ( The film was formed by sputtering using a target of oxide containing zinc and silicon oxide. The semiconductor film 703 is formed at a substrate temperature of room temperature (25° C.) or higher and lower than 200° C. is preferred.

[0123] In forming the semiconductor film 703, an oxide semiconductor film to be used as the semiconductor film 703 was separately formed. The physical properties of the oxide semiconductor film were evaluated. A stereoscopic view of the sample 510 is shown. The sample 510 for evaluating physical properties was prepared and the Hall effect was measured at room temperature. The carrier concentration and Hall mobility of the oxide semiconductor film were evaluated. The physical property evaluation sample 510 has an insulating film 501 made of silicon oxynitride formed on a substrate 500. An oxide semiconductor film 502 to be evaluated is formed thereon, and electrodes 503 to 506 are formed thereon. The oxide semiconductor film to be evaluated was fabricated by forming a target material having two layers of silicon oxide. The samples were formed using three types of targets, each containing 10% by weight, 5% by weight, and 10% by weight of the doped material. A physical property evaluation sample 510 was prepared for each oxide semiconductor film and the Hall effect was measured at room temperature. In addition, a target without added silicon oxide was used as a reference. A sample with an oxide semiconductor film formed thereon was also prepared and the same evaluation was performed.

[0124] Fig. 25(B) shows the carrier concentration of the oxide semiconductor film obtained from Hall effect measurement. Fig. In 25(B), the horizontal axis represents the amount of silicon oxide added and the vertical axis represents the carrier concentration. As the amount of silicon oxide added increases from 0 wt% to 2 wt%, 5 wt%, and 10 wt%, the carrier concentration decreases from 1.6×10 19 / cm 3 to 8.0×10 17 / cm 3 , 2.7×10 16 / cm 3 , 2.0×10 12 / cm 3 respectively.

[0125] Fig. 25(C) shows the Hall mobility of the oxide semiconductor film obtained from Hall effect measurement. Fig. In 25(C), the horizontal axis represents the amount of silicon oxide added and the vertical axis represents the Hall mobility. As the amount of silicon oxide added increases from 0 wt% to 2 wt%, 5 wt%, and 10 wt%, the Hall mobility decreases from 15.1 cm 2 / Vs to 8.1 cm 2 / Vs, 2.6 cm 2 / Vs, 1.8 cm 2 / Vs respectively.

[0126] From the results shown in Fig. 25(B) and Fig. 25(C), it can be seen that as the amount of silicon oxide added increases, the carrier concentration and Hall mobility tend to decrease. However, there is no significant difference in Hall mobility between 5 wt% and 10 wt% of the silicon oxide added amount. Therefore, when adding silicon oxide to the IGZO semiconductor layer, the amount of silicon oxide in the target should be more than 0 wt% and within the range of 10 wt% or less. Silicon may be added, preferably in an amount more than 0 wt% and not more than 6 wt%. That is, the carrier concentration may be in the range of 2.0×10 / cm 12 / cm 3 or more and less than 1.6×1 0 19 / cm 3 Although it may be in the range of 2.0×10 16 / cm 3 or more and less than 1.6×10 19 / cm 3 is preferred, and the Hall mobility may be in the range of 1.8 cm 2 / Vs or more and less than 15. 1 cm 2 / Vs. Although it may be in the range of 2.4 cm 2 / Vs or more and less than 15.1 cm 2 / Vs, it is preferably in the range where it is less than .

[0127] After forming the semiconductor film 703, it is preferably heat-treated at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. Here, it is placed in a furnace and heat-treated at 350 °C for 1 hour in a nitrogen atmosphere containing oxygen. By this heat treatment, atomic-level rearrangement of the IGZO semiconductor layer is performed. By this heat treatment (including photo annealing), the strain that inhibits the movement of carriers is released . Note that the timing of the heat treatment is not particularly limited as long as it is after the formation of the semiconductor film 703 .

[0128] Next, in order to pattern the semiconductor film 703, the semiconductor film 703 is selectively etched to form the IGZO semiconductor layer 705. The etching is performed by the dry etching method using chlorine gas. At this stage, the surface of the gate insulating film is exposed in the region where the semiconductor film 703 has been removed. Here, the second photomask is used. During patterning, the semiconductor film 703 ​The mask formed thereon is removed by ashing treatment in an oxygen atmosphere. The substrate at this stage has a cross-sectional structure corresponding to the cross-sectional view of the substrate shown in Fig. 24(C) (see Fig. 24(C)). In order to exclude moisture as much as possible from the manufacturing process of the thin film transistor, subsequent washing with water may not be performed.

[0129] Next, a metal multilayer film serving as a source electrode or a drain electrode is formed. Here, a DC magnetron sputtering method is used to laminate an aluminum film on a titanium film, and further laminate a titanium film on the aluminum film. Both a titanium target and an aluminum target are installed in the sputtering chamber, and sequential lamination and continuous film formation are performed using a shutter, so that continuous lamination can be performed in the same chamber.

[0130] Next, selective etching of the metal multilayer film is performed to form a source electrode 708 or a drain electrode 709. Here, a third photomask is used. The etching is performed by a dry etching method. At this time, conditions under which the metal multilayer film can be etched and the etching rate is sufficiently different from that of the IGZO semiconductor layer 705 are used. Thereby, the formation of the source electrode 708 and the drain electrode 709 can be performed in the same etching process (see Fig. 24(D)).

[0131] Next, in order to prevent intrusion or diffusion of hydrogen, moisture, etc. from the outside, a third insulating film 710 is formed so as to cover the thin film transistor. The formation of the third insulating film 710 is preferably performed under conditions that do not cause hysteresis or charge-up in the thin film transistor. The third insulating film 710 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. It is possible. For example, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less may be formed by an RF sputtering method. By using a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less, invasion or diffusion of hydrogen, moisture, etc. into the thin film transistor can be prevented.

[0132] Before forming the third insulating film 710, the surfaces of the IGZO semiconductor layer 705, the source electrode 708, and the drain electrode 709 may be etched by about 10 nm by performing reverse sputtering. By performing reverse sputtering, hydrogen, moisture, hydrocarbons, etc. attached to the surfaces of the source electrode 708 and the drain electrode 709 can be removed.

[0133] In the channel formation region in the present embodiment, in the IGZO semiconductor layer 705, the gate electrode 701 and the IGZO semiconductor layer 705 overlap, and the region is sandwiched between the source electrode 708 and the drain electrode 709. The distance L5 to the source electrode 708 and the drain electrode 709 corresponds to the channel length (see Fig. 24(E)).

[0134] On the upper and lower layers of the channel formation region of the IGZO semiconductor layer 705, a silicon oxynitride film having a nitrogen content of 3 atomic % or more and 30 atomic % or less is formed, and by forming a structure in which the channel formation region is sandwiched by the silicon oxynitride film, invasion or diffusion of hydrogen, moisture, etc. into the channel formation region can be prevented.

[0135] In this way, a thin film transistor using an IGZO semiconductor layer can be manufactured.

[0136] From Figs. 25(C) and 26, it can be seen that the addition of silicon oxide causes the amorphization of the oxide semiconductor layer. ​​​​​​​It can be seen that the effect of promoting and reducing the characteristic variations during the fabrication of the semiconductor device is obtained. In addition, although Ga contained in the IGZO semiconductor layer has the effect of promoting amorphization, by using silicon oxide instead of Ga, expensive Ga contained in the IGZO semiconductor layer can be reduced or eliminated, and the productivity can be improved.

[0137] (Embodiment 6) In this embodiment, in a display device which is a form of the semiconductor device, an example of fabricating a thin film transistor disposed in a pixel portion and at least a part of a drive circuit on the same substrate will be described below. explained.

[0138] The thin film transistor disposed in the pixel portion is formed according to Embodiments 1 to 5. In addition, since the thin film transistors shown in Embodiments 1 to 5 are n-channel type TFTs, a part of the drive circuit that can be configured by n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion.

[0139] An example of a block diagram of an active matrix type liquid crystal display device which is a form of the semiconductor device is shown in FIG. 5(A). The display device shown in FIG. 5(A) includes a pixel portion 5301 having a plurality of pixels provided with display elements on a substrate 5300, a scanning line drive circuit 5302 for selecting each pixel, and a signal line drive circuit 5303 for controlling the input of a video signal to the selected pixel. pixels.

[0140] The pixel portion 5301 is connected to the signal line drive circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction from the signal line drive circuit 5303, and is connected to the scanning line drive circuit 5302 by a plurality of scanning lines G1 to Gn (not shown) extending in the row direction from the scanning line drive circuit 5302. It is connected to the scanning line driving circuit 5302 and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn). Moreover, the thin film transistors shown in Embodiments 1 to 5 are n-channel type TFTs, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to FIG. 6. The signal line driving circuit shown in FIG. 6 includes a driver IC 5601, a switch group 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c. And is connected to the scanning line driving circuit 5302 and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

[0141] Moreover, the thin film transistors shown in Embodiments 1 to 5 are n-channel type TFTs, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to FIG. 6. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

[0142] The signal line driving circuit shown in FIG. 6 includes a driver IC 5601, a switch group 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The switch groups 5602_1 to 5602_M each have a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

[0143] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines (signal line Sm - 2, signal line Sm - 1, signal line S) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. It is connected to m (m = 3M)). For example, the wiring 5621_J in the J-th column (any one of the wirings 5621_1 ~ 5621_M) is connected to the signal lines Sj-2, Sj-1, and Sj (j = 3J) via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c in the switch group 5602_J. Continued.

[0144] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0145] Note that the driver IC 5601 is preferably formed using a single crystal semiconductor. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 56 02_M may be formed on different substrates and connected to each other via an FPC or the like. Alternatively, a single crystal semiconductor layer may be provided by bonding or the like on the same substrate as the pixel portion, and the driver IC 5 601 may be formed.

[0146] Next, the operation of the signal line driving circuit shown in FIG. 6 will be described with reference to the timing chart of FIG. 7. The timing chart of FIG. 7 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 6 operates in the same manner as FIG. 7 even when the scanning lines of other rows are selected.

[0147] ​​​​​​​​Note that the timing chart in Fig. 7 shows the case where the wiring 5621_J in the J column is connected to the signal line Sj-2, the signal line Sj-1, and the signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart in Fig. 7 shows the case where the wiring 5621_J in the J column is connected to the signal line Sj-2, the signal line Sj-1, and the signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. is shown.

[0148] Note that the timing chart in Fig. 7 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J column. 5603a, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J column. 5603b, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J column. 5603c, and the signal 5721_J input to the wiring 5621_J in the J column. is shown.

[0149] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively. 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-2, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-2, Data_j-1, and Data_j, respectively.

[0150] As shown in Fig. 7, during the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-2 input to the wiring 5621_J is input to the signal line Sj-2 via the first thin film transistor 5603a. In the second sub-selection period T2 the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j−1 input to the wiring 5621_J is input to the signal line Sj−1 via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the third thin film transistor 5 603c.

[0151] From the above, the signal line driving circuit in FIG. 6 divides one gate selection period into three, and can input video signals from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 6 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to approximately 1 / 3 compared to the number of signal lines. By reducing the number of connections to approximately 1 / 3, the signal line driving circuit in FIG. 6 can improve reliability, yield, etc. Note that as shown in FIG. 6, if one gate selection period is divided into a plurality of sub-selection periods, and in each of the plurality of sub-selection

[0152] periods, video signals can be input from one wiring to each of a plurality of signal lines, the arrangement, number, driving method, etc. of the thin film transistors are not limited. periods, and video signals can be input from one wiring to each of a plurality of signal lines, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0153] For example, when inputting video signals from one wiring to three or more signal lines respectively in each of three or more sub-selection periods, thin film transistors and wiring for controlling the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. As another example, as shown in the timing chart of FIG. 8, one selection period may be divided into a precharge

[0154] period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Further, the timing chart of FIG. 8 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 8, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-2, the signal lines Sj-1, and the signal line Sj through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. transistor 5603b and the third thin film transistor 5603c are turned off. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, the Data_j input to the wiring 5621_J is turned off. −2 is input to the signal line Sj-2 via the first thin film transistor 5603a. In the sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j-1 input to 5621_J is input through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin-film transistor The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j input to the wiring 5621_J is the third The signal is input to the signal line Sj via the thin film transistor 5603c.

[0155] From the above, the signal line driver circuit of FIG. 6 to which the timing chart of FIG. 8 is applied By providing a precharge selection period before the selection period, the signal line can be precharged. Therefore, the video signal can be written to the pixel at high speed. The same reference numerals are used to denote the same parts or parts having similar functions as those in FIG. A detailed description of the relevant parts will be omitted.

[0156] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP ) is input, the selection signal is generated. The generated selection signal is buffered is buffer-amplified and supplied to the corresponding scanning line. The scanning line is connected to the gate electrodes of the transistors for one line of pixels. And since the transistors for one line of pixels must be turned on all at once, a buffer that can pass a large current is used. One form of the shift register used as part of the scanning line drive circuit will be described with reference to FIGS. 9 and 10. Since the transistors for one line of pixels must be turned on all at once, a buffer that can pass a large current is used. used.

[0157] One form of the shift register used as part of the scanning line drive circuit will be described with reference to FIGS. 9 and 10. described.

[0158] FIG. 9 shows the circuit configuration of the shift register. The shift register shown in FIG. 9 is composed of a plurality of flip-flops 5701_1 to 5701_n. Also, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and operate. of flip-flops 5701_1 to 5701_n. Also, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and operate. The first clock signal, the second clock signal, the start pulse signal, and the reset signal are input and operate. operate.

[0159] The connection relationship of the shift register in FIG. 9 will be described. The first-stage flip-flop 5701_1 is connected to the first wiring 5711, the second wiring 5712, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. _1 is connected to the first wiring 5711, the second wiring 5712, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. 715, the seventh wiring 5717_1, and the seventh wiring 5717_2. Also, the second-stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. stage flip-flop 5701_2 is connected to the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. 5 of the fifth wiring 5715, the seventh wiring 5717_1, the seventh wiring 5717_2, and the seventh wiring 5717_3. 717_3.

[0160] Similarly, the i-th stage flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) is either the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_i-1, the seventh wiring 5 01_n) is either the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_i-1, the seventh wiring 5 714, the fifth wiring 5715, the seventh wiring 5717_i-1, the seventh wiring 5 717_i is connected to the seventh wiring 5717_i+1. Here, when i is odd the flip-flop 5701_i at the i-th stage is connected to the second wiring 5712, and when i is even the flip-flop 5701_i at the i-th stage is connected to the third wiring 5713 will be.

[0161] Also, the flip-flop 5701_n at the n-th stage is connected to one of the second wiring 5712 or the third wiring 5713, the fourth wiring 5714, the fifth wiring 5715, the seventh wiring 5717_n- 1, the seventh wiring 5717_n, and the sixth wiring 5716.

[0162] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be respectively referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be respectively referred to as the first power supply line and the second power supply line.

[0163] Next, the details of the flip-flop shown in FIG. 9 will be described with reference to FIG. 10. In FIG. 10 the flip-flop shown has the first thin film transistor 5571, the second thin film transistor 5 572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5 577, and the eighth thin film transistor 5578. Note that the first thin film transistor 5 571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5 576. The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel type transistors, and are assumed to be in the conducting state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth ).

[0164] Also, the flip-flop shown in FIG. 10 includes a first wiring 5501, a second wiring 5502, a third wiring 5503, a fourth wiring 5504, a fifth wiring 5505, and a sixth wiring 5506 .

[0165] Here, all the thin film transistors are shown as enhancement-type n-channel transistors, but are not particularly limited. For example, a depletion-type n-channel transistor can also be used to drive the drive circuit.

[0166] Next, the connection configuration of the flip-flop shown in FIG. 10 is shown below.

[0167] The first electrode (either the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0168] The first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

[0169] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 is connected, and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505 is done.

[0170] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth The second electrode of the thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572 is connected, and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0171] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the fifth The second electrode of the thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 is done.

[0172] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth The second electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0173] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh The second electrode of the thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 is done.

[0174] The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506, and the eighth The second electrode of the thin film transistor 5578 is the gate electrode of the second thin film transistor 5572 and is connected, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501 .

[0175] Note that the connection points of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 , the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 are set as the node 5543. Further, the connection points of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573 , the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576 and the second electrode of the eighth thin film transistor 5578 are set as the node 5544 .

[0176] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5 504 may be respectively referred to as the first signal line, the second signal, the third signal line and the fourth signal line. Further, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line .

[0177] In the i-th stage flip-flop 5701_i, the first wiring 5501 in FIG. 10 is connected to the seventh wiring 5717_i - 1 in FIG. 9. Also, the second wiring 5502 in FIG. 10 is connected to the seventh wiring 5717_i + 1 in FIG. 9. Also, the third wiring 5 503 in FIG. 10 is connected to the seventh wiring 5717_i. Further, the sixth wiring 550 6 in FIG. 10 is connected to the fifth wiring 5715 .

[0178] ​​When i is odd, the fourth wiring 5504 in FIG. 10 is connected to the second wiring 5712 in FIG. 9. When i is even, it is connected to the third wiring 5713 in FIG. 9. Also, the fifth wiring 5505 in FIG. 10 is connected to the fourth wiring 5714 in FIG. 9.

[0179] However, in the first-stage flip-flop 5701_1, the first wiring 5501 in FIG. 10 is connected to the first wiring 5711 in FIG. 9. Also, in the nth-stage flip-flop 5701_n, the second wiring 5502 in FIG. 10 is connected to the sixth wiring 5716 in FIG. 9.

[0180] Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel TFTs shown in Embodiments 1 to 5. Since the n-channel TFTs shown in Embodiments 1 to 5 have a high mobility of transistors, it is possible to increase the driving frequency of the driving circuit. That is, by using an oxide semiconductor layer for the n-channel TFTs shown in Embodiments 1 to 5, it is possible to improve the frequency characteristics (referred to as f characteristics). For example, since the scanning line driving circuit using the n-channel TFTs shown in Embodiments 1 to 5 can operate at high speed, it is possible to realize black screen insertion by increasing the frame

[0181] Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving The line inspection drive circuit is arranged on one side, and the scan line drive circuit for driving the scan lines of odd rows is arranged on the opposite side, thereby enabling the frame frequency to be increased. Also, when a plurality of scan line drive circuits output signals to the same scan line, it is advantageous for the size reduction of the display device. Also, when manufacturing an active matrix light-emitting display device, which is a form of semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scan line drive circuits. An example of a block diagram of an active matrix light-emitting display device is shown in Fig. 5(B).

[0182] The light-emitting display device shown in Fig. 5(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scan line drive circuit 5402 and a second scan line drive circuit 5404 for selecting each pixel, and a signal line drive circuit 5403 for controlling the input of video signals to the selected pixels. When the video signal input to the pixels of the light-emitting display device shown in Fig. 5(B) is in digital format,

[0183] the pixels are turned on and off by transistors to be in a light-emitting or non-light-emitting state. Therefore, gradation display can be performed using an area gradation method or a time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. Also, the time gradation method is a driving method for performing gradation display by controlling the period during which the pixels emit light.

[0184] Since the light-emitting element has a higher response speed than a liquid crystal element, etc., it is more suitable for the time gradation method than the liquid crystal element.

[0185] Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting elements of the pixels are made to be in a light-emitting or non-light-emitting state in each sub-frame period. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixels actually emit light within one frame period can be controlled by the video signal, and gradation can be displayed. In the light-emitting display device shown in FIG. 5(B), when two switching TFTs are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit together. Also, for example, depending on the number of switching TFTs that one pixel has, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements. In this case, the signals input to the plurality of scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. Further, also in the light-emitting display device, a part of the driving circuit that can be configured by n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin film transistors in the pixel portion. Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiment 1 to Embodiment 5. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixels actually emit light within one frame period can be controlled by the video signal, and gradation can be displayed. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting elements of the pixels are made to be in a light-emitting or non-light-emitting state in each sub-frame period.

[0186] In the light-emitting display device shown in FIG. 5(B), when two switching TFTs are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit together. Also, for example, depending on the number of switching TFTs that one pixel has, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements. In this case, the signals input to the plurality of scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. Further, also in the light-emitting display device, a part of the driving circuit that can be configured by n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin film transistors in the pixel portion. Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiment 1 to Embodiment 5. In the light-emitting display device shown in FIG. 5(B), when two switching TFTs are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit together. Also, for example, depending on the number of switching TFTs that one pixel has, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements. In this case, the signals input to the plurality of scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. Further, also in the light-emitting display device, a part of the driving circuit that can be configured by n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin film transistors in the pixel portion. Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiment 1 to Embodiment 5.

[0187] Further, also in the light-emitting display device, a part of the driving circuit that can be configured by n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin film transistors in the pixel portion. Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiment 1 to Embodiment 5. In the light-emitting display device shown in FIG. 5(B), when two switching TFTs are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit together. Also, for example, depending on the number of switching TFTs that one pixel has, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements.

[0188] Further, the drive circuit described above is not limited to liquid crystal display devices and light-emitting display devices, and may also be used for electronic paper that drives electronic ink using a switching element and an element electrically connected thereto. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as readability comparable to that of paper, low power consumption compared to other display devices, and the ability to be thin and lightweight. (Embodiment 7) The thin film transistors shown in Embodiments 1 to 5 can be fabricated, and a semiconductor device (also referred to as a display device) having a display function can be fabricated by using the thin film transistors in a pixel portion and further in a drive circuit. Further, part or all of the drive circuit can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0189] (Embodiment 7) The thin film transistors shown in Embodiments 1 to 5 can be fabricated, and a semiconductor device (also referred to as a display device) having a display function can be fabricated by using the thin film transistors in a pixel portion and further in a drive circuit. Further, part or all of the drive circuit can be integrally formed on the same substrate as the pixel portion to form a system-on-panel. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, any electronic ink or a display medium whose contrast changes by an electrical action can be used.

[0190] The display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, the display device can be fabricated. Also, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, the display device can be fabricated. Also, any electronic ink or a display medium whose contrast changes by an electrical action can be used.

[0191] The display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, the display device can be fabricated. Regarding the element substrate corresponding to a form before the display element is completed in the process, the element substrate is provided with means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or it may be in a state after forming a conductive film to be the pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0192] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, connectors such as FPC (Flexible Pr inted Circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) attached modules, modules with a printed wiring board provided at the end of the TAB tape or TCP, or modules with an IC (integrated circuit) directly mounted on the display element by the COG (Chip On Glass) method are all included in the display device.

[0193] In this embodiment, the appearance and cross-section of the liquid crystal display panel corresponding to a form of the semiconductor device will be described with reference to FIG. 11. FIGS. 11(A1)(A2) are highly reliable thin films using the oxide semiconductor layers shown in Embodiments 1 to 5 formed on the first substrate 4001 transistors 4010, 4011, and liquid crystal element 4013, sealed with a sealing material 4005 between the second substrate 4006, and is a top view of the panel. FIG. 11(B) corresponds to the cross-sectional view at M-N in FIGS. 11 (A1)(A2). (A1)(A2).

[0194] ​​​​The pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 are surrounded by a sealing material 4005 is provided in such a manner. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0195] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 11(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 11(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0196] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 11(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are exemplified. Insulating layers 4020 and 402 1 are provided on the thin film transistors 4010 and 4011.

[0197] The thin film transistors 4010 and 4011 can be applied to the highly reliable thin film transistors shown in Embodiment Modes 1 to 5 using an oxide semiconductor layer. In this embodiment mode In this case, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. .

[0198] Also, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0199] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0200] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. It is possible to electrically connect the counter electrode layer 40 31 and the common potential line through the conductive particles disposed between the pair of substrates using the common connection portion. Note that the conductive particles are contained in the sealing material 40 05.

[0201] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range . A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 10 μs to 10 0 μs, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0202] Note that the present embodiment is an example of a transmissive liquid crystal display device, but the present invention can also be used for a reflective liquid crystal display device and a transflective liquid crystal display device.

[0203] Also, in the liquid crystal display device of the present embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate . Also, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Further, a light-shielding film functioning as a black matrix may be provided.

[0204] Also, in the present embodiment, in order to reduce the surface unevenness of the thin film transistor and to improve the reliability of the thin film transistor , the thin film transistors obtained in Embodiments 1 to 5 are used The dissta is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a planarizing insulating film. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and a dense film is preferable. The protective film may be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing the hillock of the aluminum film used as the source electrode layer and the drain electrode layer.

[0205]

[0206]

[0207] Also, annealing (300°C to 400°C) of the oxide semiconductor layer may be performed after forming the protective film.

[0208] ​​​​​​​​​​​​​​Organic materials with heat resistance, such as mid, acrylic, benzocyclobutene, polyamide, and epoxy, can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) , siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0209] The siloxane resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

[0210] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method , spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, annealing (300 °C to 400 °C) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0211] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter, referred to as ITO). Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0212] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0213] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0214] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0215] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 30. The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0216] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0217] In FIG. 11, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0218] FIG. 12 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by applying the TFTs shown in Embodiments 1 to 5.

[0219] FIG. 12 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display area. The coloring layer 2605 is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer.

[0220] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode. n-Plane-Switching) mode, FFS (Fringe Field Switching) mode Switching mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. lignment) mode, PVA (Patterned Vertical Alig nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0221] Through the above steps, a highly reliable liquid crystal display panel can be fabricated as a semiconductor device. can be fabricated.

[0222] Note that the configurations shown in this embodiment can be used in appropriate combinations with the configurations shown in other embodiments. shall be used. (Embodiment 8)

[0223] In this embodiment, as an example of a semiconductor device applying the thin film transistors shown in Embodiments 1 to 5, an example of an electronic paper is shown. shall be shown as an example of an electronic paper.

[0224] FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. As the thin film transistor 581 used in the semiconductor device, the thin film transistors shown in Embodiments 1 to 5 can be applied. shall be applied. The thin film transistors shown in Embodiments 1 to 5 can be applied.

[0225] The electronic paper in FIG. 13 is an example of a display device using the twisted ball display method. The twisted ball display method is an electrode layer that uses spherical particles painted white and black as display elements. shall be an electrode layer that uses spherical particles painted white and black as display elements. It is arranged between the first electrode layer and the second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of spherical particles, thereby performing display. This is a method of performing display by controlling the orientation of spherical particles by generating a potential difference.

[0226] The thin film transistor 581 formed on the substrate 596 is a thin film transistor with a bottom gate structure, and is in contact with and electrically connected to the first electrode layer 587 through the source electrode layer or the drain electrode layer. There is a cavity 594 having black regions 590a and white regions 590b and filled with liquid around it between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 597. Spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In the present embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. The thin film transistor 581 formed on the substrate 596 is a thin film transistor with a bottom gate structure, and is in contact with and electrically connected to the first electrode layer 587 through the source electrode layer or the drain electrode layer. There is a cavity 594 having black regions 590a and white regions 590b and filled with liquid around it between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 597. Spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In the present embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. 85 and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 5 97, there are spherical particles 589 having black regions 590a and white regions 59 0b and having a cavity 594 filled with liquid around it, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 13). In the present embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second The electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. The electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. It is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates. It is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. Using any one of the common connection portions shown in Embodiments 1 to 5, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates.

[0227] Also, instead of the twist ball, an electrophoresis element can be used. A microcapsule having a diameter of about 10 μm to 2 00 μm, which encapsulates a transparent liquid, positively charged white fine particles, and negatively charged black fine particles, is used. When an electric field is applied to the microcapsules provided between the first electrode layer and the second electrode layer by the first electrode layer and the second electrode layer, The white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. The microcapsules provided between the first electrode layer and the second electrode layer can display white or black when an electric field is applied by the first electrode layer and the second electrode layer, causing the white fine particles and the black fine particles to move in opposite directions. The white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element that applies the principle of is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required. Also, the power consumption is small, and it is possible to recognize the display section even in a dim place. In addition, even when the power supply is not supplied to the display section, it is possible to hold the image once displayed. Therefore, even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is moved away from the radio wave transmission source, the displayed image can be saved.

[0228] The electrophoretic display element is a display element that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The electrophoretic display element does not require a polarizing plate that is necessary for a liquid crystal display device, and the thickness and weight can be reduced compared to a liquid crystal display device.

[0229] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having color filters or dyes.

[0230] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 5 can be used.

[0231] ​​​​​Note that the fine particles in the microcapsules may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material , a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and one kind of material selected from a magnetophoretic material, or a composite material thereof may be used.

[0232] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0233] (Embodiment 9) In this embodiment, an example of a light-emitting display device is shown as one form of a semiconductor device to which the thin-film transistors shown in Embodiments 1 to 5 are applied. As a display element included in the display device, a light-emitting element using electroluminescence is shown here. The light-emitting element using electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element. Here, it is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that utilizes electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element. The light-emitting element that utilizes electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element. The light-emitting element that utilizes electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0234] In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0235] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. ​It is a device that uses a donor-acceptor recombination type of luminescence mechanism that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the luminescence mechanism is a localized luminescence that utilizes the inner-shell electron transition of metal ions. Here, an organic EL element is used as the light-emitting element for explanation. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the luminescence mechanism is a localized luminescence that utilizes the inner-shell electron transition of metal ions. Here, an organic EL element is used as the light-emitting element for explanation. Figure 14 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device to which the present invention is applied. The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an example in which two n-channel transistors using an oxide semiconductor layer as a channel formation region shown in Embodiments 1 to 5 are used in one pixel is shown.

[0236] The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The gate of the switching transistor 6401 is connected to the scanning line 6406, one of the first electrodes (either the source electrode and the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has a gate connected to the power supply line 6407 via the capacitive element 6403, one of the first electrodes connected to the power supply line 6407, and the other of the second electrodes connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. Figure 14 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device to which the present invention is applied.

[0237] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an example in which two n-channel transistors using an oxide semiconductor layer as a channel formation region shown in Embodiments 1 to 5 are used in one pixel is shown. Here, an example in which two n-channel transistors using an oxide semiconductor layer as a channel formation region shown in Embodiments 1 to 5 are used in one pixel is shown. Here, an example in which two n-channel transistors using an oxide semiconductor layer as a channel formation region shown in Embodiments 1 to 5 are used in one pixel is shown.

[0238] The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The gate of the switching transistor 6401 is connected to the scanning line 6406, one of the first electrodes (either the source electrode and the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has a gate connected to the power supply line 6407 via the capacitive element 6403, one of the first electrodes connected to the power supply line 6407, and the other of the second electrodes connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The gate of the switching transistor 6401 is connected to the scanning line 6406, one of the first electrodes (either the source electrode and the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The gate of the switching transistor 6401 is connected to the scanning line 6406, one of the first electrodes (either the source electrode and the drain electrode) is connected to the signal line 6405, and the other of the second electrodes (the other of the source electrode and the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has a gate connected to the power supply line 6407 via the capacitive element 6403, one of the first electrodes connected to the power supply line 6407, and the other of the second electrodes connected to the first electrode (pixel electrode) of the light-emitting element 6404. The driving transistor 6402 has a gate connected to the power supply line 6407 via the capacitive element 6403, one of the first electrodes connected to the power supply line 6407, and the other of the second electrodes connected to the first electrode (pixel electrode) of the light-emitting element 6404. The driving transistor 6402 has a gate connected to the power supply line 6407 via the capacitive element 6403, one of the first electrodes connected to the power supply line 6407, and the other of the second electrodes connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0239] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential that satisfies < high power supply potential with respect to the high power supply potential set on the power supply line 6407, and for example, GND, 0V, etc. may be set as the low power supply potential. This potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or higher than the forward threshold voltage of the light-emitting element 6404.

[0240] Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

[0241] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

[0242] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 14 can be used by changing the signal input.

[0243] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0244] Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0245] Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 15(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are It can be fabricated in the same manner as the thin film transistors shown in the first to fifth embodiments. Highly reliable thin-film transistors using oxide semiconductor layers, such as nO-based non-single crystal films It is.

[0246] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top surface emission takes the light out from the surface on the substrate side, the bottom surface emission takes the light out from the surface on the substrate side, There are light emitting devices with a dual-side emission structure in which light is emitted from the opposite surface. The present invention can also be applied to a light emitting device having a light emitting structure.

[0247] A light emitting element having a top emission structure will be described with reference to FIG.

[0248] In FIG. 15A, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 15(A) shows a cross-sectional view of a pixel when the light incident on the pixel is guided to the anode 7005 side. A cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. 004 may be composed of a single layer or may be composed of multiple layers stacked together. In the case where the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a The light-transmitting layer, the light-emitting layer, the hole-transporting layer, and the hole-injecting layer are laminated in this order. The anode 7005 is formed using a light-transmitting conductive material. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and silicon oxide are added. A light-transmitting conductive film such as indium tin oxide added may also be used.

[0249] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 15(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow.

[0250] Next, the light-emitting element having a bottom emission structure will be described with reference to FIG. 15(B). FIG. 15(B) shows a cross-sectional view of a pixel when the driving TFT 7011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. In FIG. 15(B), the cathode 7013 of the light-emitting element 7012 is formed on a light-transmitting conductive film 7017 electrically connected to the driving TFT 7011. The light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7015 has light-transmitting properties, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. Similar to the case of FIG. 15(A), the cathode 7013 can be made of various conductive materials having a small work function. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer or a plurality of laminated layers, similar to the case of FIG. 15(A). The anode 7015 does not necessarily need to transmit light, but can be formed using a light-transmitting conductive material as in the case of FIG. 15(A). The shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. ​​​​​​​​This is not the case. For example, a resin to which a black pigment is added can also be used.

[0251] In the cathode 7013 and the anode 7015, the region sandwiching the light-emitting layer 7014 is the light-emitting element 7012 corresponds to. In the case of the pixel shown in Fig. 15(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0252] Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 15(C). Fig. 15(C) shows that on the light-transmissive conductive film 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and the light-emitting layer 7024 and the anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023, similar to the case of Fig. 15(A), can use various materials as long as they are conductive materials with a small work function. However, its film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024, similar to Fig. 15(A), can be composed of a single layer or can be configured such that a plurality of layers are laminated. The anode 70 25, similar to Fig. 15(A), can be formed using a light-transmissive conductive material that allows light to pass through .

[0253] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in Fig. 15(C), the light emitted from the light-emitting element 7022 is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrow.

[0254] Here, although the organic EL element has been described as the light-emitting element, an inorganic E It is also possible to provide an L element.

[0255] In this embodiment, an example in which a thin film transistor (driving TFT) for controlling the driving of a light emitting element and the light emitting element are electrically connected is shown. However, a configuration in which a current control TFT is connected between the driving TFT and the light emitting element may also be used.

[0256] The semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 15, and various modifications based on the technical idea of the present invention are possible.

[0257] Next, regarding the appearance and cross section of a light emitting display panel (also referred to as a light emitting panel) corresponding to one form of the semiconductor device to which the thin film transistors shown in Embodiments 1 to 5 are applied, FIG. 16 will be used for explanation. FIG. 16(A) is a top view of the panel in which the thin film transistors and light emitting elements formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 1 6(B) corresponds to the cross-sectional view at H-I in FIG. 16(A).

[0258] A sealing material 4505 is provided so as to surround the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b are sealed together with the filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it is hermetically sealed so as not to be exposed to the outside air. ​​​​​​​​​It is preferable to package (encase) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing.

[0259] Further, the pixel portion 4502, the signal line driving circuits 4503a and 4 503b, and the scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of thin film transistors and, in FIG. 16(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated.

[0260] The thin film transistors 4509 and 4510 can be applied with highly reliable thin film transistors shown in Embodiments 1 to 5 using an oxide semiconductor layer typified by an In-Ga-Zn-O based non-single crystal film. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0261] Further, 4511 corresponds to a light emitting element, and the first electrode layer 4517 which is a pixel electrode included in the light emitting element 4511 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the configuration shown in the present embodiment. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of light extracted from the light emitting element 4511 and the like.

[0262] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side walls of the opening ​​​​​​​It is preferably formed so as to be an inclined surface formed with a continuous curvature.

[0263] The electroluminescent layer 4512 may be configured as a single layer or as a stack of multiple layers. Either is acceptable.

[0264] A protective film may be formed on the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. A protective film may be formed on the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. A protective film may be formed on the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0265] Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a, 4518b. Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a, 4518b. Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a, 4518b.

[0266] In this embodiment, the connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509, 4510. In this embodiment, the connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509, 4510. In this embodiment, the connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509, 4510.

[0267] The connection terminal electrode 4515 is electrically connected through the anisotropic conductive film 4519 to the terminal of the FPC 4518a. The connection terminal electrode 4515 is electrically connected through the anisotropic conductive film 4519 to the terminal of the FPC 4518a.

[0268] The second substrate, which is the substrate positioned in the light extraction direction from the light-emitting element 4511, must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. The second substrate, which is the substrate positioned in the light extraction direction from the light-emitting element 4511, must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. The second substrate, which is the substrate positioned in the light extraction direction from the light-emitting element 4511, must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0269] In addition, as the filler 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler.

[0270] Further, if necessary, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided on the light emitting surface of the light emitting element. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0271] The signal line drive circuits 4503a, 4503b, and the scan line drive circuits 4504a, 4504b may be mounted by a drive circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Further, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or only a part thereof may be separately formed and mounted, and this embodiment is not limited to the configuration of FIG. 16.

[0272] Through the above steps, a highly reliable light emitting display device (display panel) can be manufactured as a semiconductor device.

[0273] Note that the configuration shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0274] (Embodiment 10) ​​​​The semiconductor device applying the thin film transistor shown in Embodiment 1 to Embodiment 5 can be applied as an electronic paper. The electronic paper can be used for electronic devices in any field as long as it can display information. For example, the electronic paper can be used for display on various cards such as electronic books (e-books), posters, in-vehicle advertisements on vehicles such as trains, and credit cards. An example of the electronic device is shown in FIGS. 17 and 18. .

[0275] FIG. 17(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper print, the advertisement is replaced manually, but if electronic paper is used, the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information.

[0276] Also, FIG. 17(B) shows an in-vehicle advertisement 2632 on a vehicle such as a train. When the advertising medium is a paper print, the advertisement is replaced manually, but if electronic paper is used, the advertisement display can be changed in a short time without much manpower. Also, a stable image can be obtained without the display being distorted. Note that the in-vehicle advertisement may be configured to be able to wirelessly transmit and receive information.

[0277] Also, FIG. 18 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2 703 are integrated by a shaft portion 2711, and can perform an opening and closing operation about the shaft portion 2711 as an axis. With such a configuration, it becomes possible to perform operations similar to those of a paper book. ​ It is.

[0278] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By configuring to display different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 18), and an image can be displayed on the left display unit (display unit 2707 in FIG. 18). Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0279] Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, in FIG. 18, an example in which the housing 2701 is provided with an operation unit or the like is shown. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. are provided. The page can be sent by the operation keys 2723. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, etc. may be provided. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0280] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless, it is also possible to purchase and download desired book data, etc. from an electronic book server. Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless, it is also possible to purchase and download desired book data, etc. from an electronic book server. Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. With wireless, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0281] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments.

[0282] (Embodiment 11) The semiconductor device using the thin film transistor shown in Embodiments 1 to 5 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, tele vision devices (also referred to as televisions or television receivers), monitors for computers, etc., digital cameras, digital video cameras, digital photo frames, mobile phones ( also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, large game machines such as pachinko machines, etc.

[0283] FIG. 19(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0284] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. The operation keys 9609 provided on the remote control unit 9610 can be used to operate channels and volume, and to operate the images displayed on the display unit 9603. Further, the remote control unit 9610 may be provided with a display unit 9607 for displaying information output from the remote control unit 9610.

[0285] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, via a modem, can be connected wired or wirelessly By connecting to a communication network, it is also possible to perform one-way (from sender to receiver) or two-way (such as between a sender and a receiver, or between receivers) information communication.

[0286] FIG. 19(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0287] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, and the like. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface to improve the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion unit of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0288] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0289] FIG. 20(A) shows a portable game machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected in an openable and closable manner by a connecting portion 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, FIG. ​​The portable gaming machine shown in Fig. 20(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least the semiconductor device according to the present invention, and other accessory equipment may be appropriately provided. The portable gaming machine shown in Fig. 20(A) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit, and a function of performing wireless communication with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 20(A) are not limited to this, and it can have various functions.

[0290] Fig. 20(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Also, the slot machine 9900 includes other operation means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above , and it may be a configuration including at least one embodiment of the present invention, and other accessory equipment may be appropriately provided.

[0291] Fig. 21(A) shows an example of a mobile phone 1000. The mobile phone 1000 has a housing In addition to the display unit 1002 incorporated in 1001, there are operation buttons 1003, an external connection port 10 04, a speaker 1005, a microphone 1006, etc.

[0292] The mobile phone 1000 shown in Fig. 21(A) can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1002 with a finger or the like. 1002.

[0293] The screen of the display unit 1002 mainly has three modes. The first is the display mode mainly for displaying images, the second is the input mode mainly for inputting information such as characters, and the third is a mode in which the two modes of the display mode and the input mode are mixed. mode and the input mode are mixed.

[0294] For example, when making a call or creating an email, the display unit 1002 can be set to the character input mode mainly for character input, and the input operation of the characters displayed on the screen can be performed. In this case it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

[0295] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000 to detect the inclination, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched. 1002 can be automatically switched.

[0296] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of the image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is a video signal ​If it is data, switch to the display mode; if it is text data, switch to the input mode.

[0297] Also, in the input mode, detect the signal detected by the optical sensor of the display unit 1002, and if there is no input by the touch operation of the display unit 1002 for a certain period, the screen mode may be controlled to switch from the input mode to the display mode.

[0298] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 10 02, fingerprints, palm prints, etc. can be imaged to perform personal authentication. Also, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used in the display unit, finger veins, palm veins, etc. can also be imaged.

[0299] FIG. 21(B) is also an example of a mobile phone. The mobile phone in FIG. 21(B) includes a display device 9410 including a housing 9411, a display unit 9412, and operation buttons 9413, and a communication device 9400 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachably attachable to the communication device 9400 having a telephone function in two directions of the arrow. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange image or input information by wireless communication or wired communication, and each can be charged. 9410 ​ It has a battery.

[0300] Note that the configurations shown in this embodiment can be used by appropriately combining the configurations shown in other embodiments. It is assumed that this is possible.

[0301] (Embodiment 12) In this embodiment, as one form of a semiconductor device to which the thin film transistors shown in Embodiments 1 to 5 are applied, an example of an electronic book will be shown. In this embodiment, an example in which a double-sided display type third display panel 4313 is mounted between a first display panel 4311 and a second display panel 4312 will be described with reference to FIGS. 22(A), (B) and FIG. 23. FIG. 22(A) shows the electronic book in an open state, and FIG. 22(B) shows the electronic book in a closed state. Further, FIG. 23 is a cross-sectional view of the electronic book in the horizontal direction. The electronic book shown in FIGS. 22(A) and (B) includes a first display panel 4311 having a first display unit 4301, a second display panel 4312 having an operation unit 4304 and a second display unit 4307, a third display panel 4313 having a third display unit 4302 and a fourth display unit 4310, and a binding unit 4308 provided at one end of the first display panel 4311, the second display panel 4312, and the third display panel 4313. The third display panel 4313 is inserted between the first display panel 4311 and the second display panel 4312. The electronic book in FIGS. 22(A) and (B) has four display screens of a first display unit 4301, a second display unit 4307, a third display unit 4302, and a fourth display unit 4310.

[0302] The electronic book shown in FIGS. 22(A) and (B) has a first display panel 4311 having a first display unit 4301, a second display panel 4312 having an operation unit 4304 and a second display unit 4307, a third display panel 4313 having a third display unit 4302 and a fourth display unit 4310, and a binding unit 4308 provided at one end of the first display panel 4311, the second display panel 4312, and the third display panel 4313. The third display panel 4313 is inserted between the first display panel 4311 and the second display panel 4312. The electronic book in FIGS. 22(A) and (B) has four display screens of a first display unit 4301, a second display unit 4307, a third display unit 4302, and a fourth display unit 4310.

[0303] The first display panel 4311, the second display panel 4312, and the third display panel 4313 is flexible and easy to bend. Also, by using a plastic substrate for the first display panel 4311 and the second display panel 4312, and a thin film for the third display panel 4313, a thin electronic book can be achieved. That is, as an example in FIG. 23, a cross-sectional view in the horizontal direction of the electronic book is shown. The third display panel 4313 can be an electronic book that is easier to bend than the first display panel 4311 and the second display panel 4312. Therefore, by making the display panel outside the third display panel 4313 hard, it can be handled with the feeling of a book, and damage to the third display panel 4313 can be suppressed. The third display panel 4313 is a double-sided display panel having a third display section 4302 and a fourth display section 4310.

[0304] The third display panel 4313 may use a double-sided injection type display panel, or may use a single-sided injection type display panel bonded together. Also, two liquid crystal display panels with a backlight (preferably a thin EL light emitting panel) sandwiched in between may be used. Also, the electronic books shown in FIGS. 22(A) and (B) include a scan line drive circuit (not shown) that performs display control of the

[0305] first display section 4301, scan line drive circuits 4322a and 4322b that perform display control of the second display section 4307, a scan line drive circuit (not shown) that performs display control of the third display section 4302 and / or the fourth display section 4310, and a signal line drive circuit 4323 that performs display control of the first display section 4301, the second display section 4307, the third display section 4302, and / or the fourth display section 4310. Note that the scan line drive circuit that performs display control of the first display section 4301 is provided on the first display panel 4311, and the scan line drive circuits 4322a and 4322 are provided on the second display panel 4312, and the signal line drive circuit 4323 is provided on the third display panel 4313. b is provided on the second display panel 4312, and the signal line driving circuit 4323 is provided inside the binding part 4308.

[0306] Also, in the electronic book shown in FIGS. 22(A) and (B), the second display panel 4312 has an operation unit 4304, and can associate each function such as a power input switch and a display switching switch.

[0307] Also, the input operation of the electronic book shown in FIGS. 22(A) and (B) is performed by touching the first display unit 4301 or the second display unit 4307 with a finger or an input pen, or by operating the operation unit 4304. In FIG. 22(A), the display button 4309 displayed on the second display unit 4307 is illustrated, and input can be performed by touching it with a finger or the like.

[0308] Also, as an example of how to use the electronic book with the third display panel 4313 inserted shown in FIGS. 22(A) and (B), it is convenient to read the text on the first display unit 4301 and the fourth display unit 4310, and refer to the figures on the second display unit 4307 and the third display unit 4302. At this time, since the third display panel 4313 cannot display the third display unit 4302 and the fourth display unit 4310 simultaneously, when starting to turn the page, the display switches from the third display unit 4302 to the fourth display unit 4310.

[0309] Also, when reading from the first display unit 4301 to the third display unit 4302 and starting to turn the third display panel 4313, the fourth display unit 4310 and the second display unit 4307 display the next page at a certain angle. Also, the fourth display unit 4310 and the second display unit 4 ​​​​​​​​​​​​​When the use of 307 is finished and the third display panel 4313 is started to be turned over, the third display unit 4302 and the first display unit 4301 display the next page at a certain angle. This makes it possible to prevent the screen from being visibly switched and suppress visual discomfort and the like. The display unit 4302 and the first display unit 4301 display the next page. This makes it possible to prevent the screen from being visibly switched and suppress visual discomfort and the like. The display unit 4302 and the first display unit 4301 display the next page. This makes it possible to prevent the screen from being visibly switched and suppress visual discomfort and the like.

[0310] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

Explanation of Reference Numerals

[0311] 100 Substrate 101 Gate electrode 102 Insulating film 103 Semiconductor film 104 Insulating film 105 IGZO semiconductor layer 106 Insulator 107 Contact hole (opening) 108 Source electrode 109 Drain electrode 200 Substrate 201 Gate electrode 202 Insulating film 203 Semiconductor film 204 Insulating film 205 Semiconductor layer 206 Insulator 208 Source electrode 209 Drain electrode 210 Insulating film 211 Metal multilayer film 212 Semiconductor film 213 Source-side buffer layer 214 Drain-side buffer layer 300 Substrate 301 Gate electrode 302 Insulating film 303 Semiconductor film 304 Insulating film 305 Semiconductor layer 306 Insulator 308 Source electrode 309 Drain electrode 310 Insulating film 311 Metal multilayer film 400 Substrate 401 Gate electrode 402 Insulating film 403 Semiconductor film 405 IGZO semiconductor layer 408 Source electrode 409 Drain electrode 410 Insulating film 412 Semiconductor film 413 Source-side buffer layer 414 Drain-side buffer layer 500 Substrate 501 Insulating film 502 Oxide semiconductor film 503 Electrode 510 Sample for physical property evaluation 581 Thin film transistor 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Substrate 597 Substrate 601 Measurement result 602 Measurement result 603 Measurement result 604 Peak 700 Substrate 701 Gate electrode 702 Insulating film 703 Semiconductor film 705 IGZO semiconductor layer 708 Source electrode 709 Drain electrode 710 Insulating film 1000 Mobile phone 1001 Housing 1002 Display unit 1003 Operation button 1004 External connection port 1005 Speaker 1006 Microphone 2600 TFT Substrate 2601 Opposite Substrate 2602 Sealing Material 2603 Pixel Section 2604 Display Element 2605 Coloring Layer 2606 Polarizing Plate 2607 Polarizing Plate 2608 Wiring Circuit Section 2609 Flexible Wiring Substrate 2610 Cold Cathode Tube 2611 Reflector 2612 Circuit Board 2613 Diffusion Plate 2631 Poster 2632 In - vehicle Advertisement 2700 E - book 2701 Housing 2703 Housing 2705 Display Section 2707 Display Section 2711 Shaft Section 2721 Power Switch 2723 Operation Key 2725 Speaker 4001 Substrate 4002 Pixel Section 4003 Signal Line Driving Circuit 4004 Scanning Line Driving Circuit 4005 Sealing Material 4006 Substrate 4008 Liquid Crystal Layer 4010 Thin - film Transistor 4011 Thin - film Transistor 4013 Liquid Crystal Element 4015 Connection Terminal Electrode 4016 Terminal Electrode 4018 FPC 4019 Anisotropic Conductive Film 4020 Insulating Layer 4021 Insulating Layer 4030 Pixel Electrode Layer 4031 Opposite Electrode Layer 4032 Insulating Layer 4301 Display section 4302 Display section 4304 Operation section 4307 Display section 4308 Section 4309 Display button 4310 Display section 4311 Display panel 4312 Display panel 4313 Display panel 4323 Signal line drive circuit 4501 Substrate 4502 Pixel section 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Partition wall 5300 Substrate 5301 Pixel section 5302 Scanning line drive circuit 5303 Signal line drive circuit 5400 Substrate 5401 Pixel section 5402 Scanning line drive circuit 5403 Signal line drive circuit 5404 Scanning line drive circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Wiring 5543 Node 5544 Node 5571 Thin film transistor 5572 Thin film transistor 5573 Thin Film Transistor 5574 Thin Film Transistor 5575 Thin Film Transistor 5576 Thin Film Transistor 5577 Thin Film Transistor 5578 Thin Film Transistor 5601 Driver IC 5602 Switch Group 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 Flip-Flop 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 Wiring 5716 Wiring 5717 Wiring 5721 Signal 5821 Signal 590a Black Region 590b White Region 6400 Pixel 6401 Switching Transistor 6402 Driving Transistor 6403 Capacitor Element 6404 Light-Emitting Element 6405 Signal Line 6406 Scanning Line 6407 Power Supply Line 6408 Common Electrode 7001 TFT 7002 Light-Emitting Element 7003 Cathode 7004 Light-Emitting Layer 7005 Anode 7011 Driving TFT 7012 Light-Emitting Element 7013 Cathode 7014 Light-Emitting Layer 7015 Anode 7016 Masking Film 7017 Conductive Film 7021 TFT for driving 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9400 Communication device 9401 Housing 9402 Scanning button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display part 9413 Operation button 9600 Television device 9601 Housing 9603 Display part 9605 Stand 9607 Display part 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display part 9881 Housing 9882 Display part 9883 Display part 9884 Speaker part 9885 Operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display part 4321a Scanning line drive circuit 4322a Scanning line drive circuit 4503a Signal line drive circuit 4504a Scanning Line Drive Circuit 4518a FPC 5603a Thin Film Transistor 5603b Thin Film Transistor 5603c Thin Film Transistor 5703a Timing 5703b Timing 5703c Timing 5803a Timing 5803b Timing 5803c Timing

Claims

1. A first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region in contact with a top surface of the first insulating layer and including a channel formation region of the transistor; a second insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a second conductive layer having a region located on the second insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer and including silicon oxide; a fourth insulating layer having an area overlying the third insulating layer and comprising an organic material; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a pixel electrode; the second conductive layer is electrically connected to the oxide semiconductor layer through a first opening of the second insulating layer; the third conductive layer is electrically connected to the second conductive layer through a second opening in the third insulating layer and the fourth insulating layer; the second conductive layer has a region in contact with a top surface of the second insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the oxide semiconductor layer in the first opening; an entire region of the first opening overlaps with a top surface of the first conductive layer in a cross-sectional view of the transistor in a channel length direction, and an end portion of the oxide semiconductor layer has a region that does not overlap with the first conductive layer; the second opening does not overlap with the oxide semiconductor layer in a cross-sectional view of the transistor in a channel length direction, The semiconductor device, wherein the oxide semiconductor layer contains indium oxide.

2. A first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region in contact with a top surface of the first insulating layer and including a channel formation region of the transistor; a second insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a second conductive layer having a region located on the second insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; a third insulating layer having a region in contact with an upper surface of the second conductive layer and including silicon oxide; a fourth insulating layer having an area overlying the third insulating layer and comprising an organic material; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and functioning as a pixel electrode; the second conductive layer is electrically connected to the oxide semiconductor layer through a first opening of the second insulating layer; the third conductive layer is electrically connected to the second conductive layer through a second opening in the third insulating layer and the fourth insulating layer; the second conductive layer has a region in contact with a top surface of the second insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the oxide semiconductor layer in the first opening; an entire region of the first opening overlaps with a top surface of the first conductive layer in a cross-sectional view of the transistor in a channel length direction, and an end portion of the oxide semiconductor layer has a region that does not overlap with the first conductive layer; the second opening does not overlap with the oxide semiconductor layer in a cross-sectional view of the transistor in a channel length direction, The semiconductor device, wherein the oxide semiconductor layer includes indium oxide and zinc oxide.

Images