Semiconductor device and method of manufacturing the same

Abstract

To suppress the occurrence of connection failures of the first electrode while suppressing the degradation of the gate insulating film characteristics.SOLUTION: In a trench 16, a rounded portion 161 is formed in a connection opening 160a of the openings, which is covered by the connection portion between the gate electrode 18 and the connection wiring 180. If the portion of the opening in the trench 16 that differs from the connection opening 160a is an unconnected opening, the unconnected opening should have a radius of curvature that is smaller than the radius of curvature of the connection opening 160a.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same.

Background Art

[0002] Conventionally, a semiconductor device in which a semiconductor element such as a MOSFET (abbreviation for metal oxide semiconductor field effect transistor) is formed has been proposed. Specifically, this semiconductor device includes a semiconductor substrate having a drift layer, a base layer is formed on one surface side of the semiconductor substrate, and a source region is formed in the surface layer portion of the base layer. Further, a plurality of trenches penetrating through the source region and the base layer and extending along one direction in the plane direction of the semiconductor substrate are formed in the semiconductor substrate. Then, a trench gate structure is configured by disposing a gate insulating film and a gate electrode in the trench. Note that the opening of the trench has a shape having a corner where the side surface of the trench and one surface of the semiconductor substrate are substantially perpendicular.

[0003] A drain region is disposed on the other surface side of the semiconductor substrate. A first electrode is disposed on one surface side of the semiconductor substrate so as to be electrically connected to the source region and the base layer. A second electrode is disposed on the other surface side of the semiconductor substrate so as to be electrically connected to the drain region. Further, a connection wiring connected to the gate electrode is formed on one surface side of the semiconductor substrate.

[0004] In the semiconductor device as described above, voltage concentration of the gate voltage easily occurs in a portion where the gate electrode and the connection wiring are connected and which is located above the opening of the trench. For this reason, in such a semiconductor device, there is a concern that the characteristics of the gate insulating film disposed at the opening of the trench in a portion where the gate electrode and the connection wiring are connected may deteriorate. Note that the deterioration of the characteristics of the gate insulating film means that the leakage current of the gate insulating film increases, the breakdown voltage of the gate insulating film decreases, or the lifetime of the gate insulating film decreases.

[0005] Therefore, for example, Patent Document 1 proposes a structure in which the opening of the trench is rounded so that voltage concentration is less likely to occur in the vicinity of the opening of the trench. In this structure, the entire area at the opening of the trench is rounded.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, in the semiconductor device as described above, increasing the current capacity by shortening the length between adjacent trenches has been studied. In this case, when the entire area of the opening of the trench is rounded, the area of the source region formed in contact with the trench and the like that is exposed from one surface of the semiconductor substrate is reduced. For this reason, the connectivity between the first electrode and the source region may decrease, resulting in a connection failure.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress a decrease in the characteristics of the gate insulating film and suppress the occurrence of connection failures in the first electrode.

Means for Solving the Problems

[0009] Claim 1 for achieving the above object is a semiconductor device in which a plurality of trench gate structures are formed, comprising a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the drift layer, an impurity region (14) of the first conductivity type formed in the surface layer portion of the base layer, and a high-concentration layer (11) of the first conductivity type or the second conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer. A semiconductor substrate (10) having these components, a plurality of trench gate structures in which a gate insulating film (17) is disposed via a gate electrode (18) in a trench (16) that penetrates the impurity region and the base layer and reaches the drift layer and extends in a predetermined direction with the longitudinal direction, a connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode, a first electrode (20) electrically connected to the base layer and the impurity region, and a second electrode (22) electrically connected to the high-concentration layer. And in the trench, a rounded portion (161) is formed in a connection opening (160a) that is covered by a connection portion between the gate electrode and the connection wiring among the openings. When a portion of the opening of the trench different from the connection opening is an unconnected opening (160b), the unconnected opening has a portion where the radius of curvature is smaller than the radius of curvature of the connection opening and the connection opening is in a direction intersecting the longitudinal direction. When the length between adjacent trenches along the plane direction of the semiconductor substrate is L, the radius of curvature of the rounded portion is less than L / 2 and is.

[0010] According to this, a rounded portion is formed in the connection opening of the trench. For this reason, it is possible to suppress the occurrence of voltage concentration on the connection opening, and it is possible to suppress the deterioration of the characteristics of the gate insulating film.

[0011] Further, the unconnected opening has a portion where the radius of curvature is smaller than the radius of curvature of the connection opening. That is, the unconnected opening has a portion where the opening width is narrower than that of the connection opening. For this reason, it is easy to secure the connection area between the first electrode and the base layer or the impurity region at a portion located between the unconnected openings where the curvature is small among adjacent trenches. Therefore, it is possible to suppress the occurrence of a connection failure of the first electrode.

[0012] Also, claim 2It is a manufacturing method for the semiconductor device according to claim 1, including preparing a semiconductor substrate having a drift layer, a base layer, and an impurity region, forming a trench in the semiconductor substrate, disposing a mask (30) that covers a portion to become an unconnected opening while exposing a portion to become a connection opening among the openings of the trench, and forming a rounded portion in the connection opening of the base layer with the mask disposed.

[0013] According to this, since a rounded portion is formed in the connection opening of the trench, it is possible to suppress the occurrence of voltage concentration at the connection opening, and manufacture a semiconductor device in which the characteristics of the gate insulating film are prevented from degrading.

[0014] Also, the unconnected opening is formed to have a portion where the radius of curvature is smaller than that of the connection opening. Therefore, in a portion located between the unconnected openings with a smaller curvature among adjacent trenches, it is easy to secure the connection area between the first electrode and the base layer or the impurity region. Accordingly, it is possible to manufacture a semiconductor device in which poor connection of the first electrode is suppressed.

[0015] Note that the reference signs with parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 6C

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 8E

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

[0018] (First Embodiment) The first embodiment will be described with reference to the drawings. Note that the semiconductor device of this embodiment is preferably applied, for example, as a device mounted on a vehicle such as an automobile and for driving various in-vehicle electronic devices. In this embodiment, a semiconductor device in which a trench gate structure is formed on a semiconductor substrate 10 made of silicon carbide (hereinafter also referred to as SiC) will be described.

[0019] As shown in FIG. 1, the semiconductor device of this embodiment has a cell region 1 in which a MOSFET having a trench gate structure is formed, and an outer peripheral region 2 surrounding the cell region 1. Although the configuration of the outer peripheral region 2 will not be specifically described, in this embodiment, an FLR (abbreviation for Field Limiting Ring) portion 2a formed in a frame shape so as to surround the cell region 1 is formed in the outer peripheral region 2. FIG. 1 is a plan view in which an interlayer insulating film 19, an upper electrode 20, etc., which will be described later, are appropriately omitted. Further, although FIG. 1 is not a cross-sectional view, for easy understanding, hatching is applied to the gate insulating film 17 and the gate electrode 18, which will be described later.

[0020] As shown in FIGS. 2 to 4, the semiconductor device is configured using a semiconductor substrate 10 made of SiC. Specifically, the semiconductor substrate 10 has an n + -type substrate 11 made of SiC. On the surface of the substrate 11, an n - -type drift layer 12 and a p-type base layer 13 made of SiC are sequentially epitaxially grown. And in the surface layer portion of the base layer 13, an n + -type source region 14 and a p + -type contact region 15 are formed. Although it will be specifically described later, the source region 14 is formed so as to be in contact with the side surface of a trench 16 to be described later, and the contact region 15 is formed on the side opposite to the trench 16 across the source region 14. In this embodiment, the substrate 11 corresponds to a high-concentration layer, and the source region 14 corresponds to an impurity region.

[0021] The substrate 11 has, for example, an n-type impurity concentration of 1.0×10 19 / cm3 and the surface is a (0001) Si plane. The drift layer 12 has, for example, an n-type impurity concentration of 0.5 to 2.0×10 16 / cm 3 and a thickness of 5 to 14 μm. In this embodiment, the substrate 11 constitutes the drain layer in the MOSFET.

[0022] The base layer 13 is a portion where the channel region is formed. For example, the p-type impurity concentration is 3.0×10 17 / cm 3 or so, and the thickness is 0.5 to 2 μm. The source region 14 has a higher impurity concentration than the drift layer 12. For example, the n-type impurity concentration in the surface layer portion is 2.5×10 18 ~1.0×10 19 / cm 3 and the thickness is 0.5 to 2 μm. The contact region 15 has a higher impurity concentration than the base layer 13, and the p-type impurity concentration is 1.0×10 18 / cm 3 ~1.0×10 20 / cm 3 Note that the impurity concentrations and film thicknesses of the drift layer 12, the base layer 13, the source region 14, and the contact region 15 are arbitrary and are not limited to the above.

[0023] And a plurality of trenches 16 are formed in the semiconductor substrate 10 so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12. For this reason, the source region 14 is formed in a state of being in contact with the side surfaces of the respective trenches 16.

[0024] The plurality of trenches 16 extend in one direction in the plane direction of the semiconductor substrate 10 as the longitudinal direction, and are formed in a stripe shape arranged at equal intervals in a direction intersecting the longitudinal direction. In the present embodiment, the plurality of trenches 16 extend in the left-right direction of the paper in FIG. 1 and are arranged in the up-down direction of the paper. Hereinafter, the arrangement direction of the plurality of trenches 16 is also simply referred to as the arrangement direction. Note that the source region 14 and the contact region 15 are formed so as to terminate inside the trench 16 in the longitudinal direction of the trench 16.

[0025] A gate insulating film 17 is formed on the inner wall surface of the trench 16. A gate electrode 18 made of doped polysilicon is formed on the surface of the gate insulating film 17. Then, the trench 16 is filled with these gate insulating film 17 and gate electrode 18. In the present embodiment, a trench gate structure is configured in this way.

[0026] Note that the gate insulating film 17 is also formed on the surfaces other than the inner wall surface of the trench 16. Specifically, as shown in FIG. 2, the gate insulating film 17 is formed so as to cover a part of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 17 is formed so as to cover a part of the surface of the source region 14. In other words, a contact hole 17a for exposing the source region 14 and the contact region 15 is formed in the gate insulating film 17. However, in the present embodiment, as shown in FIGS. 3 and 4, on the end side in the longitudinal direction of the trench 16, the gate insulating film 17 is formed so as to cover the base layer 13, the source region 14, and the contact region 15.

[0027] Then, in the present embodiment, on the end side in the longitudinal direction of the trench 16, the gate electrode 18 is drawn out to the upper surface of the one surface 10a of the semiconductor substrate 10, and the drawn-out portion is used as a connection wiring 180. Note that the connection wiring 180 of the present embodiment extends along the arrangement direction so as to connect adjacent gate electrodes 18 along the arrangement direction.

[0028] Here, as shown in FIGS. 3 and 4, at the opening of the trench 16 (i.e., the shoulder on the side opposite to the bottom), a portion covered at the connection portion between the gate electrode 18 and the connection wiring 180 is defined as the connection opening 160a. In other words, the portion of the opening of the trench 16 that overlaps with the connection wiring 160 is defined as the connection opening 160a. Further, as shown in FIG. 2, at the opening of the trench 16, a portion different from the connection opening 160a is defined as the unconnected opening 160b. In this case, in the present embodiment, as shown in FIGS. 3 and 4, the connection opening 160a has a rounding portion 161 formed for rounding the opening. On the other hand, as shown in FIG. 2, the unconnected opening 160b does not have the rounding portion 161 formed, and the angle formed by the side surface of the trench 16 and the one surface 10a of the semiconductor substrate 10 is substantially perpendicular.

[0029] Therefore, the unconnected opening 160b has a smaller radius of curvature than the connection opening 160a. In other words, the unconnected opening 160b has a narrower opening width than the connection opening 160a. And on the one surface 10a of the semiconductor substrate 10, in terms of the length between adjacent trenches 16 along the arrangement direction, the length L1 of the portion located between the connection openings 160a is shorter than the length L2 of the portion located between the unconnected openings 160b. Hereinafter, adjacent trenches 16 along the arrangement direction are simply referred to as adjacent trenches 16.

[0030] Also, in the present embodiment, when the length between adjacent trenches 16 is L, the rounding portion 161 is formed such that the radius of curvature of the rounding portion 161 is less than L / 2. That is, the rounding portion 161 is formed such that at least the length L1 is not zero. In other words, the rounding portion 161 is formed such that a pointed portion is not formed between adjacent trenches 16.

[0031] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 19 is formed so as to cover the source region 14, the contact region 15, the gate electrode 18, the connection wiring 180, and the like. Then, as shown in FIG. 2, in the interlayer insulating film 19, a contact hole 19a communicating with the contact hole 17a and exposing the source region 14 and the contact region 15 is formed. Further, as shown in FIG. 4, in the interlayer insulating film 19, a contact hole 19b exposing the connection wiring 180 is formed. In the present embodiment, on the end side in the longitudinal direction of the trench 16, the contact hole 19a for exposing the source region 14 and the contact region 15 is not formed.

[0032] On the interlayer insulating film 19, as shown in FIG. 2, an upper electrode 20 electrically connected to the source region 14 and the contact region 15 through the contact holes 17a and 19a is formed. In the present embodiment, the upper electrode 20 is composed of, for example, a plurality of metals such as Ni / Al. And the part in contact with the part constituting the n-type SiC (that is, the source region 14) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the n-type SiC. Also, at least the part in contact with the p-type SiC (that is, the contact region 15) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the p-type SiC. In the present embodiment, the upper electrode 20 corresponds to the first electrode.

[0033] Further, on the interlayer insulating film 19, as shown in FIG. 4, a gate wiring 21 connected to the connection wiring 180 through the contact hole 19b is formed. The gate wiring 21 may be composed of the same material as the upper electrode 20 or may be composed of a different material.

[0034] Note that, as described above, in the interlayer insulating film 19, the contact hole 19a is not formed on the end side in the longitudinal direction of the trench 16. For this reason, the source region 14 and the contact region 15 on the end side in the longitudinal direction of the trench 16 are not directly connected to the upper electrode 20.

[0035] On the back side of the substrate 11, a lower electrode 22 corresponding to a second electrode electrically connected to the substrate 11 is formed. In the present embodiment, a MOSFET having a trench gate structure of an n-channel type and an inversion type is configured with such a structure.

[0036] The above is the configuration of the semiconductor device in the present embodiment. In the present embodiment, the n + type and the n - type correspond to the first conductivity type, and the p - type, the p-type, and the p + type correspond to the second conductivity type. Also, as described above, the semiconductor substrate 10 of the present embodiment is configured to include the substrate 11, the drift layer 12, the base layer 13, the source region 14, the contact region 15, and the like.

[0037] Next, the operation and effects of the semiconductor device will be described. In such a semiconductor device, when a gate voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 18, an n-type inversion layer (i.e., a channel region) is formed in a portion of the base layer 13 that contacts the trench 16. Then, electrons are supplied from the source region 14 to the drift layer 12 through the inversion layer, and a current flows between the upper electrode 20 and the lower electrode 22.

[0038] At this time, a voltage concentration of the gate voltage is likely to occur at a portion where the gate electrode 18 and the connection wiring 180 are connected and which is located above the opening of the trench 16. Therefore, in the present embodiment, a rounded portion 161 is formed at the connection opening 160a of the trench 16. Thereby, it is possible to suppress the occurrence of voltage concentration on the connection opening 160a and suppress the deterioration of the characteristics of the gate insulating film 17.

[0039] In addition, in the trench 16 of the present embodiment, a rounding portion 161 is not formed in the unconnected opening portion 160b, and the length L2 is made longer than the length L1. Therefore, in the portion located between the unconnected opening portions 160b of the adjacent trenches 16, it becomes easier to secure the connection area between the upper electrode 20, the source region 14, and the contact region 15. Accordingly, it is possible to suppress the occurrence of a connection failure between the upper electrode 20, the source region 14, and the contact region 15.

[0040] Next, a method for manufacturing the semiconductor device will be described with reference to FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7D. FIGS. 5A to 5C are cross-sectional views corresponding to FIG. 2, FIGS. 6A to 6C are cross-sectional views corresponding to FIG. 3, and FIGS. 7A to 7D are cross-sectional views corresponding to FIG. 4.

[0041] First, as shown in FIGS. 5A, 6A, and 7A, a semiconductor substrate 10 on which a substrate 11, a drift layer 12, a base layer 13, a source region 14, a contact region 15, etc. are formed is prepared. Then, a mask (not shown) is disposed on one surface 10a of the semiconductor substrate 10, and dry etching or the like is performed to form a plurality of trenches 16 having the above-described shape.

[0042] Subsequently, as shown in FIGS. 5B and 7B, a mask 30 that covers the portion that becomes the unconnected opening portion 160b of the trench 16 while exposing the portion that becomes the connected opening portion 160a of the trench 16 is disposed. The mask 30 is made of a heat-resistant material, and is made of, for example, a carbon film or the like.

[0043] Next, as shown in FIGS. 6B and 7C, rounding processing is performed so that a rounding portion 161 is formed in the portion that becomes the connected opening portion 160a. In the present embodiment, the rounding portion 161 is formed in the portion that becomes the connected opening portion 160a by performing rounding processing in which heat treatment is performed in a hydrogen atmosphere or an argon atmosphere. In this step, since heat treatment is performed, damage on the side surface of the trench 16 is also reduced.

[0044] Thereafter, as shown in FIGS. 5C, 6C, and 7D, although detailed description is omitted, a general semiconductor manufacturing process is performed to sequentially form a gate insulating film 17, a gate electrode 18, a connection wiring 180, an interlayer insulating film 19, an upper electrode 20, a lower electrode 22, etc. When forming the gate electrode 18 and the connection wiring 180, polysilicon is formed in the trench 16 by a method such as CVD (abbreviation for Chemical Vapor Deposition) to form the gate electrode 18. Then, by patterning the polysilicon formed on one surface 10a of the semiconductor substrate 10, the connection wiring 180 connected to the gate electrode 18 is formed.

[0045] According to the present embodiment described above, in the trench 16, a rounded portion 161 is formed at the connection opening 160a. For this reason, it is possible to suppress the occurrence of voltage concentration on the connection opening 160a, and it is possible to suppress the deterioration of the characteristics of the gate insulating film 17.

[0046] Also, in the trench 16, the rounded portion 161 is not formed at the unconnected opening 160b, and the length L2 is made longer than the length L1. For this reason, it is easy to secure the connection area between the upper electrode 20 and the source region 14 and the contact region 15 at the portion located between the unconnected openings 160b of the adjacent trenches 16. Therefore, it is possible to suppress the occurrence of connection failure between the upper electrode 20 and the source region 14 and the contact region 15.

[0047] (1) In the present embodiment, the radius of curvature of the connection opening 160a is less than L / 2. For this reason, it is possible to suppress the formation of a sharp portion between the connection openings 160a of the adjacent trenches 16 on one surface 10a of the semiconductor substrate 10. Therefore, it is possible to suppress the concentration of stress at a predetermined location of the gate insulating film 17 disposed between the connection openings 160a of the adjacent trenches 16, and it is possible to suppress the destruction of the gate insulating film 17.

[0048] (Modification of the First Embodiment) A modification of the first embodiment will be described. In the first embodiment, the position where the connection wiring 180 is formed can be appropriately changed. In other words, in the first embodiment, the positional relationship between the portion that becomes the connection opening 160a and the portion that becomes the unconnected opening 160b can be appropriately changed.

[0049] For example, as shown in FIG. 8A, the connection wiring 180 may be formed such that both end portions and intermediate portions in the longitudinal direction of the openings of the trench 16 become connection openings 160a. Further, as shown in FIG. 8B, the connection wiring 180 may not be formed such that the connection openings 160a are formed at both end portions in the longitudinal direction of the openings of the trench 16, and may be formed such that the connection openings 160a are formed only at the intermediate portions. In this case, as shown in FIG. 8C, a plurality of connection wirings 180 may be formed such that the connection openings 160a are formed at a plurality of intermediate portions of the openings of the trench 16. Further, as shown in FIG. 8D, the connection wiring 180 may not be formed to connect adjacent gate electrodes 18 and may be divided in the array direction. Then, as shown in FIG. 8E, the connection wiring 180 may be formed such that only one end portion of both end portions in the longitudinal direction of the openings of the trench 16 becomes the connection opening 160a.

[0050] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, more, or less thereof, fall within the scope and spirit of the present disclosure.

[0051] For example, in the above-described first embodiment, a semiconductor device in which a MOSFET having a trench gate structure of an n-channel type with the first conductivity type being n-type and the second conductivity type being p-type was described. However, the semiconductor device may be configured, for example, with a MOSFET having a trench gate structure of a p-channel type in which the conductivity type of each component is inverted with respect to the n-channel type. Further, the semiconductor device may be configured such that, in addition to the MOSFET, an IGBT having a similar structure is formed. In the case of the IGBT, it is the same as the vertical MOSFET described in the above-described first embodiment except that the n + -type substrate 11 is changed to a P + -type collector layer. Further, the semiconductor device may be configured such that, in addition to the MOSFET, other semiconductor elements such as diodes are also formed.

[0052] Also, in the above-described first embodiment, a semiconductor device in which the semiconductor substrate 10 is made of SiC was described as an example, but the semiconductor substrate 10 may be made of a silicon substrate, a compound substrate, or the like. Further, when the semiconductor substrate 10 is made of a silicon substrate or the like, after preparing the semiconductor substrate 10, a portion to be the drain region may be formed by ion implantation or the like.

[0053] Furthermore, in the above-described first embodiment, an example in which the rounding portion 161 is formed in the connection opening 160a and the rounding portion 161 is not formed in the unconnected opening 160b was described. However, for example, the rounding portion 161 may be formed in a portion of the unconnected opening 160b on the connection opening 160a side. That is, the unconnected opening 160b may be formed so as to have a portion where the radius of curvature is smaller than the radius of curvature of the connection opening 160a. According to this, in a portion where the radius of curvature in the unconnected opening 160b is small, since the rounding portion 161 is not formed, it is possible to suppress the occurrence of a connection failure of the upper electrode 20.

[0054] In addition, in the first embodiment described above, an example was explained in which the upper electrode 20 is not connected to the source region 14 or the like on the end side in the longitudinal direction of the trench 16. However, the upper electrode 20 may be arranged so as to be connected to the source region 14 or the like even on the end side in the longitudinal direction of the trench 16.

[0055] Furthermore, in the first embodiment, the rounding process for forming the rounded portion 161 may be performed by an isotropic CDE (i.e., Chemical Dry Etching) method, a dry etching method, or the like after forming the trench 16 and disposing the mask 30. When the rounding process is performed in such a manner, particularly when the semiconductor substrate 10 is a silicon substrate, it is possible to suppress the unnecessary diffusion of impurities constituting the source region 14 and the contact region 15 as compared with the case of performing the heat treatment.

Explanation of Reference Numerals

[0056] 11 Substrate (High-Concentration Layer) 12 Drift Layer 13 Base Layer 14 Source Region (Impurity Region) 16 Trench 17 Gate Insulating Film 18 Gate Electrode 20 Upper Electrode (First Electrode) 22 Lower Electrode (Second Electrode) 160a Connection Opening 160b Unconnected Opening 161 Rounded Portion 180 Connection Wiring

Claims

1. A semiconductor device in which a plurality of trench gate structures are formed, a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the drift layer, an impurity region (14) of a first conductivity type formed in a surface layer portion of the base layer, a semiconductor substrate (10) having a high-concentration layer (11) of a first conductivity type or a second conductivity type, which is formed on the opposite side of the base layer with the drift layer interposed therebetween and has a higher impurity concentration than the drift layer, a plurality of trench gate structures in which a gate electrode (18) is disposed via a gate insulating film (17) in a trench (16) that penetrates the impurity region and the base layer and reaches the drift layer and extends in a predetermined direction as a longitudinal direction, a connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode, a first electrode (20) electrically connected to the base layer and the impurity region, a second electrode (22) electrically connected to the high-concentration layer, a rounded portion (161) is formed in a connection opening (160a) that covers a connection portion between the gate electrode and the connection wiring among the openings of the trench, when an unconnected opening (160b) is defined as a portion of the opening of the trench that is different from the connection opening, the unconnected opening has a portion where the radius of curvature is smaller than the radius of curvature of the connection opening, the semiconductor device in which, when the length between adjacent trenches in a direction intersecting the longitudinal direction and along the plane direction of the semiconductor substrate is L for the connection opening, the radius of curvature of the rounded portion is less than L / 2.

2. a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the drift layer, an impurity region (14) of a first conductivity type formed in a surface layer portion of the base layer, a semiconductor substrate (10) having a high-concentration layer (11) of a first conductivity type or a second conductivity type, which is formed on the opposite side of the base layer with the drift layer interposed therebetween and has a higher impurity concentration than the drift layer, a plurality of trench gate structures in which a gate electrode (18) is disposed via a gate insulating film (17) in a trench (16) that penetrates the impurity region and the base layer and reaches the drift layer and extends in a predetermined direction as a longitudinal direction, a connection wiring (180) formed on the semiconductor substrate and electrically connected to the gate electrode, A first electrode (20) electrically connected to the base layer and the impurity region; A second electrode (22) electrically connected to the high-concentration layer; and In the trench, a rounded portion (161) is formed in a connection opening (160a) covered by a connection portion between the gate electrode and the connection wiring among the openings. A method of manufacturing a semiconductor device, wherein, when a portion of the opening of the trench different from the connection opening is an unconnected opening (160b), the unconnected opening has a portion where the radius of curvature is smaller than the radius of curvature of the connection opening. Preparing the semiconductor substrate having the drift layer, the base layer, and the impurity region; Forming the trench in the semiconductor substrate; Placing a mask (30) that covers the portion to be the unconnected opening while exposing the portion to be the connection opening among the openings of the trench; Forming a rounded portion in the connection opening in a state where the mask is placed. A method of manufacturing a semiconductor device.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the rounded portion is formed by performing a heat treatment to form the rounded portion in the connection opening.

4. The method of manufacturing a semiconductor device according to claim 2, wherein the rounded portion is formed by an isotropic chemical dry etching method or dry etching method to form the rounded portion in the connection opening.

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