Semiconductor device

Abstract

To provide a semiconductor device in which breakage of an element in an edge termination region can be suppressed.SOLUTION: A semiconductor device 600 comprises: a semiconductor element region 150 in which a plurality of unit cells of trench type MOSFETs each including a first trench 16a are provided; a gate runner region 160 overlapped with a gate runner 17 provided outside the semiconductor element region 150; a ring region 170 provided outside the gate runner region 160 and including ring electrodes 12b and 14b surrounding the semiconductor element region 150 in a plan view; and a termination region 168 surrounding the ring region 170 in a plan view. The ring region 170 includes a second trench 16b. At least a part of the ring electrodes 12b and 14b is provided inside the second trench 16b.SELECTED DRAWING: Figure 18

Description

Technical Field

[0001] This invention relates to a semiconductor device.

Background Art

[0002] Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device for controlling high voltage and large current. There are several types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used properly according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can handle a large current, but they cannot be switched at high speed. Specifically, the use of bipolar transistors is limited to a switching frequency of about several kHz, and the use of IGBTs is limited to a switching frequency of about several tens of kHz. On the other hand, power MOSFETs have a lower current density than bipolar transistors and IGBTs and it is difficult to handle a large current, but they can perform high-speed switching operations up to about several MHz.

[0004] However, in the market, there is a strong demand for a power semiconductor device that combines a large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. Currently, the development has advanced to almost the limit of the material. A semiconductor material to replace silicon has been studied from the viewpoint of power semiconductor devices, and silicon carbide (SiC) has attracted attention as a semiconductor material capable of fabricating (manufacturing) a next-generation power semiconductor device with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

[0005] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of 3 eV and can be used extremely stably as a semiconductor even at high temperatures. In addition, since the maximum electric field strength of silicon carbide is more than one order of magnitude larger than that of silicon, it is expected as a semiconductor material that can sufficiently reduce the on-resistance. Such characteristics of silicon carbide also apply to other wide-bandgap semiconductors with a wider bandgap than silicon, such as gallium nitride (GaN). Therefore, by using a wide-bandgap semiconductor, the breakdown voltage of a semiconductor device can be increased.

[0006] Regarding the structure of a conventional silicon carbide semiconductor device, a vertical MOSFET will be taken as an example for explanation. FIG. 22 is a top view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 22, in a semiconductor chip (vertical MOSFET) 1600, an edge termination region 1168 that surrounds the periphery of an active region 1150 where the main current flows and holds the breakdown voltage is provided on the outer peripheral portion of the active region 1150. The active region 1150 is provided with a gate electrode pad 1100 that is electrically connected to a gate electrode and a source electrode pad 1104 that is electrically connected to a source electrode. Further, a gate ring region 1160 in which a wiring for connecting the gate electrode and the gate electrode pad 1100 is formed is provided between the active region 1150 and the edge termination region 1168.

[0007] In order to further improve the reliability of a silicon carbide semiconductor device, a semiconductor device has been proposed in which high-function regions 1400 such as a current sense portion, a temperature sense portion (not shown), and an overvoltage protection portion (not shown) are arranged on the same semiconductor substrate as the semiconductor chip 1600. In the case of a high-function structure, in order to stably form the high-function region 1400, a region where only the high-function region 1400 is arranged is provided in the active region 1150, separated from the unit cell of the main semiconductor element and adjacent to the edge termination region 1168. The active region 1150 is a region where the main current flows when the main semiconductor element is turned on. The edge termination region 1168 is a region for relaxing the electric field on the front surface side of the semiconductor substrate and holding the breakdown voltage (breakdown withstand voltage). The breakdown voltage is the limit voltage at which the element does not malfunction or break.

[0008] The current sense section is provided with an active region 1230 of the current sense section having the same structure as the active region 1150 and a current sense section pad 1202 for current detection. The temperature sense section has a function of detecting the temperature of the semiconductor chip by utilizing the temperature characteristics of the diode.

[0009] FIG. 23 is a cross-sectional view taken along line A-A of FIG. 22 showing the structure of a conventional silicon carbide semiconductor device. FIG. 23 is a cross-sectional view showing the structure of a conventional trench-type silicon carbide semiconductor device. In the trench-type MOSFET 1600, an n + type silicon carbide epitaxial layer 1002 is deposited on the front surface of the n-type silicon carbide substrate 1001. In the active region 1150, an n + type high-concentration region 1005 is provided on the surface side opposite to the n-type silicon carbide substrate 1001 side of the n-type silicon carbide epitaxial layer 1002. Further, a second p + type base region 1004 is selectively provided so as to cover the entire bottom surface of the trench 1016. On the surface layer of the n + type high-concentration region 1005 opposite to the n-type silicon carbide substrate 1001 side, a first p + type base region 1003 is selectively provided.

[0010] Further, in the active region 1150 of the conventional trench-type MOSFET 1600, a p-type base layer 1006, an n + type source region 1007, a p ++ type contact region 1008, a gate insulating film 1009, a gate electrode 1010, an interlayer insulating film 1011, a source electrode 1012, a back surface electrode 1013, a trench 1016, a source electrode pad (not shown), and a drain electrode pad (not shown) are provided.

[0011] The source electrode 1012 is connected to the n + type source region 1007, the p ++On the p-type contact region 1008, a multilayer film in which a NiSi electrode 1015, a first TiN film 1020, a first Ti film 1021, a second TiN film 1022, a second Ti film 1033, and an Al alloy film 1029 are laminated in sequence. Also, on the upper part of the source electrode 1012, a plating film 1014, solder 1024, an external electrode pin 1026, a first protective film 1023, and a second protective film 1025 are provided.

[0012] Also, in the gate ring region 1160 of the conventional trench-type MOSFET 1600, a first p + -type base region 1003, a p-type base layer 1006, p ++ -type contact region 1008 are provided. On the p ++ -type contact region 1008, an insulating film 1530, a gate electrode 1010, an interlayer insulating film 1011, a gate wiring electrode 1017, and a first protective film 1023 are provided.

[0013] Also, in the edge termination region 1168 of the conventional trench-type MOSFET 1600, the p-type base layer 1006 and p ++ -type contact region 1008 are removed over the entire area, and a step (recessed on the drain side) in which the edge termination region 1168 is made lower than the active region 1150 is formed on the front surface, and an n-type silicon carbide epitaxial layer 1002 is exposed on the bottom surface of the step.

[0014] Also, in the edge termination region 1168, a JTE structure in which a plurality of p + -type regions (here, two, the first JTE region 1163 and the second JTE region 1165) are arranged adjacent to each other is provided. Also, an n + -type semiconductor region 1167 that functions as a channel stopper is provided outside the JTE structure (on the chip end side).

[0015] The first JTE region 1163 and the second JTE region 1165 are selectively provided at portions of the n-type silicon carbide epitaxial layer 1002 that are exposed at the bottom of the step, respectively. When a high voltage is applied, the lateral high voltage outside the active region 1150 is ensured by the pn junction between the first JTE region 1163, the second JTE region 1165 and the n-type silicon carbide epitaxial layer 1002.

[0016] Further, an n-type epitaxial layer having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed so as to straddle the cell portion and the outer peripheral portion and formed to be thinner than the portion in the outer peripheral portion in the cell portion are included. A semiconductor device that can improve the flatness of the surface metal layer without sacrificing the conventional breakdown voltage characteristics is known (see, for example, Patent Document 1 below). - Also, at the boundary between the high-function region and the edge termination region, a drawing electrode having a function of drawing out the hole current flowing from the edge termination region to the high-function region when the main semiconductor element is off is provided on the front surface of the semiconductor substrate, and a semiconductor device capable of suppressing breakdown in the edge termination region is known (see, for example, Patent Document 2 below).

[0017]

Prior Art Documents

Patent Documents

Patent Document 1

[0018]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0019] In the conventional semiconductor device described above (see FIG. 23), since a wide-bandgap semiconductor is used as the semiconductor material, the width of the edge termination region 1168 can be made about 1 / 5 to 1 / 2 times narrower than when silicon is used as the semiconductor material. Also, the thickness of the edge termination region 1168 can be made thinner by more than 1 / 2 times. Therefore, by narrowing the width of the edge termination region 1168 or thinning the thickness of the edge termination region 1168, it is possible to reduce the on-resistance (RonA) of the MOSFET.

[0020] However, by narrowing the width of the edge termination region 1168 or thinning the thickness of the edge termination region 1168, the capacitance of the depletion layer (pn junction capacitance) that extends in a direction parallel to the front surface of the semiconductor substrate (lateral direction) from the pn junction between the p-type base layer 1006 and the n-type silicon carbide epitaxial layer 1002 toward the chip end side decreases when the MOSFET is off. For this reason, when the drain-source voltage changes in a very short time (hereinafter, dv / dt surge) due to noise such as a surge especially when the MOSFET is turned off during switching of the MOSFET, the displacement current flowing through the pn junction capacitance becomes extremely large. Specifically, the current value of the displacement current flowing during charging and discharging of the pn junction capacitance is the volume multiple of the current value when silicon is used as the semiconductor material with the volume of the edge termination region 1168 decreased.

[0021] When the MOSFET is off, the displacement current caused by holes (hereinafter abbreviated as hole current) flows from the edge termination region 1168 toward the active region 1150 and is drawn out from the p-type contact region 1008 of the active region 1150 to the source electrode 1012. Since the n-type source region 1007 and the like are not arranged in the gate ring region 1160, the area of the p-type contact region 1008 is larger than other parts of the active region 1150. For this reason, in particular, the hole current concentrates in the gate ring region 1160. In the gate ring region 1160, between the gate electrode 1010 and the p ++ type contact region 1008 is larger than other parts of the active region 1150. For this reason, in particular, the hole current concentrates in the gate ring region 1160. In the gate ring region 1160, between the gate electrode 1010 and the p + type contact region 1008 is larger than other parts of the active region 1150. For this reason, in particular, the hole current concentrates in the gate ring region 1160. In the gate ring region 1160, between the gate electrode 1010 and the p ++ type contact region 1008 is larger than other parts of the active region 1150. For this reason, in particular, the hole current concentrates in the gate ring region 1160. In the gate ring region 1160, between the gate electrode 1010 and the p ++Since an insulating film 1530 is disposed between the type contact region 1008, the hole current is not extracted. Therefore, there is a risk that the element may be destroyed at the end of the active region 1150 due to the hole current concentrating on the MOSFET at the end of the active region 1150.

[0022] An object of the present invention is to provide a semiconductor device capable of suppressing breakdown in an edge termination region in order to solve the problems caused by the above-described prior art.

Means for Solving the Problems

[0023] Upper In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A semiconductor element region in which a plurality of unit cells of a trench-type MOSFET including a first trench are provided, a gate runner region overlapping with a gate runner provided outside the semiconductor element region, and a ring provided outside the gate runner region and surrounding the semiconductor element region in plan view. A ring region including an electrode, and a termination region surrounding the ring region in plan view. The semiconductor element region and the gate runner region have a first pn junction interface at a position deeper than the bottom surface of the first trench on the front surface side of the semiconductor substrate, and the ring region includes a second trench. A second pn junction interface provided at a position deeper than the first pn junction interface is provided below the second trench, and at least a part of the ring electrode is provided inside the second trench.

[0024] Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second trench is wider than the first trench.

[0025] Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the unit cell includes a gate insulating film and a gate electrode provided in the first trench, a source region of a first conductivity type in contact with the gate insulating film, and at least a part provided under the source region. And a base layer of a second conductivity type in contact with the gate insulating film.

[0026] Further, in the semiconductor device according to the present invention, in the above-described invention, the semiconductor device includes a source electrode that contacts the source region, and the ring electrode is fixed to the potential of the source electrode.

[0027] Further, in the semiconductor device according to the present invention, in the above-described invention, the ring electrode is short-circuited to the source electrode.

[0028] Further, in the semiconductor device according to the present invention, in the above-described invention, a high-concentration region of the second conductivity type having an impurity concentration higher than that of the base layer region is provided, The high-concentration region forms the second pn junction interface, and the ring electrode is in contact with the high-concentration region.

[0029] In order to solve the above-described problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor element region in which a plurality of unit cells of a trench-type MOSFET including a first trench, a source region of the first conductivity type in contact with the first trench, and a base layer of the second conductivity type provided at least partially under the source region and in contact with the first trench are provided, a gate runner region overlapping with a gate runner provided outside the semiconductor element region, a ring region including a ring electrode provided outside the gate runner region and surrounding the semiconductor element region in a plan view, a termination region surrounding the ring region in a plan view, and a high-concentration region of the second conductivity type having an impurity concentration higher than that of the base layer, the high-concentration region having a pn junction interface at a position deeper than the bottom surface of the first trench. and a well region of a second conductivity type provided from the semiconductor element region to the ring region, is provided. In the ring region, the The ring electrode is is electrically connected to the well region, in contact with The upper surface of which is the lower surface of the well region the high-concentration region.

[0030] Further, in the semiconductor device according to the present invention, in the above-described invention, the semiconductor device is configured to include a silicon carbide semiconductor substrate, and the high-concentration region is in contact with the bottom surface of a step where the thickness of the silicon carbide semiconductor substrate is reduced.

[0031] Also, in the semiconductor device according to the present invention, in the above-described invention, at least a part of the ring electrode is embedded in the second trench, and the remaining part protrudes from above the second trench. The first ring electrode and a second ring electrode disposed on the surface of the first ring electrode are included.

[0032] Also, in the semiconductor device according to the present invention, in the above-described invention, the second ring electrode is a plating film.

[0033] Also, in the semiconductor device according to the present invention, in the above-described invention, the second trench is not provided in the semiconductor element region.

[0034] Also, in the semiconductor device according to the present invention, in the above-described invention, the termination region includes at least one of a guard ring or a JTE. 。

Effect of the Invention

[0035] According to the semiconductor device of the present invention, there is an effect that breakdown in the edge termination region can be suppressed.

Brief Description of the Drawings

[0036]

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Mode for Carrying Out the Invention

[0037] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the layers and regions preceded by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. When the notations of n and p including + and - are the same, it indicates that they are at similar concentrations, but the concentrations are not necessarily equal. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. Also, in this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index.

[0038] (Embodiment 1) The semiconductor device according to Embodiment 1 is configured using a semiconductor having a wider bandgap than silicon (Si) (referred to as a wide bandgap semiconductor). Regarding the structure of the semiconductor device according to this Embodiment 1, the case where silicon carbide (SiC) is used as the wide bandgap semiconductor will be described as an example. FIG. 1 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. FIG. 1 shows the electrode pads of each element arranged on the semiconductor substrate (semiconductor chip) and the layout of each region.

[0039] The silicon carbide semiconductor device according to Embodiment 1 shown in FIG. 1 has, on the same semiconductor substrate made of silicon carbide, a main semiconductor element and high - function parts such as a current sense part, a temperature sense part (not shown), an over - voltage protection part (not shown), and an arithmetic circuit part (not shown) as a circuit part for protecting and controlling the main semiconductor element. The main semiconductor element is a trench - type MOSFET600 in which a drift current flows in the longitudinal direction (depth direction z of the semiconductor substrate) in the on - state, and is composed of a plurality of adjacent unit cells (functional units: not shown) and performs the main operation.

[0040] The main semiconductor element is provided in the effective region (the region that functions as a MOS gate) 150a of the active region 150. The effective region 150a of the active region 150 is the region where the main current flows when the main semiconductor element is on, and is surrounded by a gate - ring region 160. On the front surface of the semiconductor substrate in the effective region 150a of the active region 150, a source electrode 12 of the main semiconductor element is provided. The source electrode 12 (first source electrode 12a) covers, for example, substantially the entire surface of the effective region 150a of the active region 150. Further, on the front surface of the source electrode 12, a source - electrode pad 104 having, for example, a rectangular planar shape is provided.

[0041] The edge - termination region 168 is the region between the active region 150 and the side surface of the chip (semiconductor substrate), and is a region for relaxing the electric field on the front - surface side of the semiconductor substrate and maintaining the breakdown voltage (voltage withstand). In the edge - termination region 168, for example, a guard ring, a p - type region constituting a junction - termination (JTE) structure described later, and a voltage - withstand structure such as a field - plate and RESURF (not shown) are arranged. The breakdown voltage is the limit voltage at which the element does not malfunction or break.

[0042] Further, a high - performance region 400 is provided in the active region 150 adjacent to the gate - ring region 160. The high - performance region 400 has, for example, a substantially rectangular planar shape. In the high - performance region 400, high - performance parts such as a current - sense part, a temperature - sense part (not shown), an over - voltage protection part (not shown), and an arithmetic - circuit part (not shown) are provided. In FIG. 1, only the current - sense part is shown as the high - performance part, but other high - performance parts other than the current - sense part may be arranged in the high - performance region 400.

[0043] The current - sense part has a function of detecting an over - current (OC: Over Current) flowing through the main semiconductor element. The current - sense part is provided under the electrode pad 202 of the current - sense part (in the depth direction z of the semiconductor substrate), and is a vertical MOSFET having several unit cells with the same configuration as the main semiconductor element in the active region 230 of the current - sense part.

[0044] Also, in the high - performance region 400, on the front surface of the semiconductor substrate, along the boundary between the active region 150 and the edge - termination region 168, and separated from the source electrode 12 (the first source electrode 12a) and the edge - termination region 168, the gate - electrode pad 100 of the main semiconductor element and the electrode pad 202 of the current - sense part are provided in contact with each other. These electrode pads have, for example, a substantially rectangular planar shape.

[0045] The gate - electrode pad 100 is electrically connected to the gate electrodes (see FIG. 2) of all the unit cells of the main semiconductor element through a gate runner (gate wiring electrode, see FIG. 2) provided in the gate - ring region 160. The gate - ring region 160 is provided between the active region 150 and the edge - termination region (termination region) 168 so as to surround the active region 150.

[0046] In addition, a source ring region (ring region) 170 is provided between the gate ring region 160 and the edge termination region 168 so as to surround the gate ring region 160. The source ring region 170 is provided with a second source electrode 12b as described later, and is fixed to the potential (source potential) of the first source electrode 12a of the active region 150 via a p-type base layer 6 as described later. The source ring region 170 has a function of drawing out hole current flowing from the edge termination region 168 to the active region 150 via the p-type base layer 6 when the main semiconductor element is off. Since the source ring region 170 surrounds the gate ring region 160, the hole current flowing from the edge termination region 168 can be drawn out via the p-type base layer 6, eliminating the influence on the active region 150.

[0047] Next, a description will be given of an example of the cross-sectional structure of the above-mentioned active region 150, gate ring region 160, edge termination region 168, and source ring region 170. Figure 2 is a cross-sectional view taken along line AA in Figure 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. Only two adjacent unit cells of the main semiconductor element are shown, and other unit cells of the main semiconductor element adjacent to the unit cells on the central side of the chip (semiconductor substrate) are not shown.

[0048] The main semiconductor element is a trench-type MOSFET 600 having a MOS gate with a trench gate structure on the front surface (the surface on the p-type base layer 6 side) of the semiconductor substrate. + The n-type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 and p-type base layer (second semiconductor layer of second conductivity type) 6 are epitaxially grown in this order on a silicon carbide substrate (semiconductor substrate of first conductivity type) 1. An n-type high concentration region 5 may be epitaxially grown on the n-type silicon carbide epitaxial layer 2.

[0049] A MOS gate is provided in the active region 150. The MOS gate is formed by a p-type base layer 6, a n + A first conductive type source region (first semiconductor region) 7, p ++It is composed of a Type - contact region 8, a trench 16, a gate insulating film 9, and a first gate electrode 10a.

[0050] Specifically, the trench 16 penetrates the p - type base layer 6 in the depth direction z from the front surface of the semiconductor substrate and reaches an n - type high - concentration region 5 (when the n - type high - concentration region 5 is not provided, an n - type silicon carbide epitaxial layer 2, hereinafter referred to as (2)). The depth direction z is the direction from the front surface to the back surface of the semiconductor substrate. The trench 16 is arranged, for example, in a stripe shape.

[0051] The trench 16 may be arranged in a matrix shape when viewed from the front - surface side of the semiconductor substrate, for example. Inside the trench 16, a gate insulating film 9 is provided along the inner wall of the trench 16, and a first gate electrode 10a10 is provided so as to be embedded inside the trench 16 on the gate insulating film 9. One unit cell of the main semiconductor element is composed of the first gate electrode 10a in one trench 16 and the mesa region (the region between adjacent trenches 16) sandwiching the first gate electrode 10a.

[0052] An n - type region (hereinafter referred to as an n - type high - concentration region) 5 may be provided on the surface layer of the source side (the first source electrode 12a side) of the n - type silicon carbide epitaxial layer 2 so as to be in contact with the p - type base layer 6. The n - type high - concentration region 5 is a so - called Current Spreading Layer (CSL) that reduces the spreading resistance of carriers. This n - type high - concentration region 5 is provided uniformly, for example, in a direction parallel to the front - surface of the substrate (the front - surface of the semiconductor substrate) so as to cover the inner wall of the trench 16.

[0053] The n - type high - concentration region 5 reaches a position deeper on the drain side (the back - surface electrode 13 side) than the bottom surface of the trench 16 from the interface with the p - type base layer 6. Inside the n - type high - concentration region 5, first and second p + type base regions 3 and 4 may be selectively provided, respectively. The first p + type base region 3 is between adjacent trenches 16 (mesa region), and the second p +The p-type base region 4 is provided apart from the trench 16 and is in contact with the p-type base layer 6. The second p + -type base region 4 covers at least the bottom surface among the bottom surface and the bottom corner portions of the trench 16. The bottom corner portion of the trench 16 is the boundary between the bottom surface and the side wall of the trench 16.

[0054] The first and second p + -type base regions 3 and 4 and the pn junction with the n-type high-concentration region 5(2) are formed at a position deeper on the drain side than the bottom surface of the trench 16. Without providing the n-type high-concentration region 5, the first and second p + -type base regions 3 and 4 may be provided inside the n-type silicon carbide epitaxial layer 2. The first and second p + -type base regions 3 and 4 only need to be at a position deeper on the drain side than the pn junction between the first and second p + -type base regions 3 and 4 and the n-type high-concentration region 5(2), and can be variously changed according to the design conditions. The first and second p + -type base regions 3 and 4 can prevent a high electric field from being applied to the gate insulating film 9 at the portion along the bottom surface of the trench 16.

[0055] Inside the p-type base layer 6, an n + -type source region 7 is selectively provided. An n + -type contact region 8 may be selectively provided so as to be in contact with the n ++ -type source region 7. The n + -type source region 7 is in contact with the gate insulating film 9 on the side wall of the trench 16 and faces the first gate electrode 10a through the gate insulating film 9 on the side wall of the trench 16.

[0056] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate so as to cover the first gate electrode 10a and the second gate electrode 10b of the gate ring region 160 described later. All the first gate electrodes 10a are electrically connected to the gate electrode pad 100 (see FIG. 1) via the second gate electrode 10b of the gate ring region 160 and the gate wiring electrode 17. In the interlayer insulating film 11, contact holes penetrating the interlayer insulating film 11 in the depth direction z and reaching the front surface of the substrate are opened.

[0057] The first source electrode (first first electrode) 12a makes an ohmic contact with the semiconductor substrate (n + -type source region 7) in the contact hole and is electrically insulated from the first gate electrode 10a by the interlayer insulating film 11. The first source electrode 12a is an n + -type multilayer film in which an NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29 are laminated in this order on the source region 7. When a p ++ -type contact region 8 is provided, the first source electrode 12a makes an ohmic contact with the p ++ -type contact region 8.

[0058] One end of a first external electrode pin (first electrode pin) 26a is joined to a first source electrode 12a via a first plating film (first plating film) 14a and a first solder (first solder) 24a. Among these, the first plating film 14a corresponds to a source electrode pad 104. The other end of the first external electrode pin 26a is joined to a metal bar (not shown) arranged so as to face the front surface of the semiconductor substrate. Also, the other end of the first external electrode pin 26a is exposed outside a case (not shown) on which the semiconductor chip is mounted and is electrically connected to an external device (not shown). A portion other than the first plating film 14a on the surface of the first source electrode 12a is covered with a first protective film 23. Specifically, the first protective film 23 is provided so as to cover the first source electrode 12a, and the first plating film 14a is provided in an opening of the first protective film 23. The first external electrode pin 26a is joined to the surface of the first plating film 14a via the first solder 24a. In order to limit the region of the first solder 24a, a first second protective film 25a may be provided on the surface of the first plating film 14a. The first and second protective films 23 and 25 are, for example, polyimide films.

[0059] A back surface electrode (second electrode) 13 serving as a drain electrode is provided on the back surface of the semiconductor substrate 10. A drain electrode pad (not shown) is provided on the back surface electrode 13.

[0060] Also, in the gate ring region 160, a second gate electrode 10b is provided on a p-type contact region 8 of a silicon carbide semiconductor substrate via an insulating film (first insulating film) 530. The second gate electrode 10b is insulated from the p-type contact region 8 by the insulating film 530. The second gate electrode 10b is covered with an interlayer insulating film 11. A contact hole that penetrates the interlayer insulating film 11 in the depth direction z and reaches the second gate electrode 10b is opened in the interlayer insulating film 11. A gate wiring electrode 17 is embedded in the contact hole. The gate wiring electrode 17 electrically connects the first gate electrode 10a in the active region 150 to a gate electrode pad 100. Also, a first protective film 23 is provided on the interlayer insulating film 11 and the gate wiring electrode 17. ++ type contact region 8 via an insulating film (first insulating film) 530. The second gate electrode 10b is insulated from the p ++ type contact region 8 by the insulating film 530. The second gate electrode 10b is covered with an interlayer insulating film 11. A contact hole that penetrates the interlayer insulating film 11 in the depth direction z and reaches the second gate electrode 10b is opened in the interlayer insulating film 11. A gate wiring electrode 17 is embedded in the contact hole. The gate wiring electrode 17 electrically connects the first gate electrode 10a in the active region 150 to a gate electrode pad 100. Also, a first protective film 23 is provided on the interlayer insulating film 11 and the gate wiring electrode 17.

[0061] In the edge termination region 168, p is present throughout the region. ++ The p-type contact region 8 and the p-type base layer 6 are removed in the edge termination region 168, and a step is formed on the front surface of the silicon carbide semiconductor substrate such that the edge termination region 168 is lower than the active region 150 (recessed on the drain side), and the n-type silicon carbide epitaxial layer 2 is exposed on the bottom surface of the step. Further, in the edge termination region 168, a JTE structure in which a plurality of p + -type regions (here, two, the first JTE region 163 and the second JTE region 165) are arranged adjacent to each other is provided. Also, an n + -type stopper region 167 that functions as a channel stopper is provided outside the JTE structure (on the chip end side).

[0062] The first JTE region 163 and the second JTE region 165 are selectively provided in the portions of the n-type silicon carbide epitaxial layer 2 that are exposed on the bottom surface of the step, respectively. When a high voltage is applied, the lateral high breakdown voltage outside the active region 150 is ensured by the pn junction between the first JTE region 163, the second JTE region 165, and the n-type silicon carbide epitaxial layer 2.

[0063] Also, in the source ring region 170, on the p ++ -type contact region 8 (when the p ++ -type contact region 8 is not provided, the p-type base layer 6, hereinafter referred to as (6)), an interlayer insulating film 11 is provided. In the interlayer insulating film 11, a contact hole that penetrates the interlayer insulating film 11 in the depth direction z and reaches the p ++ -type contact region 8 (6) is opened. The second source electrode 12b is embedded in the contact hole. Therefore, the second source electrode (the second first electrode) 12b, like the first source electrode 12a, is p ++It is provided on the type contact region 8(6). The second source electrode 12b is a multilayer film in which a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29 are laminated, similar to the first source electrode 12a. Inside the semiconductor substrate, since the p-type region (p ++ type contact region 8(6), etc.) provided below the active region 150 is connected to the p-type region provided below the source ring region 170, the second source electrode 12b has the same potential as the first source electrode 12a.

[0064] A plating film (second plating film) 14 is provided on the surface of the second source electrode 12b, and portions other than the second plating film 14b are covered with the first protective film 23. Specifically, the first protective film 23 is provided so as to cover the second source electrode 12b, and the second plating film 14b is provided in the opening of the first protective film 23. A part of the second plating film 14b and the first protective film 23 may be covered with the first second protective film 25a. The second plating film 14b may be provided on the entire surface of the second source electrode 12b, or selectively, for example, only on the second source electrode 12b at the corner of the source ring region 170.

[0065] As described above, the source ring region 170 has a function of extracting the hole current flowing from the edge termination region 168 to the active region 150 when the main semiconductor element is off, through the p-type base layer 6. Therefore, the source ring region 170 can alleviate the current concentration at the end of the active region 150. Also, by providing the second plating film 14b on the second source electrode 12b, the resistance of the second source electrode 12b can be reduced, and the breakdown withstand voltage of the second source electrode 12b can be improved. Further, at the corner portion between the active region 150 and the edge termination region 168, by bulging the source ring region 170 outward, the width of the source ring region 170 can be made wider than the width of the straight portion, and the width of the corner portion of the second source electrode 12b can be made wider than the width of the straight portion (see region S in FIG. 1). In FIG. 1, only one corner is widened, but all four corners may be widened, or only two corners may be widened. Thereby, it becomes easier to extract the hole current, and the current concentration in the active region 150 can be further alleviated. Also, the area where the second source electrode 12b contacts the silicon carbide semiconductor substrate (p ++ -type contact region 8, p ++ -type contact region 8 is not provided, it is the p-type base layer 6) is preferably made more than twice as wide as the area where the first source electrode 12a contacts the silicon carbide semiconductor substrate (p ++ -type contact region 8, p ++ -type contact region 8 is not provided, it is the p-type base layer 6).

[0066] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 will be described. FIGS. 3 to 8 are cross-sectional views showing the states during the manufacture of the silicon carbide semiconductor device according to the embodiment.

[0067] First, an n + -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. And this n +On the first main surface of the silicon carbide substrate 1, a first n-type silicon carbide epitaxial layer 2a made of silicon carbide is epitaxially grown to a thickness of about 30 μm while doping with an n-type impurity, for example, nitrogen atoms (N). The state up to this point is shown in FIG. 3.

[0068] Next, an ion implantation mask having a predetermined opening is formed, for example, of an oxide film, on the surface of the first n-type silicon carbide epitaxial layer 2a by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p + type base region 3a and a second p + type base region 4.

[0069] Also, the distance between adjacent lower first p + type base regions 3a and the second p + type base region 4 is formed to be about 1.5 μm. The impurity concentration of the lower first p + type base region 3a and the second p + type base region 4 is set to, for example, 5×10 18 / cm 3 or so.

[0070] Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion implanted into the opening to form a lower n-type high-concentration region 5a having a depth of about 0.5 μm in a part of the surface region of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high-concentration region 5a is set to, for example, 1×10 17 / cm 3 or so. The state up to this point is shown in FIG. 4.

[0071] Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of the first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is 3×10 15 / cm 3Set it so as to reach a certain level. Thereafter, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b are combined to form an n-type silicon carbide epitaxial layer 2.

[0072] Next, on the surface of the second n-type silicon carbide epitaxial layer 2b, a mask for ion implantation having a predetermined opening is formed, for example, with an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form an upper first p + -type base region 3b with a depth of about 0.5 μm so as to overlap the lower first p + -type base region 3a. The lower first p + -type base region 3a and the upper first p + -type base region 3b form a continuous region to form a first p + -type base region 3. Set the impurity concentration of the upper first p + -type base region 3b to be, for example, 5×10 18 / cm 3 or so.

[0073] Next, a part of the mask for ion implantation is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to form, for example, an upper n-type high-concentration region 5b with a depth of about 0.5 μm in a part of the surface region of the second silicon carbide epitaxial layer 2b. Set the impurity concentration of the upper n-type high-concentration region 5b to be, for example, 1×10 17 / cm 3 or so. The upper n-type high-concentration region 5b and the lower n-type high-concentration region 5a are formed so that at least a part of them is in contact with each other to form an n-type high-concentration region 5. However, there are cases where this n-type high-concentration region 5 is formed over the entire surface of the substrate and cases where it is not formed. The state up to this point is shown in FIG. 5.

[0074] Next, on the surface of the n-type silicon carbide epitaxial layer 2, a p-type base layer 6 is formed to a thickness of about 1.1 μm by epitaxial growth. The impurity concentration of the p-type base layer 6 is 4×10 17 / cm 3Set to a certain degree. After forming the p-type base layer 6 by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the p-type base layer 6.

[0075] Next, an ion implantation mask having a predetermined opening is formed, for example, of an oxide film, on the surface of the p-type base layer 6 by photolithography. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening, and an n + -type source region 7 is formed in a part of the surface of the p-type base layer 6. Next, + the ion implantation mask used for forming the n ++ -type source region 7 is removed, and in the same manner, an ion implantation mask having a predetermined opening is formed, and p-type impurities such as phosphorus are ion-implanted into a part of the surface of the p-type base layer 6 to form a p ++ -type contact region 8. The impurity concentration of the p

[0076] -type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6. The state up to this point is shown in FIG. 6. + Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700 °C to activate the first p + -type base region 3, the second p + -type base region 4, the n ++ -type source region 7, and the p

[0077] -type contact region 8. Note that, as described above, each ion implantation region may be activated collectively by one heat treatment, or heat treatment may be performed each time ion implantation is performed to activate it. + Next, a trench formation mask having a predetermined opening is formed, for example, of an oxide film, on the surface of the p-type base layer 6 by photolithography. Next, a trench 16 that penetrates the p-type base layer 6 and reaches the n-type high-concentration region 5(2) is formed by dry etching. The bottom of the trench 16 may reach the second p

[0078] Next, n + A gate insulating film 9 is formed along the surface of the n-type source region 7, the bottom and side walls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000 °C in an oxygen atmosphere. Further, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as high temperature oxide (HTO).

[0079] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. The polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the first gate electrode 10a.

[0080] Next, for example, phosphosilicate glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the first gate electrode 10a to form an interlayer insulating film 11. Next, a barrier metal made of titanium (Ti) or titanium nitride (TiN) or a laminate of titanium and titanium nitride may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography and n + type source region 7 and p ++ type contact region 8 are exposed to form contact holes. Thereafter, heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG. 8. Further, after forming contact holes in the interlayer insulating film 11, a barrier metal made of titanium (Ti) or titanium nitride (TiN) or a laminate of titanium and titanium nitride may be formed. In this case, the barrier metal also has n + type source region 7 and p ++ type contact region 8 are provided with contact holes for exposure.

[0081] Next, a conductive film that will become the NiSi electrode 15 is formed in the contact holes provided in the interlayer insulating film 11 and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. Also, n +A nickel (Ni) film is similarly formed on the second main surface of the silicon carbide substrate 1. Then, heat treatment is performed at a temperature of about 970° C., for example, to silicidize the nickel film inside the contact hole to form the NiSi electrode 15. At the same time, the nickel film formed on the second main surface becomes the back electrode 13 that forms an ohmic contact with the silicon carbide substrate 1. Then, the unreacted nickel film is selectively removed, leaving the NiSi electrode 15 only in the contact hole, for example. The first gate electrode 10a and the NiSi electrode 15 are similarly formed in the source ring region 170. + The nickel film formed on the second main surface becomes the back electrode 13 that forms an ohmic contact with the silicon carbide substrate 1. Then, the unreacted nickel film is selectively removed, leaving the NiSi electrode 15 only in the contact hole, for example. The first gate electrode 10a and the NiSi electrode 15 are similarly formed in the source ring region 170.

[0082] Next, for example, by sputtering, the first TiN film 20, the first Ti film 21, the second TiN film 22, and the second Ti film 33 are sequentially laminated so as to cover the NiSi electrode 15 and the interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate. Further, an Al alloy film 29 is formed to have a thickness of about 5 μm, for example. The Al alloy film 29 may be an Al film. The Al alloy film 29 is, for example, an Al—Si film or an Al—Si—Cu film. This conductive film is patterned by photolithography and left in the active region 150 of the entire element to form the first source electrode 12a. Similarly, in the source ring region 170, the first TiN film 20, the first Ti film 21, the second TiN film 22, and the second Ti film 33 are sequentially laminated, and an Al alloy film 29 is further formed to form the second source electrode 12b.

[0083] Next, after forming a polyimide film on the Al alloy film 29, the polyimide film is selectively removed by photolithography and etching to form the first protective film 23 and an opening is formed in the first protective film 23. Next, a first plating film 14a is formed on the Al alloy film 29 exposed through the opening of the first protective film 23. Similarly, the first plating film 14a and the first protective film 23 are formed in the source ring region 170.

[0084] Next, a first second protective film 25a is formed so as to cover the boundary between the first plating film 14a and the first protective film 23. The first second protective film 25a is, for example, a polyimide film. Thereafter, a first external electrode pin 26a is formed on the first plating film 14a via a first solder 24a.

[0085] In this way, the semiconductor device shown in FIG. 1 is completed.

[0086] As described above, according to the silicon carbide semiconductor device according to Embodiment 1, a source ring region is provided between the gate ring region and the edge termination region so as to surround the gate ring region. A second source electrode is provided in the source ring region, and has a function of extracting the hole current flowing from the edge termination region to the active region when the main semiconductor element is off, through the p-type base layer. Therefore, the source ring region can mitigate the current concentration at the end of the active region. Furthermore, even if the avalanche carriers rapidly increase due to cosmic rays, the source ring can absorb them, so that the avalanche carriers can be prevented from reaching the active region, and the breakdown voltage can be improved. In addition, by providing a plating film on the second source electrode in the source ring region, the resistance of the second source electrode can be reduced, and the breakdown voltage of the second source electrode can be improved.

[0087] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. FIG. 9 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The difference between the silicon carbide semiconductor device according to Embodiment 2 and the silicon carbide semiconductor device according to Embodiment 1 is that a short-circuit electrode 500 is provided to connect the first source electrode 12a in the active region 150 and the second source electrode 12b in the source ring region 170.

[0088] Specifically, a dividing region 550 is provided in the gate ring region 160, and a short-circuit electrode 500 is provided in the dividing region 550 without providing the second gate electrode 10b and the gate wiring electrode 17. FIG. 10 is a cross-sectional view taken along line A-A of FIG. 9 showing the structure of the silicon carbide semiconductor device according to Embodiment 2. FIG. 10 is a cross-section of a portion where the short-circuit electrode 500 is provided. As shown in FIG. 10, in the gate ring region 160, an insulating film 530 and an interlayer insulating film 11 are provided on the p ++ -type contact region 8 of the silicon carbide semiconductor substrate, and a short-circuit electrode 500 is provided on the interlayer insulating film 11. By connecting the first source electrode 12a and the second source electrode 12b with the short-circuit electrode 500, the hole current extracted from the source ring region 170 can flow from the second source electrode 12b to the first source electrode 12a, and the current concentration at the end of the active region 150 can be further alleviated.

[0089] There may be at least one short-circuit electrode 500 in the semiconductor chip 600. However, in order to reduce the resistance between the first source electrode 12a and the second source electrode 12b, it is preferable to provide one or more short-circuit electrodes 500 on each side as shown in FIG. 9. Further, in the portion where the dividing region 550 is provided, the path from the second gate electrode 10b to the gate electrode pad 100 becomes long and the resistance becomes large. Therefore, in the portion where the dividing region 550 is provided, it is preferable not to form the MOS structure, for example, not to provide the n + -type source region 7. Here, since the second gate electrode 10b and the gate wiring electrode 17 are not formed in the dividing region 550, the second gate electrode 12b is not ring-shaped. Therefore, when a plurality of dividing regions 550 are provided, it is preferable to shift the positions of the dividing regions 550 on the two opposite sides in the stripe direction of the trench 16 so that the voltage is applied to all of the second gate electrodes 12b.

[0090] As described above, according to Embodiment 2, by providing a short-circuit electrode that connects the first source electrode and the second source electrode, the hole current drawn by the source ring region can flow through the first source electrode, and current concentration at the end of the active region can be further alleviated. Furthermore, the same effects as in Embodiment 1 can be obtained.

[0091] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. FIG. 11 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The difference between the silicon carbide semiconductor device according to Embodiment 3 and the silicon carbide semiconductor device according to Embodiment 2 is that a short-circuit electrode 500 that connects the first source electrode 12a of the active region 150 and the second source electrode 12b of the source ring region 170 is provided without providing a division region 550.

[0092] FIG. 12 is a cross-sectional view taken along line A-A of FIG. 11 showing the structure of the silicon carbide semiconductor device according to Embodiment 3. As shown in FIG. 12, a second insulating film (second insulating film) 532 is provided so as to cover the gate wiring electrode 17 at the location where the short-circuit electrode 500 of the gate ring region 160 is provided, and the short-circuit electrode 500 is provided on the second insulating film 532. The second insulating film 532 insulates the short-circuit electrode 500 and the second gate electrode 10b.

[0093] Alternatively, a configuration may be adopted in which the gate wiring electrode 17 is not provided at the location where the short-circuit electrode 500 of the gate ring region 160 is provided, and the short-circuit electrode 500 is provided on the interlayer insulating film 11 that covers the second gate electrode 10b.

[0094] In the above-described Embodiment 2, since the gate wiring electrode 17 is divided by the short-circuit electrode 500, the path to the gate electrode pad 100 may be long in the second gate electrode 10b close to the division location. On the other hand, in Embodiment 3, since at least the second gate electrode 10b is not divided, the path to the gate electrode pad 100 does not become long.

[0095] As described above, according to Embodiment 3, by providing a short-circuit electrode that connects the first source electrode and the second source electrode without at least interrupting the second gate electrode, it is possible to prevent the path between the second gate electrode and the gate electrode pad from becoming long. Furthermore, the same effects as those of Embodiment 1 and Embodiment 2 can be obtained.

[0096] (Embodiment 4) Next, the structure of the silicon carbide semiconductor device according to Embodiment 4 will be described. FIG. 13 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 4. The difference between the silicon carbide semiconductor device according to Embodiment 4 and the silicon carbide semiconductor device according to Embodiment 2 is that a short-circuit electrode 500 that connects the first source electrode 12a in the active region 150 and the second source electrode 12b in the source ring region 170 is provided on the first external electrode pin 26a and the second external electrode pin 26b.

[0097] FIG. 14 is a cross-sectional view taken along line A-A of FIG. 13 showing the structure of the silicon carbide semiconductor device according to Embodiment 4. As shown in FIG. 14, in the source ring region 170, the second external electrode pin 26a outside (the second electrode pin) 26b is joined via a second solder (the second solder) 24b on a plating film (the second plating film) 14. The second solder 24b may be surrounded by a second second protective film 25b. The other end of the second external electrode pin 26b is connected by a second solder 24b to a metal bar 540 arranged so as to face the front surface of the silicon carbide semiconductor substrate. This metal bar 540 serves as the short-circuit electrode 500. Since the gate wiring electrode 17 is not interrupted in Embodiment 4 as in Embodiment 3, the path to the gate electrode pad 100 does not become long. In FIG. 13, three metal bars 540 serving as the short-circuit electrode 500 are provided, but only one may be provided.

[0098] As described above, according to Embodiment 4, by providing a short-circuit electrode that connects the first source electrode and the second source electrode on the first and second external electrode pins, it is possible to prevent the path between the second gate electrode and the gate electrode pad from becoming long. Furthermore, the same effects as those of Embodiment 1 and Embodiment 2 can be obtained.

[0099] (Embodiment 5) Next, the structure of the silicon carbide semiconductor device according to Embodiment 5 will be described. FIG. 15 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 5. Since the top view is the same as that of Embodiment 1, the description thereof is omitted. The difference between the silicon carbide semiconductor device according to Embodiment 5 and the silicon carbide semiconductor devices according to Embodiments 1 to 4 is that in the n-type silicon carbide epitaxial layer 2 of the source ring region 170, a first p + -type base region 3 is deeply formed at a position facing the second source electrode 12b in the depth direction. This deeply formed portion is referred to as a p + -type region (second semiconductor region of the second conductivity type) 30.

[0100] As shown in FIG. 15, the p + -type region 30 is provided in a ring shape on the surface layer of the n-type silicon carbide epitaxial layer 2 of the source ring region 170, and is preferably wider than the width of the second source electrode 12b. At least, it is preferably wider than the width of the contact hole opened in the interlayer insulating film 11. The p + -type region 30 is a portion where the first p + -type base region 3 is deeply formed, so it has an impurity concentration similar to that of the first p + -type base region 3. Also, the p + -type region 30 preferably does not reach the n + -type silicon carbide substrate 1 in depth.

[0101] By providing the p + -type region 30, the hole current flowing from the edge termination region 168 to the active region 150 during the off state flows into the p + -type region 30 having a lower resistance than the n-type silicon carbide epitaxial layer 2, making it easier to extract the hole current to the second source electrode 12b, and further relaxing the current concentration in the active region 150.

[0102] FIG. 16 is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 5. As shown in FIG. 16, instead of the p + -type region 30, an n+ A form in which a p-type region (a second semiconductor region of the first conductivity type) 31 is provided may be used. + Similar to the p-type region 30, for the n + type region 31, in order to facilitate the flow of hole current, the + impurity concentration of the n-type region 31 is higher than the impurity concentration of the n-type silicon carbide epitaxial layer 2. Also, for the + depth and width of the n-type region 31, they may be the same as those of the p + type region 30. Also, when the impurity concentration of the n + type region 31 is higher than the impurity concentration of the n-type silicon carbide epitaxial layer 2, hole current passes through the upper part of the n + type region 31, and it becomes easier for the hole current to flow to the second source electrode 12b. Therefore, the + impurity concentration of the n-type region 31 is set to be higher than the impurity concentration of the n-type silicon carbide epitaxial layer 2.

[0103] FIG. 17 is another plan view showing the structure of the silicon carbide semiconductor device according to Embodiment 5. In this example, the + p-type region 30, the second source electrode 12b, and the second plating film 14b are the same as those in FIG. 15 in that they are square-shaped in plan view, but are different in that corner portions are intentionally provided at the side portions. Specifically, in FIG. 17, the + p-type region 30, the second source electrode 12b, and the second plating film 14b are made uneven. In this way, by forming the + p-type region 30, the second source electrode 12b, and the second plating film 14b in a closed-loop shape with corners, the + radial width of the p-type region 30 becomes wider, and since an electric field concentrates at the corner portions of the p + type region 30, an effect that it becomes easier to extract hole current is obtained. Also, the second source electrode 12b and the second plating film 14b are linear as in FIG. 15, and even if only the + p-type region 30 is made uneven, the same effect can be obtained. Note that the + p-type region 30 may have a closed-loop shape including corners in the straight-line portions of the sides and can take various shapes. For example, it may be not only uneven but also zigzag-shaped. Also, the + p-type region 30 can be changed to an n + type region 31.

[0104] Further, in the silicon carbide semiconductor device according to Embodiment 5, although the first source electrode 12a and the second source electrode 12b in Embodiment 1 are shown in a form not electrically connected by the short-circuit electrode 500, the short-circuit electrode 500 may be provided as in Embodiment 2. In this case, the top view is the same as FIG. 9. Further, as in Embodiment 3, the short-circuit electrode 500 may be provided without providing the division region 550. In this case, the top view is the same as FIG. 11. Further, as in Embodiment 4, a metal bar 540 (short-circuit electrode) may be provided on the first and second external electrode pins 26a and 26b. In this case, the top view is the same as FIG. 13.

[0105] As described above, according to Embodiment 5, the first p + -type base region is deeply formed at a position facing the second source electrode in the depth direction, and a p + -type region is provided. Alternatively, an n + -type region is provided at the same position as the p + -type region. A hole current flows through the p + -type region or the n + -type region, making it easier to extract the hole current to the second source electrode and further relaxing the current concentration at the end of the active region. Furthermore, the same effect as in Embodiment 1 can be obtained. Also, by providing a short-circuit electrode equivalent to those in Embodiments 2 to 4, the same effects as in Embodiments 2 to 4 can be obtained.

[0106] (Embodiment 6) Next, the structure of the silicon carbide semiconductor device according to Embodiment 6 will be described. FIG. 18 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6. Since the top view is the same as that in Embodiment 1, the description thereof is omitted. The difference between the silicon carbide semiconductor device according to Embodiment 6 and the silicon carbide semiconductor device according to Embodiment 5 is that the second source electrode 12b of the source ring region 170 is provided in the trench 16. Hereinafter, the trench 16 in the active region 150 is referred to as the first trench (the first trench) 16a, and the trench 16 in the source ring region 170 is referred to as the second trench (the second trench) 16b.

[0107] As shown in Fig. 18, the second trench 16b penetrates through the interlayer insulating film 11, the p ++ -type contact region 8, and the p-type base layer 6 to reach the first p + -type base region 3. A second source electrode 12b is embedded in the second trench 16b. Similar to the first embodiment, the second source electrode 12b is a multilayer film in which a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29 are laminated. A part of the second source electrode 12b protrudes from above the second trench 16 to the side of the second second protective film 25b.

[0108] A second plating film 14b is provided on the surface of the second source electrode 12b. The portion of the surface of the second source electrode 12b other than the second plating film 14b is covered with the first protective film 23. Specifically, the first protective film 23 is provided so as to cover the second source electrode 12b, and the second plating film 14b is provided in the opening of the first protective film 23. The second plating film 14b may be surrounded by the second second protective film 25b. The second plating film 14b may be provided on the entire surface of the second source electrode 12b, or selectively, for example, only on the second source electrode 12b at the corner of the source ring region 170. Also, the width of the second source electrode 12b in the sixth embodiment may be approximately the same as the width of the second source electrode 12b in the first to fifth embodiments.

[0109] Also, a p + -type region 30 may be provided at the bottom of the second trench 16b. The p + -type region 30 protects the second trench 16b in the same manner as the second p + -type base region 4, and makes it easier to draw out the hole current to the second source electrode 12b in the same manner as the p + -type region 30 in the fifth embodiment. Thus, by providing the second source electrode 12b in the second trench 16b, the contact area with the p-type region (p ++ -type contact region 8, the first p + -type base region 3, and the p-type base layer 6) can be increased, and the contact resistance can be reduced.

[0110] FIG. 19 is another cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 6. As shown in FIG. 19, instead of the p + -type region 30, an n + -type region 31 may be provided. Similar to the p + -type region 30, in order to make it easier for hole current to flow through the n + -type region 31, for example, the impurity concentration of the n + -type region 31 is higher than the impurity concentration of the n-type silicon carbide epitaxial layer 2. Also, the depth and width of the n + -type region 31 may be the same as those of the p + -type region 30.

[0111] Further, in the silicon carbide semiconductor device according to Embodiment 6, although a form is shown in which the first source electrode 12a and the second source electrode 12b of Embodiment 1 are not electrically connected by the short-circuit electrode 500, the short-circuit electrode 500 may be provided as in Embodiment 2. In this case, the top view is the same as FIG. 9. Also, as in Embodiment 3, the short-circuit electrode 500 may be provided without providing the division region 550. In this case, the top view is the same as FIG. 11. Also, as in Embodiment 4, the metal bar 540 (short-circuit electrode) may be provided on the first and second external electrode pins 26a and 26b. In this case, the top view is the same as FIG. 13.

[0112] As described above, according to Embodiment 6, by providing the second source electrode in the second trench, the contact area with the p-type region can be increased and the contact resistance can be reduced. Also, a p + -type region or an n + -type region is provided at the bottom of the second trench. Hole current flows through the p + -type region or the n + -type region, making it easier to extract hole current from the second source electrode and further relaxing the current concentration at the end of the active region. Furthermore, the same effects as in Embodiment 1 can be obtained. Also, by providing a short-circuit electrode equivalent to those in Embodiments 2 to 4, the same effects as in Embodiments 2 to 4 can be obtained.

[0113] (Embodiment 7) Next, the structure of the silicon carbide semiconductor device according to Embodiment 7 will be described. FIG. 20 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 7. Since the top view is the same as that of Embodiment 1, the description thereof is omitted. The difference between the silicon carbide semiconductor device according to Embodiment 7 and the silicon carbide semiconductor devices according to Embodiments 1 to 4 is that a lifetime killer region 32 is provided at a position facing the second source electrode 12b in the depth direction at the interface between the n-type silicon carbide epitaxial layer 2 of the source ring region 170 and the first p + type base region 3.

[0114] As shown in FIG. 20, the lifetime killer region 32 is provided at the interface between the n-type silicon carbide epitaxial layer 2 of the source ring region 170 and the first p + type base region 3. That is, the surface of the lifetime killer region 32 on the second source electrode 12b side is provided in the first p + type base region 3, and the surface of the lifetime killer region 32 on the drain electrode 13 side is provided in the n-type silicon carbide epitaxial layer 2. The surface of the lifetime killer region 32 on the drain electrode 13 side may reach the n + type silicon carbide substrate 1. The lifetime killer region 32 is preferably wider than the width of the second source electrode 12b. At least, it is preferably wider than the width of the contact hole opened in the interlayer insulating film 11.

[0115] The lifetime killer region 32 is, for example, a region in which the crystal structure is damaged by irradiating with an electron beam, protons (H + ), helium (He), platinum (Pt), etc. By providing the lifetime killer region 32, the carrier lifetime in the source ring region 170 can be shortened, the hole current flowing from the edge termination region 168 to the active region 150 can be reduced, and the current concentration in the active region 150 can be further alleviated. Also, a form in which both the lifetime killer region 32 and the p + type region 30 are provided may be adopted, or a form in which both the lifetime killer region 32 and the n+ It may be in a form in which both of the type regions 31 are provided.

[0116] Also, in the silicon carbide semiconductor device according to Embodiment 7, although the first source electrode 12a and the second source electrode 12b of Embodiment 1 are shown in a form not electrically connected by the short - circuit electrode 500, the short - circuit electrode 500 may be provided as in Embodiment 2. In this case, the top view is the same as FIG. 9. Also, as in Embodiment 3, the short - circuit electrode 500 may be provided without providing the division region 550. In this case, the top view is the same as FIG. 11. Also, as in Embodiment 4, the metal bar 540 (short - circuit electrode) may be provided on the first and second external electrode pins 26a and 26b. In this case, the top view is the same as FIG. 13.

[0117] As described above, according to Embodiment 7, a lifetime killer region is provided at a position facing the second source electrode in the depth direction. From the lifetime killer region, the carrier lifetime in the source ring region can be shortened, the hole current flowing from the edge termination region to the active region can be decreased, and the current concentration at the end of the active region can be further alleviated. Furthermore, the same effect as in Embodiment 1 can be obtained. Also, by providing a short - circuit electrode equivalent to those in Embodiments 2 - 4, the same effects as in Embodiments 2 - 4 can be obtained.

[0118] (Embodiment 8) Next, the structure of the silicon carbide semiconductor device according to Embodiment 8 will be described. FIG. 21 is a cross - sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 8. Since the top view is the same as that of Embodiment 1, the description thereof is omitted. The difference between the silicon carbide semiconductor device according to Embodiment 8 and the silicon carbide semiconductor device according to Embodiment 7 is that the second source electrode 12b of the source ring region 170 is provided in the second trench 16b.

[0119] As shown in FIG. 21, the second trench 16b penetrates the inter - layer insulating film 11, the p ++ - type contact region 8 and the p - type base layer 6 to reach the first p +It reaches the p-type base region 3. A second source electrode 12b is embedded in the second trench 16b. Similar to the first embodiment, the second source electrode 12b is a multilayer film in which a NiSi electrode 15, a first TiN film 20, a first Ti film 21, a second TiN film 22, a second Ti film 33, and an Al alloy film 29 are laminated. A part of the second source electrode 12b protrudes from above the second trench 16b toward the second second protective film 25b side.

[0120] A second plating film 14b is provided on the surface of the second source electrode 12b. The portion of the surface of the second source electrode 12b other than the second plating film 14b is covered with the first protective film 23. Specifically, the first protective film 23 is provided so as to cover the second source electrode 12b, and the second plating film 14b is provided in the opening of the first protective film 23. The second plating film 14b may be surrounded by the second second protective film 25b. The second plating film 14b may be provided on the entire surface of the second source electrode 12b, or may be selectively provided only on the second source electrode 12b at the corner portion of the source ring region 170, for example. Also, the width of the second source electrode 12b in the eighth embodiment may be about the same as the width of the second source electrode 12b in the first to fourth embodiments.

[0121] As shown in FIG. 21, the lifetime killer region 32 is provided at the interface between the n-type silicon carbide epitaxial layer 2 of the source ring region 170 and the first p + type base region 3. That is, the surface of the lifetime killer region 32 on the second source electrode 12b side is provided in the first p + type base region 3, and the surface of the lifetime killer region 32 on the drain electrode 13 side is provided in the n-type silicon carbide epitaxial layer 2. The surface of the lifetime killer region 32 on the drain electrode 13 side may reach the n + type silicon carbide substrate 1. The lifetime killer region 32 is preferably wider than the width of the second trench 16b.

[0122] The lifetime killer region 32 is, for example, an electron beam or a proton (H +) By irradiating with helium (He), platinum (Pt), etc., it is an area where the crystal structure is damaged. By providing the lifetime killer region 32, the carrier lifetime in the source ring region 170 can be shortened, the hole current flowing from the edge termination region 168 into the active region 150 can be reduced, and the current concentration in the active region 150 can be further alleviated.

[0123] Also, in the silicon carbide semiconductor device according to Embodiment 8, although the form in which the first source electrode 12a and the second source electrode 12b of Embodiment 1 are not electrically connected by the short-circuit electrode 500 is shown, the short-circuit electrode 500 may be provided as in Embodiment 2. In this case, the top view is the same as FIG. 9. Also, as in Embodiment 3, the short-circuit electrode 500 may be provided without providing the division region 550. In this case, the top view is the same as FIG. 11. Also, as in Embodiment 4, the metal bar 540 (short-circuit electrode) may be provided on the first and second external electrode pins 26a and 26b. In this case, the top view is the same as FIG. 13.

[0124] As described above, according to Embodiment 8, by providing the second source electrode in the second trench, the contact area with the p-type region can be increased and the contact resistance can be reduced. Also, a lifetime killer region is provided at the bottom of the second trench. The lifetime killer region can shorten the carrier lifetime in the source ring region, reduce the hole current flowing from the edge termination region to the active region, and further alleviate the current concentration at the end of the active region. Furthermore, the same effect as in Embodiment 1 can be obtained. Also, by providing a short-circuit electrode equivalent to those in Embodiments 2 to 4, the same effects as in Embodiments 2 to 4 can be obtained.

[0125] As described above, the present invention can be variously modified without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions and impurity concentrations of each part are variously set according to the required specifications and the like. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but the present invention is also applicable to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Further, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention also holds true when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0126] As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters for automobiles.

Explanation of Reference Numerals

[0127] 1, 1001 n + -type silicon carbide substrate 2, 1002 n-type silicon carbide epitaxial layer 2a First n-type silicon carbide epitaxial layer 2b Second n-type silicon carbide epitaxial layer 3, 1003 First p + -type base region 3a Lower first p + -type base region 3b Upper first p + -type base region 4, 1004 Second p + -type base region 5, 1005 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6, 1006 p-type base layer 7, 1007 n + -type source region 8, 1008 p ++ -type contact region 9, 1009 Gate insulating film 10. 1010 Gate electrode 10a. First gate electrode 10b. Second gate electrode 11. 1011 Interlayer insulating film 12. 1012 Source electrode 12a. First source electrode 12b. Second source electrode 13. 1013 Backside electrode 14. 1014 Plating film 14a. First plating film 14b. Second plating film 15. 1015 NiSi electrode 16. 1016 Trench 16a. First trench 16b. Second trench 17. 1017 Gate wiring electrode 20. 1020 First TiN film 21. 1021 First Ti film 22. 1022 Second TiN film 23. 1023 First protective film 24. 1024 Solder 24a. First solder 24b. Second solder 25. 1025 Second protective film 25a. First of the second protective film 25b. Second of the second protective film 26. 1026 External electrode pin 26a. First external electrode pin 26b. Second external electrode pin 29. 1029 Al alloy film 30 p + -type region 31 n + -type region 32. Lifetime killer region 33. 1033 Second Ti film 34 p-type region 100. 1100 Gate electrode pad 104. 1104 Source electrode pad 150. 1150 Active region 150a. Effective region 160, 1160 Gate ring region 163, 1163 First JTE region 165, 1165 Second JTE region 167, 1167 n + -type stopper region 168, 1168 Edge termination region 170 Source ring region 202, 1202 Electrode pads of current sense section 230, 1230 Active region of current sense section 400, 1400 High-performance region 500 Short-circuit electrode 530, 1530 Insulating film 532 Second insulating film 540 Metal bar (short-circuit electrode) 550 Disconnection region 600, 1600 Semiconductor chip

Claims

1. A semiconductor device comprising a semiconductor element region provided with a plurality of unit cells of a trench-type MOSFET including a first trench, a gate runner region overlapping with a gate runner provided outside the semiconductor element region, a ring region provided outside the gate runner region and including a ring electrode surrounding the semiconductor element region in a plan view, a termination region surrounding the ring region in a plan view, and comprising: the semiconductor element region and the gate runner region have a first pn junction interface at a position deeper than the bottom surface of the first trench on the front surface side of the semiconductor substrate, the ring region includes a second trench and has a second pn junction interface provided at a position deeper than the first pn junction interface below the second trench, a semiconductor device, characterized in that at least a part of the ring electrode is provided inside the second trench.

2. The semiconductor device according to claim 1, characterized in that the second trench is wider than the first trench.

3. The unit cell is a gate insulating film and a gate electrode provided in the first trench, a source region of a first conductivity type in contact with the gate insulating film, a base layer of a second conductivity type provided at least partially under the source region and in contact with the gate insulating film, and the semiconductor device according to claim 1, characterized by including.

4. Comprising a source electrode in contact with the source region, the semiconductor device according to claim 3, characterized in that the ring electrode is fixed to the potential of the source electrode.

5. The semiconductor device according to claim 4, characterized in that the ring electrode is short-circuited to the source electrode.

6. Comprising a high-concentration region of a second conductivity type having a higher impurity concentration than the base layer, the high-concentration region forms the second pn junction interface, the semiconductor device according to any one of claims 3 to 5, characterized in that the ring electrode is in contact with the high-concentration region.

7. A semiconductor element region provided with a plurality of unit cells of a trench-type MOSFET including a first trench, a source region of a first conductivity type in contact with the first trench, and a base layer of a second conductivity type provided at least partially under the source region and in contact with the first trench, a gate runner region overlapping with a gate runner provided outside the semiconductor element region, A ring region including a ring electrode provided outside the gate runner region and surrounding the semiconductor element region in a plan view; A termination region surrounding the ring region in a plan view; A high-concentration region of the second conductivity type having an impurity concentration higher than that of the base layer and having a pn junction interface at a position deeper than the bottom surface of the first trench; A well region of the second conductivity type provided from the semiconductor element region to the ring region; Comprising; In the ring region, the ring electrode is electrically connected to the well region, and the upper surface of the high-concentration region is in contact with the lower surface of the well region. A semiconductor device characterized by this.

8. The semiconductor device is configured to include a silicon carbide semiconductor substrate, The semiconductor device according to claim 6 or 7, wherein the high-concentration region is in contact with the bottom surface of a step where the thickness of the silicon carbide semiconductor substrate is reduced.

9. The ring electrode includes a first ring electrode at least a part of which is embedded in the second trench and the rest of which protrudes from above the second trench, and a second ring electrode disposed on the surface of the first ring electrode. The semiconductor device according to claim 1, characterized by this.

10. The semiconductor device according to claim 9, wherein the second ring electrode is a plating film.

11. The semiconductor device according to claim 1, wherein the second trench is not provided in the semiconductor element region.

12. The semiconductor device according to any one of claims 1 to 11, wherein the termination region includes at least one of a guard ring or a JTE.

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