Freely configurable power semiconductor module

Abstract

The power semiconductor module (10) includes at least one semiconductor board (16) including at least two semiconductor chips (24), each semiconductor chip (24) having two power electrodes (26, 28). The power semiconductor module (10) further includes an adapter board (14) attached to the semiconductor board (16) above the at least two semiconductor chips (24). The adapter board (14) includes a terminal area (46) for each semiconductor chip (24) on a side remote from the semiconductor board (16). The adapter board (14) provides, in each terminal area (46), a power terminal (42) for each power electrode (26, 28) of the semiconductor chip (24) associated with the terminal area (46). Each power terminal (42) is electrically connected to the semiconductor chip (24) via a conductive vertical post (34, 36) below the terminal area (46).

Description

Technical Field

[0001] Field of the Invention This invention relates to the field of power electronics. In particular, this invention relates to power semiconductor modules.

Background Art

[0002] Background of the Invention Multi-chip power semiconductor modules are typically designed for a defined topology (such as a half-bridge configuration), and since the power semiconductor chips are connected in parallel and controlled, it may not be possible to extract the individual information of the chips. By using various individual modules, it is necessary to implement a complex topology. Power module terminals are typically limited to basic connections that may not allow for the extraction of individual diagnostic signals of the chips (such as the mounting temperature and chip current).

[0003] US 2017 077 068 A1 shows a semiconductor module having a substrate to which chips are bonded and a printed circuit board connected to the substrate via conductive posts.

[0004] US 2019 / 150 268 A1 shows a semiconductor module. The semiconductor module has two substrates having switching elements thereon, which are connected to an upper circuit board via vertical posts, which connect the two substrates to each other. The circuit board includes several conductive areas connected to the vertical posts.

[0005] US 2017 / 047 923 A1 shows a power semiconductor module having a semiconductor switch on a substrate. One electrode of the semiconductor switch is connected to a circuit board above the substrate via a post.

[0006] US 2017 / 112 005 A1 relates to a power semiconductor module including a plurality of sub-modules connected via removable jumpers. The removable jumpers enable the connection between one or more power semiconductor switches in the sub-modules to be reconfigured. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] DESCRIPTION OF THE INVENTION An object of this invention is to provide a configurable power semiconductor module with a small installation area and a low stray inductance. MEANS FOR SOLVING THE PROBLEMS

[0008] This object is achieved by the subject matter of the independent claims. Further exemplary embodiments are apparent from the dependent claims and the following description.

[0009] This invention relates to a power semiconductor module. The semiconductor module can be a device that mechanically and electrically interconnects two or more semiconductor chips with each other and with terminals that can be exposed by the module's housing. Here and hereinafter, the term "power" can relate to the ability of the semiconductor module and / or components of the semiconductor module to handle currents above 10 A and / or voltages above 100 V.

[0010] According to an embodiment of this invention, the power semiconductor module includes at least one semiconductor board having at least two semiconductor chips, and each semiconductor chip has two power electrodes. The semiconductor board can be a substrate to which the semiconductor chips are bonded to a metallization layer of the substrate. The semiconductor board can be a printed circuit board to which the semiconductor chips are attached.

[0011] The semiconductor chip can be a controllable device such as a transistor and / or a thyristor. Some of the semiconductor chips may be diodes. The semiconductor chip can be based on Si or SiC or another wide bandgap material. The semiconductor chips may be arranged side by side with each other in a semiconductor board and / or may be arranged substantially in one layer.

[0012] The power electrodes can be an emitter and a collector, or a source and a drain. The controllable semiconductor chip may also include a control electrode such as a gate electrode.

[0013] According to an embodiment of the present invention, the power semiconductor module includes an adapter board attached to the semiconductor board above at least two semiconductor chips, and the adapter board includes a terminal area for each semiconductor chip on the side farther from the semiconductor board. The adapter board may be attached to the lower semiconductor board via a housing and / or may be electrically connected to the semiconductor board. The adapter board can be a printed circuit board including terminals on one (outer) side and electrical connections to the semiconductor board on the other (inner) side.

[0014] For each semiconductor chip, the terminal area can be arranged above the semiconductor area. The terminal areas for different semiconductor chips can be designed equally. The terminal area can provide terminals for individually connecting to all the electrodes of the semiconductor chip or at least the power electrodes. In the semiconductor board and the adapter board, the semiconductor chips may be electrically and / or DC insulated from each other. Only the connection of the terminals can generate an electrical connection between the semiconductor chips.

[0015] According to one embodiment of the present invention, in each terminal area, the adapter board provides power terminals for each power electrode of the semiconductor chip associated with the terminal area. Optionally, one or more auxiliary terminals for electrical connection to the control electrode, to the power electrode, and / or to the sensor associated with the semiconductor chip may also be provided in the terminal area.

[0016] Generally, a terminal can be a conductive element to which another conductor can be attached. The adapter board may be disposed on the semiconductor chip and / or may be bonded to all control signals and sensor signals of the semiconductor chip. The adapter board may enable a flexible topology configuration and / or diagnostic signal extraction.

[0017] According to one embodiment of the present invention, each power terminal for the semiconductor chip associated with the terminal area is electrically connected to the semiconductor chip via a conductive vertical post below the terminal area (and / or below the power terminal). The conductive post can be an elongated and straight metal body. The vertical direction can be perpendicular to the plane defined by the extension of the semiconductor board and / or the adapter board. The vertical direction can also be perpendicular to the plane in which the semiconductor chip is disposed. The vertical post can end directly at the power electrode of the chip or at a conductor area provided by the semiconductor board and electrically connected to the power electrode.

[0018] Using the terminal area, the semiconductor chips in the module can be interconnected in all desired topologies such as parallel, series, half-bridge, etc. The interconnection can be performed using jumpers and / or bridges. Due to the vertical posts below the terminal area, the module can be designed to be compact, have a high power density, and have a low stray inductance.

[0019] Here, the term "below ~" may refer to the projection of the terminal area onto the semiconductor board along the vertical direction. If a component is in the projected area, it can be regarded as being below the terminal area.

[0020] The multi-chip power semiconductor module may provide separate connections for all the power electrodes and optional control electrodes of each semiconductor chip, and all the semiconductor chips can be arranged to be DC-insulated from each other. This may enable the construction of various topologies and / or converter-in-packages. In that case, if auxiliary terminals are also provided, this may additionally enable advanced sensing and control for each chip.

[0021] Examples of different topologies are an interleaved topology where the midpoints of several half-bridges are star-connected, a multiphase topology, a half-bridge topology, a full-bridge topology, and / or a multilevel topology, such as an NPC bridge, etc. Also, for example, an adaptive topology that uses controlled parallelization during operation may be possible, and it can be used to optimize efficiency with respect to the load profile.

[0022] According to an embodiment of the present invention, the adapter board provides at least one auxiliary terminal in the terminal area of the semiconductor chip associated with the terminal area, and the auxiliary terminal is connected to a conductive vertical post below the terminal area and / or below the auxiliary terminal. The auxiliary terminal may be smaller than the power terminal and / or may have a lower current rating.

[0023] According to an embodiment of the present invention, the semiconductor chip associated with the terminal area includes a control electrode, and one of the auxiliary terminals is electrically connected to the control electrode of the semiconductor chip using the conductive vertical post. The vertical post may be directly connected to the gate electrode of the semiconductor chip.

[0024] According to one embodiment of the present invention, the semiconductor board includes a sensor for a semiconductor chip associated with a terminal area. The sensor can be one of a temperature sensor and a current sensor. The temperature sensor can sense the temperature of the semiconductor chip. A current sensor (such as a load current mirror) can sense the load current passing through the semiconductor chip. The sensor can be disposed below the terminal area. The auxiliary terminal can be electrically connected to the sensor via its conductive vertical post.

[0025] According to one embodiment of the present invention, the auxiliary terminal is electrically connected to the power electrode of the semiconductor chip associated with the terminal area via a conductive vertical post. Such an auxiliary terminal is connected to the conductive vertical post via an adapter board, and the conductive vertical post may also connect each power terminal to each power electrode.

[0026] According to one embodiment of the present invention, each of the power terminals has at least two plug connectors. The plug connector can be a male connector or a female connector designed to be mechanically and electrically reversibly connected to another plug connector.

[0027] The adapter board includes a jumper connector for interconnecting two plug connectors for electrically connecting the power electrodes of different semiconductor chips. The jumper connector can be regarded as a jumper.

[0028] However, it may also be possible for the power terminals of different chips to be connected to a joined interconnect such as a metal strip, line, and / or cable that can be regarded as a bridge and / or bridge interconnect.

[0029] According to one embodiment of the present invention, some or all of the power terminals are arranged in the outer region of each terminal area, and the outer region is arranged at the boundary of the adapter board. This part of the power terminal, which may include one or more plug connectors, can be used to connect the terminals of the power semiconductor module.

[0030] According to one embodiment of the present invention, at least one auxiliary terminal is arranged in the inner region of the terminal area, and the outer region is arranged between the boundary of the adapter board and the inner region. There may also be a second outer region or an intermediate region where a part of the power terminal is arranged. The second outer region or the intermediate region can be arranged between the first outer region and the inner region.

[0031] It is possible that the inner region and optionally the second outer region are covered by the gate driver board. In that case, the gate driver board can be connected to the auxiliary terminal by a vertical interconnect.

[0032] The gate driver board can cover the second outer region where the power terminals are interconnected with jumpers and / or bridges. Using the gate driver board, per-chip control and / or diagnosis can be performed. A control signal can be applied to the auxiliary terminal interconnected with the control electrode. A measurement signal can be received from the auxiliary terminal interconnected with the power electrode and / or the sensor.

[0033] According to one embodiment of the present invention, the terminal area is arranged in at least one row on the adapter board. Also, the semiconductor chips can be arranged in one or more rows below the terminal area. For example, two rows can be arranged symmetrically with respect to the central vertical plane of the power semiconductor module.

[0034] There are several possibilities regarding how the semiconductor board can be designed. For example, the semiconductor board can be designed based on a substrate with a metallization layer, based on a printed circuit board, and / or based on a chip package attached to a base plate.

[0035] According to one embodiment of the present invention, the semiconductor board includes a substrate having a structured metallization layer to which at least two semiconductor chips are bonded. The substrate may be made of polymer and / or ceramics and may be covered with a metallization layer on one or both sides. Also, one or more separated lead frames may be possible as the substrate. The metallization layer may be structured, i.e., divided, into several areas, and several areas may be used to connect and / or bond one or more semiconductor chips and / or vertical posts.

[0036] According to one embodiment of the present invention, the vertical post is a pin, and the pin is connected to an adapter board and pressed onto a contact area provided by the semiconductor board. The head of each vertical post may also be bonded to each contact area of the semiconductor board. The contact area may be an electrode of the semiconductor chip itself or may be provided by a part of the metallization layer.

[0037] The adapter board may be a printed circuit board to which a pin grid is bonded to its substrate. The pin grid may provide pins and / or vertical posts. The pin grid may be bonded to the semiconductor board. The bonding may be realized, for example, by sintering, soldering, or conductive adhesive bonding, for example, by an adhesive cap on the pin.

[0038] According to one embodiment of the present invention, the semiconductor board includes chip scale packages for each semiconductor chip. Each chip scale package may include at least one semiconductor chip, vertical posts (e.g., electroplated vias and redistribution layers) connected to the semiconductor chip, and a molded or PCB encapsulation in which the semiconductor chip and the vertical posts are embedded. Each chip package may also provide a bonding area to which the vertical posts are electrically connected. The adapter board is bonded to the bonding area of the chip scale package. The chip scale package may be attached to a common base plate of the module. The bonding area may be provided on the upper surface of the chip scale package that may be arranged in the same plane.

[0039] The semiconductor chip may be pre-mounted in a chip scale chip package having a bonding area on the upper side to which the adapter board may be bonded, for example, by soldering, sintering, or conductive adhesive bonding.

[0040] According to one embodiment of the present invention, the adapter board and the semiconductor board are provided by a multilayer circuit board in which at least two semiconductor chips are embedded. It is also possible that only the semiconductor board is provided by a multilayer circuit board. In either case, the vertical posts may be provided as through vias of the multilayer circuit board, and the through vias may pass through multiple layers of the multilayer circuit board.

[0041] The multilayer circuit board may be made of several polymer layers and conductive layers between and / or on one or both sides thereof, and they are laminated together. The semiconductor chips may be embedded in the multilayer circuit board during the lamination process.

[0042] According to one embodiment of the present invention, a power semiconductor module includes a gate driver board attached to an adapter board, and vertical pins interconnect the gate driver board with auxiliary terminals on the adapter board. The gate driver board, which may be a printed circuit board, may process measurement signals from semiconductor chips and / or generate control signals applied to the semiconductor chips. The gate driver board may be mounted on / within the adapter board.

[0043] According to one embodiment of the present invention, the gate driver board covers only a part of the power terminals in the terminal area, for example, only the power terminals in the inner area. For example, the gate driver board may cover an area where power terminals of different semiconductor chips are interconnected and / or an area where auxiliary terminals are arranged.

[0044] In summary, the power semiconductor module provides power terminals and optionally auxiliary terminals separately to all of the semiconductor chips of the module. Using the exposed terminals, each semiconductor chip can be individually inspected at the factory and / or during use.

[0045] With the vertical posts, it is possible to achieve the maximum power density with a minimum substrate area, no space is required for wire bonding, and symmetric heat dissipation and better reliability can be achieved. Further, the vertical posts can provide low inductance and a symmetric electromagnetic design.

[0046] These and other aspects of the present invention will become apparent from the embodiments described below and will be elucidated with reference to the embodiments.

[0047] Brief Description of the Drawings The subject matter of the present invention will be described in more detail in the following text with reference to exemplary embodiments shown in the accompanying drawings.

Brief Description of the Drawings

[0048]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0049] The reference signs used in the drawings, and their meanings, are listed in summary form in a list of reference signs. In principle, in the drawings, the same reference sign is given to the same part.

[0050] Detailed Description of Exemplary Embodiments FIG. 1 shows a top view of a power semiconductor module 10 to which a gate driver board 12 is attached, while FIG. 2 shows a cross-sectional view of the power semiconductor module 10.

[0051] As shown in FIG. 2, the module 10 is composed of a gate driver board 12, the gate driver board 12 is attached to an adapter board 14, and the adapter board 14 is attached to a semiconductor board 16.

[0052] The semiconductor board may include a substrate 18 having one or more metallization layers 20, 22, such as a DBC (direct bonded copper) substrate or an IMS (insulated metal substrate). The metallization layer 20 may be structured into areas 20a, 20b, 20c that are DC-insulated from each other with respect to the semiconductor board 16. On the areas 20a, 20b, 20c, semiconductor chips 24 are bonded using a first power electrode 26. Opposite sides of each of the semiconductor chips 24 provide a second power electrode 28 and a control electrode 30. For example, the semiconductor chips 24 may be Si and / or SiC devices such as transistors and / or thyristors.

[0053] For example, one or more sensors 32 that can sense, for example, the temperature of the semiconductor chip 24 and / or the current passing through the semiconductor chip 24 may be incorporated into and / or attached to the semiconductor chip 24. Such sensors 32 may provide a contact area 33 facing the adapter board 14. Also, the electrodes 28, 30, and a part of the areas 20a, 20b, 20c not covered by the chip 24 may also be regarded as contact areas facing the adapter board 14. The one or more sensors 32 may be mounted sensors of the respective semiconductor chips 24, that is, integrated into the respective semiconductor chips 24.

[0054] An adapter board 14, which can be a printed circuit board such as a metal core PCB and / or a flexible PCB, includes conductive vertical posts 34, 36, 38, 40 on the side facing the semiconductor board 16. The posts 34, 36, 38, 40 can electrically interconnect the adapter board 14 with the contact areas 28, 30, 33 of the semiconductor board 14.

[0055] On the opposite side shown in FIG. 1, the adapter board 14 includes a power terminal 42 and an auxiliary terminal 44. The terminals 42, 44 are disposed in a terminal area 46 disposed above the respective semiconductor chips 24. In FIG. 1, only one terminal area 46 and internal terminals are depicted. However, it is shown that the module 10 has two columns 48 of terminal areas 46.

[0056] In each terminal area 46, one power terminal 42 can be electrically connected to the respective areas 20a, 20b, 20c and the corresponding power electrodes 26 via one or more posts 34. One power terminal 42 can be directly electrically connected to the other power electrode 28 via one or more posts 36. One auxiliary terminal 44 can be directly electrically connected to the control electrode 30 via a post 38. One auxiliary terminal 44 can be directly electrically connected to the sensor 32 via a post 40. One auxiliary terminal 44 may also be connected to one of the power electrodes 28, 30 via the adapter board 14.

[0057] The semiconductor chips 24 can be interconnected to different topologies using a connector 50 that interconnects the power terminals 44 of different semiconductor chips 24. It may be the case that the power terminals 44 include plug connectors 52, and that the connector 50 is a jumper connector that can be inserted into these plug connectors 52. The connector 50 may also be a bridge that is joined to the power terminal 42 at its ends. Using the connector 50, the semiconductor chips inside the module 10 can be interconnected to different topologies such as series, parallel, half-bridge, etc.

[0058] Each terminal area 46 can be divided into an inner area 46a where the auxiliary terminal 44 is disposed, an intermediate area 46b where the inner portion of the power terminal 42 is disposed, and an outer area 46c where the outer portion of the power terminal 42 is disposed.

[0059] The outer region 46c may be provided at the boundary of the adapter board 14, and the outer portion of the terminal 42 (and optionally, the plug connector 52 in this outer portion) can be used to connect the module terminal 54 to the power terminal 42 (see FIG. 2).

[0060] The inner portion of the terminal 42 (and optionally, the plug connector 52 in this portion) in the intermediate region 46b between the outer region 46c and the inner region 46a can be used to interconnect the semiconductor chips 24 to each other.

[0061] In the inner region 46a, the gate driver board 12 can be connected to the auxiliary terminal 44. Returning to FIG. 2, the auxiliary terminal may include a press-fit plug into which the pin 56 protruding from the gate driver board 12 can be inserted. The pin 56, similar to the vertical posts 34, 36, 38, 40, is aligned perpendicular to the boards 12, 14, 16 and / or can protrude from the side of the gate driver board 12 facing the adapter board 14. On the opposite side, the gate driver board 12 can include gate driver components 58 such as control components, components for evaluating sensor signals, and / or passive elements such as capacitors and resistors.

[0062] The gate driver board 12 may be smaller than the adapter board 14 and / or may cover only the adapter board 14 in the inner region 46a and the intermediate region 46b of the terminal area 46.

[0063] FIG. 2 also shows that the adapter board 14 and the semiconductor board 16 can be mechanically interconnected to each other via a housing 60 that can be attached to the adapter board 14 and the semiconductor board 16.

[0064] Figures 3 and 4 show the possibilities of different terminal areas 46. Generally, the plug connectors 52 of the power terminals 42 can be arranged in two parallel rows. Also, the auxiliary terminals 44 can be arranged in a single row that can be parallel to the power terminals 42. As shown in FIGS. 1 and 4, the auxiliary terminals 44 can be arranged next to both power terminals 44. However, as shown in FIG. 3, the auxiliary terminals 44 can also be arranged between the power terminals.

[0065] FIG. 5 shows that the gate driver board 12 can have a press-fit pin array having pins 56 that can be pushed into the auxiliary terminals 44 designed as press-fit plugs. Further, the vertical posts 34, 36, 38, 40 can be pins that are pressed against the contact areas 28, 30, 33. Such pins 34, 36, 38, 40 can have heads and / or caps 62 adapted to be sintered to their respective contact areas 28, 30, 33. For example, the pins 34, 36, 38, 40 may be made of Cu and can have sintered caps made of Ag.

[0066] The interior of the module 10 between the adapter board 14, the semiconductor board 16, and the housing 60 may be filled with gel and / or embedded with resin.

[0067] The module of FIG. 5 can be manufactured by first picking up the chips 24 and placing them on the substrate 18 and then sintering them to the metallization layer 20. Thereafter, the adapter board 14 can be aligned and the pins 34, 36, 38, 40 can be sintered. Thereafter, the module can be encapsulated. Finally, for example, a customer of the module 10 can push in the jumper connector 50 and the gate driver board 12. This manufacturing can have the advantage that no embedding and / or wafer-level processing will be required.

[0068] FIG. 6 shows a power semiconductor module 10 in which the semiconductor board 16 includes chip-scale packages 64 for each semiconductor chip 24. To form the semiconductor board 16, the chip-scale packages 64 can be joined to the substrate 18 using a structured metallization layer 20.

[0069] Each chip scale package 64 can include one or more of the semiconductor chips 24, vertical posts (such as electroplated Cu vias and / or redistribution layers) 34, 36, 38, 40 connected to the semiconductor chips 24, and a molding and / or PCB encapsulation 66 in which the semiconductor chips 24 and the vertical posts 34, 36, 38, 40 are embedded. Each chip scale package can also include a lead frame and / or a base plate 65 for bonding the chip package to the substrate 18 of the module 10.

[0070] On the opposite side, each chip scale package 64 can provide a bonding area 68 to which the vertical posts 34, 36, 38, 40 are electrically connected. The adapter board 14 can then be bonded to the bonding area 68 of the chip package 64.

[0071] For example, each chip scale package 64 can house a reverse conducting IGBT with a mounted temperature and current sensor, an IGBT with a freewheeling diode, or two parallel SiC MOSFETs.

[0072] The module of FIG. 5 can be manufactured by first picking up the chip scale packages 64 and placing them on the substrate 18, and then sintering them to the metallization layer 20. Thereafter, the adapter board 14 can be aligned and bonded to the bonding area. Finally, for example, a customer of the module 10 can push in the jumper connectors 50 and the gate driver board 12. This manufacturing can have the benefits of no accuracy issues regarding aligning the boards and no need for further encapsulation.

[0073] FIG. 6 shows a power semiconductor module 10 in which an adapter board 14 and a semiconductor board 16 are provided by a multilayer circuit board 70 in which at least two semiconductor chips 24 are embedded. The multilayer circuit board 70 can be made from a metal base plate 22 and a lead frame 72 to which the semiconductor chips 24 are joined. A polymer insulating layer can be disposed between the metal layers 22, 72. Vertical posts 34, 36, 38, 40 can be provided by through vias and metallization tracks in the multilayer circuit board 70.

[0074] The module of FIG. 6 can be manufactured by picking up the semiconductor chips 24 and placing them on the lead frame 72 and then sintering them to the lead frame 72. Thereafter, a PCB laminate may be disposed between the metal layers 22, 72 and may include not only the metal layers of the adapter board 14 but also other components such as through vias 34, 36, 38, 40, terminals 42, 44, etc., all of which can be laminated together. Finally, for example, a customer of the module 10 can push in jumper connectors 50 and a gate driver board 12. This manufacturing can have the benefit that the module can have a fairly small height and that only a few bonding steps and manufacturing steps will be required. Further, no additional substrate 18 will be needed.

[0075] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered as illustrative rather than restrictive, and the present invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and achieved by those skilled in the art who are proficient in the relevant technical field and practice the claimed invention, from the study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A single processor or controller or other unit may perform the functions of several items recited in the claims. The mere fact that different dependent claims recite certain means does not indicate that a combination of these means cannot be used advantageously. Any reference signs in the claims should not be construed as limiting the scope.

Explanation of Reference Signs

[0076] List of Reference Signs 10 Power semiconductor module 12 Gate driver board 14 Adapter board 16 Semiconductor board 18 Substrate 20 Metallization layer 20a, 20b, 20c Areas 22 Metallization layer 24 Semiconductor chip 26 First power electrode 28 Second power electrode 30 Control electrode 32 Sensor 33 Contact area 34 Vertical post 36 Vertical post 38 Vertical post 40 Vertical post 42 Power terminal 44 Auxiliary terminal 46 Terminal area 46a, 46b, 46c Areas 48 Column 50 Connector 52 Plug Connector 54 Module Terminal 56 Pin 58 Gate Driver Component 60 Housing 62 Head, Cap 64 Chip Scale Package 65 Lead Frame and / or Base Plate 66 Molding and / or PCB Encapsulation 68 Bonding Area 70 Multilayer Circuit Board 72 Lead Frame.

Claims

1. A power semiconductor module (10) comprising: at least one semiconductor board (16) including at least two semiconductor chips (24), each semiconductor chip (24) having two power electrodes (26, 28), and said power semiconductor module (10) further comprising: an adapter board (14) mounted on said semiconductor board (16) above said at least two semiconductor chips (24), said adapter board (14) including a terminal area (46) for each semiconductor chip (24) on the side farther from said semiconductor board (16); said adapter board (14) providing, in each terminal area (46), a power terminal (42) for each power electrode (26, 28) of said semiconductor chip (24) associated with said terminal area (46); each power terminal (42) being electrically connected to said semiconductor chip (24) via a conductive vertical post (34, 36) below said terminal area (46); each of said power terminals (42) having at least two plug connectors (52); said adapter board (14) including jumper connectors (50) for interconnecting two plug connectors (52) for electrically connecting power electrodes (26, 28) of different semiconductor chips (24), a power semiconductor module (10).

2. Said adapter board (14) providing at least one auxiliary terminal (44) in at least one of said terminal areas (46) of said semiconductor chips (24) associated with said terminal area (46), said auxiliary terminal (44) being connected to a conductive vertical post (38, 40) below said terminal area (46), the power semiconductor module (10) according to claim 1.

3. At least one of said semiconductor chips (24) associated with said terminal area (46) includes a control electrode (30), and one of said auxiliary terminals (44) is electrically connected to said control electrode (30) of said semiconductor chip (24) using its conductive vertical post (38), the power semiconductor module (10) according to claim 2.

4. Said semiconductor board (16) including a sensor (32) for at least one of said semiconductor chips (24) associated with said terminal area (46), The auxiliary terminal (44) is electrically connected to the sensor (32) via its conductive vertical post (40), the power semiconductor module (10) according to claim 2 or 3.

5. The sensor (32) is one of a temperature sensor and a current sensor, the power semiconductor module (10) according to claim 4.

6. The auxiliary terminal (44) is electrically connected to at least one power electrode (26, 28) of the semiconductor chips (24) associated with the terminal area (46) via conductive vertical posts (34, 36), the power semiconductor module (10) according to any one of claims 2 to 5.

7. The power terminals (42) are arranged in the outer region (46c) of each of the terminal areas (46), and the outer region (46c) is arranged at the boundary of the adapter board (14), the power semiconductor module (10) according to any one of claims 1 to 6.

8. At least one auxiliary terminal (44) is arranged in the inner region (46a) of the terminal area (46), and the outer region (46c) is arranged between the boundary of the adapter board (14) and the inner region (46a), the power semiconductor module (10) according to claim 7.

9. The terminal area (46) is arranged in at least one row (48) on the adapter board (14), the power semiconductor module (10) according to any one of claims 1 to 8.

10. The semiconductor board (16) includes a substrate (18) having a structured metallization layer (20) to which the at least two semiconductor chips (24) are joined, the power semiconductor module (10) according to any one of claims 1 to 9.

11. The vertical posts (34, 36) are pins, and the pins are connected to the adapter board (14) such that the head of each pin is joined to the respective contact areas (28, 30, 33) of the semiconductor board (16) and the at least two semiconductor chips (24), and are pressed onto the contact areas (28, 30, 33) provided by the semiconductor board (16) and the at least two semiconductor chips (24), the power semiconductor module (10) according to claim 10.

12. The semiconductor board (16) includes a chip scale package (64) for each semiconductor chip (24), Each chip scale package (64) includes at least one semiconductor chip (24), the vertical posts (34, 36) connected to the semiconductor chip (24), and a molded capsule encapsulation (66) in which the semiconductor chip (24) and the vertical posts (34, 36) are embedded. Each chip package (64) provides a bonding area (68) to which the vertical posts (34, 36) are electrically connected. The adapter board (14) is bonded to the bonding area (68) of the chip scale package (64), and is the power semiconductor module (10) according to any one of claims 1 to 9.

13. The adapter board (14) and the semiconductor board (16) are provided by a multilayer circuit board (70) in which the at least two semiconductor chips (24) are embedded. The vertical posts (34, 36) are through vias of the multilayer circuit board (70), and are the power semiconductor module (10) according to any one of claims 1 to 9.

14. The power semiconductor module (10) further includes a gate driver board (12) attached to the adapter board (14). Vertical pins interconnect the gate driver board (12) with auxiliary terminals (44) on the adapter board (14). The gate driver board (12) covers only a part of the power terminals (42) of the terminal area (46), and is the power semiconductor module (10) according to any one of claims 1 to 13.

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