Inrush current limiting device and system including the same

Abstract

To provide an inrush current limiting device with a wide input voltage range, and a system including the same.SOLUTION: An inrush current limiting device 100 includes: first and second input nodes IN1 and IN2 to which an input voltage Vin is input; first and second output nodes OUT1 and OUT2 that are coupled to a load 200; a field effect transistor (FET) M1 that is coupled between the first input node and the first output node; a gate driving unit 110 that includes a first voltage dividing circuit including a first resistor R1 coupled between the first input node and a control terminal of the FET and a second resistor 110 coupled between the control terminal of the FET and the second input node and a first capacitor C1 coupled between the first input node and the control terminal of the FET, that receives the input voltage, and that adjusts the time until the FET is turned on; and a high-voltage limiting unit that limits the voltage rise between the first input node and the control terminal of the FET by varying the resistance value of a third resistor that is coupled in parallel to the first resistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an inrush current limiting device and a system including the same.

Background Art

[0002] Inrush current is a transient phenomenon that additionally occurs depending on the load magnitude when an input voltage is applied in an electric and electronic system. Such inrush current can cause permanent damage, faults, or abnormal operation of the system, so it needs to be limited. Generally, it is also essential that a battery management system (BMS) applied to a battery pack also applies a technique for limiting inrush current.

[0003] An inrush current limiting circuit in which a field effect transistor (FET) having a low on-resistance is used as a main switch for inrush current limiting has the merit of being able to maintain a low voltage drop after interrupting the inrush current. However, due to the characteristics of the FET, in order to have a low on-resistance, the gate-source voltage must be maintained at 10 V or more, and for safe control of the FET, the voltage between the gate-source terminals must not exceed 20 V at maximum. Due to such a low voltage range of the FET, when applying the inrush current limiting circuit to a battery system having a wide supply voltage range, there is a problem that it is difficult to safely control the FET of the main switch.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present disclosure relates to an inrush current limiting device having a wide input voltage range and a system including the same.

Means for Solving the Problems

[0005] For an inrush current limiting device according to an embodiment to solve the above problems, there are a first and a second input node to which an input voltage is input from a power supply, a first and a second output node connected to a load, a field effect transistor connected between the first input node and the first output node, a first resistor connected between the first input node and the control terminal of the field effect transistor, and a second resistor connected between the control terminal of the field effect transistor and the second input node, which constitute a first voltage dividing circuit, and a first capacitor connected between the first input node and the control terminal of the field effect transistor. There is a gate driving unit for adjusting the time until the input voltage is input and the field effect transistor is turned on, and a third resistor connected in parallel with the first resistor and having a variable resistance value according to the voltage between the first input node and the control terminal of the field effect transistor. It can include a high voltage limiting unit for varying the resistance value of the third resistor to limit the voltage rise between the first input node and the control terminal of the field effect transistor.

[0006] The high voltage limiting unit can include a first transistor connected between the first input node and the control terminal of the field effect transistor, and a second voltage dividing circuit for varying the voltage applied to the control terminal of the first transistor according to the voltage between the first input node and the control terminal of the field effect transistor. The third resistor may be the on-resistance of the first transistor.

[0007] The second voltage dividing circuit can include a fourth resistor connected between the first input node and the control terminal of the first transistor, and a fifth resistor connected between the control terminal of the first transistor and the control terminal of the field effect transistor.

[0008] The second voltage dividing circuit may further include a sixth resistor connected to the control terminal of the field effect transistor. The first resistor, the second resistor, the first capacitor, and the first transistor are connected to the control terminal of the field effect transistor via the sixth resistor.

[0009] The first transistor may be a PNP transistor including an emitter terminal connected to the first input node, a collector terminal connected to the control terminal of the field effect transistor, and a base terminal operating as the control terminal of the first transistor.

[0010] The inrush current limiting device may further include a low voltage release unit that increases the voltage division ratio corresponding to the first resistor in the first voltage dividing circuit when the input voltage becomes lower than a predetermined value.

[0011] The low voltage release unit may include a second transistor connected in parallel with the second resistor, and a control circuit that turns on the second transistor when the input voltage becomes lower than the predetermined value.

[0012] The control circuit may include a third transistor connected between the control terminal of the second transistor and the second input node, and a Zener diode connected between the first input node and the control terminal of the third transistor and conducting when the input voltage becomes equal to or higher than the predetermined value. The third transistor is turned on when the Zener diode conducts. The second transistor is turned on when the third transistor is turned off.

[0013] The control circuit may further include a seventh resistor connected between the first input node and the third transistor, an eighth resistor connected between the third transistor and the control terminal of the second transistor, and a ninth resistor connected between the control terminal of the second transistor and the second input node.

[0014] The control circuit may further include a tenth resistor connected between the control terminal of the third transistor and the second input node.

[0015] The second transistor may be an NPN transistor including a collector terminal and an emitter terminal respectively connected to both ends of the second resistor, and a base terminal which is the control terminal of the second transistor. The third transistor may be an NPN transistor including a collector terminal connected to the control terminal of the second transistor, an emitter terminal connected to the second input node, and a base terminal which is the control terminal of the third transistor.

[0016] The low-voltage release unit may further include an eleventh resistor connected in series with the second transistor between both ends of the second resistor.

[0017] The inrush current limiting device may further include a feedback control unit connected between the first output node and the control terminal of the field-effect transistor, and reducing the voltage between the first input node and the control terminal of the field-effect transistor when the current output to the first output node increases.

[0018] The feedback control unit may include a second capacitor connected to the first output node, and a twelfth resistor connected between the second capacitor and the control terminal of the field-effect transistor.

[0019] The field-effect transistor may be a metal oxide semiconductor field effect transistor (MOSFET) including a source terminal connected to the first input node, a drain terminal connected to the first output node, and a gate terminal which is the control terminal of the field-effect transistor.

[0020] A system according to an embodiment may include an inrush current limiting device including at least one of the features described above.

Advantages of the Invention

[0021] According to the present disclosure, an inrush current limiting device having a wide input voltage range can be provided.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the effects, features, and realization methods of the embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same components, and redundant descriptions thereof are omitted. However, the present invention can be realized in various forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those of ordinary skill in the art.

[0024] Therefore, processes, elements, and techniques that are not considered necessary for those of ordinary skill in the art to fully understand the aspects and features of the present invention are not described. In the drawings, the relative sizes of elements, layers, and regions are exaggerated for clarity.

[0025] In this document, the term "and / or" includes all combinations or any combination of a plurality of items listed in relation thereto. When describing embodiments of the present invention, using "can be" means "one or more embodiments of the present invention". In the following description of embodiments of the present invention, terms in the singular form can include the plural form unless otherwise explicitly stated in the context.

[0026] The terms "first" and "second" are used to describe various components, but these components are not limited by these terms. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may also be named the second component.

[0027] In this document, when one component or layer is described as "above", "connected to", or "coupled to" another component or layer, "above", "connected to", and "coupled to" include all those formed directly or through one or more other components or layers intervening. Also, when one component or layer is described as being "between" two components or layers, it must be understood that it is the only component or layer between the two components or layers, or that one or more intervening other elements or layers exist.

[0028] In this specification, "electrically connecting" two components can include not only the case where the two components are directly connected, but also the case where they are connected through other components intervening between the two components. The other components can include switches, resistors, capacitors, etc. When explaining embodiments, the expression "connect" means electrically connecting when there is no expression of direct connection.

[0029] Hereinafter, with reference to the necessary drawings, an inrush current limiter according to an embodiment of the present invention and a system including the same will be described in detail.

[0030] FIG. 1 schematically shows a system including an inrush current limiter according to an embodiment. Further, FIG. 2 shows the inrush current limiter according to an embodiment in more detail.

[0031] Referring to FIGS. 1 and 2, the system 10 can include an inrush current limiter 100 electrically connected between a power supply 300 and a load 200. Such a system 10 may be, for example, a vehicle system.

[0032] The power supply 300 can be electrically connected to the input nodes IN1, IN2 of the inrush current limiter 100 to supply an input voltage Vin to the inrush current limiter 100. For example, when the system 10 includes a high-voltage battery pack, the power supply 300 may be the high-voltage battery pack. The load 200 can be electrically connected to the output nodes OUT1, OUT2 of the inrush current limiter 100 to receive an output voltage Vout from the inrush current limiter 100.

[0033] The system 10 can further include a main switch SW1. The power supply 300 can control the electrical connection with the inrush current limiter 100 by the main switch SW1.

[0034] The inrush current limiter 100 can include a transistor M1, a gate driving unit 110, a feedback control unit 120, a high-voltage limiting unit 130, and a low-voltage release unit 140.

[0035] Transistor M1 includes a first terminal and a second terminal respectively connected to an input node IN1 and an output node OUT1, and a control terminal, and can operate as a switch that blocks or allows the flow of current between the two nodes according to the voltage input to the control terminal. Taking FIG. 1 as an example, transistor M1 may be a P-channel metal oxide semiconductor field effect transistor (P-channel MOSFET) in which the first and second terminals are a source terminal and a drain terminal respectively, and the control terminal is a gate terminal. However, since the embodiments of the present invention are not limited thereby, transistor M1 may be an N-channel MOSFET. Hereinafter, for the convenience of explanation, the case where transistor M1 is a P-channel MOSFET will be described as an example.

[0036] When a voltage is supplied from power supply 300, gate driver 110 can control the gate voltage of transistor M1 so that the voltage Vgs between the gate and source terminals of transistor M1 (that is, the voltage between input node IN1 and the gate terminal of transistor M1) gradually increases. Gate driver 110 can include a capacitor C1 and a resistor R1 electrically connected in parallel between input node IN1 (that is, the source terminal of transistor M1) and the gate terminal, and a resistor R2 connected between the gate terminal of transistor M1 and input node IN2.

[0037] When the main switch SW1 is turned on and the input voltage Vin is supplied from the power supply 300, the current supplied from the power supply 300 flows through the resistors R1 and R2, which are distribution resistors, and the capacitor C1 is charged by the supply voltage of the power supply 300. As a result, the gate voltage Vg of the transistor M1 gradually decreases due to the charging of the capacitor C1, and the voltage Vgs between the gate and source terminals of the transistor M1 gradually increases. When the voltage Vgs between the gate and source terminals of the transistor M1 is low, it has a high resistance value, and as the voltage Vgs between the gate and source terminals increases, the resistance value gradually decreases. Therefore, at the initial stage of connection of the power supply 300, the voltage Vgs between the gate and source terminals of the transistor M1 gradually increases due to the capacitor C1, and the inrush current is limited by the high on-resistance of the transistor M1. After that, when a predetermined time has elapsed and the voltage Vgs between the gate and source terminals becomes equal to or higher than a predetermined value, the on-resistance of the transistor M1 converges to the minimum value, and the voltage drop by the transistor M1 can be minimized.

[0038] The feedback control unit 120 is connected between the output terminal OUT1 (that is, the drain terminal of the transistor M1) and the gate terminal, and when the current transmitted to the load 200 through the transistor M1 increases, it can perform a function of limiting the inrush current output to the capacitor C_L on the load 200 side by decreasing the voltage Vgs between the gate and source terminals of the transistor M1.

[0039] The feedback control unit 120 can include a capacitor C2 and a resistor R3 that are electrically connected in series with each other between the drain terminal and the gate terminal of the transistor M1. The capacitor C2 and the resistor R3 can decrease the voltage Vgs between the gate and source terminals of the transistor M1 by discharging the capacitor C1 when the inrush current increases. As a result, the on-resistance of the transistor M1 increases, and the increase in the inrush current output to the capacitor C_L on the load 200 side can be suppressed.

[0040] FIG. 3A and FIG. 3B are diagrams for explaining the operation of the feedback control unit according to an embodiment. FIG. 3A shows, as an example, the source voltage Vs of transistor M1, the voltage Vgs between the gate-source terminals, the drain voltage Vd, and the change in the inrush current when the feedback control unit is omitted in the inrush current limiting device. FIG. 3B shows, as an example, the source voltage Vs of transistor M1, the voltage Vgs between the gate-source terminals, the drain voltage Vd, and the change in the inrush current in the inrush current limiting device including the feedback control unit.

[0041] Referring to FIGS. 3A and 3B, when the main switch SW1 is turned on and the voltage supply from the power source 300 is started, the voltage Vs is applied to the source terminal of the transistor M1, and the voltage Vgs between the gate-source terminals of the transistor M1 gradually increases by the gate drive unit 110. Thereafter, at time t1, when the voltage Vgs between the gate-source terminals of the transistor M1 becomes equal to or higher than the threshold voltage Vth, the transistor M1 is turned on and the voltage Vd is output to the drain terminal of the transistor M1, thereby generating an inrush current output to the load 200 side capacitor C_L. When the inrush current is generated, the feedback control unit 120 discharges the capacitor C1, whereby the voltage Vgs between the gate-source terminals of the transistor M1 decreases as shown in FIG. 3B, and the inrush current is limited.

[0042] Referring again to FIGS. 1 and 2, the high voltage limiting unit 130 can limit the increase in the voltage Vgs between the gate-source terminals of the transistor M1 by varying the voltage distribution ratio of the voltage dividing circuits R1 and R2 of the gate drive unit 110 according to the voltage Vgs between the gate-source terminals of the transistor M1. The high voltage limiting unit 130 can include a transistor Q1 electrically connected in parallel with the resistor R1 and the capacitor C1 of the gate drive unit 110, and a resistor circuit for varying the on-resistance of the transistor Q1.

[0043] Transistor Q1 includes a first and a second terminal respectively connected to both ends of resistor R1 and a control terminal, and its on-resistance is variable according to the voltage applied to the control terminal. The resistor circuit is a voltage-dividing circuit that can vary the voltage applied to the control terminal of transistor Q1 according to the voltage Vgs between the gate-source terminals of transistor M1. The resistor circuit can include a resistor R4 connected between the source terminal of transistor M1 and the control terminal (e.g., base terminal) of transistor Q1, and a resistor R5 connected between the control terminal of transistor Q1 and the gate terminal of transistor M1. Thereby, the voltage Vgs between the gate-source terminals of transistor M1 is distributed by resistors R4 and R5 and applied to the control terminal of transistor Q1.

[0044] Transistor Q1 may be a PNP transistor whose control terminal is a base terminal and the first and second terminals are an emitter terminal and a collector terminal respectively. Therefore, as the voltage Vgs between the gate-source terminals of transistor M1 increases and the voltage between the emitter-base terminals of transistor Q1 increases, the on-resistance of transistor Q1 can be decreased. The on-resistance of transistor Q1 is electrically connected in parallel between the source terminal and the gate terminal of transistor M1 together with resistor R1 of the gate driving unit 110. Therefore, as the on-resistance of transistor Q1 decreases, the resistance value connected between the source terminal and the gate terminal of transistor M1 can be decreased. As the resistance value connected between the source terminal and the gate terminal of transistor M1 decreases, the voltage division ratio corresponding to resistor R1 of the gate driving unit 110 decreases, whereby the voltage Vgs between the gate-source terminals of transistor M1 can be decreased.

[0045] In this way, when the voltage Vgs between the gate-source terminals of transistor M1 increases, the high voltage limiting unit 130 can adjust the voltage division ratio of the voltage-dividing circuits R1 and R2 of the gate driving unit 110 to limit the voltage Vgs between the gate-source terminals of transistor M1.

[0046] FIG. 4 is a diagram for explaining the operation of the high voltage limiting section according to an embodiment.

[0047] Referring to FIG. 4, when the main switch SW1 is turned on and the supply of the voltage Vin from the power supply 300 is started, the voltage Vgs between the gate-source terminals of the transistor M1 gradually increases. When the voltage Vgs between the gate-source terminals of the transistor M1 becomes equal to or higher than a predetermined value, the transistor Q1 of the high voltage limiting section 130 is turned on to limit the increase in the voltage Vgs between the gate-source terminals of the transistor M1. Therefore, the voltage Vgs between the gate-source terminals of the transistor M1 can be maintained at a lower voltage as compared with the case where the high voltage limiting section 130 is not provided.

[0048] Referring again to FIGS. 1 and 2, the resistance circuit of the high voltage limiting section 130 can include a resistor R6 connected between the gate terminal of the transistor M1 and the node N1. In this case, the resistors R1, R2 and the capacitor C1 of the gate driving section 110, and the resistor R3 of the feedback control section 120 are connected to the gate terminal of the transistor M1 via the node N1 and the resistor R6. Therefore, the voltage Vgs between the gate-source terminals of the transistor M1 may be a voltage obtained by distributing the voltage across the resistor R1 via the resistance circuits R4, R5, R6.

[0049] The low voltage release section 140 varies the voltage division ratio of the voltage dividing circuit R1, R2 of the gate driving section 110 by the input voltage Vin, so that the voltage drop by the transistor M1 can be minimized even at an input voltage Vin lower than a predetermined value. The low voltage release section 140 can include a transistor Q2 connected in parallel with the resistor R2 of the gate driving section 110, and a control circuit that controls the turn-on / turn-off of the transistor Q2. The control circuit is connected between the control terminal of the transistor Q2 and the input node IN2, and includes a transistor Q3 that controls the turn-on / turn-off of the transistor Q2 by the input voltage Vin, and a Zener diode D1 that is connected between the input node IN1 and the control terminal of the transistor Q3 and controls the turn-on / turn-off of the transistor Q2 by the input voltage Vin.

[0050] The Zener diode D1 can include a cathode connected to the input node IN1 and an anode connected to the control terminal of the transistor Q3. If the input voltage Vin is higher than a predetermined value, the Zener diode D1 can conduct and transmit the input voltage Vin to the control terminal of the transistor Q3.

[0051] The transistor Q3 can include a first terminal connected to the control terminal of the transistor Q2, a second terminal connected to the input node IN2, and a control terminal connected to the anode of the Zener diode D1. The transistor Q2 is turned on or off depending on whether the Zener diode D1 conducts. The transistor Q3 can operate as a switch that connects the control terminal of the transistor Q2 and the input node IN2 when turned on, and disconnects the electrical connection between the control terminal of the transistor Q2 and the input node IN2 when turned off.

[0052] The transistor Q3 may be an NPN transistor whose control terminal is a base terminal and whose first and second terminals are a collector terminal and an emitter terminal, respectively. Therefore, the transistor Q3 is turned on when a voltage equal to or higher than a predetermined value is applied to the base terminal. That is, when a voltage equal to or higher than a predetermined value is applied from the power supply 300 and the Zener diode D1 conducts, a voltage equal to or higher than a predetermined value is applied to the base terminal of the transistor Q3 via the Zener diode D1, and the transistor Q3 is turned on. On the contrary, when a voltage lower than a predetermined value is applied from the power supply 300 and the Zener diode D1 becomes non-conductive, the transistor Q3 is turned off.

[0053] The undervoltage release unit 140 can further include a resistor R11 connected between the input node IN1 and the cathode of the Zener diode D1, and a resistor R12 and a capacitor C4 connected in parallel between the base terminal of the transistor Q3 and the input node IN2 for stable operation of the transistor Q3.

[0054] Transistor Q2 can include a first and a second terminal respectively connected to both ends of resistor R2, and a control terminal. The voltage input to the control terminal of transistor Q2 varies depending on the presence or absence of the turn-on of transistor Q3. That is, transistor Q2 can operate as a switch that is turned on or off depending on the presence or absence of the turn-on of transistor Q3. When transistor Q3 is turned on, the control terminal of transistor Q2 is connected to input node IN2. When transistor Q3 is turned off, a voltage distributed from input voltage Vin by resistors R10, R8, and R9 is input to the control terminal of transistor Q2.

[0055] Transistor Q3 may be an NPN transistor whose control terminal is a base terminal, and the first and second terminals are a collector terminal and an emitter terminal respectively. Therefore, when a voltage equal to or higher than a predetermined value is applied to the base terminal of transistor Q2, it is turned on. That is, when transistor Q3 is turned on and the control terminal of transistor Q2 is connected to input node IN2, transistor Q3 is turned off. On the contrary, when transistor Q3 is turned off, the voltage of the control terminal of transistor Q2 increases due to input voltage Vin, and transistor Q2 is turned on.

[0056] Transistor Q2 is connected in series with resistor R7, and the series combination of transistor Q2 and resistor R7 is connected in parallel with resistor R2 of gate driving unit 110. Therefore, when transistor Q2 is turned on, resistor R2 and resistor R7 of gate driving unit 110 are connected in parallel, whereby the voltage division ratio by resistors R1 and R2 of gate driving unit 110 can be changed. That is, when transistor Q2 is turned on, the resistance value between the gate terminal of transistor M1 and input node IN2 decreases, whereby the voltage division ratio corresponding to resistor R1 of gate driving unit 110 increases, and the difference between input voltage Vin and the voltage Vgs between the gate-source terminals of transistor M1 decreases.

[0057] The low-voltage release unit 140 can further include a resistor R10 connected between the input node IN1 and the first terminal of the transistor Q3, a resistor R8 connected between the first terminal of the transistor Q3 and the control terminal of the transistor Q2, a resistor R9 connected between the control terminal and the second terminal of the transistor Q2, and a capacitor C3 connected between the first terminal of the transistor Q3 and the input node IN2 for the stable operation of the transistor Q2.

[0058] On the other hand, the resistor R7 connected between the first terminal of the transistor Q2 and the resistor R1 in the low-voltage release unit 140 may be omitted. In this case, when the transistor Q2 is turned on, the resistance value between the gate terminal of the transistor M1 and the input node IN2 further decreases, thereby further increasing the voltage distribution ratio corresponding to the resistor R1 of the gate drive unit 110.

[0059] According to the foregoing, when the input voltage Vin becomes lower than a predetermined value, the low-voltage release unit 140 can turn on the transistor Q2 and decrease the resistance value of the resistor connected between the gate terminal of the transistor M1 and the input node IN2. As a result, the voltage drop due to the voltage distribution of the gate drive unit 110 decreases, and the difference between the input voltage Vin and the voltage Vgs between the gate-source terminals of the transistor M1 decreases.

[0060] FIG. 5 is a diagram for explaining the operation of the low-voltage release unit according to an embodiment.

[0061] Referring to FIG. 5, at time t1, when the input voltage Vin is lower than the conduction voltage Vth1 of the Zener diode D1, the transistor Q2 of the low-voltage release unit 140 is turned on. As a result, the voltage drop due to the resistance between the gate terminal of the transistor M1 and the input node IN2 decreases, and the voltage Vgs between the gate-source terminals of the transistor M1 becomes very close to the input voltage Vin. Thereafter, at time t2, when the input voltage Vin becomes higher than the conduction voltage Vth1 of the Zener diode D1, the transistor Q2 of the low-voltage release unit 140 is turned off. As a result, only the resistor R2 is connected between the gate terminal of the transistor M1 and the input node IN2, the voltage drop due to the resistance between the gate terminal of the transistor M1 and the input node IN2 increases, and the voltage difference between the voltage Vgs between the gate-source terminals of the transistor M1 and the input voltage Vin increases.

[0062] According to the above, the inrush current limiting device 100 according to an embodiment can protect the transistor M1 by limiting an increase in the voltage Vgs between the gate-source terminals of the transistor M1 using the high-voltage limiting unit 130 when the input voltage Vin is high. Also, when the input voltage Vin is low, the inrush current limiting device 100 can minimize the voltage drop of the voltage Vgs between the gate-source terminals of the transistor M1 by the gate driving unit 110 to ensure stable operation of the transistor M1. In this way, the inrush current limiting device 100 can operate stably over a wide range of input voltages and can be applied without the need to change the circuit according to the specifications of the power supply 300 when applied to the system 10. Further, by configuring the high-voltage limiting unit 130 and the low-voltage release unit 140 using low-cost passive elements, the inrush current limiting device 100 can be miniaturized and the cost increase can be minimized.

[0063] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on individual IC chips. Also, various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or on one substrate. The electrical connections or interconnections described herein can be realized, for example, by wiring or conductive elements on a PCB or other types of circuit carriers. The conductive elements can include, for example, metallizations such as surface metallizations, and / or pins, and can include conductive polymers or ceramics. Also, electrical energy can be transmitted, for example, by a wireless connection using electromagnetic radiation or light.

[0064] Furthermore, various components of these devices can be executed on one or more processors to perform the various functions described herein, and can be processes or threads executed within one or more computing devices, executing computer program instructions and interacting with other system components. The computer program instructions can be stored in a memory that can be realized in a computing device using a standard memory device, such as a random access memory (RAM). The computer program instructions can also be stored on other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, etc.

[0065] Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of the exemplary embodiments of the present invention.

Description of Reference Numerals

[0066] 10: System 100: Inrush Current Limiting Device 110: Gate Driving Unit 120: Feedback Control Unit 130: High Voltage Limiting Unit 140: Low Voltage Release Unit 200: Load 300: Power Supply SW1: Main Switch M1: Transistor IN1, IN2: Input Nodes OUT1, OUT2: Output Nodes

Claims

1. First and second input nodes to which an input voltage is input from a power supply, First and second output nodes connected to a load, A field effect transistor connected between the first input node and the first output node, A first resistor connected between the first input node and the control terminal of the field effect transistor, and a first voltage dividing circuit composed of a second resistor connected between the control terminal of the field effect transistor and a node between the second input node and the second output node, and a first capacitor connected between the first input node and the control terminal of the field effect transistor, and a gate driving unit that adjusts the time until the input voltage is input and the field effect transistor is turned on, Including a third resistor connected in parallel with the first resistor and having a variable resistance value depending on the voltage between the first input node and the control terminal of the field effect transistor, and a high voltage limiting unit that varies the resistance value of the third resistor to limit the voltage rise between the first input node and the control terminal of the field effect transistor, The high voltage limiting unit includes: A first transistor connected between the first input node and the control terminal of the field effect transistor, A second voltage dividing circuit that varies the voltage applied to the control terminal of the first transistor depending on the voltage between the first input node and the control terminal of the field effect transistor, The third resistor is the on-resistance of the first transistor, The second voltage dividing circuit includes: A fourth resistor connected between the first input node and the control terminal of the first transistor, A fifth resistor connected between the control terminal of the first transistor and the control terminal of the field effect transistor, A sixth resistor connected between the control terminal of the field effect transistor and the node to which the first resistor, the second resistor, the first capacitor, and the first transistor are connected, The first resistor, the second resistor, the first capacitor, and the first transistor are connected to the control terminal of the field effect transistor via the sixth resistor, Inrush current limiting device.

2. The inrush current limiting device according to claim 1, wherein the first transistor is a PNP transistor including an emitter terminal connected to the first input node, a collector terminal connected to the control terminal of the field effect transistor, and a base terminal operating as the control terminal of the first transistor.

3. The inrush current limiting device according to claim 1, further comprising a low voltage release unit that increases a voltage division ratio corresponding to the first resistor in the first voltage division circuit when the input voltage becomes lower than a predetermined value.

4. The low voltage release unit includes a second transistor connected in parallel with the second resistor, and a control circuit that turns on the second transistor when the input voltage becomes lower than the predetermined value. The inrush current limiting device according to claim 3.

5. The control circuit includes a third transistor connected between a control terminal of the second transistor and the second input node, and a Zener diode connected between the first input node and the control terminal of the third transistor and conducting when the input voltage becomes equal to or higher than the predetermined value. The third transistor is turned on when the Zener diode conducts, and the second transistor is turned on when the third transistor is turned off. The inrush current limiting device according to claim 4.

6. The control circuit further includes a seventh resistor connected between the first input node and the third transistor, an eighth resistor connected between the third transistor and the control terminal of the second transistor, and a ninth resistor connected between the control terminal of the second transistor and the second input node. The inrush current limiting device according to claim 5.

7. The control circuit further includes a tenth resistor connected between the control terminal of the third transistor and the second input node. The inrush current limiting device according to claim 5.

8. The second transistor is an NPN transistor including a collector terminal and an emitter terminal respectively connected to both ends of the second resistor, and a base terminal which is a control terminal of the second transistor. The third transistor is an NPN transistor including a collector terminal connected to the control terminal of the second transistor, an emitter terminal connected to the second input node, and a base terminal which is a control terminal of the third transistor. The inrush current limiting device according to claim 5.

9. The low voltage release unit further includes an eleventh resistor connected in series with the second transistor between both ends of the second resistor. The inrush current limiting device according to claim 4.

10. A rush current limiting device according to claim 1, further comprising a feedback control unit connected between the first output node and a control terminal of the field effect transistor, and configured to reduce a voltage between the first input node and the control terminal of the field effect transistor when a current output to the first output node increases.

11. The feedback control unit includes a second capacitor connected to the first output node, and a twelfth resistor connected between the second capacitor and the control terminal of the field effect transistor. A rush current limiting device according to claim 10.

12. The field effect transistor is a metal oxide semiconductor field effect transistor (MOSFET) including a source terminal connected to the first input node, a drain terminal connected to the first output node, and a gate terminal which is a control terminal of the field effect transistor. A rush current limiting device according to claim 1.

13. A system including the rush current limiting device according to any one of claims 1 to 12.

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