Power conversion device, control method for power conversion device, and program

Abstract

To provide a power conversion device having high reliability, a method for controlling the power conversion device, and a program.SOLUTION: A power conversion device of an embodiment has a power converter and a converter control part. The power converter includes at least one arm unit in which there is connected in series a plurality of unit converters having an energy storage element and a plurality of switching elements. The converter control part switches between a first control state in which the unit converters are made output a voltage of the energy storage element and a second control state in which the unit converters are shorted, thereby controlling conversion operation of the power converter. The converter control part has a state count computation part for calculating the number of unit converters to which the control state is allocated, a list computation part for generating list information of voltage magnitude relations for each second time interval which is longer than a first time interval in which voltages are detected, and a unit converter selection part for selecting a unit converter the control state of which is to be changed. The unit converter selection part selects another unit converters in place of a unit converter whose voltage has exceeded a threshold.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a power conversion device, a control method for the power conversion device, and a program.

Background Art

[0002] In recent years, as a power converter, the practical application of a modular multilevel converter (MMC) has been promoted. An MMC is a power converter that includes an arm unit including a plurality of unit converters (hereinafter referred to as "cells") connected in series, and can handle high voltage and large capacity by adding the voltages output by each cell. The power converter is utilized, for example, in a DC power transmission system or a reactive power compensation device. For example, a power converter for a DC power transmission system is connected between an AC system and a DC system and performs mutual conversion of power between them. For example, a power converter for a reactive power compensation device is connected to an AC system and adjusts the reactive power at the connection point.

[0003] When performing mutual conversion of power or adjusting reactive power in a power converter, the switching elements included in the power converter are controlled. As a switching control method in a power converter, for example, there is known a phase shift PWM (pulse width modulation) method in which a multi-step staircase-shaped sine wave is synthesized over the entire arm unit by equally shifting the phases of triangular wave carriers assigned to each cell. However, in the phase shift PWM method, it is necessary to make the frequency of the triangular wave carrier higher than the frequency of the AC system, and the loss (switching loss) in switching control increases.

[0004] In this regard, for example, Patent Documents 1 and 2 disclose a technique for one-pulse control in which each cell is switched once during one cycle of the AC voltage. However, conventional switching control has the problem that when the switching frequency decreases, the variation in the voltage of the capacitors in each cell becomes large. For this reason, in power converters, methods have been proposed to equalize the voltage of the capacitors in each cell during switching control, such as adjusting the rising and falling phases of the output voltage of each cell, or changing the rising and falling order of the output voltage according to the relative magnitudes of the capacitors in each cell.

[0005] A method to change the rise and fall order of the output voltage according to the relative magnitudes of the capacitor voltages in each cell can be achieved by acquiring the voltage of the capacitor in each cell of the arm unit at regular intervals and selecting the cell to be switched controlled by comparing it with the relative magnitudes of these voltages. However, with this method, the time required for sorting the acquired capacitor voltages of each cell based on their relative magnitudes (the so-called sorting process) can sometimes be longer than the time interval required for the switching control process. In this case, it becomes difficult to control the capacitors in each cell to minimize the difference in charge levels (balance them so that the charge levels are relatively uniform). Therefore, if the cell to be switched controlled is selected after the sorting process is completed, it may not be possible to obtain sufficient balancing performance to balance the capacitor voltages, which could lead to an increase in the fluctuation range of the capacitor voltage. When the fluctuation range of the capacitor voltage increases, the output voltage of each cell decreases, which imposes limitations on the operation of the power converter. Furthermore, an increase in the fluctuation range of the capacitor voltage also increases the maximum value of the capacitor voltage, which could lead to failure of the capacitors or switching elements. In this case, the reliability of the power converter is significantly reduced. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-233126 [Patent Document 2] Japanese Patent Publication No. 2015-159687 [Overview of the project] [Problems that the invention aims to solve]

[0007] The problem that this invention aims to solve is to provide a highly reliable power converter, a control method for a power converter, and a program by controlling the unit converter provided in the power converter. [Means for solving the problem]

[0008] The power converter of the embodiment comprises a power converter and a converter control unit. The power converter has at least one arm unit in which a plurality of unit converters are connected in series, each unit converter having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element. The converter control unit controls the power conversion operation in the power converter by switching to at least one of two control states: a first control state in which the terminal voltage of the energy storage element is output between the first and second terminals of the unit converter, and a second control state in which the first and second terminals of the unit converter are short-circuited. The converter control unit comprises a state number calculation unit, a list calculation unit, and a unit converter selection unit. The state number calculation unit calculates a state number, which represents the number of unit converters belonging to the arm unit that are assigned to any of the control states, according to an arm voltage command value, which is a target value of the arm voltage output from the arm unit. The list calculation unit generates list information representing the relative magnitudes of the terminal voltages of the energy storage element, based on the terminal voltages of the energy storage element detected at predetermined first time intervals, at predetermined second time intervals that are longer than the first time interval. The unit converter selection unit selects the unit converter to change the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the terminal voltages of the energy storage element.The unit converter selection unit, in the case of a charging period when the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state, detects at the first time interval that the terminal voltage of the energy storage element of the first unit converter, which is the unit converter in the first control state, exceeds a first threshold higher than the rated voltage, changes the first unit converter to the second control state, and changes the same number of other unit converters in the second control state as the first unit converter to the first control state. If the polarity of the arm current is selected and the discharge period is such that the polarity of the unit converter in the first control state is such that power is discharged from the energy storage element, then when the terminal voltage of the energy storage element of the second unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a second threshold lower than the rated voltage, the second unit converter is changed to the second control state, and the same number of other unit converters in the second control state as the second unit converter are selected as the unit converters to be changed to the first control state. [Brief explanation of the drawing]

[0009] [Figure 1] A diagram showing an example of the configuration of a power conversion device according to the first embodiment. [Figure 2] A diagram showing an example of the cell configuration within a leg of a power converter. [Figure 3] A diagram showing an example of the configuration of the converter control unit included in a power conversion device. [Figure 4] A timing chart illustrating an example of the operating timing for the first operation in a power converter. [Figure 5] A timing chart illustrating an example of the operating timing for the second operation in a power converter. [Figure 6] A diagram showing an example of the configuration of a power converter according to the second embodiment. [Figure 7] A diagram showing an example of the cell configuration within a leg of a power converter. [Figure 8]A timing chart illustrating an example of the operating timing for the third operation in a power converter. [Figure 9] A timing chart illustrating an example of the operating timing for the fourth operation in a power converter. [Modes for carrying out the invention]

[0010] The power converter, control method for the power converter, and program of the embodiment will be described below with reference to the drawings.

[0011] (First Embodiment) [Configuration of the power converter] Figure 1 is a diagram showing an example of the configuration of a power conversion device according to the first embodiment. Figure 1 shows an example of a power conversion device 1 that is installed at the interconnection point between an AC system and a DC system, and converts AC power supplied by the AC system and DC power supplied by the DC system to each other. The AC system may be, for example, an AC power source or an AC load. The DC system may be, for example, a DC power source or a DC load. The power conversion device 1 comprises a power converter 10 and a converter control unit 50.

[0012] The power converter 10 is a dual-star connected modular multilevel converter (MMC) that converts AC power and DC power to each other in response to control from the converter control unit 50. The power converter 10 is equipped with multiple legs 12 between the positive terminal P of the DC system and the negative terminal N of the DC system. The number of legs 12 equipped in the power converter 10 corresponds to the number of phases of the AC power supplied by the AC system. Figure 1 shows the case where the AC system supplies three phases of AC power: the first phase (R phase), the second phase (S phase), and the third phase (T phase). Therefore, Figure 1 shows the configuration of the power converter 10 equipped with three legs 12: leg 12-R, leg 12-S, and leg 12-T. Legs 12-R, 12-S, and 12-T each have the same configuration.

[0013] In each leg 12, the AC terminal CA is connected to the terminal of the corresponding phase in the AC system. More specifically, in leg 12-R corresponding to the R phase, the AC terminal CA-R is connected to the AC terminal R of the R phase in the AC system; in leg 12-S corresponding to the S phase, the AC terminal CA-S is connected to the AC terminal S of the S phase in the AC system; and in leg 12-T corresponding to the T phase, the AC terminal CA-T is connected to the AC terminal T of the T phase in the AC system. Figure 1 shows the case where the AC terminal CA of each leg 12 is connected to the terminal of the corresponding phase in the AC system via the transformer TR.

[0014] In each leg 12, the terminal opposite to the AC terminal CA is connected to the respective DC terminal of the DC system. More specifically, in each leg 12, the terminal that is at the same potential as the positive terminal of the DC voltage output by the power converter 10 is connected to the positive terminal P, and the terminal that is at the same potential as the negative terminal of the DC voltage output by the power converter 10 is connected to the negative terminal N. In the following explanation, the terminal of leg 12 connected to the positive terminal P is also referred to as the DC terminal CP of leg 12, and the terminal of leg 12 connected to the negative terminal N is also referred to as the DC terminal CN of leg 12.

[0015] Each leg 12 comprises, for example, two reactors 14 and two arm units 16. Each arm unit 16 comprises, for example, n cells 162 (cells 162-1 to 162-n) connected in series (where n is a natural number). In Figure 1, to distinguish whether each component of leg 12 corresponds to the positive or negative side of a DC system, or to which phase of an AC system, a hyphen "-" and the letter "P" representing the positive side or "N" representing the negative side are added after each component's code, followed by another hyphen and the letter "R" representing the R phase, the letter "S" representing the S phase, or the letter "T" representing the T phase. In the following explanation, when it is not necessary to distinguish whether each component corresponds to the positive or negative side of a DC system or to which phase of an AC system, the hyphen and the identifying letter following the hyphen are omitted from the code of each component.

[0016] In each leg 12, the reactor 14-P on the positive electrode side and the arm unit 16-P on the positive electrode side are connected in series, and the reactor 14-N on the negative electrode side and the arm unit 16-N on the negative electrode side are connected in series. And in each leg 12, the connection point between the reactor 14-P and the reactor 14-N serves as the DC terminal CP. In each leg 12, the terminal on the side opposite to the reactor 14-P in the arm unit 16-P serves as the DC terminal CP of the leg 12, and the terminal on the side opposite to the reactor 14-N in the arm unit 16-N serves as the DC terminal CN of the leg 12. In other words, in each leg 12, from the DC terminal CP side toward the AC terminal CA side, the cells 162-1 to 162-n and the reactor 14-P are connected in series in this order and connected to the AC terminal CA. Further, in each leg 12, from the DC terminal CN side toward the AC terminal CA side, the cells 162-n to 162-1 and the reactor 14-N are connected in series in this order and connected to the AC terminal CA.

[0017] The leg 12 is an example of the "phase unit" in the claims. The arm unit 16-P (which may include the reactor 14-P) is an example of the "first arm unit" in the claims, and the arm unit 16-N (which may include the reactor 14-N) is an example of the "second arm unit" in the claims. The cell 162 is an example of the "unit converter" in the claims. The reactor 14 is an example of the "inductance element" in the claims.

[0018] In FIG. 1, in each leg 12, a case where the reactor 14 is arranged on the AC terminal CA side of the arm unit 16 is shown. However, the reactor 14 may be arranged on the side opposite to the AC terminal CA side of the arm unit 16 (that is, the DC terminal CP side or the DC terminal CN side), or at an arbitrary position within the arm unit 16 (that is, a position between any two cells 162 connected in series in the arm unit 16). The reactor 14 may be replaced with a transformer having a special winding structure with leakage reactance only to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

[0019] Each arm unit 16 generates a multi-level waveform AC voltage, which is a stepped sine wave representing the AC waveform to be supplied to the corresponding phase of the AC system, in response to the control from the converter control unit 50 for each of the cells 162 connected in series.

[0020] Here, an example of the configuration of the cell 162 included in the arm unit 16 will be described. The cell 162 is, for example, a half-bridge circuit. FIG. 2 is a diagram showing an example of the configuration of the cell 162 in the leg 12 included in the power converter 10. The cell 162 includes two switching elements Q (switching element Q1 and switching element Q), two diodes D (diode D1 and diode D2), and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor). The switching element Q is not limited to IGBT. The switching element Q may be any element as long as it is a self-extinguishing semiconductor switching element capable of realizing a converter or an inverter.

[0021] In cell 162, switching elements Q1 and Q2 are connected in series with each other. In cell 162, the series circuit of switching elements Q1 and Q2 and capacitor C are connected in parallel with each other. In cell 162, each switching element Q and its corresponding diode D are connected in parallel with each other. In cell 162, the connection point between the emitter of switching element Q1 and the collector of switching element Q2 is the positive terminal TP(+) connected to the positive terminal P side in leg 12, and the connection point between the emitter of switching element Q2 and capacitor C is the negative terminal TN(-) connected to the negative terminal N side in leg 12.

[0022] Control signals from the converter control unit 50 are input to the gates of switching elements Q1 and Q2 in cell 162 (a control voltage is applied or a control current is supplied). The gate signal gtp is input to the gate of switching element Q1 as a control signal from the converter control unit 50, and the gate signal gtn is input to the gate of switching element Q2 as a control signal from the converter control unit 50. As a result, switching elements Q1 and Q2 are switched by the converter control unit 50 to either an on state or an off state. In the following description, it is assumed that when a control signal of "1" ("High" level) (gate signal gtp, gate signal gtn) is input, each switching element Q is turned on, and when a control signal of "0" ("Low" level) (gate signal gtp, gate signal gtn) is input, each switching element Q is turned off.

[0023] Capacitor C is charged or discharged according to the state of each switching element Q. In cell 162, the terminal voltage of capacitor C (hereinafter referred to as "capacitor voltage Vc") is generated as the terminal voltage between the positive terminal TP and the negative terminal TN of cell 162 (hereinafter referred to as "cell voltage Vo"). More specifically, when the converter control unit 50 sets the control signal (gtp,gtn)=(1,0), current flows in the order of positive terminal TP, switching element Q1, capacitor C, and negative terminal TN, and the cell voltage Vo of cell 162 matches the capacitor voltage Vc. In other words, when the converter control unit 50 sets the control signal (gtp,gtn)=(1,0), capacitor C is inserted between the positive terminal TP and the negative terminal TN of cell 162, and the capacitor voltage Vc is output as the cell voltage Vo. In the following explanation, when the converter control unit 50 sets the control signal (gtp,gtn)=(1,0), it is referred to as "insert," and the state of cell 162 in this case is referred to as the "insert state." On the other hand, when the converter control unit 50 sets the control signal (gtp,gtn)=(0,1), for example, current flows in the order of positive terminal TP, switching element Q2, and negative terminal TN, and the cell voltage Vo of cell 162 becomes 0[V]. In other words, when the converter control unit 50 sets the control signal (gtp,gtn)=(0,1), the positive terminal TP and negative terminal TN of cell 162 are short-circuited, and current flows without passing through capacitor C, resulting in the cell voltage Vo of cell 162 becoming 0[V]. In the following explanation, when the converter control unit 50 sets the control signal (gtp,gtn)=(0,1), it is referred to as "bypass," and the state of cell 162 in this case is referred to as the "bypass state."

[0024] Cell 162 is not limited to the configuration shown in Figure 2; any configuration that achieves the same functionality as cell 162 is acceptable.

[0025] Switching element Q1 and diode D1 are examples of the "switching element" and "first switching element" in the claims, and switching element Q2 and diode D2 are examples of the "switching element" and "second switching element" in the claims. The ON state is an example of the "conducting state" in the claims, and the OFF state is an example of the "non-conducting state" in the claims. Capacitor C is an example of the "energy storage element" in the claims. Positive terminal TP is an example of the "first end" in the claims, and negative terminal TN is an example of the "second end" in the claims. The insert state is an example of the "first control state" in the claims, and the bypass state is an example of the "second control state" in the claims.

[0026] By connecting multiple cells 162 with this configuration in series, the arm unit 16 outputs a voltage that is the sum of the cell voltages Vo of each cell 162 controlled to the insert state. Therefore, the arm unit 16 outputs a voltage corresponding to the number of cells 162 controlled to the insert state by the converter control unit 50. As a result, the arm unit 16 generates a multilevel waveform in response to the control from the converter control unit 50.

[0027] Incidentally, in cell 162, setting the control signal (gtp,gtn)=(1,1) should be prohibited. This is because setting the control signal (gtp,gtn)=(1,1) would turn on both switching elements Q1 and Q2, short-circuiting the ends of capacitor C. For this reason, when the converter control unit 50 changes the control signal (gtp,gtn) from (1,0) to (0,1) or vice versa, it controls the system to provide a very short transient period during which the control signal (gtp,gtn)=(0,0), a so-called dead time. The converter control unit 50 may also fix the control signal (gtp,gtn)=(0,0) when stopping the operation of cell 162. In the following explanation, the state in which the converter control unit 50 fixes all control signals (gtp,gtn) to (0,0) and stops the operation of all cells 162 of the arm unit 16 of the power converter 10 is referred to as a "gate block," and the state of the cells 162 in this case is referred to as the "gate block state."

[0028] Returning to Figure 1, the converter control unit 50 calculates AC voltage command values ​​and DC voltage command values, including the frequency of the AC system, based on the operating state of the power converter 1 and the detected values ​​at each location within the power converter 1 (current value, direction of current flow (polarity), voltage value). For this purpose, the converter control unit 50 acquires the detected values ​​output by detectors (described later) installed at desired locations inside and outside the power converter 1 at predetermined (constant) acquisition cycles TS1. The converter control unit 50 then determines a voltage command value for each arm unit 16, including the voltage component represented by the calculated AC voltage command value and DC voltage command value. Based on the obtained voltage command values, the converter control unit 50 generates a control signal to control (switching control) the switching element Q in the cell 162 provided in each arm unit 16. The converter control unit 50 then outputs the generated control signal to the corresponding cell 162. For example, when the converter control unit 50 controls arm unit 16-PR, which corresponds to the R phase of the AC system and is connected to the positive side of the DC system, it calculates an arm voltage command value Varm* to be output to arm unit 16-PR based on the AC voltage component output to the AC terminal CA-R and the DC voltage component output between the DC terminal CP-R and the DC terminal CN-R. In the following explanation, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as the direction in which the potential on the cell 162-1 side is higher when viewed from the cell 162-n side. Then, based on the calculated arm voltage command value Varm*, the converter control unit 50 generates gate signals gtp (gate signals gtp-1-PR to gtp-nPR) and gtn (gate signals gtn-1-PR to gtn-nPR) to control each switching element Q in each cell 162 (cells 162-1-PR to 162-nPR) of arm unit 16-PR. The converter control unit 50 outputs the generated gate signals gtp and gtn to the corresponding cells 162. The same applies when the converter control unit 50 controls other arm units 16. The converter control unit 50 includes, for example, an insert count calculation unit 52, a sort list calculation unit 54, a cell selection control unit 56, and a gate signal generation unit 58.

[0029] The converter control unit 50 controls the operation of the power converter 10 by having a hardware processor, such as a CPU (Central Processing Unit), execute a program (software). The converter control unit 50 may be implemented by hardware (including circuitry) such as an LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), or GPU (Graphics Processing Unit), or by the cooperation of software and hardware. The converter control unit 50 may also be implemented by a dedicated LSI. The program may be stored in advance in a storage device (a storage device with a non-transient storage medium) such as an HDD (Hard Disk Drive) or flash memory provided by the converter control unit 50 or the power converter 1, or it may be stored in a removable storage medium (a non-transient storage medium) such as a DVD or CD-ROM, and installed in the HDD or flash memory of the converter control unit 50 or the power converter 1 when the storage medium is mounted in a drive device provided by the converter control unit 50 or the power converter 1.

[0030] In the power converter 1, current detectors and voltage detectors are provided at desired locations to detect the current value, current polarity, and voltage value. In the example in Figure 1, a current detector for detecting the positive arm current Ip flowing from the positive terminal P to the AC terminal CA is provided within each leg 12, and a current detector for detecting the negative arm current In flowing from the AC terminal CA to the negative terminal N is provided. More specifically, in leg 12-R, a current detector for detecting the positive arm current Ipr flowing from the positive terminal P to the AC terminal CA-R is provided between the arm unit 16-PR and the reactor 14-PR, and a current detector for detecting the negative arm current Inr flowing from the AC terminal CA-R to the negative terminal N is provided between the arm unit 16-NR and the reactor 14-NR. The other legs 12 are similar. Although not shown in Figure 2, each cell 162 is also provided with a voltage detector for detecting the capacitor voltage Vc. The AC currents Isr of the R phase, Iss of the S phase, and Isst of the T phase may be directly detected by providing current detectors at AC terminals R, S, and T, respectively. Alternatively, they may be indirectly detected by calculating the positive arm current Ip and negative arm current In detected at each leg 12. For example, the AC current Isr of the R phase may be indirectly detected by calculating the difference between the positive arm current Ipr and the negative arm current Inr (i.e., Inr-Ipr). Furthermore, although the voltage detector is not shown in Figure 1, it illustrates the case where the AC voltage Vsr of the R phase, the AC voltage Vss of the S phase, and the AC voltage Vst of the T phase are detected.

[0031] Figure 3 shows an example of the configuration of the converter control unit 50 provided in the power converter 1.

[0032] The insert count calculation unit 52 receives at least the arm voltage command value Varm* that the arm unit 16 should output. The arm voltage command value Varm* is a value (real value) obtained by distributing the voltage components to be output to the AC or DC system, which are obtained as a result of calculations such as the operating state of the power converter 1 and voltage / current control based on each detected value in the power converter 1, to each arm unit 16. The insert count calculation unit 52 calculates the insert count Ncells for each arm unit 16, which represents the number (integer value) of cells 162 that each arm unit 16 has, that will be assigned to the insert state (to be put into the insert state), according to the arm voltage command value Varm*. The insert count calculation unit 52 outputs the calculated insert count Ncells to the cell selection control unit 56.

[0033] There are various methods by which the insert count calculation unit 52 calculates the insert count Ncells. For example, the insert count calculation unit 52 calculates the insert count Ncells, which represents the number of cells 162 to be put into the insert state, by approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 162 belonging to the arm unit 16 to an integer. In this case, the converter control unit 50 performs 1-pulse control, controlling each cell 162 belonging to the arm unit 16 once within one cycle of the AC voltage in the AC system (putting them into the insert state and bypass state). For example, the insert count calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with the number of triangular wave carriers that are phase-shifted from each other, equal to the number of cells 162 belonging to the arm unit 16 (in Figure 1, "n"). The number of triangular wave carriers in which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (is greater than the value of the triangular wave carrier) is calculated as the insert count Ncells, which represents the number of cells 162 that should be put into the insert state. In this case, the converter control unit 50 performs multi-pulse control, controlling the cells 162 belonging to the arm unit 16 multiple times within one cycle of the AC voltage in the AC system (putting them into the insert state and bypass state). For example, the insert count calculation unit 52 compares the modulated wave based on the arm voltage command value Varm* with each triangular wave carrier whose level is shifted by the same number as the number of cells 162 belonging to the arm unit 16 (in Figure 1, "n"). The number of triangular wave carriers in which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier (is greater than the value of the triangular wave carrier) is calculated as the insert count Ncells, which represents the number of cells 162 to be put into the insert state. In this case as well, the converter control unit 50 performs multi-pulse control. The method by which the insert count calculation unit 52 calculates the insert count Ncells is not limited to the method described above. Any method can be used as long as the value (real value) distributed to each arm unit 16 can be expressed as the number of cells 162 to be put into the insert state (integer value).

[0034] The insert count calculation unit 52 is an example of the "state count calculation unit" in the claims. The insert count Ncells is an example of the "state count" in the claims.

[0035] The sort list calculation unit 54 calculates (generates) a sort list for each arm unit 16 that represents the relative magnitudes of the capacitor voltages Vc of each cell 162 in the power converter 10. The sort list calculation unit 54 generates a sort list, for example, at predetermined (constant) calculation cycles TS2. The sort list is sorted in descending or ascending order based on the relative magnitudes of the capacitor voltages Vc (in Figure 3, capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n) of at least two cells 162 belonging to the same arm unit 16. The calculation cycle TS2 for which the sort list calculation unit 54 generates the sort list is a longer interval than the acquisition cycle TS1 for acquiring each detected value in the power converter 1 (TS2 > TS1). This is because the sort list calculation unit 54 considers that sorting the voltage values ​​of the multiple acquired capacitor voltages Vc takes time. Therefore, the sort list calculation unit 54 generates a sort list based on the voltage value of the capacitor voltage Vc acquired in the acquisition cycle TS1 that matches the timing for generating the next sort list in the calculation cycle TS2, that is, the timing for updating the sort list. For example, the sort list calculation unit 54 generates a sort list by sorting the voltage values ​​of the capacitor voltage Vc acquired in the acquisition cycle TS1 immediately before the timing for starting the generation of the sort list, after ensuring that time is allocated for the processing required to sort the voltage values ​​of the capacitor voltage Vc. The voltage value of the capacitor voltage Vc used by the sort list calculation unit 54 when generating the sort list is not limited to the one acquired at the timing immediately before starting the generation of the sort list as described above, but may also be used, for example, the average value or maximum value of the voltage values ​​of the capacitor voltage Vc corresponding to the same capacitor C acquired in multiple acquisition cycles TS1. In the following description, the sort list calculation unit 54 will generate a sort list in which the voltage values ​​of the capacitor voltage Vc are sorted in descending order. The sort list calculation unit 54 outputs the generated sort list to the cell selection control unit 56.

[0036] The sort list calculation unit 54 is an example of the "list calculation unit" in the claims. The sort list is an example of the "list information" in the claims.

[0037] The cell selection control unit 56 selects a cell 162 to change the current control state of at least each time the number of inserts Ncells output by the number of inserts calculation unit 52 changes, that is, each time a control timing is used to control a cell 162 (to put it into an insert state or a bypass state). More specifically, the cell selection control unit 56 starts selecting a cell 162 when the number of inserts Ncells changes. The cell selection control unit 56 then refers to the polarity of the arm current Iarm (i.e., the positive arm current Ip and the negative arm current In) flowing through the arm unit 16 to be controlled, and the sort list of the arm unit 16 to be controlled output by the sort list calculation unit 54, and selects a cell 162 to change to the insert state or a cell 162 to change to the bypass state.

[0038] When the number of inserts Ncells increases, the cell selection control unit 56, during the period (charging period) when the polarity of the arm current Iarm is a charging polarity that stores power in the capacitor C of the cell 162 in the insert state, thereby increasing the total charge of the arm unit 16, prioritizes selecting the cell 162 equipped with a capacitor C that has less stored power from among the cells 162 currently in the bypass state to be changed to the insert state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order from those equipped with a capacitor C that has a relatively low capacitor voltage Vc. The charging polarity is the polarity in which the arm current Iarm flows in the same direction as the positive arm current Ip and the negative arm current In shown in Figure 1. On the other hand, when the number of inserts Ncells increases, the cell selection control unit 56, during the period (discharge period) when the polarity of the arm current Iarm is discharge polarity, which discharges the power stored in the capacitor C of the cell 162 that is in the insert state and increases the total discharge amount of the arm unit 16, prioritizes selecting the cell 162 equipped with a capacitor C that has a large amount of stored power from among the cells 162 that are currently in the bypass state as the cell 162 to be changed to the insert state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order from those equipped with capacitor C that have a relatively high capacitor voltage Vc. The discharge polarity is the polarity in which the arm current Iarm flows in the opposite direction to the positive arm current Ip and negative arm current In shown in Figure 1.

[0039] When the number of inserts Ncells decreases, the cell selection control unit 56, during the charging period (charging period) when the polarity of the arm current Iarm is a charging polarity that stores power in the capacitor C of the cell 162 that is in the insert state, thereby increasing the total charge of the arm unit 16, prioritizes selecting the cell 162 equipped with a capacitor C that has a large amount of stored power from among the cells 162 that are currently in the insert state, and changes it to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects the cells 162 in order from those equipped with capacitor C that have a relatively high capacitor voltage Vc. On the other hand, when the number of inserts Ncells decreases, the cell selection control unit 56, during the discharging period (discharge period) when the polarity of the arm current Iarm is a discharging polarity that discharges the power stored in the capacitor C of the cell 162 that is in the insert state, thereby increasing the total discharge of the arm unit 16, prioritizes selecting the cell 162 equipped with a capacitor C that has a small amount of stored power from among the cells 162 that are currently in the insert state, and changes it to the bypass state. In this case, the cell selection control unit 56 refers to the sort list and selects cells 162 in order, starting with those containing capacitors C with relatively low capacitor voltage Vc values.

[0040] As a result, cells 162 equipped with capacitors C having a relatively high capacitor voltage Vc are preferentially given shorter charging times and longer discharge times, thus equalizing the capacitor voltage Vc in each cell 162 of the arm unit 16. On the other hand, cells 162 equipped with capacitors C having a relatively low capacitor voltage Vc are preferentially given longer charging times and shorter discharge times, so similarly, the capacitor voltage Vc in each cell 162 of the arm unit 16 is also equalized.

[0041] Furthermore, the cell selection control unit 56 controls each cell 162 in the arm unit 16 to reduce the difference in the charge amount of capacitor C (balance so that the charge amounts become relatively uniform). Hereinafter, the control by the cell selection control unit 56 to balance the charge amount of capacitor C (more specifically, the capacitor voltage Vc) so that it becomes uniform will be called "balance control". In the balance control by the cell selection control unit 56, the voltage values ​​of the capacitor voltage Vc of cells 162 belonging to the same arm unit 16 (in Figure 3, the capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n) are acquired at each acquisition cycle TS1, that is, at a cycle shorter than the calculation cycle TS2 in which the sort list calculation unit 54 generates the sort list. The cell selection control unit 56 then compares the acquired voltage values ​​of each capacitor voltage Vc with the upper threshold Vc-max and the lower threshold Vc-min of the capacitor voltage Vc in capacitor C. As a result of this comparison, if the capacitor voltage Vc of cell 162 in the insert state exceeds the threshold Vc-max during the charging period, the cell selection control unit 56 controls this cell 162 to a bypass state to prevent further charging (i.e., to prevent overcharging), and instead selects an equal number of other cells 162 from the bypass state that have a capacitor C with a lower capacitor voltage Vc, and changes them to the insert state. On the other hand, if the capacitor voltage Vc of cell 162 in the insert state exceeds the threshold Vc-min during the discharge period, the cell selection control unit 56 controls this cell 162 to a bypass state to prevent further discharge (i.e., to prevent over-discharge), and instead selects an equal number of other cells 162 from the bypass state that have a capacitor C with a higher capacitor voltage Vc, and changes them to the insert state. The thresholds Vc-max and Vc-min are set, for example, to values ​​that take into account the allowable fluctuation range of the capacitor C with respect to the rated capacitor voltage command value Vc*. More specifically, the threshold Vc-max is set as, for example, the upper limit of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and is set to approximately Vc-max = Vc* × 1.1, which is higher than the rated capacitor voltage command value Vc*.The threshold Vc-min is, for example, set as the lower limit of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and is set to approximately Vc-min = Vc* × 0.9, which is lower than the rated capacitor voltage command value Vc*. The threshold Vc-max and threshold Vc-min may be set based on the average voltage Vc-ave (fluctuation value) of the capacitor voltage Vc in the capacitor C provided in the arm unit 16. The threshold Vc-max is set to approximately Vc-max = Vc-ave × 1.1, which is higher than the average voltage Vc-ave, so that the capacitor voltage Vc of capacitor C does not fluctuate above a certain level from the average voltage Vc-ave. The threshold Vc-min is set to approximately Vc-min = Vc-ave × 0.9, which is lower than the average voltage Vc-ave, so that the capacitor voltage Vc of capacitor C does not fluctuate above a certain level from the average voltage Vc-ave.

[0042] The cell selection control unit 56 generates a cell control state CL* for each cell 162. At this time, the cell selection control unit 56 may generate the cell control state CL* at any timing that matches the timing of the sort list calculation (generation) in the sort list calculation unit 54, the timing of the balance control in the sort list calculation unit 54, and the timing of the operation cycle (so-called operation clock and calculation clock) of the converter control unit 50 and the components provided by the converter control unit 50. The cell control state CL* contains information indicating whether the corresponding cell 162 should be controlled to at least the insert state or the bypass state. The cell selection control unit 56 outputs the cell control state CL* corresponding to each cell 162 to the gate signal generation unit 58. Figure 3 shows the cell control states CL*-1 to CL*-n corresponding to cells 162-1 to 162-n.

[0043] The cell selection control unit 56 is an example of the "unit converter selection unit" in the claims. The acquisition period TS1 is an example of the "first time interval" in the claims, and the calculation period TS2 is an example of the "second time interval" in the claims. The threshold Vc-max is an example of the "first threshold" in the claims, and the threshold Vc-min is an example of the "second threshold" in the claims.

[0044] The gate signal generation unit 58 generates control signals (gate signals) to be output to all cells 162 in each arm unit 16 according to the respective cell control states CL* output by the cell selection control unit 56. More specifically, the gate signal generation unit 58 generates a gate signal gtp corresponding to the switching element Q1 and a gate signal gtn corresponding to the switching element Q2 in each cell 162. Figure 3 shows the gate signals gtp-1 to gtp-n and gate signals gtn-1 to gtn-n corresponding to cells 162-1 to 162-n, respectively. In this case, the gate signal generation unit 58 may generate the gate signal gtn by, for example, logically inverting the gate signal gtp. However, even in this case, as described above, a short dead time is provided to prevent the ends of the capacitor C in cell 162 from being short-circuited. The gate signal generation unit 58 outputs each of the generated gate signals to the corresponding cell 162 (more specifically, the switching element Q provided in cell 162).

[0045] Figure 3 shows a configuration in which the gate signal generation unit 58 generates a gate signal corresponding to each cell 162 and outputs it to the corresponding cell 162. However, for example, the cell selection control unit 56 may output a cell control state CL* to each cell 162, and each cell 162 may generate a gate signal corresponding to the cell control state CL*. In this case, each cell 162 will be equipped with a component that has a function equivalent to that of the gate signal generation unit 58.

[0046] With this configuration, the converter control unit 50 controls the cells 162 within each arm unit 16 of the power converter 10, causing the power converter 10 to convert between AC power from an AC system and DC power from a DC system.

[0047] Incidentally, in the conventional and widely known phase-shift PWM method, a separate triangular wave carrier and voltage command value (modulation wave) are assigned to each cell, and a control signal (gate signal) is calculated for each cell. In contrast, in the converter control unit 50, the insert number calculation unit 52 calculates the number of inserts Ncells, which represents the number of cells 162 to be put into the insert state, based on, for example, a triangular wave carrier that is not assigned to each cell 162 and a modulation wave based on the arm voltage command value Varm* for each arm unit 16. Then, in the converter control unit 50, the cell selection control unit 56, triggered by at least a change in the number of inserts Ncells, selects the cells 162 to be changed to the insert state or bypass state by referring to the polarity of the arm current Iarm and the sort list output by the sort list calculation unit 54. As a result, the gate signal generation unit 58 generates a gate signal to turn on or off the switching element Q of each cell 162. In other words, in the converter control unit 50, there are no triangular wave carriers and voltage command values ​​(modulation waves) that are individually assigned to each cell.

[0048] Furthermore, in conventional phase-shift PWM methods, the average power flowing into and out of a cell over a relatively long period is manipulated by adjusting the amplitude of the voltage command value (modulated wave) for each cell, thereby equalizing the capacitor voltage. As a result, in conventional phase-shift PWM methods, the time required to balance the charge levels of the capacitors in each cell to be relatively uniform becomes long. In contrast, in the converter control unit 50 of the embodiment, the cell selection control unit 56 can balance the charge levels of the capacitor C in cell 162 to be relatively uniform at each timing of switching control of the switching element Q in cell 162, for example. As a result, the converter control unit 50 of the embodiment can equalize the charge levels of capacitor C in a shorter time than conventional phase-shift PWM methods. Consequently, the power converter 10 can suppress the fluctuation range of the capacitor voltage Vc through the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment, secure an output voltage for each cell 162, and reduce operational constraints. Furthermore, in the power converter 10, the maximum value of the capacitor voltage Vc is suppressed by the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment, thereby reducing the risk of failure of the capacitor C and switching element Q provided in the cell 162.

[0049] From these considerations, the power converter 1 can simultaneously achieve high capacitor voltage balance performance in the power converter 10 and high reliability with reduced failure risk. Moreover, in the power converter 1, balance control by the converter control unit 50 (more specifically, the cell selection control unit 56) is performed when the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min. Therefore, even during operation in the power converter 10 where the fluctuation range of the capacitor voltage Vc is narrow, such as during low-power operation, the switching control period for the cell 162 is shortened, preventing the switching frequency from becoming high. Furthermore, in the power converter 1, even in the event of a grid fault, for example, the balance control by the converter control unit 50 operates to prevent the capacitor voltage Vc from deviating from the normal voltage range. This reduces the risk of the power converter 10's protection device activating and stopping operation due to the capacitor voltage Vc reaching an overvoltage or undervoltage. As a result, the power converter 1 can improve its ability to continue operation in the event of a grid fault.

[0050] [First operation of the power converter] Next, an example of the operation of the power converter 1, that is, the control of cell 162 in the converter control unit 50, will be described. In the following description, the control of arm unit 16-PR provided by leg 12-R will be described, representing each of the legs 12 of leg 12-R, leg 12-S, and leg 12-T provided by the power converter 10. In the following description, for the sake of simplicity, the operation of each component provided by the converter control unit 50 will be described as being performed by the converter control unit 50 itself.

[0051] Figure 4 is a timing chart illustrating an example of the operation timing of the first operation in the power converter 1. The example of operation of the power converter 1 shown in Figure 4 is an example of operation when the arm unit 16-PR (hereinafter simply referred to as "arm unit 16") has six cells 162 (n=6). Figure 4 shows an example of balance control of the converter control unit 50 when the capacitor voltage Vc-5 of cell 162-5 of the arm unit 16 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). Figure 4 shows the arm voltage command value Varm*, arm current Iarm, the arm voltage Varm generated by the arm unit 16 based on the arm voltage command value Varm*, and the temporal changes of the gate signals gtp-1 to gtp-6 output by the converter control unit 50 to the switching elements Q1 of cells 162-1 to 162-6, all on the same time axis. Figure 4 also shows a schematic change in the capacitor voltage Vc(Vc-5) of cell 162-5, which is balanced by the converter control unit 50, on the same time axis. Furthermore, Figure 4 shows an example of a sort list calculated (generated) by the converter control unit 50 (more specifically, the sort list calculation unit 54). In the first operation shown in Figure 4, the sort list is generated (updated) for each cycle of the arm voltage command value Varm*. Figure 4 also shows an example of the acquisition cycle TS1 for acquiring the voltage value of the capacitor voltage Vc-5, and the calculation cycle TS2 for creating the sort list.

[0052] The arm voltage command value Varm* includes the frequency and DC component of the AC system. As described above, the converter control unit 50 (more specifically, the insert number calculation unit 52) ​​calculates the insert number Ncells, which is represented by a stepped pseudo-sine wave, based on the arm voltage command value Varm*. In Figure 4, the insert number Ncells is an integer value with a minimum value of "0" and a maximum value of "n" (here, "6"). The insert number Ncells is calculated, for example, by approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of cell 162 belonging to the arm unit 16 to an integer. In other words, the operating timing of the power converter 1 shown in Figure 4 is the operating timing when the converter control unit 50 performs 1-pulse control. The insert number Ncells represents something equivalent to the arm voltage Varm shown in Figure 4.

[0053] The converter control unit 50 (more specifically, the cell selection control unit 56 and the gate signal generation unit 58) controls the gate signal gtp output to each cell 162 so that the number of cells 162 belonging to the arm unit 16 that are in the insert state match the number of cells 162 that should be put into the insert state (integer value) represented by the number of inserts Ncells, at each timing when the number of inserts Ncells changes. Each gate signal gtp turns on the switching element Q1 when it is "1" ("High" level) and turns off the switching element Q1 when it is "0" ("Low" level). Here, the gate signal gtn output to the switching element Q2 provided by cell 162 can be generated by logically inverting the gate signal gtp, as described above. For this reason, the gate signal gtn is not shown in Figure 4. Accordingly, in Figure 4, cell 162 is in the insert state when the gate signal gtp is "1", and in the bypass state when the gate signal gtp is "0". Furthermore, in Figure 4, dead time is omitted for the sake of clarity. The arm voltage Varm is approximately the number of cells 162 that are put into the insert state (an integer value) represented by the number of inserts Ncells, multiplied by the capacitor voltage Vc, assuming that the capacitor voltage Vc of cell 162 is uniformly controlled.

[0054] The arm current Iarm includes the frequency and DC component of the AC system. In arm unit 16, when the arm current Iarm is positive (Iarm>0), the capacitor C in the inserted cell 162 is charged, and the capacitor voltage Vc rises during this charging period. In arm unit 16, when the arm current Iarm is negative (Iarm<0), the capacitor C in the inserted cell 162 is discharged, and the capacitor voltage Vc falls during this discharge period. In arm unit 16, regardless of the polarity of the arm current Iarm, the capacitor C in the bypassed cell 162 is neither charged nor discharged, and maintains its current capacitor voltage Vc.

[0055] At time t0 shown in Figure 4, the number of inserts Ncells is "3". Since the polarity of the arm current Iarm at this time is negative, the converter control unit 50 determines that it is discharge polarity. Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which has a capacitor C with a large amount of stored power, as the cell 162 to be put into the insert state. More specifically, the converter control unit 50 selects cells 162-1, 162-2, and 162-3, which are the three highest capacitor voltages Vc (Vc-1, Vc-2, and Vc-3) in the sort list. Therefore, at time t0 shown in Figure 4, the converter control unit 50 sets the gate signals gtp-1, gtp-2, and gtp-3 to "1" in order to put the three selected cells 162 into the insert state. Here, cell 162-5 is in the bypass state because its gate signal gtp-5 is "0". Therefore, the capacitor C-5 in cell 162-5 is neither charged nor discharged, maintaining its current capacitor voltage Vc-5.

[0056] Subsequently, at time t1, when the number of inserts Ncells changes (increases) to "4", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the bypass state and has the next highest stored power capacitor C, as the cell 162 to be put into the insert state. Here, since the converter control unit 50 has already selected the three cells 162 with the third highest capacitor voltage Vc in the sort list, it selects cell 162-4, which has the next highest capacitor voltage Vc (i.e., the fourth highest Vc-4). Then, at time t1, the converter control unit 50 sets the gate signal gtp-4 to "1" in order to put the selected cell 162-4 into the insert state. At this time, cell 162-5 is still in the bypass state, so cell 162-5 continues to maintain its current capacitor voltage Vc-5.

[0057] Subsequently, at time t2, when the number of inserts Ncells changes (increases) to "5", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the bypass state and has a capacitor C with low stored power, as the cell 162 to be put into the insert state. Here, the converter control unit 50 selects cell 162-6, which is the first cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-6). Then, at time t2, the converter control unit 50 sets the gate signal gtp-6 to "1" in order to put the selected cell 162-6 into the insert state. At this time, since cell 162-5 is still in the bypass state, cell 162-5 continues to maintain its current capacitor voltage Vc-5.

[0058] Subsequently, at time t3, when the number of inserts Ncells changes (increases) to "6", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162 that is currently in the bypass state and has the next lowest stored power capacitor C as the cell 162 to be put into the insert state. Here, since the converter control unit 50 has already selected one cell 162 with the lowest capacitor voltage Vc in the sort list, it selects cell 162-5 with the next lowest capacitor voltage Vc (i.e., the second lowest Vc-5). Then, at time t3, the converter control unit 50 sets the gate signal gtp-5 to "1" in order to put the selected cell 162-5 into the insert state. As a result, the capacitor C-5 in cell 162-5 is charged, and the capacitor voltage Vc-5 rises (increases) as it charges.

[0059] Subsequently, at time t4, when the number of inserts Ncells changes (decreases) to "5", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the insert state and has a large amount of stored power, as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t4, the converter control unit 50 sets the gate signal gtp-1 to "0" in order to put the selected cell 162-1 into the bypass state. At this time, since cell 162-5 is still in the insert state, capacitor C-5 continues to charge, and the capacitor voltage Vc-5 continues to rise.

[0060] Subsequently, at time t5, when the number of inserts Ncells changes (decreases) to "4", the converter control unit 50, as at time t4, selects cell 162-2, which is the second highest capacitor voltage Vc in the sort list (i.e., Vc-2), and sets the gate signal gtp-2 to "0" to bypass the selected cell 162-2. At this time, since cell 162-5 is still in the insert state, capacitor C-5 continues to charge, and the capacitor voltage Vc-5 continues to rise.

[0061] Subsequently, at time t6, when the polarity of the arm current Iarm becomes negative (discharge polarity), cell 162-5, which is in the insert state, begins to discharge the power stored in capacitor C-5. As a result, the capacitor voltage Vc-5 decreases as the discharge occurs.

[0062] Subsequently, at time t7, when the number of inserts Ncells changes (decreases) to "3", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the insert state and has a capacitor C with low stored power, as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects cell 162-6, which is the first cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-6). Then, at time t6, the converter control unit 50 sets the gate signal gtp-6 to "0" in order to put the selected cell 162-6 into the bypass state. At this time, cell 162-5 is still in the insert state, so it continues to discharge the power stored in capacitor C-5, and the capacitor voltage Vc-5 decreases.

[0063] Subsequently, at time t8, if the capacitor voltage Vc-5 of cell 162-5 exceeds the threshold Vc-min, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the bypass state and has a large amount of stored power, to be inserted in place of the bypassed cell 162-5. Here, the converter control unit 50 selects cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t8, the converter control unit 50 sets the gate signal gtp-5 to "0" in order to bypass cell 162-5. As a result, the discharge from cell 162-5 is stopped, and the discharge from the capacitor C-5 of cell 162-5 continues, preventing the capacitor voltage Vc-5 from falling significantly below the threshold Vc-min, as shown by the dashed line in Figure 4. In other words, the capacitor voltage Vc-5 is maintained at a voltage value close to the threshold Vc-min, as shown by the solid line in Figure 4. Furthermore, at time t8, the converter control unit 50 sets the gate signal gtp-1 to "1" in order to put the selected cell 162-1 into the insert state. As a result, the capacitor voltage of cell 162-1 is output as a substitute, and the arm voltage Varm does not deviate (including errors) from the ideal step-shaped waveform according to the arm voltage command value Varm*.

[0064] Subsequently, at time t9, when the number of inserts Ncells changes (decreases) to "2", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162 that is currently in the insert state and has a capacitor C with low stored power as the cell 162 to be put into the bypass state. Here, since the converter control unit 50 has already selected two cells 162 with the first and second lowest capacitor voltages Vc in the sort list, it selects cell 162-4, which has the next lowest capacitor voltage Vc (i.e., the third lowest Vc-4). Then, at time t9, the converter control unit 50 sets the gate signal gtp-4 to "0" in order to put the selected cell 162-4 into the bypass state. Alternatively, at time t9, the converter control unit 50 may select cell 162-1, which was in the insert state at time t8, instead of cell 162-5, which was put into the bypass state at time t8, and put it into the bypass state. Even in this state, since cell 162-5 is in a bypass state, the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0065] Subsequently, between times t10 and t11, each time the number of inserts Ncells changes (decreases) from "1" to "0", the converter control unit 50, as with time t7, sequentially selects cell 162, which is the fourth and sixth cell in the sort list with the lowest capacitor voltage Vc (i.e., Vc-3 and Vc-1), and sets the gate signal gtp to "0" to bypass the selected cell 162. More specifically, at time t10, the converter control unit 50 selects cell 162-3 and sets the gate signal gtp-3 to "0", and at time t11, it selects cell 162-1 and sets the gate signal gtp-1 to "0". At this time as well, since cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0066] Subsequently, at time t12, the sort list is updated. Here, it is assumed that the updated sort list also has the same order of voltage values ​​of the capacitor voltages Vc sorted in descending order as the sort list before the update.

[0067] Subsequently, at time t13, when the number of inserts Ncells changes (increases) to "1", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the bypass state and has a large amount of stored power, as the cell 162 to be put into the insert state. Here, the converter control unit 50 selects cell 162-1, which is the first cell in the sort list with the highest capacitor voltage Vc (i.e., Vc-1). Then, at time t13, the converter control unit 50 sets the gate signal gtp-1 to "1" in order to put the selected cell 162-1 into the insert state. At this time, since cell 162-5 is still in the bypass state, the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0068] Subsequently, between times t14 and t15, as the number of inserts Ncells changes (increases) sequentially to "2" and "3", the converter control unit 50, as in time t13, sequentially selects cell 162, which is the second and third highest capacitor voltage Vc in the sort list (i.e., Vc-2 and Vc-3), and sets the gate signal gtp to "1" to put the selected cell 162 into the insert state. More specifically, at time t14, the converter control unit 50 selects cell 162-2 and sets the gate signal gtp-2 to "1", and at time t15, it selects cell 162-3 and sets the gate signal gtp-3 to "1". At this time as well, since cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0069] In this way, the converter control unit 50 determines whether the polarity is discharge polarity or charge polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), refers to the sort list, selects a cell 162 to be put into an insert state or a bypass state, and controls the gate signal gtp of the selected cell 162. At this time, if the capacitor voltage Vc in any cell 162 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (falls below the threshold Vc-min), the converter control unit 50 performs balance control. In other words, the converter control unit 50 performs balance control when the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, regardless of the timing of the sort list calculation (generation) or the switching control. In balance control, the converter control unit 50 puts the cell 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min into a bypass state. As a result, the cell 162 in the bypass state stops charging to or discharging from capacitor C. The converter control unit 50 then refers to the sort list and selects a cell 162 from among the currently bypassed cells 162 to replace the bypassed cell 162, and puts it into the insert state. This ensures that the capacitor C in cell 162 is not charged or discharged any further in the power converter 10 (without overcharging or over-discharging), and the charge levels of the capacitor C are balanced to be relatively uniform. In the first operation of the power converter 1 shown in Figure 4, the case where the capacitor voltage Vc-5 of cell 162-5 exceeds the threshold Vc-min at time t8 is shown, but the balance control in the converter control unit 50 is the same for other cells 162. In the first operation of the power converter 1 shown in Figure 4, the case where cell 162-1 is selected as a replacement for cell 162-5 at time t8 is shown, but the selection as a replacement is the same for other cells 162.In the first operation of the power converter 1 shown in Figure 4, the balance control in the converter control unit 50 was shown as the balance control when the capacitor voltage Vc-5 of cell 162-5 exceeded the threshold Vc-min. However, the balance control when the capacitor voltage Vc of any cell 162 in the arm unit 16 exceeds the threshold Vc-max should also be equivalent to the balance control in the first operation described above.

[0070] [Second operation of the power converter] In the first operation described above, we showed the case where the converter control unit 50 performs single-pulse control, but the converter control unit 50 can also perform double-pulse control. Next, as another operation of the power converter 1 (another example of balance control in the converter control unit 50), we will describe the operation when the converter control unit 50 performs double-pulse control.

[0071] Figure 5 is a timing chart illustrating an example of the operating timing for the second operation in the power converter 1. The second operation shown in Figure 5, like the first operation shown in Figure 4, is the operation when the arm unit 16 has six cells 162 (n=6). The number of inserts, Ncells, is calculated by comparing the modulated wave based on the arm voltage command value Varm* with the number of triangular wave carriers that are shifted in phase and level to the same number as the number of cells 162 belonging to the arm unit 16 (here, "6"), and determining the number of triangular wave carriers where the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier. In the second operation, the converter control unit 50 performs multi-pulse control, controlling the cells 162 belonging to the arm unit 16 multiple times within one cycle of the arm voltage command value Varm*. Therefore, the operating timing of the power converter 1 shown in Figure 5 is shown as an enlarged portion of the range within one cycle of the arm voltage command value Varm*.

[0072] The second operation shown in Figure 5 is an example of balance control performed during a discharge polarity (discharge period) where the polarity of the arm current Iarm is negative (Iarm<0), specifically during the period when the number of insert-state cells 162, represented by the number of inserts Ncells, is "2" before it changes from "2" to "1". In other words, during the period when the number of insert-state cells 262 remains "2" and does not change. In the second operation shown in Figure 5, the sort list calculation unit 54 generates the sort list with a shorter calculation period TS2 than in the first operation shown in Figure 4. However, even in the second operation shown in Figure 5, the calculation period TS2 is a period with a longer time interval than the acquisition period TS1 (TS2>TS1). Figure 5 shows an example of balance control by the converter control unit 50 when the capacitor voltage Vc-3 of cell 162-3 in the arm unit 16 exceeds the threshold Vc-min (when it falls below the threshold Vc-min).

[0073] At time t0 shown in Figure 5, the number of inserts, Ncells, is "2". Therefore, the converter control unit 50 refers to the sort list and selects cell 162, which has a capacitor C with a large amount of stored power, as the cell 162 to be put into the insert state. More specifically, the converter control unit 50 selects cell 162-1 and cell 162-3, which have the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. Therefore, at time t0 shown in Figure 5, the converter control unit 50 sets gate signals gtp-1 and gtp-3 to "1" in order to put the two selected cells 162 into the insert state. As a result, the power stored in capacitor C-3 of cell 162-3 is discharged, and the capacitor voltage Vc-3 decreases as it discharges.

[0074] Subsequently, at time t1, if the capacitor voltage Vc-3 of cell 162-3 exceeds the threshold Vc-min, the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the bypass state and has a large amount of stored power, to be inserted in place of the bypassed cell 162-3. Here, the converter control unit 50 selects cell 162-2, which has the third highest capacitor voltage Vc (i.e., Vc-2) in the sort list. Then, at time t1, the converter control unit 50 sets the gate signal gtp-3 to "0" to bypass cell 162-3. As a result, discharge from cell 162-3 is stopped, and discharge from capacitor C-3 of cell 162-3 continues, preventing the capacitor voltage Vc-3 from falling significantly below the threshold Vc-min, as shown by the dashed line in Figure 5 (when balance control is performed only in conjunction with the sort list update). In other words, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold Vc-min, as shown by the solid line in Figure 5. Furthermore, at time t1, the converter control unit 50 sets the gate signal gtp-2 to "1" in order to put the selected cell 162-2 into the insert state. As a result, the capacitor voltage of cell 162-2 is output as a substitute, and the arm voltage Varm is maintained.

[0075] Subsequently, at time t2, the sort list is updated. Here, it is assumed that the sort list has been updated to include the capacitor voltage Vc of cell 162-3, where Vc-3 is the lowest capacitor voltage Vc.

[0076] Subsequently, at time t3, when the number of inserts Ncells changes (decreases) to "1", the converter control unit 50 refers to the sort list and selects cell 162, which is currently in the insert state and has a capacitor C with low stored power, as the cell 162 to be put into the bypass state. Here, the converter control unit 50 selects cell 162-2, which has a lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from among the insert states of cell 162-1 and cell 162-2. Then, at time t3, the converter control unit 50 sets the gate signal gtp-2 to "0" in order to put the selected cell 162-2 into the bypass state. At this time, since cell 162-3 is also in the bypass state, the capacitor voltage Vc-3 of cell 162-3 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0077] Thus, in the second operation (multiple pulse control), just like in the first operation (single pulse control) shown in Figure 4, the converter control unit 50 determines whether the polarity is discharge or charge based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (increases or decreases), refers to the sort list, selects a cell 162 to be put into the insert state or bypass state, and controls the gate signal gtp of the selected cell 162. At this time, in the second operation as well, if the capacitor voltage Vc in any cell 162 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (falls below the threshold Vc-min), the converter control unit 50 performs balance control. In other words, in the second operation as well, regardless of the timing of the sort list calculation (generation) or the switching control, the converter control unit 50 performs balance control if the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min. In the second operation's balance control, the converter control unit 50 also bypasses any cell 162 whose capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min. As a result, in the second operation as well, the bypassed cell 162 stops charging its capacitor C or discharging its capacitor C. In the second operation as well, the converter control unit 50 refers to the sort list and selects a replacement cell 162 from among the currently bypassed cells 162 to replace the bypassed cell 162, and puts it into the insert state. As a result, in the second operation as well, the power converter 10 prevents the capacitor C of cell 162 from being charged or discharged any further (without overcharging or over-discharging), and balances the charge amount of capacitor C to be relatively uniform. In the second operation of the power converter 1 shown in Figure 5, the case where the capacitor voltage Vc-3 of cell 162-3 exceeds the threshold Vc-min at time t1 is shown, but the balance control in the converter control unit 50 is the same for other cells 162.In the second operation of the power converter 1 shown in Figure 5, cell 162-2 is selected as a substitute for cell 162-3 at time t1, but the same selection applies to other cells 162 as substitutes. In the second operation of the power converter 1 shown in Figure 5, the balance control in the converter control unit 50 is shown when the capacitor voltage Vc-3 of cell 162-3 exceeds the threshold Vc-min, but the balance control when the capacitor voltage Vc of any cell 162 in the arm unit 16 exceeds the threshold Vc-max should also be equivalent to the balance control in the second operation described above.

[0078] With this configuration and operation, the power converter 1's converter control unit 50 determines whether each arm unit 16 of the power converter 10 is discharged or charged based on the polarity of the arm current Iarm, at each timing when the number of insert cells Ncells of the cell 162 changes (increases or decreases). The power converter 1's converter control unit 50 then refers to a sort list calculated (generated) for each arm unit 16 to select a cell 162 to be put into an insert state or a bypass state, and changes the control state of the selected cell 162. At this time, if the capacitor voltage Vc of any cell 162 exceeds the threshold Vc-max or threshold Vc-min, the converter control unit 50 puts that cell 162 into a bypass state, refers to the sort list to select an alternative cell 162 from among the currently bypassed cells 162, and puts it into an insert state. In this way, the power converter 1 can prevent overcharging or over-discharging of the capacitor C of the cell 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, and can balance the charge amount of the capacitor C so that it is relatively uniform. As a result, the power converter 1 can reduce the risk of failure of the capacitor C and switching element Q in the power converter 10. For example, in the event of a grid fault, it can reduce the risk that the capacitor voltage Vc will reach an overvoltage or undervoltage, causing the power converter 10's protection device to activate and shut down operation. This makes the power converter 1 a highly reliable power converter with improved operational continuity performance in the event of a grid fault.

[0079] As described above, in the power converter 1 of the first embodiment, the converter control unit 50 determines whether each arm unit 16 of the power converter 10 is discharge polarity or charging polarity based on the polarity of the arm current Iarm at each timing when the number of inserts Ncells of cells 162 changes (increases or decreases). Then, in the power converter 1 of the first embodiment, the converter control unit 50 refers to a sort list calculated (generated) for each arm unit 16 to select a cell 162 to be put into an insert state or a bypass state, and changes the control state of the selected cell 162. At this time, in the power converter 1 of the first embodiment, if the capacitor voltage Vc in any cell 162 exceeds the threshold Vc-max or threshold Vc-min, the converter control unit 50 puts that cell 162 into a bypass state, refers to the sort list to select an alternative cell 162 from among the currently bypassed cells 162 and puts it into an insert state. As a result, in the power converter 1 of the first embodiment, it is possible to prevent overcharging or over-discharging of the capacitor C in cell 162 when the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, and to balance the charge amount of capacitor C so that it is relatively uniform. As a result, in the power converter 1 of the first embodiment, the risk of failure of the capacitor C and switching element Q in cell 162 in the power converter 10 can be reduced, and even in the event of a grid fault, the risk of the power converter 10's protection device activating and stopping operation due to the capacitor voltage Vc reaching an overvoltage or undervoltage can be reduced. As a result, the power converter 1 of the first embodiment can realize a highly reliable power converter with improved operational continuity performance in the event of a grid fault.

[0080] In the power converter 1 of the first embodiment described above, the power converter 10 is, for example, a dual star-connected MMC that is installed at the interconnection point between the AC system and the DC system, and converts between AC power supplied by the AC system and DC power supplied by the DC system in response to control from the converter control unit 50. However, the power converter 10 may be a power converter with other configurations.

[0081] (Second embodiment) [Configuration of the power converter] The second embodiment will now be described. Figure 6 is a diagram showing an example of the configuration of a power converter according to the second embodiment. Figure 6 shows an example of a power converter 2 that is connected to an AC system and adjusts the reactive power of the AC system. If the power converter 2 is configured to include an energy storage element such as a battery in the cell 262, which will be described later, it may adjust the active power of the AC system. The AC system may be an AC power source or an AC load, as in the first embodiment. The power converter 2 comprises a power converter 20 and a converter control unit 50a. In Figure 6, components having the same function as the power converter 1 of the first embodiment are denoted by the same reference numerals, and detailed descriptions are omitted.

[0082] The power converter 20 is a single delta-connected modular multilevel converter (MMC) that converts AC power in response to control from the converter control unit 50a. The power converter 20 is equipped with multiple legs 22 between the lines of the AC system. The number of legs 22 equipped in the power converter 20 corresponds to the number of lines between the phases of the AC power supplied by the AC system. Figure 6 shows the case where the AC system supplies three phases of AC power: the first phase (R phase), the second phase (S phase), and the third phase (T phase). Therefore, Figure 6 shows the configuration of the power converter 20 equipped with three legs 22: leg 22-RS, leg 22-ST, and leg 22-TR. Legs 22-RS, 22-ST, and 22-TR each have the same configuration.

[0083] In each leg 22, AC terminal CA is connected to a terminal of one of the phases of the AC system, and AC terminal CB is connected to a terminal of any other phase in the AC system that is different from the phase to which AC terminal CA is connected. More specifically, in leg 22-RS, which corresponds to the phase between the R phase and the S phase, AC terminal CA-R is connected to AC terminal R of the R phase of the AC system, and AC terminal CB-S is connected to AC terminal S of the S phase of the AC system. In leg 22-ST, which corresponds to the phase between the S phase and the T phase, AC terminal CA-S is connected to AC terminal S of the AC system, and AC terminal CB-T is connected to AC terminal T of the T phase of the AC system. In leg 22-TR, which corresponds to the phase between the T phase and the R phase, AC terminal CA-T is connected to AC terminal T of the AC system, and AC terminal CB-R is connected to AC terminal R of the AC system. Figure 6 shows the case where AC terminal CA of each leg 22 is connected to the terminal of the corresponding phase in the AC system via transformer TR.

[0084] Each leg 22 comprises, for example, a reactor 14 and an arm unit 26. Each arm unit 26 comprises, for example, n cells 262 (cells 262-1 to 262-n) connected in series (where n is a natural number). In Figure 6, to distinguish which phase or which pair of phases in the AC system each component of leg 22 corresponds to, a hyphen "-" and the letters "R" (representing the R phase), "S" (representing the S phase), "T" (representing the T phase), "RS" (representing the R phase and S phase), "ST" (representing the S phase and T phase), or "TR" (representing the T phase and R phase) are added after each component's code. In the following description, if it is not necessary to distinguish which phase or which pair of phases in the AC system each component corresponds to, the hyphen and the identifying letters following the hyphen are omitted.

[0085] In each leg 22, the reactor 14 is connected in series to the AC terminal CA side of the arm unit 26. In each leg 22, the end of the reactor 14 that is not connected to the arm unit 26 is the AC terminal CA. In each leg 22, the terminal on the arm unit 26 opposite to the reactor 14 is the AC terminal CB of leg 22. In other words, in each leg 22, the reactor 14 and cells 262-1 to 262-n are connected in series in this order from the AC terminal CA side to the AC terminal CB side and connected to the AC terminal CA.

[0086] Leg 22 is an example of a "phase unit" in the claims. Arm unit 26 (which may include reactor 14) is an example of an "arm unit" in the claims. Cell 262 is an example of a "unit converter" in the claims. Reactor 14 is an example of an "inductance element" in the claims.

[0087] Figure 6 shows the case where the reactor 14 is located on the AC terminal CA side of the arm unit 26 in each leg 22. However, the reactor 14 may be located on the opposite side of the AC terminal CA side of the arm unit 26 (i.e., on the AC terminal CB side) or at any position within the arm unit 26 (i.e., between any two cells 262 connected in series in the arm unit 26). The reactor 14 may be replaced by a transformer with a special winding structure that has sufficient leakage reactance to replace the function of the reactor. In this case, the reactor 14 may be integrated with the transformer TR.

[0088] Each arm unit 26 generates a stepped sinusoidal (multilevel waveform) AC voltage representing the AC waveform supplied between the corresponding phases of the AC system, in response to control from the converter control unit 50a to each of the series-connected cells 262.

[0089] Here, an example of the configuration of cell 262 in arm unit 26 will be described. Cell 262 is, for example, a full-bridge circuit. Figure 7 shows an example of the configuration of cell 262 in leg 22 of power converter 20. Cell 262 comprises four switching elements Q (switching elements Q1 to Q4), four diodes D (diodes D1 to D4), and a capacitor C. The switching elements Q are, for example, insulated-gate bipolar transistors (IGBTs), similar to the switching elements Q in cell 162 of the first embodiment. Therefore, the switching elements Q are not limited to IGBTs, but can be any self-extinguishing semiconductor switching elements capable of realizing a converter or inverter.

[0090] In cell 262, switching elements Q1 and Q2 are connected in series with each other, and switching elements Q3 and Q4 are connected in series with each other. In cell 262, the series circuits of switching elements Q1 and Q2, the series circuits of switching elements Q3 and Q4, and capacitor C are connected in parallel with each other. In cell 262, each switching element Q and its corresponding diode D are connected in parallel with each other. In cell 262, the connection point between the emitter of switching element Q1 and the collector of switching element Q2 is the positive terminal TP(+) connected to the AC terminal CA side in leg 22, and the connection point between the emitter of switching element Q3 and the collector of switching element Q4 is the negative terminal TN(-) connected to the AC terminal CB side in leg 22.

[0091] Each of the switching elements Q1 to Q4 in cell 262 receives a control signal from the converter control unit 50a (either a control voltage is applied or a control current is supplied). The gate of switching element Q1 receives the gate signal gta as a control signal from the converter control unit 50a, the gate of switching element Q2 receives the gate signal gtb as a control signal from the converter control unit 50a, the gate of switching element Q3 receives the gate signal gtc as a control signal from the converter control unit 50a, and the gate of switching element Q4 receives the gate signal gtd as a control signal from the converter control unit 50a. As a result, each of the switching elements Q1 to Q4 is switched by the converter control unit 50a to either an on state or an off state. In the following explanation, it is assumed that when a control signal of "1" ("High" level) (gate signals gta, gtb, gtc, and gtd) is input, each switching element Q turns on, and when a control signal of "0" ("Low" level) (gate signals gta, gtb, gtc, and gtd) is input, each switching element Q turns off.

[0092] Capacitor C is charged or discharged according to the state of each switching element Q. In cell 262, the terminal voltage of capacitor C (capacitor voltage Vc) is generated as the terminal voltage between the positive terminal TP and the negative terminal TN of cell 262 (cell voltage Vo). More specifically, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd) = (1, 0, 0, 1), current flows in the order of positive terminal TP, switching element Q1, capacitor C, switching element Q4, and negative terminal TN, and the cell voltage Vo of cell 262 matches the capacitor voltage Vc. In other words, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd) = (1, 0, 0, 1), capacitor C is inserted between the positive terminal TP and the negative terminal TN of cell 262, and the capacitor voltage Vc is output as the cell voltage Vo. In the following explanation, setting the control signal (gta,gtb,gtc,gtd)=(1,0,0,1) by the converter control unit 50a is referred to as "positive voltage insert," and the state of cell 262 in this case is referred to as the "positive voltage insert state." On the other hand, when the converter control unit 50a sets the control signal (gta,gtb,gtc,gtd)=(0,1,1,0), for example, current flows in the order of positive terminal TP, switching element Q2, capacitor C, switching element Q3, and negative terminal TN, and the cell voltage Vo of cell 262 coincides with the inversion of the capacitor voltage Vc. In other words, by setting the control signal (gta,gtb,gtc,gtd)=(0,1,1,0) by the converter control unit 50a, capacitor C is inserted in the reverse direction between the positive terminal TP and the negative terminal TN of cell 262, and the negative capacitor voltage Vc is output as the cell voltage Vo. In the following explanation, the setting of the converter control unit 50a to the control signals (gta,gtb,gtc,gtd) = (0,1,1,0) is referred to as "negative voltage insert," and the state of cell 262 in this case is referred to as the "negative voltage insert state."Furthermore, when the converter control unit 50a sets the control signal (gta,gtb,gtc,gtd) = (1,0,1,0) or (0,1,0,1), current flows, for example, from the positive terminal TP, diode D1, switching element Q3, and negative terminal TN, or from the positive terminal TP, switching element Q2, diode D4, and negative terminal TN, resulting in a cell voltage Vo of cell 262 of 0[V]. In other words, when the converter control unit 50a sets the control signal (gta,gtb,gtc,gtd) = (1,0,1,0) or (0,1,0,1), the positive terminal TP and negative terminal TN of cell 262 are short-circuited, and current flows without passing through capacitor C, resulting in a cell voltage Vo of cell 262 of 0[V]. In the following explanation, setting the converter control unit 50a to control signals (gta,gtb,gtc,gtd) = (1,0,1,0) or (0,1,0,1) is referred to as "bypass," and the state of cell 262 in this case is referred to as the "bypass state."

[0093] Cell 262 is not limited to the configuration shown in Figure 7; any configuration that achieves the same functionality as cell 262 is acceptable.

[0094] Switching element Q1 and diode D1 are examples of the "switching element" and "first switching element" in the claims; switching element Q2 and diode D2 are examples of the "switching element" and "second switching element" in the claims; switching element Q3 and diode D3 are examples of the "switching element" and "third switching element" in the claims; and switching element Q4 and diode D4 are examples of the "switching element" and "fourth switching element" in the claims. A series circuit of a parallel circuit of switching element Q1 and diode D1 and a parallel circuit of switching element Q2 and diode D2 is an example of the "first series circuit" in the claims; and a series circuit of a parallel circuit of switching element Q3 and diode D3 and a parallel circuit of switching element Q4 and diode D4 is an example of the "second series circuit" in the claims. The ON state is an example of the "conducting state" in the claims, and the OFF state is an example of the "non-conducting state" in the claims. Capacitor C is an example of an "energy storage element" in the claims. Positive terminal TP is an example of a "first terminal" in the claims, and negative terminal TN is an example of a "second terminal" in the claims. Positive voltage insert state is an example of a "first first control state" in the claims, negative voltage insert state is an example of a "second first control state" in the claims, and bypass state is an example of a "second control state" in the claims.

[0095] By connecting multiple cells 262 with this configuration in series, the arm unit 26 outputs a voltage which is the sum of the cell voltages Vo of each cell 262 controlled to be in an insert state (positive voltage insert state or negative voltage insert state). Therefore, the arm unit 26 outputs a voltage corresponding to the number of cells 262 controlled to be in an insert state (positive voltage insert state or negative voltage insert state) by the converter control unit 50a. As a result, the arm unit 26 generates a multilevel waveform in response to the control from the converter control unit 50a. The cells 262 may be provided in each arm unit 16 of the power converter 10 of the first embodiment instead of the cells 162 of the first embodiment.

[0096] By the way, in cell 262, it should be prohibited to set the control signals (gta,gtb)=(1,1) or (gtc,gtd)=(1,1). This is because setting the control signal (gta,gtb)=(1,1) turns on both switching elements Q1 and Q2, and setting the control signal (gtc,gtd)=(1,1) turns on both switching elements Q3 and Q4, and in either case the ends of capacitor C are short-circuited. Therefore, when the converter control unit 50a switches (changes) the control signals (gta,gtb,gtc,gtd) between (1,0,0,1), (0,1,1,0), (1,0,1,0), and (0,1,0,1), it controls the system to provide a very short transient period (so-called dead time) in which the control signals (gta,gtb) = (0,0) or (gtc,gtd) = (0,0). The converter control unit 50a may also fix the control signals (gta,gtb,gtc,gtd) = (0,0,0,0) when stopping the operation of cell 262. In the following explanation, the converter control unit 50a fixing all control signals (gta, gtb, gtc, gtd) to (0,0,0,0) and stopping the operation of all cells 262 of the arm unit 26 of the power converter 20 is referred to as a "gate block," and the state of the cells 262 in this case is referred to as the "gate block state."

[0097] Returning to Figure 6, the converter control unit 50a, similar to the converter control unit 50 in the power converter 1 of the first embodiment, calculates an AC voltage command value including the frequency of the AC system based on the operating state of the power converter 2 and the detected values ​​(current value, direction of current flow (polarity), voltage value) at each position within the power converter 2. For this reason, the converter control unit 50a, similar to the converter control unit 50, acquires the detected values ​​output by detectors (described later) provided at desired positions inside and outside the power converter 2 at predetermined (constant) acquisition cycles TS1. The converter control unit 50a then determines a voltage command value for each arm unit 26, including the voltage component represented by the calculated AC voltage command value. Based on the obtained voltage command value, the converter control unit 50a generates a control signal for switching control of the switching element Q in the cell 262 of each arm unit 26. The converter control unit 50a then outputs the generated control signal to the corresponding cell 262. For example, when the converter control unit 50a controls the arm unit 26-RS, which is the arm unit 26 between the R phase and S phase of the AC system, it calculates an arm voltage command value Varm* corresponding to the arm voltage Varm-R to be output between the AC terminal CA-R and the AC terminal CB-S. In the following explanation, the positive polarity of the arm voltage Varm and the arm voltage command value Varm* is defined as being in the direction in which the potential on the cell 262-1 side is higher when viewed from the cell 262-n side. The converter control unit 50a then generates gate signals gta (gate signal gta-1-RS to gta-n-RS), gtb (gate signal gtb-1-RS to gtb-n-RS), gtc (gate signal gtc-1-RS to gtc-n-RS), and gtd (gate signal gtd-1-RS to gtd-n-RS) for controlling each switching element Q in each cell 262 (cells 262-1-RS to 262-n-RS) of the arm unit 26-RS, based on the calculated arm voltage command value Varm*. The converter control unit 50a outputs each of the generated gate signals gta, gtb, gtc, and gtd to the corresponding cell 262. The same applies when the converter control unit 50a controls other arm units 16.The converter control unit 50a includes, for example, an insert count calculation unit 52a, a sort list calculation unit 54a, a cell selection control unit 56a, and a gate signal generation unit 58a.

[0098] The converter control unit 50a controls the operation of the power converter 20 by having a hardware processor, such as a CPU, execute a program (software). The converter control unit 50a may be implemented by hardware (including circuitry) such as an LSI, ASIC, FPGA, or GPU, or by the cooperation of software and hardware. The converter control unit 50a may also be implemented by a dedicated LSI. The program may be stored in advance in a storage device (a storage device with a non-transient storage medium) such as an HDD or flash memory provided by the converter control unit 50a or the power converter 2, or it may be stored in a removable storage medium (a non-transient storage medium) such as a DVD or CD-ROM, and installed in the HDD or flash memory provided by the converter control unit 50a or the power converter 2 when the storage medium is mounted in a drive device provided by the converter control unit 50a or the power converter 2.

[0099] In the power converter 2, as in the power converter 1 of the first embodiment, current detectors and voltage detectors are provided at desired positions to detect the current value, current polarity, and voltage value. The example in Figure 6 shows a case where a current detector is provided in each leg 22 to detect the arm current I flowing from the AC terminal CA side to the AC terminal CB side. More specifically, in leg 22-RS, a current detector is provided between the reactor 14-RS and the arm unit 26-RS to detect the arm current Irs flowing from the AC terminal CA-R side to the AC terminal CB-S side. The same applies to the other legs 22. Although not shown in Figure 7, each cell 262 is also provided with a voltage detector to detect the capacitor voltage Vc. The AC current Ir of the R phase, the AC current Is of the S phase, and the AC current It of the T phase may be directly detected by providing current detectors at the AC terminals R, S, and T, respectively, but they may also be indirectly detected by calculating the arm current I detected in each leg 22. For example, the AC current Ir of the R phase may be indirectly detected by calculating the difference between the phase arm current Irs between the R phase and the S phase and the phase arm current Itr between the T phase and the R phase (i.e., Irs - Itr). Furthermore, although the voltage detector is not shown in Figure 6, it illustrates a case where the AC voltage Vsr of the R phase, the AC voltage Vss of the S phase, and the AC voltage Vst of the T phase are detected.

[0100] In the power converter 2, the arm unit 26 replaces the arm unit 16 in the power converter 1 of the first embodiment, so that the output control signals (gate signals) correspond to each cell 262 of the arm unit 26. However, the configuration of the converter control unit 50a is the same as the configuration of the converter control unit 50 in the power converter 1 of the first embodiment shown in Figure 3. Therefore, an illustration of an example of the configuration of the converter control unit 50a in the power converter 2 is omitted, and the different operations of each component of the converter control unit 50 in the first embodiment and each component of the converter control unit 50a will be described below.

[0101] The insert count calculation unit 52a performs the same processing as the insert count calculation unit 52 of the first embodiment. The insert count calculation unit 52a calculates the number of inserts Ncells for each arm unit 26 based on the arm voltage command value Varm*. However, unlike the insert count calculation unit 52, the insert count calculation unit 52a calculates the number of inserts Ncells for each arm unit 26, which includes information indicating whether the insert state is a positive voltage insert state or a negative voltage insert state. More specifically, for example, the insert count calculation unit 52a calculates the number of cells 162 of the cells 262 provided by the arm unit 26 that are assigned to the insert state (to be put into the insert state) (integer value, absolute value) and the signed number of inserts Ncells that indicates whether it is a positive voltage insert state or a negative voltage insert state (polarity, sign). The insert count calculation unit 52a also performs single-pulse control or multi-pulse control by calculating the number of inserts Ncells, similar to the insert count calculation unit 52. The insert count calculation unit 52a outputs the calculated insert count Ncells to the cell selection control unit 56a. The insert count calculation unit 52a is an example of the "state count calculation unit" in the claims.

[0102] The sort list calculation unit 54a performs the same processing as the sort list calculation unit 54 of the first embodiment. The sort list calculation unit 54a calculates (generates) a sort list for each arm unit 26 that represents the magnitude relationship of the capacitor voltage Vc of each cell 262 provided in the power converter 20. The sort list calculation unit 54a also generates a sort list at predetermined (constant) calculation cycles TS2 (TS2 > TS1) that are longer than the acquisition cycle TS1. The method of generating the sort list in the sort list calculation unit 54a is the same as that of the sort list calculation unit 54. The sort list calculation unit 54a outputs the generated sort list to the cell selection control unit 56a. The sort list calculation unit 54a is an example of a "list calculation unit" in the claims.

[0103] The cell selection control unit 56a performs the same processing as the cell selection control unit 56 of the first embodiment. At least every time the number of inserts Ncells output by the number of inserts calculation unit 52a changes, that is, every control timing for controlling cell 262 (to a positive voltage insert state, a negative voltage insert state, and a bypass state), the cell selection control unit 56a refers to the sort list and selects the cell 262 to which the current cell control state CL* will be changed.

[0104] When the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a, based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, selects cells 262 equipped with capacitors C that have less stored power from among the currently bypassed cells 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list and selects cells 262 equipped with capacitors C that have relatively low capacitor voltage Vc values ​​in order, and generates a cell control state CL* representing the selected cells 262. The charging polarity corresponds to either (1) the polarity where the arm voltage command value Varm* is such that the potential on the cell 262-1 side is higher than that on the cell 262-n side as shown in Figure 6, and the arm current Iarm flows in the same direction as the arm current I shown in Figure 6, or (2) the polarity where the arm voltage command value Varm* is such that the potential on the cell 262-1 side is lower than that on the cell 262-n side as shown in Figure 6, and the arm current Iarm flows in the opposite direction to the arm current I shown in Figure 6. On the other hand, when the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a, based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, selects a cell 262 equipped with a capacitor C that has a large amount of stored power from among the cells 262 that are currently in the bypass state, as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list and selects cells 262 in order from those having capacitors C with relatively high capacitor voltage Vc values, and generates a cell control state CL* representing the selected cells 262.The discharge polarity corresponds to either (1) the case where the arm voltage command value Varm* is such that the potential on the cell 262-1 side is higher than that on the cell 262-n side as shown in Figure 6, and the arm current Iarm flows in the opposite direction to the arm current I shown in Figure 6, or (2) the case where the arm voltage command value Varm* is such that the potential on the cell 262-1 side is lower than that on the cell 262-n side as shown in Figure 6, and the arm current Iarm flows in the direction of the arm current I shown in Figure 6.

[0105] When the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a, based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, selects cells 262 that are currently in the insert state (positive voltage insert state or negative voltage insert state) and have capacitors C with a large amount of stored power as the cells 262 to be changed to the bypass state, prioritizing the selection of cells 262 that have capacitors C with a large amount of stored power. In this case, the cell selection control unit 56a refers to the sort list and selects cells 262 in order from those with capacitors C with relatively high capacitor voltage Vc values, and generates a cell control state CL* representing the selected cells 262. On the other hand, when the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a, based on the combination of the polarity of the arm voltage command value Varm* and the arm current Iarm, selects cells 262 equipped with capacitors C that have less stored power from among the cells 262 that are currently in the insert state (positive voltage insert state or negative voltage insert state) to be changed to the bypass state. In this case, the cell selection control unit 56a refers to the sort list and selects cells 262 equipped with capacitors C that have relatively low capacitor voltage Vc values ​​in order, and generates a cell control state CL* representing the selected cells 262.

[0106] As a result, cells 262 equipped with capacitors C having a relatively high capacitor voltage Vc are preferentially given shorter charging times and longer discharge times, thus equalizing the capacitor voltage Vc in each cell 262 of the arm unit 26. On the other hand, cells 262 equipped with capacitors C having a relatively low capacitor voltage Vc are preferentially given longer charging times and shorter discharge times, so similarly, the capacitor voltage Vc in each cell 262 of the arm unit 26 is also equalized.

[0107] The cell selection control unit 56a, like the cell selection control unit 56 in the first embodiment, balances the charge levels of the capacitors C in each cell 262 of the arm unit 26 to reduce the difference in charge levels (balance them so that the charge levels are relatively uniform). In the balance control of the cell selection control unit 56a, as with the cell selection control unit 56, the voltage value of the capacitor voltage Vc of the cells 262 belonging to the same arm unit 26 is acquired at each acquisition cycle TS1, that is, at a shorter cycle than the calculation cycle TS2 in which the sort list calculation unit 54 generates the sort list, and the acquired voltage value of each capacitor voltage Vc is compared with the threshold Vc-max and threshold Vc-min. Then, as with the cell selection control unit 56, the cell selection control unit 56a controls the cells 262 whose capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min to a bypass state based on the comparison result, and selects the same number of other cells 162 from among the bypassed cells 162 to change to an insert state (positive voltage insert state or negative voltage insert state). In this case, the cell selection control unit 56a generates cell control states CL* representing cells 262 to be put into a bypass state and cells 262 to be put into an insert state (positive voltage insert state or negative voltage insert state).

[0108] The cell selection control unit 56a outputs a cell control state CL* corresponding to each cell 262 to the gate signal generation unit 58a. The cell selection control unit 56a is an example of the "unit converter selection unit" in the claims. The acquisition period TS1 is an example of the "first time interval" in the claims, and the calculation period TS2 is an example of the "second time interval" in the claims. The threshold Vc-max is an example of the "first threshold" in the claims, and the threshold Vc-min is an example of the "second threshold" in the claims.

[0109] The gate signal generation unit 58a performs the same processing as the gate signal generation unit 58 in the first embodiment. The gate signal generation unit 58a generates control signals (gate signals) to be output to all cells 262 provided in each arm unit 26 according to the respective cell control states CL* output by the cell selection control unit 56a. More specifically, the gate signal generation unit 58a generates combinations of gate signals corresponding to switching elements Q1, Q2, Q3, and Q4 provided in each cell 262 in order to realize the cell control state CL*. At this time, the gate signal generation unit 58a also provides a short dead time to prevent the ends of the capacitor C provided in the cell 262 from being short-circuited. The gate signal generation unit 58a outputs each of the generated gate signals to the corresponding cell 262 (more specifically, the switching element Q provided in the cell 262).

[0110] In the power converter 2, for example, the cell selection control unit 56a may output a cell control state CL* to each cell 262, and each cell 262 may generate a gate signal corresponding to the cell control state CL*. In this case, each cell 262 will be configured to have a component that has a function equivalent to that of the gate signal generation unit 58a.

[0111] With this configuration, the converter control unit 50a controls the cells 262 in each arm unit 26 of the power converter 20, causing the power converter 20 to adjust the reactive power (which may also be active power) of the AC system.

[0112] [Third operation of the power converter] Next, an example of the operation of the power converter 2, that is, the control of cell 262 in the converter control unit 50a, will be described. In the following description, the control of the arm unit 26-RS of leg 22-RS will be described, representing each of the legs 22 of leg 22-RS, leg 22-ST, and leg 22-TR of the power converter 20. In the following description, for the sake of simplicity, the operation of each component of the converter control unit 50a will be described as being performed by the converter control unit 50a itself.

[0113] Figure 8 is a timing chart illustrating an example of the operation timing of the third operation in the power converter 2. The example of operation of the power converter 2 shown in Figure 8 is an example of operation when there are three cells 262 in the arm unit 26-RS (hereinafter simply referred to as "arm unit 26") (n=3). Figure 8 shows an example of balance control of the converter control unit 50a when the capacitor voltage Vc-2 of cell 262-2 in the arm unit 26 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). Similar to the operations in the power converter 1 of the first embodiment, Figure 8 shows the time change of the arm voltage Varm generated by the arm unit 26 based on the arm voltage command value Varm*, the arm current Iarm, and the arm voltage command value Varm* on the same time axis. In Figure 8, instead of the gate signal gtp shown in each operation of the power converter 1, the temporal changes in the cell control states CL*-1 to CL*-3 of cells 262-1 to 262-3, which are modified by the converter control unit 50a, are shown on the same time axis. Figure 8 also shows the schematic change in the capacitor voltage Vc(Vc-2) of cell 262-2, which is balanced by the converter control unit 50a, on the same time axis. In Figure 8, as with each operation of the power converter 1, dead time is omitted for the sake of clarity. Furthermore, Figure 8 shows an example of a sort list calculated (generated) by the converter control unit 50a (more specifically, the sort list calculation unit 54a). In the third operation shown in Figure 8, the sort list is generated (updated) for each cycle of the arm voltage command value Varm*, similar to the first operation of the power converter 1 in the first embodiment shown in Figure 4. Figure 8 also shows an example of the acquisition period TS1 for obtaining the voltage value of the capacitor voltage Vc-2, and the calculation period TS2 for creating the sort list.

[0114] In the power converter 20, the arm voltage command value Varm* includes the frequency of the AC system. The converter control unit 50a (more specifically, the insert number calculation unit 52a) calculates the insert number Ncells, which is represented by a stepped pseudo-sine wave, based on the arm voltage command value Varm*. In Figure 8, the insert number Ncells is an integer value with a minimum value of "-n" (here, "-3") and a maximum value of "n" (here, "3"). The insert number Ncells represents the number of cells 262 that will be in a positive voltage insert state if it is positive (i.e., "0" to "3"), and the number of cells 262 that will be in a negative voltage insert state if it is negative (i.e., "-1" to "-3"). The insert number Ncells is calculated, for example, by approximating the value obtained by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cells 262 belonging to the arm unit 26 to an integer. In other words, the operating timing of the power converter 2 shown in Figure 8 is the same as the first operation in the power converter 1 of the first embodiment, and is the operating timing when the converter control unit 50a performs 1-pulse control. Therefore, the number of inserts Ncells represents the same as the first operation in the power converter 1, and is equivalent to the arm voltage Varm shown in Figure 8.

[0115] The converter control unit 50a (more specifically, the cell selection control unit 56a) generates a cell control state CL* for each cell 262 at each timing when the number of inserts Ncells changes, such that the number of cells 262 belonging to the arm unit 26 that are in an insert state (positive voltage insert state or negative voltage insert state) matches the number of cells 262 that should be in the insert state (positive voltage insert state or negative voltage insert state) represented by the number of inserts Ncells (an integer value). When the arm voltage command value Varm* is positive (Varm*>0), the number of inserts Ncells will be a value of "0" or greater, so the converter control unit 50a generates a cell control state CL* that sets each cell 262 to either a positive voltage insert state or a bypass state. On the other hand, when the arm voltage command value Varm* is negative (Varm*<0), the number of inserts Ncells will be a value of "0" or less, so the converter control unit 50a generates a cell control state CL* that sets each cell 262 to either a negative voltage insert state or a bypass state. Each cell control state CL* represents the following: "1" indicates a positive voltage insert state, "0" indicates a bypass state, and "-1" indicates a negative voltage insert state.

[0116] The converter control unit 50a (more specifically, the gate signal generation unit 58a) generates control signals (gate signals gta, gtb, gtc, and gtd) to be output to all cells 262 in each arm unit 26, according to the cell control state CL* generated by the cell selection control unit 56a. Then, each arm unit 26 outputs an arm voltage Varm when each cell 262 is placed in a positive voltage insert state, bypass state, or negative voltage insert state by the gate signal output by the gate signal generation unit 58a. The arm voltage Varm is approximately the voltage value obtained by multiplying the capacitor voltage Vc by the number of cells 262 that are placed in the insert state (positive voltage insert state or negative voltage insert state) represented by the number of inserts Ncells (an integer value).

[0117] The arm current Iarm includes the frequency of the AC system. In arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is positive (Iarm>0), the capacitor C in cell 262 in the positive voltage insert state is charged, and the capacitor voltage Vc rises during this charging period. In arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is negative (Iarm<0), the capacitor C in cell 262 in the negative voltage insert state is charged, and the capacitor voltage Vc rises during this charging period. In arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), the capacitor C in cell 262 in the positive voltage insert state is discharged, and the capacitor voltage Vc falls during this discharge period. In arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is positive (Iarm>0), the capacitor C in cell 262 in the negative voltage insert state is discharged, and the capacitor voltage Vc decreases during this discharge period. Thus, in arm unit 26, a charging period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are equal, and a discharge period occurs when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are different. In arm unit 26, regardless of the polarity of the arm voltage command value Varm* or the polarity of the arm current Iarm, the capacitor C in cell 262 in the bypass state is neither charged nor discharged, and maintains its current capacitor voltage Vc.

[0118] At time t0 shown in Figure 8, the number of inserts Ncells is "0". The polarity of the arm current Iarm at this time is positive. The converter control unit 50a can arbitrarily decide whether to determine that the number of inserts Ncells and the arm current Iarm are "0" to be charging polarity or discharging polarity. In any case, the converter control unit 50a generates a cell control state CL* which indicates that all cells 262 should be in a bypass state to match the number of inserts Ncells. Here, cell 262-2 is in a bypass state because the cell control state CL*-2 is "0". Therefore, the capacitor C-2 of cell 262-2 is neither charged nor discharged and maintains its current capacitor voltage Vc-2.

[0119] Subsequently, at time t1, when the number of inserts Ncells changes to "1" (its absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive, and the polarity of the arm current Iarm is also positive (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which is currently in the bypass state and has a capacitor C with low stored power, as the cell 262 to be put into the positive voltage insert state. Here, the converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t1, the converter control unit 50a sets the cell control state CL*-3 to "1" in order to put the selected cell 262-3 into the positive voltage insert state. At this time, since cell 262-2 is still in the bypass state, cell 262-2 continues to maintain its current capacitor voltage Vc-2.

[0120] Subsequently, between times t2 and t3, each time the number of inserts Ncells changes sequentially to "2" and "3" (the absolute value increases), the converter control unit 50a, as at time t1, sequentially selects cell 262, which is the second and third lowest capacitor voltage Vc in the sort list (i.e., Vc-2 and Vc-1), and sets the cell control state CL* to "1" in order to put the selected cell 262 into a positive voltage insert state. More specifically, at time t2, the converter control unit 50a selects cell 262-2 and sets the cell control state CL*-2 to "1", and at time t3, it selects cell 262-1 and sets the cell control state CL*-1 to "1". By setting the cell control state CL*-2 to "1" at time t2, the capacitor C-2 of cell 262-2 is charged, and the capacitor voltage Vc-2 rises (increases) as it charges.

[0121] Subsequently, at time t4, when the polarity of the arm current Iarm becomes negative (discharge polarity), cell 262-2, which is in a positive voltage insert state, begins to discharge the power stored in capacitor C-2. As a result, the capacitor voltage Vc-2 decreases as the discharge occurs.

[0122] Subsequently, at time t5, when the number of inserts Ncells changes to "2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive, and the polarity of the arm current Iarm is negative (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which is currently in a positive voltage insert state and has a capacitor C with low stored power, as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t5, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to put the selected cell 262-3 into the bypass state. At this time, since cell 262-2 is still in a positive voltage insert state, it continues to discharge the power stored in capacitor C-2, and the capacitor voltage Vc-2 decreases.

[0123] Subsequently, at time t6, if the capacitor voltage Vc-2 of cell 262-2 exceeds the threshold Vc-min, the converter control unit 50a, in order to bypass cell 262-2, refers to the sort list and selects a cell 262 that is currently in the bypass state and has a large amount of stored power (capacitor C) as the cell 262 to be put into the positive voltage insert state in place of the bypassed cell 262-2. In this case, only cell 262-3 is in the positive voltage insert state. Therefore, the converter control unit 50a selects cell 262-3 from the sort list, which has the lowest capacitor voltage Vc (i.e., Vc-3) but is currently in the bypass state. Then, at time t6, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to bypass cell 262-2. As a result, the discharge from cell 262-2 is stopped, and the discharge from capacitor C-2 of cell 262-2 continues, preventing the capacitor voltage Vc-2 from falling significantly below the threshold Vc-min, as shown by the dashed line in Figure 8. In other words, the capacitor voltage Vc-2 is maintained at a voltage value close to the threshold Vc-min, as shown by the solid line in Figure 8. Furthermore, at time t6, the converter control unit 50a sets the cell control state CL*-3 to "1" in order to put the selected cell 262-3 into a positive voltage insert state. As a result, the capacitor voltage of cell 262-3 is output as a substitute, preventing the arm voltage Varm from deviating (including errors) from the ideal step-shaped waveform according to the arm voltage command value Varm*.

[0124] Subsequently, at time t7, when the number of inserts Ncells changes to "1" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive, and the polarity of the arm current Iarm is negative (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which is currently in a positive voltage insert state and has a capacitor C with low stored power, as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t7, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to put the selected cell 262-3 into the bypass state. At this time, since cell 262-2 is also in the bypass state, the capacitor voltage Vc-2 of cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0125] Subsequently, at time t8, when the number of inserts Ncells changes to "0" (its absolute value decreases), the converter control unit 50a, as at time t5, selects cell 262 from the sort list with the lowest capacitor voltage Vc, and sets the cell control state CL* to "0" to bypass the selected cell 262. Here, since only cell 262-1 is in a positive voltage insert state, the converter control unit 50a selects cell 262-1, which has the highest capacitor voltage Vc in the sort list (i.e., Vc-1), but is currently in a positive voltage insert state. At this time as well, since cell 262-2 is in a bypass state, the capacitor voltage Vc-2 of cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0126] Subsequently, at time t9, when the number of inserts Ncells changes to "-1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative, and the polarity of the arm current Iarm is also negative (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which is currently in the bypass state and has a capacitor C with low stored power, as the cell 262 to be put into the negative voltage insert state. Here, the converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc (i.e., Vc-3) in the sort list. Then, at time t9, the converter control unit 50a sets the cell control state CL*-3 to "-1" in order to put the selected cell 262-3 into the negative voltage insert state. At this time, since cell 262-2 is still in the bypass state, the capacitor voltage Vc-2 of cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0127] Subsequently, between times t10 and t11, each time the number of inserts Ncells changes sequentially to "-2" and "-3" (the absolute value increases), the converter control unit 50a, similar to time t9, sequentially selects cell 262, which is the second and third lowest capacitor voltage Vc in the sort list (i.e., Vc-2 and Vc-1), and sets the cell control state CL* to "-1" in order to put the selected cell 262 into a negative voltage insert state. More specifically, at time t10, the converter control unit 50a selects cell 262-2 and sets the cell control state CL*-2 to "-1", and at time t11, it selects cell 262-1 and sets the cell control state CL*-1 to "-1". By setting the cell control state CL*-2 to "-1" at time t10, the capacitor C-2 of cell 262-2 is charged, and the capacitor voltage Vc-2 rises (increases) as it charges.

[0128] Subsequently, at time t12, the sort list is updated. Also, when the polarity of the arm current Iarm becomes positive (discharge polarity), cell 262-2, which is in a negative voltage insert state, begins to discharge the power stored in capacitor C-2. As a result, the capacitor voltage Vc-2 decreases as the discharge occurs.

[0129] Subsequently, at time t13, when the number of inserts Ncells changes to "-2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative, and the polarity of the arm current Iarm is positive (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which is currently in a negative voltage insert state and has a capacitor C with low stored power, as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects cell 262-1, which has the lowest capacitor voltage Vc (i.e., Vc-1) in the sort list. Then, at time t13, the converter control unit 50a sets the cell control state CL*-1 to "0" in order to put the selected cell 262-1 into the bypass state. At this time, since cell 262-2 is still in a negative voltage insert state, capacitor C-2 continues to discharge, and the capacitor voltage Vc-2 decreases.

[0130] Subsequently, between times t14 and t15, each time the number of inserts Ncells changes sequentially to "-1" and "0" (the absolute value decreases), the converter control unit 50a, as at time t13, sequentially selects cell 262, which is the second and third lowest capacitor voltage Vc in the sort list (i.e., Vc-2 and Vc-3), and sets the cell control state CL* to "0" to bypass the selected cell 262. More specifically, at time t14, the converter control unit 50a selects cell 262-2 and sets the cell control state CL*-2 to "0", and at time t15, it selects cell 262-3 and sets the cell control state CL*-3 to "0". By setting the cell control state CL*-2 to "0" at time t14, cell 262-2 stops discharging from capacitor C-2, and the capacitor voltage Vc-2 is maintained at its current voltage value.

[0131] Thus, at each timing when the number of inserts Ncells changes (the absolute value increases or decreases), the converter control unit 50a determines whether it is discharge polarity or charging polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, and by referring to the sort list, selects a cell 262 to set the control state (cell control state CL*) to positive voltage insert state, bypass state, or negative voltage insert state, and controls the control state of the selected cell 262, i.e., the gate signals gta, gtb, gtc, and gtd. At this time, if the capacitor voltage Vc in any cell 262 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (falls below the threshold Vc-min), the converter control unit 50a performs balance control. In other words, regardless of the timing of the sort list calculation (generation) or the switching control, the converter control unit 50a performs balance control when the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min. In balance control, the converter control unit 50a puts any cell 262 whose capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min into a bypass state. As a result, the bypassed cell 262 stops charging its capacitor C or discharging its capacitor C. The converter control unit 50a then refers to a sort list and selects a replacement cell 262 from among the currently bypassed cells 262 to put into an insert state (positive voltage insert state or negative voltage insert state). This ensures that the capacitor C in the cell 262 is not charged or discharged any further in the power converter 10 (without overcharging or over-discharging), and the charge levels of the capacitor C are balanced to be relatively uniform. In the third operation of the power converter 2 shown in Figure 8, the case where the capacitor voltage Vc-2 of cell 262-2 exceeds the threshold Vc-min at time t6 is shown, but the balance control in the converter control unit 50a is the same for other cells 262.In the third operation of the power converter 2 shown in Figure 8, the case where cell 262-3 is selected as a substitute for cell 262-2 at time t6 is shown, but the same selection applies to other cells 262 as well. In the third operation of the power converter 2 shown in Figure 8, the balance control in the converter control unit 50a is shown when the capacitor voltage Vc-2 of cell 262-2 exceeds the threshold Vc-min, but the balance control when the capacitor voltage Vc of any cell 262 in the arm unit 26 exceeds the threshold Vc-max should also be equivalent to the balance control in the first operation described above.

[0132] [Fourth operation of the power converter] In the third operation described above, we showed the case where the converter control unit 50a performs single-pulse control, but the converter control unit 50a can also perform double-pulse control. Next, as another operation of the power converter 2 (another example of balance control in the converter control unit 50a), we will describe the operation when the converter control unit 50a performs double-pulse control.

[0133] Figure 9 is a timing chart illustrating an example of the operating timing for the fourth operation in the power converter 2. The fourth operation shown in Figure 9, like the third operation shown in Figure 8, is the operation when the arm unit 26 has three cells 262 (n=3). In the fourth operation, the number of inserts Ncells is calculated by comparing the modulated wave based on the arm voltage command value Varm* with the number of triangular wave carriers that are shifted in phase and level from each other, equal to the number of cells 262 belonging to the arm unit 26 (here, "3"), and determining the number of triangular wave carriers where the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular wave carrier. In other words, the fourth operation shown in Figure 9 is the operating timing when the converter control unit 50a performs multi-pulse control. For this reason, the operating timing of the fourth operation shown in Figure 9 is shown by expanding a portion of the range within one period of the arm voltage command value Varm*.

[0134] The fourth operation shown in Figure 9 is an example of balance control performed during a discharge polarity (discharge period) where the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), specifically during the period when the number of cells 262 in a positive voltage insert state, represented by the number of inserts Ncells, is "2" before it changes from "2" to "1". In other words, during the period when the number of cells 262 in a positive voltage insert state remains "2" and does not change. In the fourth operation shown in Figure 9, the sort list calculation unit 54a generates the sort list with a shorter calculation period TS2 than the third operation shown in Figure 8. However, even in the fourth operation shown in Figure 9, the calculation period TS2 is a period with a longer time interval than the acquisition period TS1 (TS2>TS1). Figure 9 shows an example of balance control by the converter control unit 50a when the capacitor voltage Vc-3 of cell 262-3 in the arm unit 26 exceeds the threshold Vc-min (when it falls below the threshold Vc-min).

[0135] At time t0 shown in Figure 9, the number of inserts Ncells is "2". Therefore, the converter control unit 50a refers to the sort list and selects cell 262, which has a capacitor C with a large amount of stored power, as the cell 262 to be put into a positive voltage insert state. More specifically, the converter control unit 50a selects cell 262-1 and cell 262-3, which have the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. Therefore, at time t0 shown in Figure 9, the converter control unit 50a sets cell control states CL*-1 and CL*-3 to "1" in order to put the two selected cells 262 into a positive voltage insert state. As a result, the power stored in capacitor C-3 of cell 262-3 is discharged, and the capacitor voltage Vc-3 decreases as it discharges.

[0136] Subsequently, at time t1, if the capacitor voltage Vc-3 of cell 262-3 exceeds the threshold Vc-min, the converter control unit 50a, in order to put cell 262-3 into a bypass state, refers to the sort list and selects a cell 262 that is currently in a bypass state and has a large amount of stored power (capacitor C) as the cell 262 to be put into a positive voltage insert state in place of the bypassed cell 262-3. In this case, only cell 262-2 is in a bypass state. Therefore, the converter control unit 50a selects cell 262-2, which has the third highest capacitor voltage Vc (i.e., Vc-2) in the sort list but is currently in a bypass state. Then, at time t1, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to put cell 262-3 into a bypass state. As a result, the discharge from cell 262-3 is stopped, and the discharge from capacitor C-3 of cell 262-3 continues, preventing the capacitor voltage Vc-3 from falling significantly below the threshold Vc-min, as shown by the dashed line in Figure 9 (when balance control is performed only in conjunction with the sort list update). In other words, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold Vc-min, as shown by the solid line in Figure 9. Furthermore, at time t1, the converter control unit 50a sets the cell control state CL*-2 to "1" in order to put the selected cell 262-2 into a positive voltage insert state. As a result, the capacitor voltage of cell 262-2 is output as a substitute, and the arm voltage Varm is maintained.

[0137] Subsequently, at time t2, the sort list is updated. Here, it is assumed that the sort list has been updated to include the cell 262-3 with the lowest capacitor voltage Vc, where Vc-3 is the lowest capacitor voltage Vc.

[0138] Subsequently, at time t3, when the number of inserts Ncells changes (decreases) to "1", the converter control unit 50a refers to the sort list and selects cell 262, which is currently in a positive voltage insert state and has a capacitor C with low stored power, as the cell 262 to be put into the bypass state. Here, the converter control unit 50a selects cell 262-2, which has a lower capacitor voltage Vc (i.e., Vc-2) in the sort list, from among cells 262-1 and 262-2, which are in a positive voltage insert state. Then, at time t3, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to put the selected cell 262-2 into the bypass state. At this time, since cell 262-3 is also in the bypass state, the capacitor voltage Vc-3 of cell 262-3 continues to be maintained at a voltage value close to the current threshold Vc-min.

[0139] Thus, in the fourth operation (multiple pulse control), similar to the third operation (single pulse control) shown in Figure 8, the converter control unit 50a determines whether it is discharge polarity or charging polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm at each timing when the number of inserts Ncells changes (the absolute value increases or decreases), refers to the sort list, selects a cell 262 to set the control state (cell control state CL*) to a positive voltage insert state, bypass state, or negative voltage insert state, and controls the control state of the selected cell 262, i.e., the gate signals gta, gtb, gtc, and gtd. At this time, in the fourth operation as well, if the capacitor voltage Vc in any cell 262 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (falls below the threshold Vc-min), the converter control unit 50a performs balance control. In other words, even in the fourth operation, the converter control unit 50a performs balance control when the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, regardless of the timing of the sort list calculation (generation) or the switching control. In the balance control of the fourth operation, the converter control unit 50a also puts cells 262 whose capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min into a bypass state. As a result, even in the fourth operation, cells 262 that are in a bypass state stop charging to or discharging from capacitor C. Then, in the fourth operation, the converter control unit 50a refers to the sort list and selects a cell 262 from among the cells 262 that are currently in a bypass state to replace the bypassed cell 262 and puts it into an insert state (positive voltage insert state or negative voltage insert state). As a result, even in the fourth operation, the power converter 10 can balance the charge amount of capacitor C so that it is relatively uniform, without further charging or discharging of the capacitor C in cell 262 (without overcharging or over-discharging).In the fourth operation of the power converter 2 shown in Figure 9, the case where the capacitor voltage Vc-3 of cell 262-3 exceeds the threshold Vc-min at time t1 is shown, but the balance control in the converter control unit 50a is the same for the other cells 262. In the fourth operation of the power converter 2 shown in Figure 9, the case where cell 262-2 is selected as a substitute for cell 262-3 at time t1 is shown, but the selection as a substitute is the same for the other cells 262. In the fourth operation of the power converter 2 shown in Figure 9, the balance control in the converter control unit 50a is shown when the capacitor voltage Vc-3 of cell 262-3 exceeds the threshold Vc-min, but the balance control when the capacitor voltage Vc of any cell 262 in the arm unit 26 exceeds the threshold Vc-max should also be equivalent to the balance control of the fourth operation described above.

[0140] With this configuration and operation, the power converter 2's converter control unit 50a determines whether each arm unit 26 of the power converter 20 is discharged or charged based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, at each timing when the number of insert cells Ncells of the cell 262 changes (increases or decreases). Then, the power converter 2's converter control unit 50a refers to a sort list calculated (generated) for each arm unit 26 to select a cell 262 to be set to a positive voltage insert state, bypass state, or negative voltage insert state, and changes the control state of the selected cell 262. At this time, if the capacitor voltage Vc in any cell 262 exceeds the threshold Vc-max or threshold Vc-min, the converter control unit 50a puts that cell 262 into a bypass state, refers to the sort list to select an alternative cell 262 from among the currently bypassed cells 262 to be set to an insert state (positive voltage insert state or negative voltage insert state). As a result, the power converter 2 can prevent overcharging or over-discharging of capacitor C in cell 262 where the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, and balance the charge amount of capacitor C so that it is relatively uniform. This reduces the risk of failure of capacitor C and switching element Q in cell 262 of the power converter 20 in the power converter 2. For example, in the event of a grid fault, it reduces the risk that the capacitor voltage Vc will reach an overvoltage or undervoltage, causing the protection device of the power converter 10 to activate and stop operation. As a result, the power converter 2 can be realized as a highly reliable power converter with improved operational continuity performance in the event of a grid fault.

[0141] As described above, in the power converter 2 of the second embodiment, similar to the power converter 1 of the first embodiment, the converter control unit 50a determines whether each arm unit 26 of the power converter 20 is discharge polarity or charge polarity based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, at each timing when the number of inserts Ncells of cells 262 changes (increases or decreases). Then, in the power converter 2 of the second embodiment, the converter control unit 50a refers to a sort list calculated (generated) for each arm unit 26, selects a cell 262 to which the control state should be set to a positive voltage insert state, a bypass state, or a negative voltage insert state, and changes the control state of the selected cell 262. In this case, in the power converter 2 of the second embodiment, if the capacitor voltage Vc in any cell 262 exceeds the threshold Vc-max or threshold Vc-min, the converter control unit 50a puts that cell 262 into a bypass state, and by referring to the sort list, selects an alternative cell 262 from among the currently bypassed cells 262 and puts it into an insert state (positive voltage insert state or negative voltage insert state). As a result, in the power converter 2 of the second embodiment, as in the power converter 1 of the first embodiment, it is possible to prevent overcharging or over-discharging of the capacitor C in the cell 262 in which the capacitor voltage Vc exceeds the threshold Vc-max or threshold Vc-min, and to balance the charge amount of the capacitor C so that it is relatively uniform. As a result, in the power converter 2 of the second embodiment, similar to the power converter 1 of the first embodiment, the risk of failure of the capacitor C and switching element Q in the cell 262 of the power converter 20 can be reduced. For example, in the event of a grid fault, the risk of the capacitor voltage Vc reaching an overvoltage or undervoltage, causing the protection device of the power converter 10 to activate and stop operation, can be reduced. As a result, in the power converter 2 of the second embodiment, a highly reliable power converter with improved operational continuity performance in the event of a grid fault can be realized.

[0142] As described above, in each embodiment of the power converter, the converter control unit, which changes the control state of the unit converters within the arm unit of the power converter, acquires the capacitor voltage of the capacitors in the power converter at predetermined (constant) acquisition cycles TS1. Then, in each embodiment of the power converter, if the capacitor voltage of any unit converter exceeds a threshold (upper threshold Vc-max or lower threshold Vc-min), the converter control unit changes the control state of the unit converter whose capacitor voltage has exceeded the threshold, regardless of the timing of controlling each unit converter, to stop charging the capacitor or discharging the capacitor. In other words, in each embodiment of the power converter, the converter control unit stops charging and discharging the unit converter whose capacitor voltage has exceeded the threshold, and excludes it from the unit converters that output the capacitor voltage in the arm unit. Then, in each embodiment of the power converter, as a replacement for the unit converters whose charging and discharging have been stopped due to the capacitor voltage exceeding the threshold, the control state of the same number of other unit converters that were not outputting the capacitor voltage in the arm unit is changed to start charging and discharging. As a result, in each embodiment of the power converter, the charge levels of the capacitors in the unit converter are balanced to be relatively uniform, and the risk of failure of the capacitors and switching elements in the unit converter is reduced. This reduces the risk that, for example, in the AC system to which the power converter is connected, a system fault occurs and the capacitor voltage reaches an overvoltage or undervoltage, causing the power converter's protection device to activate and stop operation. As a result, in each embodiment of the power converter, a highly reliable power converter is realized with improved operational continuity performance in the event of a system fault.

[0143] In the power conversion devices of the embodiments described above, the insert number calculation unit in the converter control unit calculates the insert number Ncells, which represents the number of cells (integer value) to be put into the insert state, and the cell selection control unit in the converter control unit selects cells to be changed to the insert state or bypass state based on a change in the insert number Ncells. However, the trigger for the cell selection control unit to select cells is not limited to a change in the insert number Ncells. For example, the cell selection control unit may select cells to be changed to the insert state or bypass state based on a change in the number of cells (integer value) to be put into the bypass state, instead of the insert number Ncells representing the number of cells to be put into the insert state. In this case, the operation and processing of the power conversion device and converter control unit should be equivalent to the operation and processing of the power conversion device and converter control unit in the embodiments described above.

[0144] According to at least one embodiment described above, the power converter (10) has at least one arm unit (16) in which a plurality of unit converters (162) are connected in series, each unit converter having an energy storage element (C) for storing power and a plurality of switching elements (Q, D) capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element. The power converter (10) has at least one arm unit (16) in which a plurality of unit converters (162) are connected in series. The power converter (10) has at least one arm unit (16) in which a plurality of unit converters (162) for storing power and a plurality of switching elements (Q, D) capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element. The power converter (10) has at least one arm unit (16) in which a plurality of unit converters (162) for storing power and a plurality of switching elements (Q, D) capable of adjusting the storage of power in the energy storage element or the discharge of power stored in the energy storage element. The unit comprises a list calculation unit (54) that generates list information (sort list) representing the magnitude relationship of terminal voltages based on the terminal voltages of the product element at predetermined second time intervals (TS2) that are longer than the first time interval, and a unit converter selection unit (56) that selects a unit converter to change the current control state based on the polarity of the arm current (Iarm) flowing through the arm unit, the number of states, the list information, and the terminal voltage of the energy storage element, wherein the unit converter selection unit selects a unit converter whose polarity of the arm current is a charging polarity that stores power in the energy storage element of the unit converter in the first control state. In the case of a charging period, when the terminal voltage of the energy storage element of the first unit converter, which is a unit converter in the first control state, detected at the first time interval exceeds a first threshold (Vc-max) that is higher than the rated voltage, the first unit converter is changed to the second control state, and the same number of other unit converters as the first unit converter are selected from among the unit converters in the second control state to be changed to the first control state, and in the case of a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, detected at the first time interval,When the terminal voltage of the energy storage element of the second unit converter, which is a unit converter in the first control state, exceeds a second threshold (Vc-min) lower than the rated voltage, the second unit converter is changed to the second control state. From among the unit converters in the second control state, the same number of other unit converters as the second unit converter are selected to be changed to the first control state. This suppresses the increase in the fluctuation range of the terminal voltage of the energy storage element of the unit converters, thereby realizing a highly reliable power converter.

[0145] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0146] 1,2...Power converter, 10...Power converter, 12,12-R,12-S,12-T...Reg, 14,14-PR,14-NR,14-PS,14-NS,14-PT,14-NT,14-RS,14-ST,14-TR...Reactor, 16,16-PR,16-NR,16-PS,16-NS,16-PT,16-NT...Arm unit, 162,162-1,162-n,16 2-1-PR, 162-nPR, 162-1-NR, 162-nNR, 162-1-PS, 162-nPS, 162-1-NS, 162-nNS, 162-1-PT, 162-nPT, 162-1-NT, 162-nNT... Cell, 20... Power converter, 22, 22-RS, 22-ST, 22-TR... Leg, 26, 26-RS, 26-ST, 26-TR... Arm unit, 262, 262 -1,262-n,262-1-RS,262-n-RS,262-1-ST,262-n-ST,262-1-TR,262-n-TR...Cells, 50,50a...Converter control unit, 52,52a...Insert count calculation unit, 54,54a...Sort list calculation unit, 56,56a...Cell selection control unit, 58,58a...Gate signal generation unit, Q,Q1,Q2,Q3,Q4...Switching elements D, D1, D2, D3, D4...Diode, C...Capacitor, TR...Transformer, R, S, T...AC terminal, P...Positive side terminal, N...Negative side terminal, CA, CA-R, CA-S, CA -T, CB, CB-R, CB-S, CB-T...AC terminal, CP,CP-R,CP-S,CP-T,CN,CN-R,CN-S,CN-T...DC terminal, TP...Positive terminal, TN...Negative terminal

Claims

1. a power converter having at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of power stored in the energy storage element; a converter control unit that controls the power conversion operation of the power converter by switching the control state to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited; Equipped with The converter control unit a state number calculation unit that calculates a state number representing the number of converter units that are assigned to any one of the control states among the converter units belonging to the arm unit according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit; a list calculation unit that generates list information representing a magnitude relationship between the terminal voltages of the energy storage element detected at predetermined first time intervals, for each predetermined second time interval that is longer than the first time interval; a unit converter selection unit that selects the unit converter whose current control state is to be changed based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage between the terminals of the energy storage element; Equipped with The unit converter selection unit In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, changing the first unit converter to the second control state, and selecting, from the unit converters in the second control state, other unit converters, the same number as the first unit converter, as the unit converters to be changed to the first control state; In a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of a second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value that is lower than a rated voltage, the second unit converter is changed to the second control state, and the same number of other unit converters as the second unit converter are selected from the unit converters in the second control state as the unit converters to be changed to the first control state; Power conversion device.

2. The unit converter selection unit When selecting the unit converter to be changed to the first control state from the unit converters in the second control state, During the charging period, the unit converter having the energy storage element included in the list information and having a relatively low inter-terminal voltage is selected preferentially; During the discharge period, the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage is selected preferentially; When selecting the unit converter to be changed to the second control state from the unit converters in the first control state, During the charging period, the unit converter having the energy storage element included in the list information and having a relatively high inter-terminal voltage of the energy storage element is selected preferentially; During the discharge period, the unit converter having the energy storage element included in the list information, the terminal voltage of which is relatively low, is preferentially selected. The power conversion device according to claim 1 .

3. The unit converter selection unit When the number of states changes, selection of the unit converter for changing the control state is started; When the absolute value of the number of states to be assigned to the first control state increases, the unit converter to be changed to the first control state is selected from the unit converters in the second control state; When the absolute value of the number of states to be assigned to the first control state decreases, the unit converter to be changed to the second control state is selected from the unit converters in the first control state. The power conversion device according to claim 1 or 2.

4. the state number calculation unit approximates a value obtained by dividing the arm voltage command value by an average value or a rated value of the inter-terminal voltage of the energy storage element included in the unit converter belonging to the arm unit to an integer, and calculates the resulting value approximated to the integer as the state number to be assigned to the first control state. The power conversion device according to any one of claims 1 to 3.

5. The state number calculation unit a comparison of a modulated wave based on the arm voltage command value with each of triangular wave carriers, the number of which is the same as the number of unit converters belonging to the arm unit and which are phase-shifted from each other, and a calculation of the number of triangular wave carriers for which the value of the modulated wave is greater than the value of the triangular wave carrier as the number of states to be assigned to the first control state; The power conversion device according to any one of claims 1 to 3.

6. The state number calculation unit a comparison of a modulated wave based on the arm voltage command value with each of triangular wave carriers, the number of which is the same as the number of unit converters belonging to the arm unit and whose levels are shifted from each other, and a calculation of the number of triangular wave carriers, the number of which has a modulated wave value greater than the value of the triangular wave carrier, as the number of states to be assigned to the first control state; The power conversion device according to any one of claims 1 to 3.

7. the unit converter is a half-bridge circuit in which a series circuit in which two switching elements, a first switching element and a second switching element, are connected in series and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element is the first end, and a connection point between the second switching element and the energy storage element is the second end, The converter control unit the first switching element is brought into a conductive state and the second switching element is brought into a non-conductive state, thereby bringing the unit converter into the first control state; the first switching element is brought into a non-conductive state and the second switching element is brought into a conductive state, thereby bringing the unit converter into the second control state; The power conversion device according to any one of claims 1 to 6.

8. the unit converter is a full bridge circuit in which a first series circuit in which two switching elements, a first switching element and a second switching element, are connected in series, a second series circuit in which two switching elements, a third switching element and a fourth switching element, are connected in series, and the energy storage element are connected in parallel, the first end being a connection point between the first switching element and the second switching element, and the second end being a connection point between the third switching element and the fourth switching element; The converter control unit by setting the first switching element to a conductive state, the second switching element to a non-conductive state, the third switching element to a non-conductive state, and the fourth switching element to a conductive state, the unit converter is set to a first first control state, which is the first control state in which a positive voltage is output; by setting the first switching element to a non-conductive state, the second switching element to a conductive state, the third switching element to a conductive state, and the fourth switching element to a non-conductive state, the unit converter is set to a second first control state, which is the first control state in which a negative voltage is output; the first switching element is in a conductive state, the second switching element is in a non-conductive state, the third switching element is in a conductive state, and the fourth switching element is in a non-conductive state, or the first switching element is in a non-conductive state, the second switching element is in a conductive state, the third switching element is in a non-conductive state, and the fourth switching element is in a conductive state, thereby putting the unit converter into the second control state; determining the first control state and the second control state according to the polarity of the valve branch voltage represented by the valve branch voltage command value; The power conversion device according to any one of claims 1 to 6.

9. the power converter is a double star-connected modular multilevel converter having a phase unit for each AC phase, in which two arm units, a first arm unit and a second arm unit, are connected in series, a connection point between the first arm unit and the second arm unit belonging to each phase unit is an AC terminal connected to the corresponding AC phase, an inductance element is connected to one end of each of the first arm unit and the second arm unit or at an arbitrary position between each of the unit converters connected in series, and a terminal on the opposite side to the AC terminal in each of the first arm unit and the second arm unit is a DC terminal, The converter control unit distributing an AC voltage command value and a DC voltage command value to the first arm unit and the second arm unit belonging to each of the phase units to obtain the respective arm voltage command values; changing the control state for each of the arm units in accordance with the distributed arm voltage command value; The power conversion device according to any one of claims 1 to 8.

10. the power converter is a single delta-connected modular multilevel converter in which the arm units are connected between AC terminals of AC phases, and inductance elements are connected to one end of each of the arm units or at any position between the unit converters connected in series, The converter control unit Distributing an AC voltage command value to each of the arm units between the AC terminals to obtain each of the arm voltage command values; changing the control state for each of the arm units in accordance with the distributed arm voltage command value; The power conversion device according to any one of claims 1 to 8.

11. a power converter having at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of power stored in the energy storage element; a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited, The computer of the converter control unit calculating a state number representing the number of converter units to be assigned to any one of the control states among the converter units belonging to the arm unit according to an arm voltage command value that is a target value of the voltage to be output from the arm unit; generating list information representing a magnitude relationship between the terminal voltages of the energy storage element detected at predetermined first time intervals, for each predetermined second time interval longer than the first time interval; When selecting the unit converter for changing the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage between the terminals of the energy storage element, In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, changing the first unit converter to the second control state, and selecting, from the unit converters in the second control state, other unit converters, the same number as the first unit converter, as the unit converters to be changed to the first control state; In a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of a second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value that is lower than a rated voltage, the second unit converter is changed to the second control state, and the same number of other unit converters as the second unit converter are selected from the unit converters in the second control state as the unit converters to be changed to the first control state; A method for controlling a power conversion device.

12. a power converter having at least one arm unit in which a plurality of unit converters are connected in series, the unit converter having an energy storage element that stores power and a plurality of switching elements that can adjust the storage of power in the energy storage element or the discharge of power stored in the energy storage element; a converter control unit that controls a power conversion operation of the power converter by switching to at least one of a first control state in which a terminal voltage of the energy storage element is output between a first end and a second end of the unit converter, and a second control state in which the first end and the second end of the unit converter are short-circuited, The computer of the converter control unit calculate a state number representing the number of converter units to be assigned to any one of the control states among the converter units belonging to the arm unit according to an arm voltage command value that is a target value of the voltage to be output from the arm unit; generating list information representing a magnitude relationship between the terminal voltages of the energy storage element detected at predetermined first time intervals, for each predetermined second time interval longer than the first time interval; When selecting the unit converter for changing the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage between the terminals of the energy storage element, In a charging period in which the polarity of the arm current becomes a charging polarity that stores power in the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of a first unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a first threshold value higher than a rated voltage, the first unit converter is changed to the second control state, and other unit converters, the same number as the first unit converter, are selected from the unit converters in the second control state as the unit converters to be changed to the first control state; In a discharge period in which the polarity of the arm current becomes a discharge polarity that discharges power from the energy storage element of the unit converter in the first control state, when the voltage between the terminals of the energy storage element of the second unit converter, which is the unit converter in the first control state and detected at the first time interval, exceeds a second threshold value lower than a rated voltage, the second unit converter is changed to the second control state, and the same number of other unit converters as the second unit converter are selected from the unit converters in the second control state as the unit converters to be changed to the first control state; program.

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