Imaging device and electronic device

Abstract

Provided is an imaging device that has an image processing function and can operate at high speeds. The imaging device has additional functions such as image processing. The imaging device binarizes image data, which is acquired in an imaging operation, in a pixel portion and performs a product-sum operation by using the binarized data. The pixel portion is provided with a storage circuit that holds a weighting factor used for the product-sum operation. This eliminates the need for reading a weighting factor from the outside each time the operation is performed, thereby reducing power consumption. Moreover, circuits such as a pixel circuit, a storage circuit, and a product-sum operation circuit are stacked, thereby shortening a wiring length between the circuits. This enables high-speed operations with low power consumption.

Description

Imaging devices and electronic devices

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, and an operation method thereof or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

[0004] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit including a transistor that includes an oxide semiconductor and has extremely low off-state current.

[0005] Furthermore, Japanese Patent Application Laid-Open No. 2003-144229 discloses a technique for adding a calculation function to an imaging device.

[0006] JP 2011-119711 A JP 2016-123087 A

[0007] The imaging devices installed in mobile devices and the like are generally capable of capturing high-resolution images. In the next generation, imaging devices are expected to be equipped with even more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted to digital data, and after being output externally, image processing is performed as needed. If this processing can be performed within the imaging device, linking with external devices will become faster, improving user convenience. It will also reduce the load and power consumption of peripheral devices.

[0009] Furthermore, when adding functions to an imaging device, it is preferable to stack additional circuits and other elements. For example, by arranging multiple circuits so that they overlap with pixel circuits, it is possible to suppress an increase in area and form a compact imaging device with high functionality. Furthermore, it is possible to shorten the wiring length between stacked circuits, thereby achieving high-speed, low-power operation.

[0010] Therefore, an object of one embodiment of the present invention is to provide an imaging device capable of image processing. Another object is to provide a high-performance and small-sized imaging device. Another object is to provide an imaging device that can operate at high speed. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention relates to an imaging device that has an image processing function and is capable of high-speed operation.

[0013] One embodiment of the present invention is an imaging device including a plurality of pixel blocks, each of which includes a first layer and a second layer. The first layer has an overlapping region with the second layer. The pixel block includes a plurality of pixel circuits and a plurality of first memory circuits in the first layer, and a plurality of product-accumulation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer. The pixel circuits and the first memory circuits each include a transistor having a metal oxide in a channel formation region.

[0014] Another embodiment of the present invention is an imaging device including a plurality of pixel blocks, each of which includes a first layer, a second layer, and a third layer. The first layer is located between the second layer and the third layer, or the third layer is located between the first layer and the second layer. The first layer to the third layer have overlapping regions. The pixel block includes a plurality of pixel circuits in the first layer, a plurality of product-accumulation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and a plurality of first memory circuits in the third layer. The pixel circuits and the first memory circuits each include a transistor having a metal oxide in a channel formation region.

[0015] The product-sum operation circuit, the first binarization circuit, and the second binarization circuit preferably include transistors having silicon in their channel formation regions.

[0016] The number of pixel circuits and the number of first binarization circuits are the same, and each pixel circuit can be electrically connected to one first binarization circuit.

[0017] One first binarization circuit can be electrically connected to a plurality of product-sum calculation circuits.

[0018] One first memory circuit can be electrically connected to a plurality of product-sum calculation circuits.

[0019] The number of product-sum calculation circuits and the number of second binarization circuits are the same, and one product-sum calculation circuit can be electrically connected to one second binarization circuit.

[0020] A driver circuit for the pixel circuit and a driver circuit for the first memory circuit can be provided in the second layer.

[0021] The digital signal processing device may further include a second memory circuit, the input terminal of which is electrically connected to a plurality of second binarization circuits, and the output terminal of which is electrically connected to a plurality of product-sum calculation circuits.

[0022] The digital signal processing device may further include a third storage circuit and a third binarization circuit, and the third storage circuit may be electrically connected to the plurality of product-sum calculation circuits via the third binarization circuit.

[0023] The second memory circuit, the third memory circuit, and the third binarization circuit can be provided in the second layer.

[0024] The metal oxide preferably comprises In, Zn, and M (wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0025] By using one embodiment of the present invention, an imaging device capable of performing image processing can be provided. Alternatively, a highly functional and small imaging device can be provided. Alternatively, an imaging device capable of high-speed operation can be provided. Alternatively, an imaging device with low power consumption can be provided. Alternatively, an imaging device with high reliability can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a driving method of the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

[0026] FIG. 1 is a diagram illustrating an imaging device. FIGS. 2A to 2C are diagrams illustrating a pixel unit. FIG. 3 is a diagram illustrating a pixel block. FIG. 4 is a diagram illustrating a pixel block. FIG. 5 is a diagram illustrating a pixel block. FIG. 6A is a diagram illustrating a product-sum operation circuit. FIG. 6B is a diagram illustrating a binarization circuit. FIG. 7 is a diagram illustrating a pixel block. FIG. 8 is a diagram illustrating a pixel block and a readout circuit. FIG. 9 is a timing chart illustrating the operation of the readout circuit. FIGS. 10A to 10C are diagrams illustrating a pixel circuit. FIG. 11A is a diagram illustrating a memory circuit. FIGS. 11B and 11C are diagrams illustrating memory cells. FIGS. 12A and 12B are diagrams illustrating the layout of a pixel circuit. FIG. 13 is a diagram illustrating the operation of reading data from a pixel block. FIG. 14 is a diagram illustrating the operation of distributing data to pixel blocks. FIG. 15A is a diagram illustrating the operation of reading data from a pixel block. FIG. 15B is a diagram illustrating circuit 25. FIG. 16A is a diagram illustrating the readout circuit. FIG. 16B is a timing chart illustrating the operation of the readout circuit. FIGS. 17A to 17D are diagrams illustrating the configuration of a pixel of an imaging device. FIGS. 18A to 18C are diagrams illustrating the configuration of a photoelectric conversion device. FIG. 19 is a cross-sectional view illustrating a pixel. FIGS. 20A to 20C are diagrams illustrating a Si transistor. FIG. 21 is a cross-sectional view illustrating a pixel. FIG. 22 is a cross-sectional view illustrating a pixel. FIG. 23 is a cross-sectional view illustrating a pixel. FIGS. 24A to 24D are diagrams illustrating an OS transistor. FIG. 25 is a cross-sectional view illustrating a pixel. FIG. 26 is a cross-sectional view illustrating a pixel. FIG. 27 is a cross-sectional view illustrating a pixel. FIGS. 28A to 28C are perspective views (cross-sectional views) illustrating a pixel. FIG. 29A is a diagram illustrating a package that houses an imaging device. FIG. 29B is a diagram illustrating a module that houses an imaging device. FIGS. 30A to 30F are diagrams illustrating electronic devices. FIGS. 31A and 31B are diagrams illustrating moving objects.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0028] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0029] Furthermore, a single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0030] Embodiment 1 In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0031] One embodiment of the present invention is an imaging device having additional functions such as image processing. The imaging device binarizes analog data (image data) acquired during imaging operation in a pixel unit and performs a product-sum operation using the binarized data. The pixel unit is provided with a memory circuit that stores weighting coefficients (also called weighting data or filters) used in the product-sum operation. Therefore, the operation can be performed without having to read the weighting coefficients from an external device each time, thereby reducing power consumption.

[0032] In addition, in an imaging device according to one embodiment of the present invention, a pixel circuit, a memory circuit, or the like, and a product-sum operation circuit or the like are stacked, so that the wiring length between circuits can be shortened, and low power consumption and high-speed operation can be achieved.

[0033] 1 is a perspective view illustrating an imaging device of one embodiment of the present invention. The imaging device includes a layer 10 and a layer 20. The layer 10 can be provided over the layer 20. The imaging device includes a pixel portion 11 in which a pixel circuit, a memory circuit, and the like are provided. The pixel portion 11 includes elements provided in the layer 10 and elements provided in the layer 20.

[0034] Layer 10 may be provided with a pixel circuit and a memory circuit. Layer 20 may be provided with a drive circuit for the circuits in layer 10, an arithmetic circuit for data acquired by the circuits in layer 10, a data conversion circuit, a memory circuit, and the like. For example, layer 20 may be provided with a calculation unit 21, a row driver 31 and a column driver 32 for driving the pixel circuits, a row driver 33 and a column driver 34 for driving the memory circuit, and the like. Layer 20 may also be provided with circuits 35 and 36, etc., having functions such as data selection, retention, conversion, and readout, as necessary.

[0035] The circuits in layer 10 and the circuits in layer 20 can be electrically connected by electrodes or wiring that penetrate layer 10. Note that some of the circuits described above can also be provided in the opposite layer to that described above or outside the imaging device.

[0036] 2A is a diagram illustrating the details of the pixel section 11. The pixel section 11 has a plurality of pixel blocks 12 arranged in a matrix. Furthermore, the pixel blocks 12 have pixel blocks 13 arranged in a 3×3 array. Furthermore, the pixel blocks 13 have 3×3 pixels 14. That is, the pixel blocks 12 have 9×9 pixels 14. Each pixel 14 has a pixel circuit 15 and a memory circuit 16.

[0037] In one embodiment of the present invention, various calculations and the like are performed on the assumption that the pixel block 13 has a configuration of 3×3 pixels 14. However, the number of pixels is not limited to the above, and may be, for example, 2×2, 4×4, 5×5, or 25×25. Alternatively, the number of pixels 14 in the horizontal and vertical directions may be different. Also, some pixel blocks 13 may be shared by adjacent pixel blocks 12. Also, some pixels 14 may be shared by adjacent pixel blocks 13. The number of pixel blocks 13 included in a pixel block 12 may also be changed as appropriate.

[0038] 2A is an example in which the pixel circuit 15 and the memory circuit 16 are provided side by side on the layer 10, but as shown in Fig. 2B, the pixel circuit 15 may be provided overlapping the memory circuit 16. Alternatively, as shown in Fig. 2C, the memory circuit 16 may be provided overlapping the pixel circuit 15.

[0039] 3 is a diagram illustrating the components of a pixel block 13. The pixel block 13 has 3×3 pixels 14. Therefore, the pixel block 13 has nine pixel circuits 15 and nine memory circuits 16 in the layer 10. In addition, in an area (layer 20) overlapping with the pixel circuits 15 or the memory circuits 16, a plurality of binarization circuits 22, a plurality of product-sum operation circuits 23, and a plurality of binarization circuits 24 are provided as an arithmetic unit 21.

[0040] The number of binarization circuits 22 is the same as the number of pixel circuits 15, i.e., nine. The binarization circuits 22 are provided at positions that have overlapping areas with the pixel circuits 15. Fig. 4 is a diagram showing the connection relationship between the pixel circuits 15 and the binarization circuits 22, and one pixel circuit 15 is electrically connected to one binarization circuit 22 that has an overlapping area.

[0041] The binarization circuit 22 is a circuit that judges the image data (analog data) acquired by the pixel circuit 15 using a preset threshold value to binarize the image data, and may be implemented by a comparator, for example.

[0042] A plurality of product-sum calculation circuits 23 are provided in one pixel block 13, and in this embodiment, six product-sum calculation circuits 23 are provided. The number of product-sum calculation circuits 23 can be increased or decreased as appropriate depending on the purpose. The input terminals of the product-sum calculation circuits 23 are electrically connected to the memory circuit 16 and the binarization circuit 22.

[0043] 5 is a diagram showing the connection relationship between the product-sum operation circuit 23, the storage circuit 16, and the binarization circuits 22. In order to clearly show the connection relationship, only nine binarization circuits 22 are shown.

[0044] The pixel block 13 has nine storage circuits 16, each of which has a plurality of memory cells. A 1-bit weighting coefficient can be written in advance to each of the plurality of memory cells. Each of the nine storage circuits 16 is electrically connected to each of the six product-sum calculation circuits 23. Therefore, a 9-bit weighting coefficient can be supplied to each of the product-sum calculation circuits 23. Since weighting coefficients can be supplied from one storage circuit 16 to six product-sum calculation circuits 23, this operation can be performed as long as at least a 1-bit weighting coefficient is written in one storage circuit 16.

[0045] Each of the binarization circuits 22 can output image data converted to 1 bit. Each of the nine binarization circuits 22 is electrically connected to each of the six product-sum calculation circuits 23. Since one binarization circuit 22 can supply image data to the six product-sum calculation circuits 23, each of the product-sum calculation circuits 23 is supplied with 9-bit image data.

[0046] 6A is a diagram briefly illustrating the configuration and operation of the product-sum operation circuit 23. The product-sum operation circuit 23 can be configured to have, for example, nine multipliers 23a and one adder 23b. Each multiplier 23a receives image data (X1 to X9) converted to 1 bit by the binarization circuit 22 and a 1-bit weighting coefficient (W1 to W9) read from the memory circuit 16, performs a multiplication operation, and outputs 1-bit data to the adder 23b. The adder 23b adds the data input from each multiplier 23a and outputs the result to the binarization circuit 24. The data output from the adder 23b (product-sum operation circuit 23) takes values ​​from 0 to 9, resulting in 4-bit data.

[0047] The number of binarization circuits 24 is the same as the number of product-sum calculation circuits 23, i.e., six. As shown in FIGS. 6A, 6B, and 7, one binarization circuit 24 is electrically connected to one product-sum calculation circuit 23. As shown in FIGS. 6A and 6B, data input to the binarization circuit 24 is 4-bit digital data corresponding to 0 to 9. The binarization circuit 24 outputs 1 if it determines that the input data is 5 or greater, and outputs 0 if it determines that the input data is 4 or less. In other words, the binarization circuit 24 is a circuit that has the function of converting 4-bit data into 1 bit.

[0048] As shown in Fig. 7, 6-bit calculation data can be output from one pixel block 13. Fig. 8 is a diagram illustrating reading of calculation data from pixel blocks 12 (pixel blocks 13[1,1] to 13[3,3]).

[0049] Each of the six binarization circuits 24 included in the pixel block 13 has a selection transistor 24S that controls the output. The gates of the six selection transistors 24S are electrically connected to wirings RSEL (wirings RSEL[0], RSEL[1], and RSEL[2]). The wirings RSEL are shared by the pixel blocks 13 arranged in the row direction. In addition, the six output lines OUT (OUT[0] to OUT[5]) to which the six binarization circuits 24 are electrically connected are shared by the pixel blocks 13 arranged in the column direction.

[0050] The six output lines OUT are electrically connected to a readout circuit 40. The readout circuit 40 has switches 40S, 41S, and 42S that are electrically connected to the six output lines OUT of each column, respectively.

[0051] The switches 40S to 42S each include a plurality of transistors. A gate of the transistor included in the switch 40S is electrically connected to the wiring CSEL[0]. A gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL[1]. A gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL[2].

[0052] Every three wirings on the output side of the switches 40S to 42S are electrically connected to one output line OUT. With this configuration, data for each pixel block 13 can be output.

[0053] It should be noted that the readout circuit 40 can be provided in the layer 20 as an element of the circuit 35 or the circuit 36 ​​shown in FIG.

[0054] 9 is a timing chart illustrating the reading of calculation data from the pixel blocks 12 (pixel blocks 13[1,1] to 13[3,3]). Note that all calculations in each pixel block 13 are completed before time T1, and the calculation data is held in the binarization circuit 24. In the following description, a potential (high potential) that makes a transistor conductive is represented as "H," and a potential (low potential) that makes a transistor non-conductive is represented as "L."

[0055] At time T1, when the potential of the wiring RSEL[0] is set to “H”, the selection transistors 24S of all the binarization circuits 24 of the pixel blocks 13 arranged in the 0th row become conductive, and the calculation data is output to the readout circuit 40.

[0056] Furthermore, when the potential of the wiring CSEL[0] is set to "H" at time T1, the switch 40S, whose gate is electrically connected to the wiring CSEL[0], becomes conductive, and the calculation data of the pixel block 13[1,1] is output to the output lines OUT[0] to OUT[5].

[0057] At time T2, when the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H", switch 40S becomes non-conductive, switch 41S, whose gate is electrically connected to wiring CSEL[1], becomes conductive, and calculation data of pixel block 13[1,2] is output to output lines OUT[0] to OUT[5].

[0058] At time T3, when the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H", switch 41S becomes non-conductive, switch 42S, whose gate is electrically connected to wiring CSEL[2], becomes conductive, and calculation data of pixel block 13[1, 3] is output to output lines OUT[0] to OUT[5].

[0059] At time T4, the potential of the wiring RSEL[0] is set to “L” and the potential of the wiring CSEL[2] is set to “L”, and the output of the calculation data of the pixel block 13 in the 0th row (pixel block 13[1,1] to pixel block 13[1,3]) is completed.

[0060] From time T4 to time T7, the potential of wiring RSEL[1] is set to “H” and the same operation as described above is performed to output the calculation data of pixel block 13 in the first row (pixel block 13[2,1] to pixel block 13[2,3]).

[0061] Also, from time T7 to time T10, the potential of wiring RSEL[2] is set to “H” and the same operation as above is performed to output the calculation data of pixel block 13 in the second row (pixel block 13[3,1] to pixel block 13[3,3]).

[0062] Here, if the calculation operation is completed in one clock and the readout operation of one pixel block 13 is performed in one clock, one pixel block 12 can be read out in a total of 10 clocks. Note that by providing the same number of readout circuits 40 as the number of columns of pixel blocks 12, one row of pixel blocks 12 can be read out in parallel.

[0063] Pixel Circuit As shown in FIG. 10A, the pixel circuit 15 can have a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106.

[0064] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one of the source and drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104. The one of the source and drain of the transistor 104 is electrically connected to one of the source and drain of the transistor 105.

[0065] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 111. The gate of the transistor 102 is electrically connected to a wiring 114. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 112. The gate of the transistor 103 is electrically connected to a wiring 115. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 113. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 117. The gate of the transistor 105 is electrically connected to a wiring 116.

[0066] Here, the electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104 is referred to as a node N.

[0067] The wirings 111, 112, and 113 can function as power supply lines. For example, the wiring 111 can function as a low-potential power supply line, and the wirings 112 and 113 can function as high-potential power supply lines. Note that the wirings 112 and 113 may be electrically connected. The wirings 114, 115, and 116 can function as signal lines that control the conduction of each transistor. The wiring 117 can function as a wiring that electrically connects the pixel circuit 15 and the binarization circuit 22.

[0068] A photodiode can be used as the photoelectric conversion device 101. When it is desired to increase the light detection sensitivity at low illuminance, it is preferable to use an avalanche photodiode.

[0069] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 104 can have a function of causing a current to flow in accordance with the potential of the node N. The transistor 105 can have a function of selecting a pixel.

[0070] Note that the connection direction of a pair of electrodes of the photoelectric conversion device 101 may be reversed. In this case, the wiring 111 may function as a high-potential power supply line, and the wirings 112 and 113 may function as low-potential power supply lines.

[0071] The transistors 102 and 103 are preferably OS transistors (OS transistors) that use metal oxide in their channel formation regions. OS transistors have extremely low off-state current. By using OS transistors as the transistors 102 and 103, the period during which charge can be held at the node N can be significantly extended. Furthermore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method.

[0072] On the other hand, it may be desirable for the transistor 104 to have excellent amplification characteristics. Also, it may be preferable to use a transistor with high mobility that can operate at high speed as the transistor 105. Therefore, the transistors 104 and 105 may be transistors that use silicon in their channel formation regions (Si transistors).

[0073] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. Furthermore, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single-crystal silicon).

[0074] As shown in FIG. 10B , a transistor may be provided with a back gate (second gate). By electrically connecting the back gate to the front gate, the on-state current of the transistor can be increased. Furthermore, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the structure in which a transistor is provided with a back gate can also be applied to other circuits described in this specification. Furthermore, a circuit may be configured by mixing transistors with and without a back gate.

[0075] 10C , a transistor 107 and a transistor 108 may be added to the configuration of FIG. 10A . The gate of the transistor 107 is electrically connected to the gate of the transistor 104. The source or the drain of the transistor 107 is electrically connected to the source or the drain of the transistor 108. The other of the source or the drain of the transistor 107 is electrically connected to a wiring 113. The gate of the transistor 108 is electrically connected to a wiring 118. The other of the source or the drain of the transistor 108 is electrically connected to a wiring 119.

[0076] Here, the wiring 118 can function as a signal line that controls the conduction of the transistor 108. The wiring 119 can be electrically connected to the circuit 60. The circuit 60 is an image reading circuit, and for example, a CDS circuit (correlated double sampling circuit) or the like can be used. By using this configuration, image data can be output to the wiring 117 and the wiring 119. The image data output to the wiring 117 is input to the binarization circuit 22, and then a product-sum operation is performed. The image data output to the wiring 119 is read out to the outside via the circuit 60. These operations can be performed in parallel. Alternatively, only the operation (image processing) or only the reading of image data can be performed.

[0077] It should be noted that the circuit 60 can be provided on the layer 20 as an element of the circuit 35 or the circuit 36 ​​shown in FIG.

[0078] 2, the memory circuit 16 is provided in the pixel 14. The memory circuit 16 has a plurality of memory cells, and each memory cell stores 1-bit data corresponding to a weighting coefficient.

[0079] 11A is a diagram showing the connection relationship between a memory cell 150, a row driver 33, and a column driver 34. An OS transistor is preferably used as a transistor constituting the memory cell 150. A plurality of memory cells 150 are provided in layer 10 as a memory circuit 16. The row driver 33 and the column driver 34 are drive circuits for the memory cells 150 and can be provided in layer 20.

[0080] The memory circuit 16 has m (m is an integer greater than or equal to 1) memory cells 150 in each column and n (n is an integer greater than or equal to 1) memory cells 150 in each row, for a total of m×n memory cells 150, which are arranged in a matrix.

[0081] 11B and 11C are diagrams illustrating memory cells 150a and 150b that can be used in memory cell 150. In the following description, the bit lines can be connected to a column driver 34. The word lines can be connected to a row driver 33. The bit lines are also electrically connected to a product-sum operation circuit 23, but this is not shown here.

[0082] For example, a decoder or a shift register can be used for the row driver 33 and the column driver 34. Note that a plurality of row drivers 33 and a plurality of column drivers 34 may be provided.

[0083] 11B shows an example of a circuit configuration of a gain cell type (also called a “2Tr1C type”) memory cell 150a having two transistors and one capacitor. The memory cell 150a has a transistor 273, a transistor 272, and a capacitor 274.

[0084] One of the source or drain of the transistor 273 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 273 is connected to the wiring WBL, the gate of the transistor 273 is connected to the wiring WL, and the back gate of the transistor 273 is connected to the wiring BGL. The other electrode of the capacitor 274 is connected to the wiring RL. One of the source or drain of the transistor 272 is connected to the wiring RBL, the other of the source or drain of the transistor 272 is connected to the wiring SL, and the gate of the transistor 272 is connected to one electrode of the capacitor 274.

[0085] The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor 274. When writing data and while the data is being held, it is preferable to apply a reference potential to the wiring RL.

[0086] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 273. The threshold voltage of the transistor 273 can be increased or decreased by applying any potential to the wiring BGL.

[0087] Data is written by applying a high-level potential to the wiring WL, turning on the transistor 273, and electrically connecting the wiring WBL to one electrode of the capacitor 274. Specifically, when the transistor 273 is turned on, a potential corresponding to information to be recorded is applied to the wiring WBL, and the potential is written to one electrode of the capacitor 274 and the gate of the transistor 272. After that, a low-level potential is applied to the wiring WL, turning off the transistor 273, thereby holding the potential of one electrode of the capacitor 274 and the potential of the gate of the transistor 272.

[0088] Data is read by applying a predetermined potential to the wiring RL and the wiring SL. The current flowing between the source and drain of the transistor 272 and the potential of one of the source and drain of the transistor 273 are determined by the potential of the gate of the transistor 272 and the potential of the other of the source and drain of the transistor 273. Therefore, by reading the potential of the wiring RBL connected to one of the source and drain of the transistor 272, the potential held in one electrode of the capacitor 274 (or the gate of the transistor 272) can be read. In other words, information written in this memory cell can be read from the potential held in one electrode of the capacitor 274 (or the gate of the transistor 272). Alternatively, it can be determined whether or not information is written in this memory cell.

[0089] 11C , the wiring WBL and the wiring RBL may be combined into a single wiring BIL. The memory cell 150b shown in FIG. 11C has a configuration in which the wiring WBL and the wiring RBL of the memory cell 150a are combined into a single wiring BIL, and the other of the source or the drain of the transistor 273 and one of the source or the drain of the transistor 272 are connected to the wiring BIL. In other words, the memory cell 150b is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0090] Note that in the memory cell 150a and the memory cell 150b, an OS transistor is preferably used as the transistor 273. A storage device using an OS transistor as the transistor 273 and using a 2Tr1C memory cell such as the memory cell 150a and the memory cell 150b is called a non-volatile oxide semiconductor random access memory (NOSRAM). Note that the circuit configuration of the memory cell can be changed as appropriate.

[0091] 12A and 12B are examples of a layout (top view) that can be used for a pixel circuit of one embodiment of the present invention. The layout of the pixel circuit shown in FIG. 10B includes a back-gate wiring 170, a metal oxide layer 175, and a source-drain wiring 180. The metal oxide layer 175 is a layer in which a channel formation region of an OS transistor is provided.

[0092] Improving the resolution of an imaging device requires miniaturization of pixel circuits. In the miniaturization process, adjacent structures affect each other, so randomly arranging the structures increases variations in wiring width, etc. Therefore, as shown in Figure 12A, it is preferable to arrange the structures at equal intervals in the horizontal direction (X direction) and vertical direction (Y direction).

[0093] 12B shows a configuration in which gate wiring 185 and wiring 190 electrically connected to gate wiring 185 are added to FIG. 12A. By overlapping the elements in this manner, transistors 102, 103, 104, and 105 shown in FIG. 10B are formed. In addition, a plurality of transistors 109 are formed. Transistor 109 is a dummy transistor that is not involved in circuit operation, but such a configuration can improve the uniformity of wiring width and the like, and can suppress variations in transistor characteristics.

[0094] According to one embodiment of the present invention described in this embodiment, an imaging device which has an image processing function and can operate at high speed can be provided.

[0095] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0096] (Embodiment 2) In this embodiment, an imaging device having a different configuration from that of Embodiment 1 will be described with reference to the drawings. The imaging device described in Embodiment 1 is configured to perform a product-sum operation on image data once and extract the calculated data, but the imaging device described in this embodiment is configured to perform a product-sum operation on image data multiple times and extract the calculated data.

[0097] The basic configuration of the pixel 14 and pixel blocks (pixel block 12, pixel block 13) is the same as that of the first embodiment, and therefore detailed description thereof will be omitted.

[0098] The imaging device has two registers as elements for performing multiply-and-accumulate operations multiple times and extracting the operation data. Fig. 13 is a diagram illustrating the connection between pixel block 12 and register 51, which is one of the two registers (register 51 and register 52). Note that a selection circuit can be provided between pixel block 12 and register 51 to reduce the number of wires.

[0099] The pixel block 12 shown in Fig. 13 is a simplified diagram of the pixel block 12 shown in Fig. 8, and shows that the calculation data output from each pixel block 13 after the first multiply-and-accumulate operation is 6 bits (1 bit x 6). The 6 bits of calculation data output from each pixel block 13 is input to and stored in a register 51. Here, the 6 bits of calculation data output from nine pixel blocks 13 are input to the register 51, so a total of 54 bits of calculation data (6 bits x 9) is stored.

[0100] Next, as shown in Fig. 14, the 54-bit operation data stored in the register 51 is redistributed to each pixel block 13. Each pixel block 13 is provided with six product-sum operation circuits 23 each capable of processing 9-bit data as shown in Fig. 6A, and 9-bit operation data is distributed to each product-sum operation circuit 23. Furthermore, each product-sum operation circuit 23 is supplied with 9-bit weighting coefficients from the nine memory circuits 16 included in the pixel block 13. Therefore, each product-sum operation circuit 23 can perform a second product-sum operation.

[0101] 15A, the 4-bit operation data output by each product-sum operation circuit 23 is input to circuits 25, the number of which is the same as the number of pixel blocks 13. Here, since there are six product-sum operation circuits 23, the operation data input to the circuits 25 is 24 bits (4 bits x 6).

[0102] FIG. 15B is a diagram illustrating the circuit 25. The circuit 25 has an adder circuit 26a and a binarization circuit 26b. Since 4-bit (equivalent to 0 to 9) operation data is input to the adder circuit 26a from each of the six product-sum calculation circuits 23, the output of the adder circuit 26a becomes 6-bit (equivalent to 0 to 54) operation data. The 6-bit data is input to the binarization circuit 26b. The binarization circuit 26b can convert the input data to 1 bit, outputting 1 if the data is 28 or greater and 0 if the data is 27 or less. Note that although the circuit 25 is illustrated within the pixel block 12 in FIG. 15, it may also be provided outside the pixel block 12.

[0103] The 1-bit calculation data output from each circuit 25 (total of 9 bits of data) is input to and stored in the register 52. Here, the 9-bit calculation data can be read out as needed. Note that a selection circuit can be provided between the circuit 25 and the register 52 to reduce the number of wires.

[0104] In this embodiment, an operation of repeating the product-sum operation by further changing the weighting coefficient will be described. After the above operation, the product-sum operation circuit 23 of the pixel block 13 holds 54 bits of operation data redistributed from the register 51, and by changing the weighting coefficient supplied from the memory circuit 16, a product-sum operation can be performed again to obtain different operation data. The operation data is then stored in the register 52 in the same way as the operation data obtained in the previous product-sum operation. Therefore, a total of 18 bits of operation data is stored in the register 52.

[0105] 16A is a diagram illustrating a read circuit 41 connected to the output side of a register 52. Six output lines are provided on the output side of the register 52 so that operation data can be read out in 6-bit increments. The six output lines are electrically connected to a read circuit 41. The read circuit 41 has switches 43S, 44S, and 45S that are electrically connected to the six output lines, respectively.

[0106] The switches 43S to 45S each include a plurality of transistors. A gate of the transistor included in the switch 43S is electrically connected to the wiring CSEL[0]. A gate of the transistor included in the switch 44S is electrically connected to the wiring CSEL[1]. A gate of the transistor included in the switch 45S is electrically connected to the wiring CSEL[2].

[0107] Every three wirings on the output side of the switches 43S to 45S are electrically connected to one output line OUT (OUT[0] to OUT[5]). With this configuration, calculation data can be output every 6 bits.

[0108] The register 51, the register 52 and the read circuit 41 can be provided in the layer 20 as elements of the circuit 35 or the circuit 36 ​​shown in FIG.

[0109] 16B is a timing chart illustrating the reading of the calculation data stored in the register 52. It is assumed that all the calculation data (18 bits) is held in the register 52 before time T1. In the following description, a potential (high potential) that makes a transistor conductive is expressed as "H", and a potential (low potential) that makes a transistor non-conductive is expressed as "L".

[0110] When the potential of the wiring CSEL[0] is set to "H" at time T1, the switch 43S, whose gate is electrically connected to the wiring CSEL[0], becomes conductive, and the first 6-bit calculation data is output to the output lines OUT[0] to OUT[5].

[0111] At time T2, when the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H", switch 43S becomes non-conductive, switch 44S, whose gate is electrically connected to wiring CSEL[1], becomes conductive, and the second 6-bit calculation data, which is different from the first data, is output to output lines OUT[0] to OUT[5].

[0112] At time T3, when the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H", switch 44S becomes non-conductive, switch 45S, whose gate is electrically connected to wiring CSEL[2], becomes conductive, and the third 6-bit calculation data, which is different from the first and second data, is output to output lines OUT[0] to OUT[5].

[0113] Here, it is assumed that the first clock cycle is used to store 54-bit calculation data in register 51, the second clock cycle is used to store the first 9-bit calculation data in register 52, and the third clock cycle is used to store the second 9-bit calculation data in register 52. If the first 6-bit calculation data is read from register 52 in the fourth clock cycle, the second 6-bit calculation data is read in the fifth clock cycle, and the third 6-bit calculation data is read in the sixth clock cycle, all operations can be completed in six clock cycles.

[0114] 16B corresponds to the fourth clock, the period from time T2 to time T3 corresponds to the fifth clock, and the period from time T3 to time T4 corresponds to the sixth clock, then the next 18 bits of calculation data can be read out from time T4 to time T7. Furthermore, the next 18 bits of calculation data can be read out from time T7 to time T10.

[0115] Note that the operation of reading out the calculation data from the pixel block 12 in the first and second embodiments corresponds to the operation of stride 3, and the pooling process is omitted, but the calculation data may be further compressed by performing the pooling process.

[0116] According to one embodiment of the present invention described in this embodiment, an imaging device which has an image processing function and can operate at high speed can be provided.

[0117] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0118] Embodiment 3 In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0119] <Structural Example> FIG. 17A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0120] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 18A. Note that the term "layer" may be replaced with "region" in some cases.

[0121] 18A is a pn junction photodiode, and for example, a p-type semiconductor may be used for the layer 565a and an n-type semiconductor may be used for the layer 565b. Alternatively, an n-type semiconductor may be used for the layer 565a and a p-type semiconductor may be used for the layer 565b.

[0122] The pn junction photodiode can be typically formed using single crystal silicon. Photodiodes using single crystal silicon as a photoelectric conversion layer have a relatively wide spectral sensitivity characteristic, from ultraviolet light to near-infrared light, and can detect light of various wavelengths when combined with an optical conversion layer, which will be described later.

[0123] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode, such as a gallium-arsenic-phosphorus compound (GaAsP), a gallium-phosphorus compound (GaP), an indium-gallium-arsenic compound (InGaAs), a lead-sulfur compound (PbS), a lead-selenium compound (PbSe), an indium-arsenic compound (InAs), an indium-antimony compound (InSb), or a mercury-cadmium-tellurium compound (HgCdTe).

[0124] The compound semiconductor is preferably a compound semiconductor having a Group 13 element (aluminum, gallium, indium, etc.) and a Group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also called a Group 3-5 compound semiconductor), or a compound semiconductor having a Group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a Group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (also called a Group 2-6 compound semiconductor).

[0125] Compound semiconductors can change their band gap depending on the combination of constituent elements and their atomic ratio, making it possible to form photodiodes that are sensitive to a wide range of wavelengths, from ultraviolet light to infrared light.

[0126] The wavelength of ultraviolet light can generally be defined as being around 0.01 μm to around 0.38 μm, the wavelength of visible light as being around 0.38 μm to around 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to around 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to around 4 μm, and the wavelength of far-infrared light as being around 4 μm to around 1000 μm.

[0127] For example, to form a photodiode having photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode having photosensitivity from ultraviolet light to near-infrared light, silicon or GaAsP or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode having photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode having photosensitivity from near-infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. Furthermore, to form a photodiode having photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0128] The photodiode using the compound semiconductor may have a pin junction instead of a pn junction. The pn junction and pin junction are not limited to a homojunction structure, and may have a heterojunction structure.

[0129] For example, in a heterojunction, a first compound semiconductor can be used in one layer of a pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the other layer. Alternatively, a first compound semiconductor can be used in one or two layers of a pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the remaining layers. Note that either the first compound semiconductor or the second compound semiconductor can be a simple semiconductor such as silicon.

[0130] Note that the photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this structure, an imaging device having two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light, can be formed.

[0131] 18B, the photoelectric conversion device 101 included in the layer 561 may be a stack of layers 566a, 566b, 566c, and 566d. The photoelectric conversion device 101 shown in FIG. 18B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0132] The layer 566a is preferably a low-resistance metal layer, etc. For example, aluminum, titanium, tungsten, tantalum, silver, or a laminate of these may be used.

[0133] The layer 566d is preferably a conductive layer that has a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0134] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable that the layer 566b is made of a selenium-based material, which is a p-type semiconductor, and the layer 566c is made of an n-type semiconductor such as gallium oxide.

[0135] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In these photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production, such as the ability to fabricate thin-film photoelectric conversion layers. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering.

[0136] As the selenium-based material, crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. In addition, a compound of copper, indium, and selenium (CIS) or a compound of copper, indium, gallium, and selenium (CIGS) can also be used. These have photosensitivity from ultraviolet light to near-infrared light.

[0137] The n-type semiconductor is preferably formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer and can reduce dark current.

[0138] 18C , the photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e. The photoelectric conversion device 101 shown in FIG. 18C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0139] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0140] For example, molybdenum oxide can be used as the hole transport layer. For example, C ６０ , C ７０ or derivatives thereof can be used.

[0141] The photoelectric conversion layer can be a mixed layer (bulk heterojunction structure) of n-type organic semiconductor and p-type organic semiconductor. There are various types of organic semiconductors, and a material that has photosensitivity to the target wavelength can be selected for the photoelectric conversion layer.

[0142] 17A , for example, a silicon substrate can be used. The silicon substrate includes Si transistors and the like. The Si transistors can be used to form pixel circuits, as well as circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like. Furthermore, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may also be formed. In this embodiment, the above circuits excluding the pixel circuits are referred to as functional circuits.

[0143] For example, some or all of the transistors included in the functional circuits (such as the calculation unit 21, row driver 31, column driver 32, row driver 33, column driver 34, circuit 35, and circuit 36) provided in layer 20 described in embodiment 1 can be provided in layer 563.

[0144] Furthermore, the layer 563 may be a stack of multiple layers as shown in FIG. 17B. Although FIG. 17B illustrates three layers, ie, layers 563a, 563b, and 563c, the layer 563 may be a stack of two layers. Alternatively, the layer 563 may be a stack of four or more layers. These layers can be stacked using, for example, a bonding process. With this configuration, the pixel circuits and functional circuits can be distributed across multiple layers and can be stacked on top of each other, thereby enabling the manufacture of a small, highly functional imaging device.

[0145] Alternatively, the pixel may have a stacked structure of layers 561, 562, and 563 as shown in FIG. 17C.

[0146] The layer 562 corresponds to the layer 10 described in Embodiment 1 and can include an OS transistor. One or more of the above-described functional circuits may be formed using an OS transistor. Alternatively, one or more of the functional circuits may be formed using a Si transistor included in the layer 563 and an OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a supporting substrate such as a glass substrate, and a pixel circuit and a functional circuit may be formed using the OS transistor included in the layer 562.

[0147] For example, a normally-off CPU (also referred to as a "NoffCPU (registered trademark)") can be realized using an OS transistor and a Si transistor. Note that a NoffCPU is an integrated circuit including a normally-off transistor that is off (also referred to as off) even when a gate voltage is 0 V.

[0148] The NoffCPU can stop the power supply to circuits within the NoffCPU that are not required to operate, putting those circuits into a standby state. Circuits that have had their power supply stopped and are now in a standby state do not consume power. Therefore, the NoffCPU can minimize power consumption. Furthermore, the NoffCPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from a standby state, it is sufficient to simply resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, high-speed return from a standby state is possible. In this way, the NoffCPU can reduce power consumption without significantly reducing operating speed.

[0149] Furthermore, the layer 562 may be a laminate of multiple layers as shown in Fig. 17D. While Fig. 17D illustrates two layers, layers 562a and 562b, the layer 562 may be a laminate of three or more layers. These layers may be formed, for example, by stacking them on the layer 563. Alternatively, the layer 562 may be formed by bonding a layer formed on the layer 563 to a layer formed on the layer 561.

[0150] As a semiconductor material for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors in which reliability is important. Furthermore, CAC-OS exhibits high mobility and is therefore suitable for transistors that operate at high speed.

[0151] Because of the large energy gap of the semiconductor layer, OS transistors exhibit extremely low off-state current of several yA / μm (current value per μm of channel width). Furthermore, OS transistors have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short-channel effects, and can form highly reliable circuits with high breakdown voltage. Furthermore, OS transistors are less susceptible to variations in electrical characteristics due to non-uniformity in crystallinity, which is a problem in Si transistors.

[0152] A semiconductor layer included in an OS transistor can be, for example, a film represented by an In-M-Zn-based oxide containing indium, zinc, and M (one or more metals selected from aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

[0153] The atomic ratio of the metal elements in a sputtering target used to form an In-M-Zn-based oxide by a sputtering method preferably satisfies In≧M and Zn≧M. Preferred atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratios of the semiconductor layer to be formed each include a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target.

[0154] For the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 １７ / cm ３ Below 1 × 10, preferably １５ / cm ３ More preferably, 1×10 １３ / cm ３ or less, more preferably 1 × 10 １１ / cm ３ More preferably, 1×10 １０ / cm ３ is less than 1×10 −９ / cm ３ An oxide semiconductor having a carrier density above or equal to this can be used. Such an oxide semiconductor is called a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and stable characteristics.

[0155] Note that the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0156] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0157] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0158] Furthermore, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons serving as carriers are generated, increasing the carrier density and making the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 １８ atoms / cm ３ It is preferable to do the following:

[0159] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0160] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0161] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is set to 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0162] The semiconductor layer may have, for example, a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, an amorphous structure has the highest density of defect states, and a CAAC-OS has the lowest density of defect states.

[0163] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0164] The semiconductor layer may be a mixed film including two or more of an amorphous region, a microcrystalline region, a polycrystalline region, a CAAC-OS region, and a single-crystal region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above-described regions.

[0165] The structure of a cloud-aligned composite (CAC)-OS, which is one mode of a non-single-crystal semiconductor layer, will be described below.

[0166] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0167] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0168] For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter, InO Ｘ１ (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter referred to as In Ｘ２ Zn Ｙ２ O Ｚ２ (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter, GaO Ｘ３ (X3 is a real number greater than 0).) or gallium zinc oxide (hereinafter referred to as GaＸ４ Zn Ｙ４ O Ｚ４ (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic structure, and the mosaic structure of InO Ｘ１ , or In Ｘ２ Zn Ｙ２ O Ｚ２ However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0169] That is, CAC-OS is Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ In this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, the first region is said to have a higher In concentration than the second region.

[0170] IGZO is a common name and may refer to a compound of In, Ga, Zn, and O. A typical example is InGaO ３ (ZnO) ｍ１ (m1 is a natural number), or In （１＋ｘ０） Ga （１−ｘ０） O ３ (ZnO) ｍ０ (-1≦x0≦1, m0 is an arbitrary number).

[0171] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the a-b plane.

[0172] On the other hand, CAC-OS refers to a material structure of an oxide semiconductor. CAC-OS refers to a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0173] Note that the CAC-OS does not include a stacked structure of two or more films with different compositions, for example, a two-layer structure including a film containing In as the main component and a film containing Ga as the main component.

[0174] In addition, GaO Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0175] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0176] The CAC-OS can be formed by sputtering, for example, under the condition that the substrate is not intentionally heated. When the CAC-OS is formed by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0177] CAC-OS has a characteristic that no clear peak is observed when measured using θ / 2θ scanning by an out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, the X-ray diffraction measurement reveals that the orientation of the measurement region in the a-b plane direction and the c-axis direction is not observed.

[0178] In addition, in an electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also referred to as a nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0179] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX) revealed that GaO Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0180] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of an IGZO compound. Ｘ３ and In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0181] Here, In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The region where is the main component is GaO Ｘ３This region has higher conductivity than the region where the main component is In. Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited. Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ When the region containing the main component is distributed in a cloud-like shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0182] On the other hand, GaO Ｘ３ The region where the main components are In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ This region has higher insulating properties than the region where GaO is the main component. Ｘ３ When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0183] Therefore, when CAC-OS is used in a semiconductor device, GaO Ｘ３ Insulation caused by Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The conductivity due to the high on-state current (I ｏｎ ), and high field-effect mobility (μ) can be achieved.

[0184] Furthermore, semiconductor elements using the CAC-OS have high reliability, making the CAC-OS suitable as a component material for various semiconductor devices.

[0185] <Layer Structure 1> Next, the layer structure of the imaging device will be described using cross-sectional views. Note that the elements such as the insulating layer and conductive layer shown below are examples, and other elements may be included. Alternatively, some of the elements shown below may be omitted. Furthermore, the layer structure shown below can be formed using a bonding process, a polishing process, or the like, as necessary.

[0186] FIG. 19 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563, and having a bonding surface between layers 563a and 563b that constitute the layer 563.

[0187] <Layer 563b> The layer 563b can have a functional circuit provided over the silicon substrate 611. Here, the transistors 223, 224, and 225 are shown as some of the transistors included in the functional circuit. Note that the transistor 225 is shown as an example of a transistor included in the binarization circuit 22.

[0188] The layer 563b includes a silicon substrate 611 and insulating layers 612, 613, 614, 616, 617, and 618. The insulating layer 612 functions as a protective film. The insulating layers 613, 614, 616, and 617 function as interlayer insulating films and planarizing films. The insulating layer 618 and the conductive layer 619 function as bonding layers. The conductive layer 619 is electrically connected to the gate of the transistor 225.

[0189] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The lamination layer will be described later.

[0190] Conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may also be made of multiple layers composed of different materials.

[0191] <Layer 563a> The layer 563a includes elements of the pixel 14. It may also include elements of a functional circuit. Here, the transistor 102 and the transistor 105 included in the pixel circuit 15 are shown as some of the elements of the pixel 14. In the cross-sectional view of FIG. 19 , electrical connection between the two is not shown.

[0192] The layer 563a is provided with a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, and 638. Also, conductive layers 636 and 639 are provided.

[0193] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as interlayer insulating films and planarizing films. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 from the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. Alternatively, the insulating layer 638 may be formed of the same material as the insulating layer 631.

[0194] The conductive layer 639 is electrically connected to the other of the source and the drain of the transistor 105 and the conductive layer 619. The conductive layer 636 is electrically connected to the wiring 111 (see FIG. 10A).

[0195] The Si transistor shown in Fig. 19 is a fin type having a channel formation region in a silicon substrate (silicon substrates 611 and 632). A cross section in the channel width direction (a cross section taken along A1-A2 shown in layer 563a in Fig. 19) is shown in Fig. 20A. The Si transistor may also be a planar type, as shown in Fig. 20B.

[0196] 20C, the transistor may have a silicon thin film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0197] <Layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Figure 19 shows a configuration in which the organic photoconductive film shown in Figure 18C is used as the photoelectric conversion layer for the photoelectric conversion device 101. Note that here, the layer 567a is the cathode, and the layer 567e is the anode.

[0198] The layer 561 is provided with insulating layers 651 , 652 , 653 , 654 and a conductive layer 655 .

[0199] The insulating layers 651, 653, and 654 function as interlayer insulating films and planarizing films. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101 and also functions to prevent short-circuiting between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0200] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0201] <Layer 560> The layer 560 is formed on the layer 561. The layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0202] The light-shielding layer 671 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. The metal layer may also be stacked with a dielectric film that functions as an anti-reflection film.

[0203] When the photoelectric conversion device 101 is sensitive to visible light, a color filter can be used in the optical conversion layer 672. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters for each pixel. For example, as shown in the perspective view (including cross section) of FIG. 28A , a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to each pixel.

[0204] Furthermore, in a suitable combination of the photoelectric conversion device 101 and the optical conversion layer 672, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0205] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths shorter than visible light in the optical conversion layer 672. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light with wavelengths shorter than near-infrared light in the optical conversion layer 672. Alternatively, an ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths longer than visible light in the optical conversion layer 672.

[0206] It is also possible to arrange multiple different optical conversion layers within a single imaging device. For example, as shown in Figure 28B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. With this configuration, visible light images and infrared light images can be acquired simultaneously.

[0207] 28C , color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels, respectively. In this configuration, visible light images and ultraviolet light images can be acquired simultaneously.

[0208] Furthermore, if a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Image data is then obtained by detecting this light with the photoelectric conversion device 101. An imaging device having this configuration may also be used for a radiation detector or the like.

[0209] A scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, Gd ２ O ２ S: Tb, Gd ２ O ２ S: Pr, Gd ２ O ２ S: Eu, BaFCl: Eu, NaI, CsI, CaF ２ , BaF ２ , CeF ３ , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0210] Imaging using infrared or ultraviolet light can provide the imaging device with inspection functions, security functions, sensor functions, etc. For example, imaging using infrared light can be used for non-destructive testing of produce, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical testing, etc. Furthermore, imaging using ultraviolet light can detect ultraviolet light emitted from a light source or flame, allowing for management of light sources, heat sources, production equipment, etc.

[0211] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, thereby enabling efficient photoelectric conversion. The microlens array 673 is preferably formed from a resin or glass that is highly translucent to light of the target wavelength.

[0212] <Bonding> Next, bonding of the layer 563b and the layer 563a will be described.

[0213] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are planarized so that they are at the same height.

[0214] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are planarized so that they are at the same height.

[0215] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component, and the insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0216] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the conductive layers 619 and 639. Cu, Al, W, or Au is preferably used because of ease of bonding. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers 618 and 631.

[0217] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded together at the boundary between them.

[0218] The conductive layers 619 and 639 may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0219] This bonding can provide electrical connection between the conductive layer 619 and the conductive layer 639. Furthermore, the insulating layer 618 and the insulating layer 631 can be connected to each other with sufficient mechanical strength.

[0220] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0221] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0222] When the layer 563b and the layer 563a are bonded to each other, an insulating layer and a metal layer are mixed on the bonding surfaces, and therefore, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0223] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0224] By the above-described bonding, the circuit included in the layer 563b can be electrically connected to the elements of the pixel 14 included in the layer 563a.

[0225] <Modification of stacked structure 1> Figure 21 is a modification of the stacked structure shown in Figure 19, in which the configuration of the photoelectric conversion device 101 in layer 561 and a portion of the configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0226] The layer 561 includes the photoelectric conversion device 101 , insulating layers 661 , 662 , 664 , 665 and conductive layers 685 , 686 .

[0227] The photoelectric conversion device 101 is a pn junction photodiode and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example is shown in which a pn junction photodiode is formed on a silicon substrate. The photoelectric conversion device 101 is a buried photodiode, and a thin p-type region (part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a can suppress dark current and reduce noise.

[0228] The insulating layer 661 and the conductive layers 685 and 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer.

[0229] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing into adjacent pixels. The insulating layer 665 also has the function of suppressing the intrusion of stray light. Therefore, the insulating layer 665 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0230] The insulating layer 664 can be formed by a local oxidation of silicon (LOCOS) method. Alternatively, it may be formed by a shallow trench isolation (STI) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or acrylic resin can be used as the insulating layer 665. The insulating layer 665 may have a multilayer structure. A space may be provided in part of the insulating layer 665. The space may contain a gas such as air or an inert gas. The space may be under reduced pressure.

[0231] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions buried in the insulating layer 661. The surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that they are at the same height.

[0232] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0233] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have regions buried in the insulating layer 638. The surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0234] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the above-described conductive layers 619 and 639. The insulating layers 638 and 661 are the same bonding layers as the above-described insulating layers 618 and 631.

[0235] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to either the source or the drain of the transistor 102. Furthermore, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 111 (see FIG. 10A ). Furthermore, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 563a.

[0236] 22 shows a modified example different from the above, in which the transistor 102 is provided in the layer 561. In this configuration, one of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node N. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an imaging device with low noise can be obtained.

[0237] The other of the source and the drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. The gate of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0238] 23 is an example of a cross-sectional view of a stack including layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Note that the structures of the layers 563, 561, and 560 are the same as those shown in FIG. 19 , and therefore will not be described here.

[0239] <Layer 562> The layer 562 is formed over the layer 563. The layer 562 includes an OS transistor. Here, the transistor 102 and the transistor 105 are shown. Electrical connection between the two is not illustrated in the cross-sectional view of FIG. 23 .

[0240] The layer 562 includes insulating layers 621, 622, 623, 624, 625, 626, and 628. A conductive layer 627 is also provided. The conductive layer 627 can be electrically connected to the wiring 111 (see FIG. 10A).

[0241] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as interlayer insulating films and planarizing films. The insulating layer 624 functions as a protective film.

[0242] The blocking layer is preferably a film that has a function of preventing hydrogen diffusion. In Si devices, hydrogen is required to terminate dangling bonds. However, hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, a hydrogen blocking film is preferably provided between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0243] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0244] The other of the source and the drain of the transistor 105 is electrically connected to the gate of the transistor 225 through a plug. The conductive layer 627 is electrically connected to the wiring 111 (see FIG. 10A).

[0245] One of the source and the drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.

[0246] 24A shows the details of an OS transistor. The OS transistor shown in FIG. 24A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0247] The OS transistor can have a structure including a channel formation region 708, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0248] As shown in FIG. 24B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0249] Alternatively, as shown in FIG. 24C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0250] Although the OS transistor has a back gate 735, it may not necessarily have a back gate. The back gate 735 may be electrically connected to the front gate of a transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in FIG. 24D . Note that FIG. 24D illustrates the cross section of the transistor taken along line B1-B2 in FIG. 24A as an example, but the same applies to transistors with other structures. Furthermore, a fixed potential different from that of the front gate may be supplied to the back gate 735.

[0251] <Modification of stack structure 2> Figure 25 is a modification of the stack structure shown in Figure 23, in which the configuration of the photoelectric conversion device 101 in layer 561 and a portion of the configuration of layer 562 are different, and a bonding surface is provided between layer 561 and layer 562.

[0252] The photoelectric conversion device 101 included in the layer 561 is a pn junction photodiode, and has the same configuration as that shown in FIG.

[0253] In the layer 562, an insulating layer 648 is formed over the insulating layer 628. In addition, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0254] The insulating layer 648 and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 688 and 689 are flattened so that they are at the same height.

[0255] Here, the conductive layers 688 and 689 are the same bonding layer as the above-described conductive layers 619 and 639. The insulating layer 648 is the same bonding layer as the above-described insulating layers 618 and 631.

[0256] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to either the source or the drain of the transistor 102. Furthermore, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 111 (see FIG. 10A ). Furthermore, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 and the layer 562.

[0257] When stacking multiple Si devices, polishing and bonding processes are required multiple times. This poses problems such as a large number of steps, the need for dedicated equipment, low yield, and high manufacturing costs. However, because OS transistors can be stacked on a semiconductor substrate on which devices are already formed, the bonding process can be eliminated.

[0258] Note that the structure in which the transistor 102 is provided in the layer 561 shown in FIG. 22 may be applied to this structure.

[0259] 26 shows a configuration in which the transistors 102 and 105, etc., which are elements of the pixel circuit, and the transistor 273, etc., which are elements of the memory cell 150, are provided on the same surface of the layer 562.

[0260] 27 shows a stacked structure in which transistors 102, 104, 105, etc., which are elements of the pixel circuit, overlap with transistors 272, 273, etc., which are elements of the memory cell 150, in the layer 562. This structure reduces the circuit area, enabling the formation of a highly functional, compact imaging device. Furthermore, the length of the wiring electrically connecting the stacked elements can be shortened, enabling high-speed operation with low power consumption.

[0261] 22 in which the transistor 102 is provided in the layer 561 may be applied to the structures shown in Fig. 26 and Fig. 27. Also, the structure of the photoelectric conversion device 101 shown in Fig. 23 may be applied.

[0262] 29A is a perspective view of the appearance of a package containing an image sensor chip. The package is a CSP (Chip Size Package), and includes an image sensor bare chip 450, a cover glass 440, and adhesive 430 for bonding the two together.

[0263] Electrode pads 425 provided outside the pixel array 455 are electrically connected to the rear surface electrodes 415 via through electrodes 420. The electrode pads 425 are electrically connected to the circuits constituting the image sensor by wiring or wires. Note that the bare chip 450 may be a laminated chip in which circuits having various functions are laminated.

[0264] 29 illustrates a BGA (Ball Grid Array) in which bumps 410 are formed with solder balls on rear surface electrodes 415. The configuration is not limited to a BGA, and may be an LGA (Land Grid Array) or a PGA (Pin Grid Array). Alternatively, a package in which bare chip 450 is mounted on a QFN (Quad Flat No-Lead Package) or a QFP (Quad Flat Package) may be used.

[0265] 29B is a perspective view of the top surface of a camera module that combines an image sensor chip and a lens. The camera module includes a lens cover 460 and multiple lenses 470 in addition to the configuration of FIG. 29A. An optical filter 480 that absorbs light of a specific wavelength is provided between the lens 470 and the cover glass 440 as needed. For example, in the case of an image sensor that primarily captures visible light, an infrared cut filter or the like can be used as the optical filter 480.

[0266] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0267] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0268] (Embodiment 4) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable ones, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio player, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS.

[0269] 30A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the mobile phone.

[0270] 30B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0271] 30C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling imaging of the entire periphery. The imaging device and its operation method according to one embodiment of the present invention can be applied to elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0272] 30D shows a drive recorder including a frame 941, a camera 942, an operation button 943, and an attachment part 944. By installing the drive recorder on the front window of a vehicle or the like via the attachment part 944, the view ahead while the vehicle is traveling can be recorded. Note that a display panel that displays recorded images is provided on the back surface (not shown). The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to the camera 942.

[0273] 30E illustrates a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the digital camera.

[0274] 30F shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0275] 31A illustrates a drone, which is an example of a moving object, including a frame 921, an arm 922, a rotor 923, blades 924, a camera 925, a battery 926, and the like, and has a function of autonomously flying, a function of remaining stationary in the air, etc. The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to the camera 925.

[0276] FIG. 31B illustrates an external view of an automobile as an example of a moving object. The automobile 890 includes multiple cameras 891 and can acquire information about the front, rear, left, right, and upper sides of the automobile 890. The imaging device and its operation method according to one embodiment of the present invention can be applied to the camera 891. The automobile 890 also includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The automobile 890 analyzes images acquired by the cameras 891 in multiple imaging directions 892, determines surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. The automobile 890 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0277] In an imaging device according to one embodiment of the present invention, the obtained image data is subjected to arithmetic processing such as a neural network, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0278] In the above description, the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, etc. Furthermore, the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), etc., and a system using artificial intelligence can be provided by applying a computer according to one embodiment of the present invention to these moving objects.

[0279] 10: Layer, 11: Pixel section, 12: Pixel block, 13: Pixel block, 14: Pixel, 15: Pixel circuit, 16: Memory circuit, 20: Layer, 21: Calculation section, 22: Binarization circuit, 23: Product-sum calculation circuit, 23a: Multiplier, 23b: Adder, 24: Binarization circuit, 24S: Selection transistor, 25: Circuit, 26a: Adder circuit, 26b: Binarization circuit, 31: Row driver, 32: Column driver, 33: Row driver, 34: Column driver, 35: Circuit, 36: Circuit, 40: Circuit, 40S: Switch, 41: Circuit, 41S: Switch, 42S: Switch, 43S: Switch, 44S: Switch, 45S: Switch, 51: Register, 52 : Register, 60: Circuit, 101: Photoelectric conversion device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Transistor, 108: Transistor, 109: Transistor, 111: Wiring, 112: Wiring, 113: Wiring, 114: Wiring, 115: Wiring, 116: Wiring, 117: Wiring, 118: Wiring, 119: Wiring, 150: Memory cell, 150a: Memory cell, 150b: Memory cell, 170: Back gate wiring, 175: Metal oxide layer, 180: Source-drain wiring, 185: Gate wiring, 190: Wiring, 223: Transistor, 224. Transistor, 225: transistor, 272: transistor, 273: transistor, 274: capacitor, 410: bump, 415: rear surface electrode, 420: through electrode, 425: electrode pad, 430: adhesive, 440: cover glass, 450: bare chip, 455: pixel array, 460: lens cover, 470: lens, 480: optical filter, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 56 3b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 614: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622: insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer,631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 664: insulating layer, 665: insulating layer, 671: light-shielding layer, 672: optical conversion layer, 672B: color filter, 672G: color filter, 672IR: infrared filter, 672R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 691: conductive layer, 692: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 70 5: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 708: channel formation region, 735: back gate, 890: automobile, 891: camera, 892: imaging direction, 911: housing, 912: display unit, 913: speaker, 919: camera, 921: frame, 922: arm, 923: rotor, 924: blade, 925: camera, 926: battery, 932: display unit, 933: housing / wrist Band, 939: camera, 941: frame, 942: camera, 943: operation button, 944: parts, 951: support base, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker, 986: microphone, 987: camera,

Claims

An imaging device having a plurality of pixel blocks, the pixel block has a first layer and a second layer; the first layer has an area overlapping with the second layer; The pixel block is the first layer includes a plurality of pixel circuits and a plurality of first memory circuits; the second layer includes a plurality of product-sum calculation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits; The pixel circuit and the first memory circuit each include a transistor having a metal oxide in a channel formation region. 　 An imaging device having a plurality of pixel blocks, the pixel block has a first layer, a second layer, and a third layer; the first layer is located between the second layer and the third layer, or the third layer is located between the first layer and the second layer; the first layer to the third layer have overlapping regions; The pixel block is The first layer has a plurality of pixel circuits, the second layer includes a plurality of product-sum calculation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits; a plurality of first memory circuits are provided in the third layer; The pixel circuit and the first memory circuit each include a transistor having a metal oxide in a channel formation region. 　 In claim 1 or 2, The image pickup device includes a multiply-accumulate circuit, a first binarization circuit, and a second binarization circuit, each of which includes a transistor having silicon in a channel forming region. 　 In any one of claims 1 to 3, the number of the pixel circuits and the number of the first binarization circuits are the same, an imaging device in which the pixel circuit is electrically connected to one of the first binarization circuits; 　 In any one of claims 1 to 4, an imaging device in which one of the first binarization circuits is electrically connected to the plurality of product-sum calculation circuits; 　 In any one of claims 1 to 5, an imaging device, wherein one of the first memory circuits is electrically connected to the plurality of product-sum calculation circuits; 　 In any one of claims 1 to 6, the number of the sum-of-products operation circuits and the number of the second binarization circuits are the same; an imaging device in which one of the product-sum calculation circuits is electrically connected to one of the second binarization circuits; 　 In any one of claims 1 to 7, a drive circuit for the pixel circuit and a drive circuit for the first memory circuit are provided on the second layer; 　 In any one of claims 1 to 8, a second memory circuit; an input terminal of the second storage circuit is electrically connected to a plurality of the second binarization circuits; an output terminal of the second memory circuit electrically connected to the plurality of product-sum calculation circuits; 　 In claim 9, a third memory circuit and a third binarization circuit; the third storage circuit is electrically connected to the plurality of product-sum calculation circuits via the third binarization circuit; 　 In claim 10, The imaging device, wherein the second memory circuit, the third memory circuit, and the third binarization circuit are provided on the second layer. 　 In any one of claims 1 to 11, The metal oxide includes In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf). 　 An electronic device comprising: the imaging device according to claim 1; and a display device.

Images