Solar cell and method for manufacturing the same

Abstract

To provide a solar cell and a method for manufacturing the solar cell.SOLUTION: A solar cell includes a substrate having a first surface and a second surface facing each other along a first direction, a tunnel oxide layer provided on the first surface and / or the second surface, a doped polycrystalline silicon layer disposed on the surface of the tunnel oxide layer remote from the substrate, a barrier layer provided in an electrode region of the solar cell and in contact with the doped polycrystalline silicon layer, and having the same doping type as the doped polycrystalline silicon layer, and an electrode in contact with the barrier layer. The solar cell according to an embodiment of the present application reduces the risk of the electrode burning through the doped polycrystalline silicon layer by providing a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region. In addition, the thickness of the doped polycrystalline silicon layer can be further reduced, thereby reducing the absorption of incident light by the doped polycrystalline silicon layer and improving the utilization rate of the incident light of the solar cell.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention mainly relates to the field of solar cells, and particularly to a kind of solar cell and a manufacturing method thereof.

Background Art

[0002] Tunnel Oxide Passivating Contacts (TOPCon) solar cells were proposed in 2014. Such solar cells include a tunnel oxide layer and a doped polycrystalline silicon layer. The tunnel oxide can selectively transport carriers, and the doped polycrystalline silicon layer functions as field passivation. The electrodes of the solar cell contact the doped polycrystalline silicon layer through a functional layer (such as an antireflection layer) located in the electrode region.

[0003] The doped polycrystalline silicon layer in the solar cell has an optical parasitic effect, which reduces the utilization rate of the incident light on the solar cell. By reducing the thickness of the doped polycrystalline silicon layer, the absorption of the incident light by the doped polycrystalline silicon layer can be reduced, and the utilization rate of the incident light on the solar cell can be increased. However, reducing the thickness of the doped polycrystalline silicon layer increases the risk that the electrode contacts the substrate after burning through the polycrystalline silicon layer. The contact between the electrode and the substrate leads to an increase in the recombination current density, which in turn seriously affects the efficiency of the solar cell.

[0004] Therefore, how to balance the merit of increasing the utilization rate of incident light due to the reduction of the thickness of the doped polycrystalline silicon layer and the demerit of increasing the risk that the electrode burns through the doped polycrystalline silicon layer due to the reduction of the thickness of the doped polycrystalline silicon layer is an urgent problem to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The technical problem to be solved by the present application is to provide a solar cell and a method for manufacturing the solar cell that can avoid the electrodes from burning through the doped polycrystalline silicon layer while reducing the thickness of the doped polycrystalline silicon layer.

Means for Solving the Problem

[0006] To solve the above technical problem, the technical idea adopted by the present application is a solar cell, which includes a substrate having a first surface and a second surface facing each other along a first direction, a tunnel oxide layer provided on the first surface and / or the second surface, a doped polycrystalline silicon layer provided on the surface of the tunnel oxide layer away from the substrate, a barrier layer provided in the electrode region of the solar cell and in contact with the doped polycrystalline silicon layer, and the doping type of which is the same as that of the doped polycrystalline silicon layer, and an electrode in contact with the barrier layer. Among them, the first direction is the thickness direction of the substrate.

[0007] In one embodiment of the present application, the barrier layer is provided on the surface of the doped polycrystalline silicon layer away from the substrate.

[0008] In one embodiment of the present application, the barrier layer penetrates along the first direction to a preset depth in the doped polycrystalline silicon layer, where the preset depth is equal to or less than the thickness of the doped polycrystalline silicon layer.

[0009] In one embodiment of the present application, the barrier layer is provided on the surface of the tunnel oxide layer away from the substrate.

[0010] In one embodiment of the present application, the surface of the barrier layer away from the substrate is flush with the surface of the doped polycrystalline silicon layer away from the substrate, or closer to the substrate than the surface of the doped polycrystalline silicon layer away from the substrate, or farther from the substrate than the surface of the doped polycrystalline silicon layer away from the substrate.

[0011] In one embodiment of the present application, the material of the barrier layer includes one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0012] In one embodiment of the present application, the crystallization rate of the polycrystalline silicon is greater than that of the doped polycrystalline silicon layer.

[0013] In one embodiment of the present application, the crystallization rate of the polycrystalline silicon is 90% or more, and the crystallization rate of the doped polycrystalline silicon layer is 80% - 95%.

[0014] In one embodiment of the present application, the composite current density of the electrode region is 100 fA / cm 2 or less.

[0015] In one embodiment of the present application, the doped polycrystalline silicon layer and the dielectric layer provided on the surface away from the substrate of the barrier layer are further provided.

[0016] In one embodiment of the present application, the electrode penetrates the dielectric layer and contacts the barrier layer.

[0017] In one embodiment of the present application, the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

[0018] This application proposes a method for manufacturing a solar cell to solve the above technical problems. The method for manufacturing the solar cell includes the steps of: providing a substrate having a first surface and a second surface facing each other along a first direction, forming a tunnel oxide layer on the first surface and / or the second surface, forming a doped polycrystalline silicon layer on the surface of the tunnel oxide layer away from the substrate, forming a barrier layer in the electrode region of the solar cell that contacts the doped polycrystalline silicon layer and has the same doping type as the doped polycrystalline silicon layer, and forming an electrode in contact with the barrier layer. Among them, the first direction is the thickness direction of the substrate.

[0019] In one embodiment of this application, the method for forming the barrier layer includes the steps of: cleaning the surface of the doped polycrystalline silicon layer, and forming a barrier layer in the electrode region that contacts the surface of the doped polycrystalline silicon layer away from the substrate.

[0020] In one embodiment of this application, the material of the barrier layer includes one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0021] In one embodiment of this application, the method for forming the barrier layer includes the steps of: etching the doped polycrystalline silicon layer in the electrode region along the first direction to form a groove with a preset depth, and forming the barrier layer in the groove. Among them, the preset depth is equal to or less than the thickness of the doped polycrystalline silicon layer.

[0022] In one embodiment of this application, the method for forming the barrier layer includes the steps of: performing heat treatment on the doped polycrystalline silicon layer located in the electrode region to form the barrier layer, and / or performing a thinning treatment on the doped polycrystalline silicon layer and / or the barrier layer.

[0023] In one embodiment of the present application, the crystallization rate of the polycrystalline silicon is 90% or more, and the crystallization rate of the doped polycrystalline silicon layer is 80% to 95%.

[0024] In one embodiment of the present application, the composite current density in the electrode region is 100 fA / cm2 or less.

[0025] In one embodiment of the present application, the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

[0026] The solar cell and the method for manufacturing the solar cell of the present application reduce the risk of the electrode burning through the doped polycrystalline silicon layer by providing a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region. Moreover, the thickness of the doped polycrystalline silicon layer can be further reduced, thereby reducing the absorption of the doped polycrystalline silicon layer for incident light and improving the utilization rate of the solar cell for incident light.

[0027] In order to make the above objects, features, and advantages of the present application clearer and easier to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Brief Description of the Drawings

[0028]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0029] In order to make the above objects, features, and advantages of the present application clearer and easier to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0030] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can also be implemented in other ways different from those described herein, so the present application is not limited to the specific embodiments disclosed below.

[0031] As shown in the present application and the claims, unless the context clearly indicates otherwise, terms such as "a", "one", "a kind", and / or "the" are not specifically intended to refer to the singular, but may include the plural. Generally, the terms "comprising" and "including" merely indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive listing, and the method or apparatus may include other steps or elements.

[0032] Also, the use of terms such as "first", "second", etc. to limit components is merely for the purpose of easily distinguishing the corresponding components, and without a separate statement, these terms have no special meaning, so it cannot be understood as a limitation on the protection scope of the present application. Furthermore, the terms used in the present application are selected from well-known technical terms, but among the terms described in the specification of the present application, there are also those selected by the applicant at his own discretion, and the detailed meanings thereof are explained in the relevant parts of the description of the present specification. It should be noted that it is required to understand the present application not only through the actual terms used, but also through the meanings included in each term.

[0033] In this specification, flowcharts are used to describe the operations performed by the system according to the embodiments of the present application. It should be understood that the above or following operations are not necessarily executed exactly in order. Conversely, various steps can be processed in reverse order or simultaneously. Additionally, other operations can be added to these procedures, or one or more steps can be removed from these procedures.

[0034] Next, the solar cell and the method for manufacturing the solar cell according to the present application will be described with specific embodiments.

[0035] FIG. 1 is a front schematic view of a solar cell according to an embodiment. As shown in FIG. 1, the solar cell includes a substrate 110, a tunnel oxide layer 120, a doped polycrystalline silicon layer 130, a barrier layer 140, and an electrode 150. The substrate 110 has a first surface 111 and a second surface 112 that face each other in a first direction D1 (which is also the thickness direction of the substrate 110). The first surface 111 and the second surface 112 may be polished surfaces or may be pile surfaces having a pyramid shape. The tunnel oxide layer 120 is provided on the first surface 111, and the doped polycrystalline silicon layer 130 is provided on the surface of the tunnel oxide layer 120 that is away from the substrate 110 in the first direction D1. The tunnel oxide layer 120 and the doped polycrystalline silicon layer 130 together constitute a tunnel oxide layer doped polycrystalline silicon layer passivation structure. In other embodiments, the tunnel oxide layer 120 may be formed on the second surface 112, or may be formed on both the first surface 111 and the second surface 112 simultaneously.

[0036] The substrate 110 may be a silicon substrate, such as a single crystal silicon substrate or a polycrystalline silicon substrate. Doping processes such as N-type doping or P-type doping can be performed on the substrate 110. The material of the tunnel oxide layer 120 is silicon oxide (SiO x) It may also be the case that the thickness of the tunnel oxide layer 120 may be any value between 1 nm and 3 nm, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. The tunnel oxide layer 120 serves to selectively collect carriers. The material of the doped polycrystalline silicon layer 130 can be selected from polycrystalline silicon, and in this application, the crystal grain size of the polycrystalline silicon is not limited. The doping type of the doped polycrystalline silicon layer 130 may be the same as that of the substrate 110 or opposite to that of the substrate 110.

[0037] The solar cell has an electrode region, and in FIG. 1, the electrode region is marked using the dashed rectangular frame 160. The electrodes of the solar cell are located in the electrode region, and the electrodes collect the electrical energy generated by the solar cell and are used to transmit the electrical energy to the outside.

[0038] As shown in FIG. 1, the barrier layer 140 is provided in the electrode region and is in contact with the doped polycrystalline silicon layer 130, and the doping type of the barrier layer 140 is the same as the doping type of the doped polycrystalline silicon layer 130. For example, both the doping type of the doped polycrystalline silicon layer 130 and the doping type of the barrier layer 140 may be N-type, and the corresponding doping element can be selected from one or more of group V elements such as phosphorus element (P), bismuth element (Bi), antimony element (Sb), arsenic element (As), etc. Both the doping type of the doped polycrystalline silicon layer 130 and the doping type of the barrier layer 140 may be P-type, and the corresponding doping element can be selected from one or more of group III elements such as boron element (B), aluminum element (Al), gallium element (Ga), or indium element (In).

[0039] Continuing as shown in FIG. 1, the electrode 150 is in contact with the barrier layer 140. It should be noted that the number of the electrode region and the electrode 150 in the solar cell is not limited to one shown in FIG. 1. The solar cell includes a certain number of electrode regions and electrodes 150 arranged at intervals along the second direction D2. Since it is limited by the drawing size, it is not shown in FIG. 1.

[0040] In one embodiment, in FIG. 1, the solar cell further includes a dielectric layer 170. The dielectric layer 170 is disposed on a surface away from the substrate 110 along a first direction D1 of the doped polycrystalline silicon layer 130 and the barrier layer 140. Alternatively, the dielectric layer 170 covers the exposed surfaces of the doped polycrystalline silicon layer 130 and the barrier layer 140. The electrode 150 penetrates the dielectric layer 170 and contacts the barrier layer 140. The dielectric layer 170 may be a stacked passivation film, which has a passivation effect on the solar cell, and the dielectric layer 170 may also be an antireflection film.

[0041] In FIG. 1, the barrier layer 140 is provided on a surface away from the substrate 110 along a first direction D1 of the doped polycrystalline silicon layer 130. The electrode 150 forms an electrical connection with the barrier layer 140 and the doped polycrystalline silicon layer 130 (an electrical connection is formed by contact between the doped polycrystalline silicon layer 130 and the barrier layer 140) by contacting the barrier layer 140 through a firing process. In FIG. 1, the electrode 150 penetrates into the barrier layer 140 and does not penetrate into the doped polycrystalline silicon layer 130. In some other embodiments, the electrode 150 can also penetrate through the barrier layer 140 and further penetrate into the doped polycrystalline silicon layer 130.

[0042] The firing process has an etching effect on the barrier layer 140 and the doped polycrystalline silicon layer 130, whereby the electrode 150 may burn through the doped polycrystalline silicon layer 130 and further contact the substrate 110. When the electrode 150 contacts the substrate 110, the composite current density in the electrode region increases rapidly, and consequently, the efficiency of the solar cell decreases.

[0043] In the present application, a barrier layer 140 that contacts the doped polycrystalline silicon layer 130 is formed in the electrode region (where the electrode 150 is fired). When the electrode 150 is fired, after the electrode 150 burns through the barrier layer 140, the doped polycrystalline silicon layer 130 is further eroded. Therefore, the barrier layer 140 reduces the risk of the electrode 150 burning through the doped polycrystalline silicon layer 130.

[0044] In one embodiment, the material of the barrier layer 140 is selected from a material more resistant to melting erosion than the doped polycrystalline silicon layer 130, such as silicon carbide and / or zinc oxide. The material of the barrier layer 140 may be polycrystalline silicon with a higher crystallization rate than the doped polycrystalline silicon layer 130. Polycrystalline silicon with a high crystallization rate has higher melting erosion resistance than polycrystalline silicon with a low crystallization rate. In some embodiments, the crystallization rate of the polycrystalline silicon in the barrier layer 140 is 90% or more, and the crystallization rate of the doped polycrystalline silicon layer 130 is 80% - 95%. For example, the crystallization rate of the polycrystalline silicon in the barrier layer 140 may be 90%, 95%, 99% or 100%, and the crystallization rate of the doped polycrystalline silicon layer 130 may be 80%, 85%, 90% or 95%. In some embodiments, the crystallization rate of the polycrystalline silicon in the barrier layer 140 decreases as the distance from the substrate 110 in the first direction D1 decreases.

[0045] The material of the barrier layer 140 may be a mixture of any two or more of silicon carbide, zinc oxide and polycrystalline silicon. In some embodiments, when the barrier layer 140 is polycrystalline silicon, the polycrystalline silicon may be doped with a carbon element (C) and / or an oxygen element (O).

[0046] Here, the technical effect that "the barrier layer 140 can prevent the electrode 150 from burning through the doped polycrystalline silicon layer 130" will be outlined. In FIG. 1, the barrier layer 140 is disposed on the surface of the doped polycrystalline silicon layer 130 away from the substrate 110, thereby increasing the length of the path through which the electrode 150 burns through the doped polycrystalline silicon layer 130, and further preventing the electrode 150 from burning through the doped polycrystalline silicon layer 130. At the same time, when the barrier layer 140 is selected from a material resistant to melting and erosion, the barrier layer 140 can also prevent the electrode 150 from burning through the doped polycrystalline silicon layer 130 by its own melting and erosion resistance characteristics. Briefly speaking, the barrier layer 140 can prevent the doped polycrystalline silicon layer 130 from being burned through by the electrode 150 by both "increasing the burning-through path" and "its own melting and erosion resistance characteristics". It should be understood that the barrier layer 140 does not have to utilize both of the above at the same time, but can prevent the polycrystalline silicon layer 130 from being burned through by the electrode 150 by only one of them.

[0047] In addition, the doped polycrystalline silicon layer 130 has an optical parasitic effect, which leads to a decrease in the utilization rate of the solar cell for incident light. By reducing the thickness of the doped polycrystalline silicon layer 130, the absorption of incident light can be reduced. However, in the prior art, the technical idea of reducing the thickness of the doped polycrystalline silicon layer 130 has a side effect of "increasing the risk of the electrode 150 burning through the tunnel oxide layer 120". The technical idea of installing the barrier layer 140 in the electrode region of the present application increases the difficulty for the electrode 150 to burn through the doped polycrystalline silicon layer 130. Therefore, even if the thickness of the doped polycrystalline silicon layer 130 is reduced, it can be guaranteed that the electrode 150 will not burn through the doped polycrystalline silicon layer 130. The absorption of the doped polycrystalline silicon layer 130 for incident light can be reduced, and the utilization rate of the solar cell for incident light can be increased. In some embodiments, the thickness of the doped polycrystalline silicon layer 130 is 3 nm or more and 200 nm or less. For example, the thickness of the doped polycrystalline silicon layer 130 may be 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm. The fact that the thickness of the doped polycrystalline silicon layer 130 is 3 nm or more can guarantee the lateral transport ability of carriers and can guarantee meeting the requirements regarding field passivation for the substrate 110. The "thickness of the doped polycrystalline silicon layer 130" means the size of the doped polycrystalline silicon layer 130 in the first direction D1.

[0048] In FIG. 1, the barrier layer 140 is disposed on the surface away from the substrate 110 along the first direction D1 of the doped polycrystalline silicon layer 130. The positional relationship between the barrier layer 140 and the doped polycrystalline silicon layer 130 in the present application is not limited to FIG. 1, and will be described below.

[0049] FIG. 2A is a front schematic view of a solar cell according to another embodiment, and FIG. 2B is an enlarged view of a partial structure in FIG. 2A. As shown with reference to FIGS. 2A and 2B, unlike FIG. 1, the barrier layer 140 in FIGS. 2A and 2B penetrates into the first direction D1 to a preset depth d1 within the doped polycrystalline silicon layer 130. Here, the preset depth d1 is less than or equal to the thickness d2 of the doped polycrystalline silicon layer 130. The present application does not limit the preset depth d1, and it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 100% of the thickness d2. When the preset depth d1 is equal to the thickness d2 of the doped polycrystalline silicon layer 130, it should be understood that the bottom surface 141 of the barrier layer 140 contacts the surface of the tunnel oxide layer 120 that is away from the surface of the substrate 110 in the first direction D1. In other words, as shown in FIG. 3, the barrier layer 140 is disposed on the surface of the tunnel oxide layer 120 that is away from the substrate 110 in the first direction D1.

[0050] FIGS. 4A and 4B are respectively front schematic views of solar cells according to two embodiments. As shown in FIG. 4A, the barrier layer 140 is disposed on the surface of the tunnel oxide layer 120 that is away from the substrate 110 in the first direction D1, that is, the bottom surface 141 of the barrier layer 140 contacts the tunnel oxide layer 120. The barrier layer 140 has an upper surface 142 that is away from the substrate 110 along the first direction D1, and the doped polycrystalline silicon layer 130 has a surface 131 that is away from the substrate 110 along the first direction D1. In FIG. 4A, the upper surface 142 of the barrier layer 140 is flush with the surface 131 of the doped polycrystalline silicon layer 130. As shown in FIG. 4B, the difference between FIG. 4B and FIG. 4A is that the upper surface 142 of the barrier layer 140 in FIG. 4B is closer to the substrate 110 than the surface 131 of the doped polycrystalline silicon layer 130. In other embodiments, the upper surface 142 may be away from the substrate 110 more than the surface 131 in the first direction D1, that is, the barrier layer 140 may protrude toward the surface 131 with its back facing the substrate 110.

[0051] In FIG. 1, the bottom surface 141 of the barrier layer 140 is in contact with the doped polycrystalline silicon layer 130. In FIGS. 2A to 4B, in addition to the bottom surface 141, the side surfaces of the barrier layer 140 are in contact with the doped polycrystalline silicon layer 130. Taking FIG. 3 as an example, as shown in FIG. 3, the barrier layer 140 has a first side surface 143 and a second side surface 144 facing each other along the second direction D2, and both the first side surface 143 and the second side surface 144 are in contact with the doped polycrystalline silicon layer 130. Increasing the contact surface between the barrier layer 140 and the doped polycrystalline silicon layer 130 is advantageous for reducing resistance.

[0052] In one embodiment, the composite current density in the electrode regions of FIGS. 1 to 4B is 100 fA / cm 2 or less. The reduction of the composite current density contributes to the improvement of the efficiency of the solar cell. One of the main factors for the composite current density to be 100 fA / cm 2 or less is that the electrode 150 avoids contacting the substrate 110 without burning through the doped polycrystalline silicon layer 130. In other embodiments, an ohmic contact is formed between the electrode 150 and the barrier layer 140, and the contact resistance between the two is 1 mΩ·cm 2 or less, and the magnitude of the contact resistance can be adjusted by adjusting the doping concentration of the barrier layer 140. For example, the contact resistance can be reduced by increasing the doping concentration.

[0053] The solar cell in the above embodiment of the present application is provided with a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region, reducing the risk of the electrode burning through the doped polycrystalline silicon layer. Moreover, the thickness of the doped polycrystalline silicon layer can be further reduced, thereby reducing the absorption of the doped polycrystalline silicon layer for incident light and improving the utilization rate of the incident light of the solar cell.

[0054] Another aspect of the present application also proposes a manufacturing method of a solar cell, and the manufacturing method will be described subsequently.

[0055] FIG. 5 is a flowchart of a method for manufacturing a solar cell according to an embodiment. As shown in FIG. 5, the manufacturing method of this embodiment includes the following steps.

[0056] Step S210: Provide a substrate having a first surface and a second surface facing each other along a first direction; Step S220: Form a tunnel oxide layer on the first surface and / or the second surface; Step S230: Form a doped polycrystalline silicon layer on the surface of the tunnel oxide layer away from the substrate; Step S240: Form a barrier layer in the electrode region of the solar cell. The barrier layer contacts the doped polycrystalline silicon layer, and the doping type of the barrier layer is the same as that of the doped polycrystalline silicon layer; Step S250: Form an electrode and make the electrode contact the barrier layer.

[0057] Next, steps S210 to S250 will be described.

[0058] As shown in FIG. 1, in step S210, substrate 110 is provided. Substrate 110 has a first surface 111 and a second surface 112 facing each other along a first direction D1. In step S220, a tunnel oxide layer 120 is formed on the first surface 111. In some other embodiments, the tunnel oxide layer may be formed on the second surface 112, or the tunnel oxide layer may be formed on both the first surface 111 and the second surface 112. In step S230, a doped polycrystalline silicon layer 130 is formed on the surface of the tunnel oxide layer 120 away from the substrate 110 along the first direction D1. The methods for forming the tunnel oxide layer 120 and the doped polycrystalline silicon layer 130 include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and thermal oxidation method. For other descriptions of the substrate 110, the tunnel oxide layer 120, and the doped polycrystalline silicon layer 130, please refer to the relevant parts above. They will not be elaborated here.

[0059] In some embodiments, the thickness of the doped polycrystalline silicon layer 130 is 3 nm or more and 200 nm or less. For example, the thickness of the doped polycrystalline silicon layer 130 may be 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm. The thickness of the doped polycrystalline silicon layer 130 being 3 nm or more can guarantee the lateral transport ability of carriers and can guarantee meeting the requirements regarding field passivation for the substrate 110.

[0060] Continuing as shown in FIG. 1, in step S240, a barrier layer 140 is formed in the electrode region of the solar cell. The barrier layer 140 is in contact with the doped polycrystalline silicon layer 130, and the doping type of the barrier layer 140 is the same as the doping type of the doped polycrystalline silicon layer 130. Both the barrier layer 140 and the doped polycrystalline silicon layer 130 may be N-type doped or P-type doped.

[0061] In one embodiment, the method of forming the barrier layer 140 in FIG. 1 includes the following steps.

[0062] Step 11: Clean the surface of the doped polycrystalline silicon layer 130. This surface includes the surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 along the first direction D1 of the doped polycrystalline silicon layer 130. Through the cleaning process, contaminants on the surface of the doped polycrystalline silicon layer 130 can be removed.

[0063] Step 12: Form a barrier layer 140 in the electrode region that is in contact with the surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 along the first direction D1 of the doped polycrystalline silicon layer 130.

[0064] The method of forming the barrier layer 140 in step 12 includes chemical vapor deposition and physical vapor deposition. Examples of the material of the barrier layer 140 include one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0065] Referring to the intermediate products in the manufacturing process of the solar cell shown in FIGS. 2A, 2B, and 6, in one embodiment, the method of forming the barrier layer 140 in FIGS. 2A and 2B includes the following steps.

[0066] Step 21: Etch the doped polycrystalline silicon layer 130 in the electrode region along the first direction D1 to form a groove 180 having a preset depth d3.

[0067] Step 22: Form a barrier layer 140 in the groove 180, where the preset depth d3 is less than or equal to the thickness d4 of the doped polycrystalline silicon layer 130.

[0068] In the present application, there is no limitation on the method of etching the doped polycrystalline silicon layer 130. For example, it may be physical etching or chemical etching. As shown in FIGS. 2A and 2B, the barrier layer 140 protrudes with its back facing away from the substrate 110 with respect to the doped polycrystalline silicon layer 130. In some other embodiments, the surface of the barrier layer 140 away from the substrate 110 can be flush with the surface of the doped polycrystalline silicon layer 130 away from the substrate 110.

[0069] As shown in FIGS. 3 and 6, when the preset depth d3 is equal to the thickness d4 of the doped polycrystalline silicon layer 130, the barrier layer 140 formed in the groove 180 contacts the surface of the tunnel oxide layer 120 away from the substrate 110.

[0070] Referring to the intermediate products in the manufacturing process of the solar cell shown in FIGS. 4B and 7, the method of forming the barrier layer 140 in FIG. 4A includes the following steps.

[0071] Step 31: Perform a heat treatment on the initial barrier layer 132 (i.e., the doped polycrystalline silicon layer located in the electrode region) to form the barrier layer 140.

[0072] Specifically, as shown in FIG. 7, a heat treatment can be performed on the initial barrier layer 132 by a laser. After the heat treatment, the crystallization rate of the initial barrier layer 132 is improved, and thereby the initial barrier layer 132 can be converted into the barrier layer 140 in FIG. 3.

[0073] In one embodiment, before step 31, it further includes a step of performing a high-temperature crystallization treatment on the doped polycrystalline silicon layer 130. The high-temperature crystallization treatment can improve the crystallization rate of the doped polycrystalline silicon layer 130. Step 31 performs a heat treatment on the initial barrier layer 132 based on this to obtain a barrier layer 140 with a higher crystallization rate. The methods of performing the high-temperature crystallization treatment on the doped polycrystalline silicon layer 130 include performing a high-temperature crystallization treatment on the polycrystalline silicon layer 130 using a tube furnace and performing a high-temperature crystallization treatment on the polycrystalline silicon layer 130 using a laser. In some embodiments, the crystallization rate of the barrier layer 140 is greater than that of the doped polycrystalline silicon layer 130, the crystallization rate of the barrier layer 140 is 90% or more, and the crystallization rate of the doped polycrystalline silicon layer 130 is 80% - 95%.

[0074] In FIG. 4B, the surface of the barrier layer 140 away from the substrate 110 in the first direction D1 is closer to the substrate 110 than the surface of the doped polycrystalline silicon layer 130 away from the substrate 110 in the first direction D1. This is because the volume of the initial barrier layer 132 shrinks after being laser heat-treated.

[0075] As shown in FIG. 4A, compared with FIG. 4B, the surface of the barrier layer 140 away from the substrate 110 in the first direction D1 in FIG. 4A is flush with the surface of the doped polycrystalline silicon layer 130 away from the substrate 110 in the first direction D1. The method of forming the barrier layer 140 in FIG. 4A includes the following steps.

[0076] Step 32: Perform a thinning process on the doped polycrystalline silicon layer 130 in FIG. 4B. By performing a thinning process on the doped polycrystalline silicon layer 130, the doped polycrystalline silicon layer 130 can be flush with the barrier layer 140, and damage to the surface of the doped polycrystalline silicon layer 130 caused by laser heat treatment can be removed.

[0077] In some embodiments, the doped polycrystalline silicon layer 130 and the barrier layer 140 can be thinned simultaneously to obtain the doped polycrystalline silicon layer 130 and the barrier layer 140 with a target thickness. By performing a thinning process on the barrier layer 140, damage to the surface of the barrier layer 140 caused by laser heat treatment can be removed. In other embodiments, a thinning process can be performed only on the doped polycrystalline silicon layer 130 to thin the surface 131 of the doped polycrystalline silicon layer 130 so as to be located above the upper surface 142 of the barrier layer 140 in the first direction D1. In other embodiments, a thinning process can be performed only on the barrier layer 140 to obtain the barrier layer 140 with a target thickness.

[0078] In one embodiment, the composite current density in the electrode region is 100 fA / cm 2 The following. The reduction of the composite current density contributes to the improvement of the efficiency of the solar cell.

[0079] As shown back in FIG. 5, in step S250, an electrode is formed and the electrode is brought into contact with the barrier layer. Taking FIG. 1 as an example, in FIG. 1, an electrode 150 that contacts the barrier layer 140 is formed. An electrical connection is established by contact between the barrier layer 140 and the electrode 150. The electrode 150 that contacts the barrier layer 140 can be formed by a firing method. The present application does not limit the depth to which the electrode 150 penetrates into the barrier layer 140. In some embodiments, the electrode 150 can also penetrate through the barrier layer 140 and further into the doped polycrystalline silicon layer 130, but the electrode 150 does not penetrate through the polycrystalline silicon layer 130.

[0080] As shown in FIG. 1, in some embodiments, before step S250, the method further includes forming a dielectric layer 170 covering the surface of the doped polycrystalline silicon layer 130 away from the substrate 110 and the surface of the barrier layer 140 away from the substrate 110. In step S250, the electrode 150 penetrates the dielectric layer 170 and enters the barrier layer 140.

[0081] The manufacturing method in the above embodiments of the present application provides a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region, reducing the risk of the electrode burning through the doped polycrystalline silicon layer. Moreover, the thickness of the doped polycrystalline silicon layer can be further reduced, thereby reducing the absorption of the doped polycrystalline silicon layer for incident light and improving the utilization rate of the incident light of the solar cell.

[0082] In the above, the basic concepts have been described. However, it is obvious to those skilled in the art that the above disclosure is only an example and does not limit the present application. Although not specified here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application and belong to the spirit and scope of the exemplary embodiments of the present application.

[0083] At the same time, the present application uses specific terms to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" mean features, configurations, or characteristics related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that the "an embodiment" or "one embodiment" or "one alternative embodiment" mentioned more than twice in different places in this specification does not necessarily mean the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application can be appropriately combined.

[0084] In some embodiments, numbers are used to describe the number of components or attributes. However, in some examples, the numbers used to describe such embodiments should be understood to be modified using the modifiers "about", "substantially", or "generally". Unless otherwise specified, "about", "substantially", or "generally" means that the numerical value allows a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and these approximate values can be changed according to the characteristics required by individual embodiments. In some embodiments, numerical parameters should consider a predetermined number of significant digits and adopt a general method of maintaining the number of digits. In some embodiments of the present application, the numerical fields and parameters used to confirm the scope are approximate values. However, in a specific embodiment, the setting of such numerical values is as accurate as possible within the possible range.

Description of Reference Numerals

[0085] 110 Substrate 111 First surface 112 Second surface 120 Tunnel oxide layer 130 Doped polycrystalline silicon layer 131 Surface 132 Initial barrier layer 140 Barrier layer 141 Bottom surface 142 Top surface 143 First side surface 144 Second side surface 150 Electrode 160 Electrode region 170 Dielectric layer 180 Groove

Claims

1. A substrate having a first surface and a second surface facing each other along a first direction; A tunnel oxide layer provided on the first surface and / or the second surface; A doped polycrystalline silicon layer provided on a surface of the tunnel oxide layer away from the substrate; A barrier layer provided in an electrode region of a solar cell and in contact with the doped polycrystalline silicon layer, the doping type of which is the same as that of the doped polycrystalline silicon layer; An electrode provided in the electrode region and in contact with the barrier layer, comprising: The first direction is the thickness direction of the substrate; The barrier layer is formed in a groove having a preset depth obtained by etching the doped polycrystalline silicon layer in the electrode region along the first direction; The preset depth is equal to or less than the thickness of the doped polycrystalline silicon layer; The material of the barrier layer includes silicon carbide and / or zinc oxide, characterized in that it is a solar cell.

2. The barrier layer penetrates along the first direction to a preset depth in the doped polycrystalline silicon layer; The preset depth is equal to or less than the thickness of the doped polycrystalline silicon layer, characterized in that it is the solar cell according to Claim 1.

3. The barrier layer is provided on a surface of the tunnel oxide layer away from the substrate. Characterized in that it is the solar cell according to Claim 1.

4. The surface of the barrier layer away from the substrate is flush with the surface of the doped polycrystalline silicon layer away from the substrate, or closer to the substrate than the surface of the doped polycrystalline silicon layer away from the substrate, or farther from the substrate than the surface of the doped polycrystalline silicon layer away from the substrate, characterized in that it is the solar cell according to Claim 3.

5. The composite current density of the electrode region is 100 fA / cm ２ The solar cell according to claim 1, characterized in that it is as follows.

6. Further comprising a dielectric layer provided on a surface of the doped polycrystalline silicon layer and the barrier layer away from the substrate, characterized in that it is the solar cell according to Claim 1.

7. The electrode penetrates through the dielectric layer and contacts the barrier layer, characterized in that it is the solar cell according to Claim 6.

8. The thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less, characterized in that it is the solar cell according to Claim 1.

9. providing a substrate having a first surface and a second surface facing each other along a first direction; forming a tunnel oxide layer on the first surface and / or the second surface; forming a doped polycrystalline silicon layer on a surface of the tunnel oxide layer away from the substrate; forming, in an electrode region of a solar cell, a barrier layer that contacts the doped polycrystalline silicon layer and has the same doping type as the doped polycrystalline silicon layer; forming an electrode that contacts the barrier layer, comprising: wherein the first direction is the thickness direction of the substrate; wherein the method of forming the barrier layer comprises etching the doped polycrystalline silicon layer in the electrode region along the first direction to form a groove having a preset depth, and forming the barrier layer in the groove; wherein the preset depth is equal to or less than the thickness of the doped polycrystalline silicon layer; wherein the material of the barrier layer comprises silicon carbide and / or zinc oxide, a method for manufacturing a solar cell.

10. The step of forming the barrier layer: cleaning the surface of the doped polycrystalline silicon layer; forming, in the electrode region, a barrier layer that contacts a surface of the doped polycrystalline silicon layer away from the substrate, the method for manufacturing a solar cell according to claim 9.

11. The composite current density of the electrode region is 100 fA / cm ２ The method for manufacturing a solar cell according to claim 9, characterized in that it is as follows.

12. wherein the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less, the method for manufacturing a solar cell according to claim 9.

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