Semiconductor device and electronic device

Abstract

Provided is a semiconductor device that restores corrupted data. This semiconductor device comprises a first circuit, a memory unit, and a calculation unit, wherein the first circuit has a current source and a first switch, the memory unit has a first transistor and a first capacitance, and the calculation unit has a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. When the data held in the calculation unit is to be restored, the first transistor is turned on to supply the data held in the memory unit to the control terminal of the first switch via the first transistor. The first switch is either turned on or turned off depending on the supplied data, causing a current to flow from the current source to the calculation unit via the second transistor to replenish the holding part of the calculation unit with charge.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. Such integrated circuits incorporate the mechanisms of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with extremely low power consumption, compared to the von Neumann architecture, which consumes more power as the processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting factor) of a synapse connecting two neurons is multiplied by a signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and add the connection strength of each synapse between a plurality of first neurons in the first layer and one of the second neurons in the second layer by each signal input from a plurality of first neurons in the first layer to one of the second neurons in the second layer, that is, to perform a product-sum operation between the connection strength and the signal. The number of connection strengths and the number of parameters indicating the signal used in the product-sum operation are determined according to the scale of the artificial neural network. In addition, the second neuron performs a calculation using an activation function using the result of the product-sum operation between the connection strength of the synapse and the signal output by the first neuron, and outputs the result of the calculation as a signal to the third neuron in the third layer. In other words, in an artificial neural network, the greater the number of layers and the number of neurons, the greater the number of circuits corresponding to "neurons" and "synapses", and the amount of calculation may become enormous. This can result in increased power consumption and increased heat generation by the circuit.

[0007] Furthermore, as the number of circuits constituting a chip increases, power consumption increases and the amount of heat generated during operation of the device also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements contained in the chip are affected, so it is preferable that the circuits constituting the chip have circuit elements that are less susceptible to temperature effects. Furthermore, if the characteristics of the transistors, current sources, etc. contained in the chip vary, the results of the calculations will also vary.

[0008] In addition, when performing the above-mentioned sum-of-products operation, the circuit that performs the multiplication (referred to as a multiplication cell in this specification) needs to keep holding a weighting factor as a multiplier (or a multiplicand). For this reason, the multiplication cell is provided with a storage element such as a capacitance that holds a weighting factor, but the data held in the storage element may deteriorate over time, causing the value of the weighting factor to change. The deterioration of data occurs when the charge held in the storage element decreases. For example, the cause of the decrease in charge is leakage current flowing from the storage element, and the types of leakage current include, for example, leakage current flowing in an OFF state in a switching element such as a transistor, and leakage current flowing through a dielectric between a pair of electrodes in a capacitance element. In the case of leakage current flowing in an OFF state in a switching element such as a transistor, the effect of the leakage current can be reduced by increasing the capacitance value of the capacitance element. On the other hand, in the case of leakage current flowing through a dielectric between a pair of electrodes in a capacitance element, the amount of leakage current per unit area of ​​the pair of electrodes does not change even if the capacitance value of the capacitance element is increased, so it is difficult to reduce the effect of the leakage current as a whole.

[0009] Therefore, in order to prevent the deterioration of the data held in the multiplication cell, the arithmetic circuit including the multiplication cell needs to take measures other than increasing the capacitance value of the capacitance element. One example of such measures is to periodically rewrite the weight coefficient to the memory element of the multiplication cell. Alternatively, it is also preferable to provide a dummy cell or the like in the arithmetic circuit including the multiplication cell, monitor the data held in the dummy cell, and rewrite the weight coefficient to the multiplication cell when the data deteriorates. In this specification, rewriting data refers to an operation of writing the same data as the data originally held in the cell back to the cell. Rewriting data also refers to an operation of refilling a cell with the same amount of charge as originally held in the cell in order to restore data to the cell whose absolute value of the charge amount has become small.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device or the like that performs a product-sum operation and / or a function operation. Another object of one embodiment of the present invention is to provide a semiconductor device that rewrites data held in a multiplication cell. Another object of one embodiment of the present invention is to provide a semiconductor device that holds a digital value, performs digital-to-analog conversion on the digital value, and performs an operation using the analog value. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that performs convolution processing such as CNN (Convolutional Neural Network). Another object of one embodiment of the present invention is to provide a semiconductor device or the like for AI (Artificial Intelligence). Another object of one embodiment of the present invention is to provide a semiconductor device or the like for DNN (Deep Neural Network). Another object of one embodiment of the present invention is to provide a semiconductor device or the like that consumes low power. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by environmental temperature. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by variation in characteristics of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device or the like that is not easily affected by variation in characteristics of a current source. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0011] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0012] (1) One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, and a third circuit. The first circuit includes a current source and a first switch, the second circuit includes a first transistor, a third transistor, a fourth transistor, and a first capacitance, and the third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a second terminal of the first transistor is electrically connected to a first terminal of the fourth transistor, a second terminal of the fourth transistor is electrically connected to a first terminal of the first capacitance, a gate of the fourth transistor is electrically connected to a second terminal of the first capacitance and a first terminal of the third transistor, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor.

[0013] (2) Alternatively, one aspect of the present invention may have a configuration in (1) above, further including a fourth circuit including a latch circuit. The first terminal of the first transistor and the control terminal of the first switch are electrically connected to each other by electrically connecting the first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting the second terminal of the fourth circuit to the control terminal of the first switch.

[0014] (3) Another embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, and a sense amplifier. The first circuit includes a current source and a first switch, the second circuit includes a first transistor and a first capacitance, and the third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch via the sense amplifier, a second terminal of the first transistor is electrically connected to a first terminal of the first capacitance, a first terminal of the first switch is electrically connected to an output terminal of the current source, and the second terminal of the first switch is electrically connected to a first terminal of the second transistor.

[0015] (4) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (3), a gate of the first transistor may be electrically connected to a gate of the second transistor.

[0016] (5) Another embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, and a third circuit. The first circuit includes a current source and a first switch, the second circuit includes a first transistor, a third transistor, and a first capacitance, and the third circuit includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the third transistor is electrically connected to a first terminal of the first capacitance and a gate of the first transistor, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor.

[0017] (6) Alternatively, one embodiment of the present invention may have a fourth circuit including a latch circuit. The first terminal of the first transistor and the control terminal of the first switch are electrically connected to each other by electrically connecting the first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting the second terminal of the fourth circuit to the control terminal of the first switch.

[0018] (7) Alternatively, according to one aspect of the present invention, in the above configuration (5) or (6), a second terminal of the first capacitor may be electrically connected to a gate of the second transistor.

[0019] (8) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (7), a transistor included in the second circuit may have a metal oxide in a channel formation region.

[0020] (9) Alternatively, one embodiment of the present invention is a semiconductor device including a first circuit and a fifth circuit. The first circuit includes a first current source, a second current source, a first switch, a fifth transistor, and a sixth transistor, and the fifth circuit includes a seventh transistor, an eighth transistor, a second capacitance, a second switch, a third switch, and a current comparison circuit. It is preferable that an output terminal of the first current source is electrically connected to a first terminal of the first switch, and an output terminal of the second current source is electrically connected to a gate of the fifth transistor, a gate of the sixth transistor, and a first terminal of the sixth transistor. It is also preferable that a first terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor, a first terminal of the second switch, and a first terminal of the third switch, and a gate of the seventh transistor is electrically connected to a second terminal of the eighth transistor and a first terminal of the second capacitance. It is also preferable that the second terminal of the first switch is electrically connected to the second terminal of the second switch, the first terminal of the current comparison circuit is electrically connected to the second terminal of the third switch, and the second terminal of the current comparison circuit is electrically connected to the first terminal of the fifth transistor.

[0021] (10) Alternatively, one embodiment of the present invention is a semiconductor device having a first circuit and a fifth circuit, and different from the semiconductor device of (9) above. The first circuit has a first current source, a third current source, a first switch, and a fourth switch, and the fifth circuit has a seventh transistor, an eighth transistor, a second capacitance, a second switch, a third switch, a fifth switch, and a current comparison circuit. It is preferable that an output terminal of the first current source is electrically connected to a first terminal of the first switch, and an input terminal of the third current source is electrically connected to a first terminal of the fourth switch. It is also preferable that a first terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor, a first terminal of the second switch, and a first terminal of the third switch, and a gate of the seventh transistor is electrically connected to a second terminal of the eighth transistor and a first terminal of the second capacitance. It is preferable that a second terminal of the first switch is electrically connected to a second terminal of the second switch, and a second terminal of the fourth switch is electrically connected to a first terminal of the fifth switch. Preferably, the first terminal of the current comparison circuit is electrically connected to the second terminal of the third switch, and the second terminal of the current comparison circuit is electrically connected to the second terminal of the fifth switch.

[0022] (11) Alternatively, in one embodiment of the present invention, in the above-mentioned (9) or (10), the seventh transistor may have silicon in a channel formation region, and the eighth transistor may have a metal oxide in a channel formation region.

[0023] (12) Alternatively, in one aspect of the present invention, in the above (10), the fifth circuit may include a ninth transistor, a tenth transistor, a third capacitance, and a sixth switch. It is preferable that a first terminal of the ninth transistor is electrically connected to a first terminal of the tenth transistor, a first terminal of the second switch, and a first terminal of the sixth switch, and a gate of the ninth transistor is electrically connected to a second terminal of the tenth transistor and a first terminal of the third capacitance. It is also preferable that a second terminal of the sixth switch is electrically connected to a first terminal of the fifth switch and a second terminal of the fourth switch. It is preferable that a gate of the eighth transistor and a gate of the tenth transistor are not directly connected.

[0024] (13) Alternatively, in one embodiment of the present invention, in the above-mentioned (12), the seventh transistor and the ninth transistor each have silicon in a channel formation region, and the eighth transistor and the tenth transistor each have metal oxide in a channel formation region.

[0025] (14) Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of (1) to (13) above and a housing.

[0026] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may themselves be a semiconductor device or may have a semiconductor device.

[0027] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in a figure or text other than the connection relationship shown in the figure or text. X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0028] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0029] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0030] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0031] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these expressions. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0032] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0033] In addition, in this specification, the term "resistance element" may be, for example, a circuit element having a resistance value higher than 0Ω, a wiring having a resistance value higher than 0Ω, etc. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, etc. Therefore, the term "resistance element" may be rephrased as "resistance", "load", "region having a resistance value", etc. Conversely, the terms "resistance", "load", and "region having a resistance value" may be rephrased as "resistance element", etc. The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0034] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" includes a circuit element including a pair of electrodes and a dielectric included between the electrodes. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like may be rephrased as "capacitance". Conversely, the term "capacitance" may be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" may be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the capacitance may be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0035] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode or the first terminal) and "the other of the source or drain" (or the second electrode or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or the backgate of the transistor may be referred to as the first gate, and the other of the gate or the backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0036] For example, in this specification and the like, as an example of a transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used. In the case of a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which a plurality of transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the breakdown voltage of the transistor (improve reliability). Alternatively, the multi-gate structure can obtain a voltage-current characteristic with a flat slope, in which the current between the drain and source does not change much even if the voltage between the drain and source changes when operating in the saturation region. By utilizing the voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0037] In addition, even when a single circuit element is illustrated on a circuit diagram, the circuit element may have multiple circuit elements. For example, when one resistor is illustrated on a circuit diagram, this includes the case where two or more resistors are electrically connected in series. For example, when one capacitance is illustrated on a circuit diagram, this includes the case where two or more capacitances are electrically connected in parallel. For example, when one transistor is illustrated on a circuit diagram, this includes the case where two or more transistors are electrically connected in series and the gates of the respective transistors are electrically connected to each other. Similarly, when one switch is illustrated on a circuit diagram, this includes the case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel, and the gates of the respective transistors are electrically connected to each other.

[0038] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0039] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0040] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0041] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is described as a positive current amount. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0042] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0043] In addition, in this specification, the terms indicating the arrangement, such as "above" and "below", may be used for convenience in order to explain the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0044] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0045] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using them. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0046] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes", "wirings", and the like are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring", "electrode", and the like, and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", and for example, a "terminal" can be a part of a "wiring" or an "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0047] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0048] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, a transition metal other than the main component, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is a silicon layer, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 15 element, and the like (however, oxygen and hydrogen are not included).

[0049] In this specification and the like, a switch refers to a device that has a function of controlling whether or not a current flows by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. Therefore, a switch may have two or three or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be regarded as being electrically short-circuited, a state in which a current can flow between the source electrode and drain electrode, etc. In addition, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be regarded as being electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (Microelectromechanical Systems) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0052] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Effect of the Invention

[0053] According to one embodiment of the present invention, a semiconductor device or the like that performs a product-sum operation and / or a function operation can be provided. According to one embodiment of the present invention, a semiconductor device that rewrites data held in a multiplication cell can be provided. According to one embodiment of the present invention, a semiconductor device that holds a digital value, performs digital-to-analog conversion on the digital value, and performs an operation using the analog value can be provided. According to one embodiment of the present invention, a semiconductor device or the like that performs convolution processing such as CNN can be provided. According to one embodiment of the present invention, a semiconductor device or the like for AI can be provided. According to one embodiment of the present invention, a semiconductor device or the like for DNN can be provided. According to one embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the influence of environmental temperature can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the influence of characteristic variations in transistors can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to the influence of characteristic variations in a current source can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

[0054] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief description of the drawings]

[0055] 1A and 1B are block diagrams showing a configuration example of a semiconductor device, and FIG. 1C is a perspective view showing the configuration example of a semiconductor device. 2A to 2C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. FIG. 3 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 4 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 5 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 6 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. 7A to 7E are circuit diagrams showing configuration examples of circuits included in a semiconductor device. FIG. 8 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 9 is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 10A is a circuit diagram showing a configuration example of a circuit included in a semiconductor device, and FIGS. 10B to 10E are circuit diagrams showing configuration examples of memory cells included in the semiconductor device. FIG. 11 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 12 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 13 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 14A is a circuit diagram showing a configuration example of a circuit included in a semiconductor device, and FIG. 14B is a circuit diagram showing a configuration example of a part of the circuit included in the circuit. FIG. 15 is a block diagram showing a configuration example of a semiconductor device. FIG. 16 is a block diagram showing a configuration example of a semiconductor device. FIG. 17A is a block diagram showing a configuration example of a semiconductor device, and FIG. 17B is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. 18A to 18D are circuit diagrams showing configuration examples of a semiconductor device. FIG. 19 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 20A is a circuit diagram showing a configuration example of a semiconductor device, and FIG. 20B is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIG. 21A is a circuit diagram showing a configuration example of a semiconductor device, and FIG. 21B is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. 22A and 22B are circuit diagrams showing configuration examples of a semiconductor device. FIG. 23 is a block diagram showing a configuration example of a semiconductor device. 24A and 24B are diagrams illustrating a hierarchical neural network. FIG. 25 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 26 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. 27A to 27C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. FIG. 28 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. 29A to 29F are circuit diagrams showing configuration examples of circuits included in a semiconductor device. FIG. 30 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 31 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 32 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. 33A to 33E are circuit diagrams showing configuration examples of circuits included in a semiconductor device. 34A to 34C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. FIG. 35 is a schematic cross-sectional view showing a configuration example of a semiconductor device. 36A to 36C are schematic cross-sectional views illustrating configuration examples of transistors. FIG. 37 is a schematic cross-sectional view showing a configuration example of a semiconductor device. 38A and 38B are schematic cross-sectional views showing configuration examples of a transistor. FIG. 39 is a schematic cross-sectional view illustrating a configuration example of a transistor. FIG. 40A is a diagram for explaining the classification of IGZO crystal structures, FIG. 40B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 40C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. FIG. 41A is a perspective view showing an example of a semiconductor wafer, FIG. 41B is a perspective view showing an example of a chip, and FIGS. 41C and 41D are perspective views showing an example of an electronic component. FIG. 42 is a schematic diagram illustrating an example of an electronic device. 43A to 43C are schematic diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] In an artificial neural network (hereafter referred to as a neural network), the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining the strength of connections is sometimes called "learning."

[0057] In addition, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), it is possible for the network to output new information based on the connection strengths. In this way, the process of outputting new information based on given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0058] Examples of neural network models include the Hopfield type and hierarchical type. In particular, a neural network with a multi-layer structure is sometimes called a "deep neural network" (DNN), and machine learning using a deep neural network is sometimes called "deep learning."

[0059] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is included in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0060] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0061] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0062] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0063] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0064] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0065] The embodiments described in this specification are described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in perspective views, etc., the description of some components may be omitted in order to ensure the clarity of the drawings.

[0066] In this specification, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification reference numeral such as "_1", "[n]", "[m,n]" may be added to the reference numeral. In addition, when an identification reference numeral such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., when it is not necessary to distinguish between them in this specification, the identification reference numeral may not be added.

[0067] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0068] (Embodiment 1) In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described.

[0069] <Configuration Example 1 of Semiconductor Device> 1A is a block diagram showing a configuration example of a semiconductor device SDV1 according to one embodiment of the present invention. As an example, the semiconductor device SDV1 includes a memory device MINT, a circuit ILD, and a calculation unit CLP. In addition, in order to show the configuration of electrical connections with the semiconductor device SDV1, a memory device MEXT is also shown in FIG. 1A.

[0070] As an example, the memory device MEXT is provided outside the semiconductor device SDV1. In this embodiment, the memory device MEXT holds data for performing calculations in the calculation unit CLP. The memory device MEXT also transmits the data to the memory device MINT as a digital voltage signal or the like. The memory device MEXT may also transmit the data not only to the memory device MINT but also to a circuit ILD, which will be described later. In other words, the semiconductor device SDV1 may be configured to be able to switch between the memory device MINT and the circuit ILD as the destination of the memory device MEXT.

[0071] Furthermore, when the semiconductor device SDV1 is configured to be able to switch between the memory device MINT and the circuit ILD as the destination of the signal output from the memory device MEXT, when data is transmitted from the memory device MEXT to the memory device MINT, the number of bits of the data may be reduced in order to reduce the memory capacity of the memory device MINT. Also, when data is transmitted from the memory device MEXT to the circuit ILD, the number of bits of the data may be increased. Alternatively, when data is transmitted from the memory device MEXT to the memory device MINT, in order to reduce the memory capacity of the memory device MINT, the high-bit value of the data may be transmitted, and if the low-bit value becomes necessary, the low-bit value may be input from the memory device MEXT to the circuit ILD. In other words, data may be input to the circuit ILD from the memory device MINT and the memory device MEXT at the same time.

[0072] Incidentally, the memory device MEXT can be, for example, a storage such as an HDD (hard disk drive) or an SSD (solid state drive).

[0073] The semiconductor device SDV1 can be fabricated, for example, by forming circuit elements and the like on one substrate BSE.

[0074] As the substrate BSE, for example, various substrates can be used. Examples of various substrates include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, base films, and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, an example is a synthetic resin such as acrylic. Alternatively, an example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor with small variations in characteristics, size, shape, and the like, high current capability, and small size. By configuring a circuit using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

[0075] Alternatively, a flexible substrate may be used as the substrate BSE, and the transistors may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors. The peeling layer can be used to separate the semiconductor device from the substrate after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, the transistors can be transferred to a substrate having poor heat resistance, a flexible substrate, or the like. For the peeling layer, for example, a laminated structure of inorganic films of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate, can be used.

[0076] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on yet another substrate (e.g., substrate BSE). Examples of substrates onto which transistors may be transferred include, in addition to the substrates on which the above-mentioned transistors may be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, impart heat resistance, and reduce weight or thickness.

[0077] It is possible to form all of the circuits required to realize a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). This makes it possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connections to the circuit components.

[0078] It is possible that all of the circuits required to realize the predetermined function are not formed on the same substrate. That is, a part of the circuit required to realize the predetermined function is formed on one substrate, and another part of the circuit required to realize the predetermined function is formed on another substrate. For example, a part of the circuit required to realize the predetermined function is formed on a glass substrate, and another part of the circuit required to realize the predetermined function is formed on a single crystal substrate (or an SOI substrate). Then, the single crystal substrate (also called an IC chip) on which another part of the circuit required to realize the predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass), and the IC chip can be arranged on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, by forming a part of the circuit on the same substrate as the pixel portion, it is possible to reduce the cost by reducing the number of components, or to improve the reliability by reducing the number of connections with the circuit components. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, such circuits are formed on a substrate (such as a single crystal substrate) separate from the pixel section to form an IC chip. By using this IC chip, it is possible to prevent an increase in power consumption.

[0079] For example, by making the substrate BSE a semiconductor substrate containing silicon, the transistors included in the arithmetic unit CLP and the transistors included in the circuit ILD can be formed as Si transistors on the substrate BSE. Also, by making the transistors included in the memory device MINT OS transistors, the memory device MINT can be provided above the arithmetic unit CLP and / or the circuit ILD. That is, as an example, the semiconductor device SDV1 can be configured as shown in FIG. 1C, in which the arithmetic unit CLP and the circuit ILD are provided above the substrate BSE, and the memory device MINT is provided above the arithmetic unit CLP and the circuit ILD.

[0080] The memory device MINT provided in the semiconductor device SDV1 has a function of acquiring information read by a memory device MEXT provided outside the semiconductor device SDV1 and holding the information, for example. The memory device MINT also has a function of reading information held in the memory device MINT and transmitting the information to the circuit ILD. The information sent from the memory device MEXT to the memory device MINT is treated as data for performing calculations by a calculation unit CLP described later.

[0081] In this specification, the memory device MINT is described as a configuration that stores digital values. By configuring the memory device MINT as a memory device that stores data as digital values, even if the absolute value of the charge amount held in the memory element decreases, the range of potential from which data can be read is large, so that data that is the same as when it was written can be read. In addition, in the case of a memory device that stores data as digital values, it is easy to refresh the data stored in the memory element, so the potential (charge) held in the memory element can be maintained for a long time. Therefore, it is preferable that the memory device MINT has a function of periodically refreshing the data stored therein. In addition, a refresh operation may be performed after transmitting data to a calculation unit CLP (circuit ILD) described later. In addition, in this specification, data refresh refers to an operation of reading a voltage corresponding to the data of the memory element, boosting or lowering the voltage to an appropriate level by an amplifier circuit such as a sense amplifier, and writing the voltage back to the memory element. In addition, when data in a memory cell of the memory device MINT is appropriately rewritten, data may be read from the memory device MEXT and written to the memory cell. In addition, the memory device MINT according to the semiconductor device of the present invention may be configured to store not only digital values ​​but also multi-values, analog values, etc. Also, for example, if the memory cell of the memory device MINT is configured to be able to hold multiple values ​​(multiple bits), by making the number of bits of the memory cell smaller than the number of bits held in the multiplication cell of the calculation unit CLP, multiple memory cells of the memory device MINT can be made to correspond to one multiplication cell of the calculation unit CLP. For example, if each memory cell of the memory device MINT can hold a 4-bit value and each multiplication cell of the calculation unit CLP can hold an 8-bit value, an 8-bit value can be written to the multiplication cell of the calculation unit CLP by writing two 4-bit values ​​to the memory cell of the memory device MINT.

[0082] Incidentally, as the transistor included in the memory device MINT, for example, it is preferable to apply an OS transistor. In particular, as the metal oxide included in the channel formation region of the OS transistor, for example, an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) is preferable. In addition, as the transistor, a transistor having silicon in the channel formation region (hereinafter, referred to as a Si transistor) may be applied. In addition, as the silicon, for example, single crystal silicon, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, etc. can be used. In addition, examples of transistors that can be used other than OS transistors and Si transistors include transistors that include Ge or the like in a channel formation region, transistors that include a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, transistors that include carbon nanotubes in a channel formation region, and transistors that include an organic semiconductor in a channel formation region.

[0083] As an example, the circuit ILD functions as a current source circuit for supplying a current to the calculation unit CLP. Specifically, the circuit ILD supplies a current corresponding to information read from the memory device MINT to a circuit included in the calculation unit CLP. Note that the circuit ILD may be a voltage source circuit (voltage generating circuit) for inputting a voltage corresponding to information read from the memory device MINT to the calculation unit CLP, instead of a current source circuit for supplying a current to the calculation unit CLP.

[0084] The calculation unit CLP has a plurality of circuits that function as multiplication cells. The multiplication cells, as an example, have a function of holding data used in calculation as an analog value. In the calculation unit CLP, the circuits are arranged in a matrix. After holding information (e.g., current, voltage, etc.) sent from the circuit ILD, the circuit can input a voltage corresponding to a multiplier to the calculation unit CLP to calculate the product of a value corresponding to the information and the multiplier. When the product calculated by the circuit is output as a current, the current sum can be an amount corresponding to the sum of the products of the information (e.g., current, voltage, etc.) held in the multiple circuits and the multiple multipliers by adding up the currents output from the multiple circuits. The calculation unit CLP also includes a drive circuit for operating the multiplication cells. The circuit configuration of the calculation unit CLP and the principle of the product-sum calculation in the calculation unit CLP will be described in detail in the second embodiment.

[0085] Incidentally, when the memory device MINT has a function of holding a digital value and the multiplication cell of the calculation unit CLP has a function of holding an analog value, it is necessary to perform digital-to-analog conversion when transmitting data used for calculation from the memory device MINT to the calculation unit. In this case, it is preferable that the circuit ILD has not only a current source circuit but also a digital-to-analog conversion circuit function. Also, the larger the analog data written to the calculation unit CLP, the larger the memory capacity required for the memory device MINT. Specifically, for example, when data corresponding to an 8-bit numerical value is held in one multiplication cell in the calculation unit CLP, eight binary memory cells are required in the memory device MINT. In this case, since it is necessary to increase the circuit area of ​​the memory device MINT, it is preferable that the semiconductor device SDV1 is configured such that the memory device MINT is provided above the calculation unit CLP (including a circuit for driving the calculation unit CLP) and the circuit ILD, as shown in FIG. 1C described above. Also, the area of ​​each memory cell can be reduced by applying a trench type as a capacity that can be provided in the memory cell of the memory device MINT.

[0086] Furthermore, when the multiplication cell of the calculation unit CLP has a function of holding an analog value, the analog data held in the multiplication cell may deteriorate due to a leak current from the multiplication cell. For this reason, it is preferable that the semiconductor device SDV1 periodically converts the digital data held in the memory device MINT (the same value as the data held in the multiplication cell) from the memory device MINT into analog data by the circuit ILD, transmits the analog data to the calculation unit CLP, and writes it again in the memory element of the multiplication cell of the calculation unit CLP (inputs a current, a voltage, or the like, or replenishes a charge). At this time, the memory device MINT functions as a circuit that holds digital data equivalent to the analog data in order to compensate for the analog data held in the memory element of the multiplication cell of the calculation unit CLP. Furthermore, with such a configuration, the memory device MINT may be referred to as a main memory for the calculation unit CLP. Furthermore, in this case, the memory element provided in the multiplication cell of the calculation unit CLP can be considered as a temporary memory. Also, for example, if the memory cell MCL of the memory device MINT is a circuit capable of holding digital data (2 bits) and the multiplication cell of the calculation unit CLP is a circuit capable of holding analog data equivalent to 8 bits, the memory cell MCL of the memory device MINT can hold data longer than the multiplication cell of the calculation unit CLP (because the value of the data is less likely to change due to a decrease in the absolute value of the charge amount caused by the leakage current), so it is preferable to treat the memory device MINT as a main memory. Also, since calculations that handle analog data have higher calculation efficiency than calculations that handle digital data, it is preferable for the semiconductor device SDV1 to be configured to convert digital data read from the memory device MINT into analog data and perform calculations that handle the analog data in the calculation unit CLP.

[0087] Furthermore, the semiconductor device SDV1 may have a plurality of arithmetic units CLP. For example, as shown in Fig. 1B, the semiconductor device SDV1 may have arithmetic units CLPa and CLPb instead of the arithmetic unit CLP in Fig. 1A. In this way, by providing a plurality of arithmetic units in the semiconductor device SDV1, the semiconductor device SDV1 can write data transmitted from the memory device MINT to one of the arithmetic units CLPa or CLPb, and during that time, perform a calculation in the other of the arithmetic units CLPa or CLPb.

[0088] 1B, one of the calculation units CLPa and CLPb may be a circuit that performs analog calculations, and the other of the calculation units CLPa and CLPb may be a circuit that performs digital calculations.Also, both the calculation units CLPa and CLPb may be circuits that perform digital calculations.

[0089] <<Circuit ILD>> Here, a specific example of the circuit configuration of the circuit ILD will be described. Note that here, a VI conversion circuit (sometimes called a digital-to-analog conversion circuit) that outputs an analog current based on a digital value read from a memory device MINT will be described as the circuit ILD. The circuit ILD shown in FIG. 2A is an example of a current source circuit that can be applied to the circuit ILD in FIG. 1A. The circuit ILD in FIG. 2A has a circuit WCS1, which has constant current sources CC[1] to CC[K] (K is an integer equal to or greater than 1) and switches SW[1] to SW[K].

[0090] An input terminal of the constant current source CC[u] (u is an integer between 1 and K) is electrically connected to the wiring VDL, an output terminal of the constant current source CC[u] is electrically connected to a first terminal of the switch SW[u], a second terminal of the switch SW[u] is electrically connected to the wiring IL, and a control terminal of the switch SW[u] is electrically connected to the wiring DIL[u].

[0091] The wirings DIL[1] to DIL[K] shown in Fig. 2A are electrically connected to the memory device MINT included in the semiconductor device SDV1 in Fig. 1A. That is, the wirings DIL[1] to DIL[K] function as wirings for transmitting information read from the memory device MINT.

[0092] The line VDL functions as, for example, a line that applies a constant voltage, which is preferably, for example, a high-level potential.

[0093] The wiring IL functions as a wiring for electrically connecting to the operation unit CLP. That is, the wiring IL functions as a wiring for passing a current corresponding to the information held in the memory device MINT, which is generated in the circuit ILD, to the operation unit CLP. The wiring IL functions as, for example, a write data line extending to the operation unit CLP. Therefore, when the operation unit CLP has a plurality of columns of multiplication cells, it is preferable that the circuit ILD has a plurality of circuits WCS1. Also, depending on the configuration of the operation unit CLP, two write data lines may be provided in a plurality of multiplication cells arranged in one column. Therefore, in FIG. 2A, one of the wirings is illustrated as the wiring IL, and the other wiring is illustrated in parentheses as the wiring ILB.

[0094] The circuit WCS1 in FIG. 2A is, as an example, K The circuit WCS1 has a function of outputting information on the uth bit value (K is an integer equal to or greater than 1) as a current. Specifically, for example, information corresponding to the 1st bit value is input to the wiring DIL[1], information corresponding to the uth bit value is input to the wiring DIL[u], and information corresponding to the Kth bit value is input to the wiring DIL[K], thereby enabling the circuit WCS1 to determine the amount of current to be passed through the wiring IL. At this time, the constant current passed by the constant current source CC[1] is referred to as I ut Then, the constant current flowing from the constant current source CC[u] is 2 u-1 ×I ut The constant current flowing from the constant current source CC[K] is 2 K-1 ×I ut It is preferable to set the above.

[0095] A decoder DEC for converting binary numbers to decimal numbers may be provided between the memory device MINT and the circuit ILD. The circuit configuration of the circuit ILD in this case is shown in FIG. 2B. In FIG. 2B, the circuit WCS2 included in the circuit ILD includes constant current sources CC[1] to CC[2]. K -1] and switch SW[1] to switch SW[2 K -1].

[0096] The decoder DEC is electrically connected to the wirings DIL[1] to DIL[K], and is also connected to the wirings DEL[1] to DEL[2 K -1]. In addition, the constant current source CC[t] (t is 1 or more, 2 K An input terminal of the constant current source CC[t] is electrically connected to a wiring VDL, an output terminal of the constant current source CC[t] is electrically connected to a first terminal of the switch SW[t], and a second terminal of the switch SW[t] is electrically connected to a wiring IL. In addition, a control terminal of the switch SW[t] is electrically connected to a wiring DEL[t].

[0097] The decoder DEC converts the K-bit (binary) information sent to the wirings DIL[1] to DIL[K] into decimal information and outputs it to the wirings DEL[1] to DEL[2]. K -1].

[0098] The circuit WCS2 of FIG. 2B is, as an example, a K-bit (2 K However, since the circuit WCS2 receives information converted to a decimal number by the decoder DEC, the constant current sources CC[1] to CC[2 K -1] flows a constant current of I ut It is preferable to set the above.

[0099] The constant current source CC included in the circuit WCS1 of Fig. 2A and the circuit WCS2 of Fig. 2B may be configured to have, for example, a transistor. Also, the switch SW included in the circuit WCS1 of Fig. 2A and the circuit WCS2 of Fig. 2B may be, for example, an electrical switch such as an analog switch or a transistor. Also, the switch SW may be, for example, a mechanical switch.

[0100] In this specification and the like, the switch SW is assumed to be in an off state when a high-level potential is applied to the control terminal, and in an on state when a low-level potential is applied to the control terminal.

[0101] A specific example of the above is shown in Fig. 2C. The circuit ILD in Fig. 2C has a circuit configuration in which, for example, in the circuit ILD in Fig. 2A, the constant current source CC[1] has a transistor CTr[1], the constant current source CC[u] has a transistor CTr[u], for example, the constant current source CC[K] has a transistor CTr[K], the switch SW[1] has a transistor STr[1], the switch SW[u] has a transistor STr[u], and the switch SW[K] has a transistor STr[K].

[0102] It is preferable to use Si transistors as each of the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] shown in Fig. 2C. In addition, as transistors other than Si transistors, for example, transistors including Ge or the like in a channel formation region, transistors including compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe in a channel formation region, transistors including carbon nanotubes in a channel formation region, transistors including organic semiconductors in a channel formation region, and the like can be used.

[0103] 2C, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] are p-channel transistors, for example. Depending on the circumstances or situation, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] may be n-channel transistors. When the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] are n-channel transistors, the transistors CTr[1] to CTr[K] and the transistors STr[1] to STr[K] may be OS transistors.

[0104] For example, the first terminal of the transistor CTr[1] is electrically connected to the wiring VDL, the second terminal of the transistor CTr[1] is electrically connected to the first terminal of the transistor STr[1], and the second terminal of the transistor STr[1] is electrically connected to the wiring IL. The gate of the transistor CTr[1] is electrically connected to the wiring BIAL, and the gate of the transistor STr[1] is electrically connected to the wiring DIL[1]. For example, the first terminal of the transistor CTr[u] is electrically connected to the wiring VDL, the second terminal of the transistor CTr[u] is electrically connected to the first terminal of the transistor STr[u], and the second terminal of the transistor STr[u] is electrically connected to the wiring IL. The gate of the transistor CTr[u] is electrically connected to the wiring BIAL, and the gate of the transistor STr[u] is electrically connected to the wiring DIL[u]. For example, a first terminal of the transistor CTr[K] is electrically connected to the wiring VDL, a second terminal of the transistor CTr[K] is electrically connected to the first terminal of the transistor STr[K], and a second terminal of the transistor STr[K] is electrically connected to the wiring IL. A gate of the transistor CTr[K] is electrically connected to the wiring BIAL, and a gate of the transistor STr[K] is electrically connected to the wiring DIL[K].

[0105] For example, the wiring BIAL functions as a wiring that applies a constant voltage. Since the wiring BIAL is electrically connected to the gates of the transistors CTr[1] to CTr[K], the constant voltage functions as a bias voltage for causing a current to flow through each of the transistors CTr[1] to CTr[K]. The bias voltage is preferably, for example, a low-level potential or a ground potential.

[0106] In the case of the circuit ILD of FIG. 2C, when the ratio of the channel width (hereinafter referred to as W length) to the channel length (hereinafter referred to as L length) of the transistor CTr[1] is W / L, the ratio of the W length to the L length of the transistor CTr[u] is 2 u-1 ×W / L or a value close to it. The ratio of the W length to the L length of the transistor CTr[K] is preferably 2 K-1 × W / L or a value close to that. As a result, the ratio of the currents flowing through the transistors CTr[1], CTr[u], and CTr[K] is approximately 1:2. u-1 :2 K-1 In addition, 2 u-1 × W / L is, for example, 2 u-1 × W / L. K-1 × W / L is, for example, 2 K-1 × W / L.

[0107] Or, in the circuit ILD of FIG. 2C, the transistor CTr[u] is 2 u-1 Alternatively, the transistor CTr[K] may be replaced with a configuration in which two transistors having the same structure are electrically connected in parallel and the gates of the transistors are electrically connected to the wiring DIL[u]. K-1Alternatively, the transistors may be electrically connected in parallel, and the gates of the transistors may be electrically connected to the wiring DIL[K]. As a result, the ratio of the currents flowing through the transistors CTr[1], CTr[u], and CTr[K] is approximately 1:2. u-1 :2 K-1 It becomes.

[0108] Incidentally, unless otherwise specified, the transistor CTr is considered to ultimately operate in the saturation region when it is on. In other words, the gate voltage, source voltage, and drain voltage of the transistor CTr are considered to include a case where the transistor CTr is appropriately biased to a voltage within a range in which the transistor CTr operates in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude value of the supplied voltage, the transistor CTr may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistor CTr, the transistor CTr may operate in a subthreshold region. Alternatively, the transistor CTr may be operated near the boundary between the saturation region and the subthreshold region. In this specification and the like, the vicinity of the boundary between the saturation region and the subthreshold region may be, for example, a threshold voltage of the transistor V th When the gate-source voltage is V th -1.0V or more, V th -0.5V or more, or V th -0.1V or more and V th +0.1V or less, V th +0.5V or less, or V th This includes the case where the input voltage is +1.0V or less. Note that the above-mentioned lower limit value and upper limit value can be combined with each other. Alternatively, for example, the transistor CTr may operate in a linear region, a saturation region, and a subthreshold region, or may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a linear region and a subthreshold region.

[0109] In this specification and the like, unless otherwise specified, the transistor STr includes a case where it finally operates in a linear region when it is in an on state. That is, the gate voltage, source voltage, and drain voltage of the transistor STr include a case where they are appropriately biased to voltages in a range where the transistor STr operates in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistor STr may operate in a saturation region or a subthreshold region when it is in an on state. Alternatively, the transistor STr may operate near the boundary between the saturation region and the subthreshold region. Alternatively, the transistor STr may operate in a linear region and a saturation region in a mixed state, or may operate in a saturation region and a subthreshold region in a mixed state, or may operate in a linear region, a saturation region, and a subthreshold region in a mixed state.

[0110] Note that the circuit ILD may be, for example, a digital-to-analog conversion circuit using an operational amplifier, instead of the configurations of Figures 2A to 2C. Note that, in order to reduce power consumption, it is preferable to use the VI conversion circuit having the configurations of Figures 2A to 2C.

[0111] <<Configuration example 1 of memory device MINT and circuit ILD>> Next, the memory device MINT and the electrical connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP will be described.

[0112] FIG. 3 is a circuit configuration example showing the memory device MINT, a part of the circuit ILD in FIG. 2A described above, and a part of the calculation unit CLP.

[0113] 3 is, by way of example, a part of the arithmetic circuit 110 described in the second embodiment. Therefore, for details of the arithmetic unit CLP shown in FIG. 3, the description of the second embodiment should be referred to.

[0114] 3, two write data lines are provided in a plurality of multiplication cells arranged in one column. One of the write data lines, the wiring IL, is electrically connected to a circuit WCS1 included in the circuit ILD. Although the electrical connection between the other write data line, the wiring ILB, and the circuit ILD is not shown, the wiring ILB is electrically connected to a circuit WCS1 different from the wiring IL.

[0115] The memory device MINT has a configuration including a memory circuit called NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) (registered trademark). Specifically, in Fig. 3, the memory device MINT includes memory cells MCL[1] to MCL[m] (m is an integer of 1 or more), a switch RSW, a circuit WWD, and a circuit RWD, and each of the memory cells MCL[1] to MCL[m] includes a transistor F1 to a transistor F3 and a capacitance CI.

[0116] As described above, each of the transistors F1 to F3 can be an OS transistor. Alternatively, each of the transistors F1 to F3 can be a Si transistor. As a transistor other than an OS transistor or a Si transistor, for example, a transistor including Ge or the like in a channel formation region, a transistor including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, a transistor including a carbon nanotube in a channel formation region, a transistor including an organic semiconductor in a channel formation region, or the like can be used.

[0117] In addition, by using an OS transistor as the transistor included in the memory device MINT and an OS transistor as the transistor included in the computing unit CLP, the OS transistors may be fabricated simultaneously in the same process. By fabricating the OS transistors included in the memory device MINT and the computing unit CLP simultaneously, the fabrication time of the semiconductor device SDV1 can be shortened.

[0118] Unless otherwise specified, the transistor F1 includes a case where it finally operates in the saturation region when it is on. That is, the gate voltage, source voltage, and drain voltage of the transistor F1 include a case where the transistor F1 is appropriately biased to a voltage in a range where the transistor F1 operates in the saturation region. However, one embodiment of the present invention is not limited to this. In order to reduce the amplitude value of the voltage supplied, the transistor F1 may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistor F1, the transistor F1 may operate in a subthreshold region. Alternatively, the transistor F1 may operate near the boundary between the saturation region and the subthreshold region. Alternatively, for example, the transistor F1 may operate in a linear region, a saturation region, and a subthreshold region, or may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a linear region and a subthreshold region.

[0119] In this specification and the like, unless otherwise specified, the transistors F2 and F3 are considered to ultimately operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include a case where they are appropriately biased to a voltage within a range in which they operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors F2 and F3 may operate in a saturation region or a subthreshold region when they are on. Alternatively, the transistors F2 and F3 may be operated near the boundary between the saturation region and the subthreshold region. Alternatively, the transistors F2 and F3 may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a linear region, a saturation region, and a subthreshold region, or may operate in a linear region and a subthreshold region.

[0120] The switch RSW may be, for example, an electrical switch such as an analog switch, a transistor, etc. The switch SW may be, for example, a mechanical switch.

[0121] In this specification and the like, the switch RSW is assumed to be in an on state when a high-level potential is applied to the control terminal, and in an off state when a low-level potential is applied to the control terminal.

[0122] As an example, the memory device MINT can be configured to have memory cells MCL arranged in a matrix. For example, the memory device MINT can be configured to have multiple columns of memory cells MCL[1] to MCL[m] arranged in one column. Note that in the memory device MINT of FIG. 3, the memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are illustrated here.

[0123] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to the wiring DIL[u]. That is, the memory cells MCL[1] to MCL[m] in the u-th column are electrically connected to the switch SW[u] of the circuit WCS1 included in the circuit ILD.

[0124] In the memory cell MCL[1], the first terminal of the transistor F1 is electrically connected to the wiring VEA, the second terminal of the transistor F1 is electrically connected to the first terminal of the transistor F3, and the gate of the transistor F1 is electrically connected to the first terminal of the transistor F2 and the first terminal of the capacitance CI. The second terminal of the transistor F2 is electrically connected to the wiring WBL[u], and the gate of the transistor F2 is electrically connected to the wiring WWL[1]. The second terminal of the transistor F3 is electrically connected to the wiring RBL[u], and the gate of the transistor F3 is electrically connected to the wiring RWL[1]. The second terminal of the capacitance CI is electrically connected to the wiring VEA.

[0125] In the memory cell MCL[m], the first terminal of the transistor F1 is electrically connected to the wiring VEA, the second terminal of the transistor F1 is electrically connected to the first terminal of the transistor F3, and the gate of the transistor F1 is electrically connected to the first terminal of the transistor F2 and the first terminal of the capacitance CI. The second terminal of the transistor F2 is electrically connected to the wiring WBL[u], and the gate of the transistor F2 is electrically connected to the wiring WWL[m]. The second terminal of the transistor F3 is electrically connected to the wiring RBL[u], and the gate of the transistor F3 is electrically connected to the wiring RWL[m]. The second terminal of the capacitance CI is electrically connected to the wiring VEA.

[0126] The wirings WWL[1] to WWL[m] are electrically connected to the circuit WWD. The wirings RWL[1] to RWL[m] are electrically connected to the circuit RWD.

[0127] The wiring RBL[u] is electrically connected to a first terminal of the switch RSW and the wiring DIL[u]. The second terminal of the switch RSW is electrically connected to the wiring VDL2. The control terminal of the switch RSW is electrically connected to the wiring SL11.

[0128] The wirings WWL[1] to WWL[m] function as write word lines for the memory cells MCL[1] to MCL[m], respectively. The circuit WWD is a driver circuit that selects a memory cell to be written to and has a function of transmitting a selection signal for writing to any one of the wirings WWL[1] to WWL[m].

[0129] The wirings RWL[1] to RWL[m] function as read word lines for the memory cells MCL[1] to MCL[m], respectively. The circuit RWD is a driver circuit that selects a memory cell from which data is to be read, and has a function of transmitting a selection signal for reading to any one of the wirings RWL[1] to RWL[m].

[0130] The wiring WBL[u] functions as a write data line (sometimes called a write bit line) in the memory cells MCL[1] to MCL[m]. Note that the wiring WBL[u] is electrically connected to the memory device MEXT in order for the memory device MINT to hold information sent from the memory device MEXT in Fig. 1. In other words, the wiring WBL[u] functions as a wiring for transmitting information read from the memory device MEXT to the memory device MINT.

[0131] The wiring RBL[u] functions as a read data line (sometimes referred to as a read bit line) in the memory cells MCL[1] to MCL[m].

[0132] The wiring VDL2 functions as a wiring for precharging the wiring RBL[u] with a predetermined potential before reading data stored in any one of the memory cells MCL[1] to MCL[m] of the memory device MINT. Therefore, the wiring VDL2 is preferably a wiring for applying a constant voltage. In addition, the constant voltage (voltage for precharging the wiring RBL[u]) can be, for example, a high-level potential.

[0133] For example, the wiring VEA functions as a wiring that applies a source potential to the first terminal of the transistor F1. Therefore, it is preferable that the wiring VEA is a wiring that applies a constant voltage. In addition, the constant voltage (voltage to be precharged to the wiring RBL[u]) can be, for example, a low-level potential.

[0134] Moreover, the wiring VEA functions as a wiring that provides a constant voltage, thereby fixing the potential of the second terminal of the capacitance CI. This allows the voltage between the first terminal and the second terminal of the capacitance CI, for example, the gate-source voltage of the transistor F1, to be held by putting the first terminal of the capacitance CI into a floating state. Note that the second terminal of the capacitance CI may be electrically connected to another wiring that provides a constant voltage, instead of the wiring VEA.

[0135] The wiring SL11 functions as a wiring for transmitting a control signal (digital value) for switching the switch RSW between the on and off states.

[0136] [Writing to the memory device MINT] When writing information read from the memory device MEXT to the memory cell MCL[1], first, a low-level potential is input to each of the wirings RWL[1] to RWL[m] to turn off the transistor F3 of each of the memory cells MCL[1] to MCL[m]. Next, a high-level potential is input to the wirings WWL[1] and a low-level potential is input to the wirings WWL[2] to WWL[m]. This turns on the transistor F2 of the memory cell MCL[1] and turns off the transistor F2 of each of the memory cells MCL[2] to MCL[m]. Here, a potential V corresponding to the information read from the memory device MEXT is input to the wiring WBL[u]. DATA When this signal is input, the potential of the first terminal of the capacitance CI of the memory cell MCL[1] becomes V DATA After that, a low-level potential is input to the wiring WWL[1] to turn off the transistor F2 of the memory cell MCL[1], thereby inputting V DATA can be held.

[0137] [Reading from the memory device MINT] Memory cell MCL[1] to V DATA When reading out and inputting to the circuit ILD, first, a high-level potential is applied to the wiring SL11 to turn on the switch RSW. As a result, the potential of the wiring RBL[u] becomes the high-level potential applied by the wiring VDL2. PR In addition, the potential of the wiring RBL[u] is V PR After the potential of the wiring RBL[u] reaches the high potential V, the switch RSW is turned off by applying a low-level potential to the wiring SL11, and the precharging of the wiring RBL[u] is completed.PR Therefore, in the circuit ILD, the switch SW[u] is in an off state, and the current generated by the current source CC[u] does not flow through the wiring IL.

[0138] Next, a high-level potential is input to the wiring RWL[1], and a low-level potential is input to the wirings RWL[2] to RWL[m]. This causes the transistor F2 in the memory cell MCL[1] to be turned on, and the transistors F2 in the memory cells MCL[2] to MCL[m] to be turned off. At this time, in the memory cell MCL[1], conduction is established between the second terminal of the transistor F1 and the wiring RBL[u], so that the second terminal of the transistor F1 is supplied with the potential V PR At this time, the gate-source voltage of transistor F1 is V DATA -V S And V DATA -V S is the threshold voltage V of transistor F1. th When the potential of the second terminal of the transistor F1 is lower than a predetermined potential, a current flows between the source and drain of the transistor F1. When the potential of the second terminal of the transistor F1 is lowered to a predetermined potential, the transistor F1 is turned off. DATA -V S is the threshold voltage V of transistor F1. th When the potential of the precharged wiring RBL[u] is lower than the potential of the precharged wiring RBL[u], the transistor F1 is turned off and no current flows between the source and drain of the transistor F1.

[0139] As described above, whether the potential of the precharged wiring RBL[u] changes or not is determined depending on the voltage held at the first terminal of the capacitance CI. Therefore, by inputting a high-level potential to the wiring RWL[1] to turn on the transistor F3, and then measuring the potential of the wiring RBL[u], the voltage held at the first terminal of the capacitance CI can be read out.

[0140] In addition, since the wiring RBL[u] is in a conductive state with the wiring DIL[u], when the potential of the wiring RBL[u] changes, the potential of the wiring DIL[u] also changes. Therefore, a potential according to the information read from the memory cell MCL[1] is applied to the control terminal of the switch SW[u] of the circuit WCS1, and the on / off state of the switch SW[u] is determined. Specifically, V DATA -V S is the threshold voltage V of transistor F1. th When the potential of the wiring DIL[u] is higher than V PR Since the voltage V is lower than V, the switch SW[u] is turned on. DATA -V S is the threshold voltage V of transistor F1. th When the potential of the wiring DIL[u] is lower than V PR Since the signal level does not change, the switch SW[u] remains in the off state.

[0141] By configuring the memory device MINT and the connection between the memory device MINT and the circuit ILD as shown in Fig. 3, the information stored in each of the memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT can be made to correspond to the on / off state of the switch SW[u] of the circuit WCS1. In addition, the circuit configuration of Fig. 3 does not require a read circuit for reading data from the memory device, which allows for reduction in the circuit area and power consumption.

[0142] 3 as the semiconductor device SDV1, data can be read from the memory device MINT and written to the multiplication cell of the calculation unit CLP. Also, by performing this operation at regular intervals, data degraded by leakage current (absolute value of the reduced charge amount) can be periodically rewritten to the original data (absolute value of the original charge amount) in the multiplication cell of the calculation unit CLP. In other words, by applying the configuration shown in FIG. 3 as the semiconductor device SDV1, the rewriting operation of the data held in the memory element of the multiplication cell of the calculation unit CLP can be easily performed.

[0143] <<Configuration example 2 of memory device MINT and circuit ILD>> Furthermore, the configuration of the memory device MINT and the circuit ILD according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 3. The configuration of the memory device MINT and the circuit ILD may change the included circuit elements, connection configuration, and the like depending on the case or situation.

[0144] For example, the configuration of the memory device MINT and the circuit ILD shown in Fig. 3 may be changed to the circuit configuration shown in Fig. 4. Fig. 4 shows a configuration in which a circuit BF is provided between the electrical path between the wiring RBL[u] and the wiring DIL[u] in Fig. 3.

[0145] The circuit BF can include, for example, an amplifier circuit such as a buffer circuit, an inverter circuit, a latch circuit, etc. Specifically, the circuit BF can have a function of referring to the potential of the wiring RBL[u] and outputting the amplified potential to the wiring DIL[u].

[0146] As shown in FIG. 4, by providing the circuit BF, it is possible to stabilize the potential input to the control terminal of the switch SW[u].

[0147] By applying the configuration shown in FIG. 4 to the semiconductor device SDV1, it is possible to easily perform the operation of rewriting data held in the memory element of the multiplication cell of the arithmetic unit CLP.

[0148] <<Configuration example 3 of memory device MINT and circuit ILD>> 5 is a circuit configuration example showing the memory device MINT, a part of the circuit ILD described above, and the arithmetic unit CLP in the case where the decoder DEC is electrically connected to the circuit ILD as shown in FIG. 2B. As shown in FIG. 5, the memory device MINT is electrically connected to the decoder DEC via wirings DIL[1] to DIL[K], and the circuit ILD is electrically connected to the decoder DEC via wirings DEL[1] to DEL[L].

[0149] For the calculation unit CLP, the description of the calculation unit CLP shown in FIG. 3 should be referred to.

[0150] In addition, in FIG. 5, as an example, a configuration having a memory circuit called NOSRAM (registered trademark) is shown, as in FIG. 3. In addition, in the memory device MINT in FIG. 5, memory cells similar to the memory cells MCL[1] to MCL[m] shown in FIG. 3 are arranged in a matrix of m rows and K columns. In addition, in FIG. 5, the memory cells arranged in the matrix are described as memory cells MCL[1,1] to MCL[m,K]. In addition, the memory device MINT in FIG. 5 has switches RSW[1] to RSW[K], a circuit WWD, and a circuit RWD, which correspond to the switch RSW shown in FIG. 3.

[0151] For the circuit WWD and the circuit RWD, please refer to the description of the circuit WWD and the circuit RWD shown in FIG.

[0152] The memory cells MCL[1,1] to MCL[m,1] located in the first column are electrically connected to the wirings WBL[1] and RBL[1]. The memory cells MCL[1,K] to MCL[m,K] located in the Kth column are electrically connected to the wirings WBL[K] and RBL[K]. The memory cells MCL[1,1] to MCL[1,K] located in the first row are electrically connected to the wirings WWL[1] and RWL[1]. The memory cells MCL[m,1] to MCL[m,K] located in the mth row are electrically connected to the wirings WWL[m] and RWL[m].

[0153] The wiring RBL[1] is electrically connected to a first terminal of the switch RSW[1] and a wiring DIL[1]. The second terminal of the switch RSW[1] is electrically connected to a wiring VDL2. The wiring RBL[K] is electrically connected to a first terminal of the switch RSW[m] and a wiring DIL[K]. The second terminal of the switch RSW[K] is electrically connected to a wiring VDL2. The control terminals of the switches RSW[1] to RSW[K] are electrically connected to a wiring SL11.

[0154] In the memory device MINT of Figure 5, by performing a data read operation in the same manner as the memory device MINT shown in Figure 3, information read from multiple memory cells MCL in any one of the first row to the mth row can be input to the decoder DEC.

[0155] For example, when memory cells MCL[1,1] to MCL[1,K] located in the first row are selected in a read operation of the memory device MINT in FIG. 5, the information read from memory cells MCL[1,1] to MCL[1,K] is input to the decoder DEC via wiring DIL[1] to wiring DIL[K]. At this time, K-bit data is transmitted to the decoder DEC from wiring DIL[1] to wiring DIL[K]. The decoder DEC converts the binary data transmitted from wiring DIL[1] to wiring DIL[K] into decimal data and transmits it to the decoder DEC via wiring DEL[1] to wiring DEL[2]. K As a result, the switches SW[1] to SW[2 K Decimal data from the decoder DEC is input to the control terminals of the switches SW[1] to SW[2-1], and the switches SW[1] to SW[2-1] are controlled in accordance with the data. K In other words, the number of switches that are turned on among the switches SW[1] to SW[2-1] is determined by the information written in the memory cells MCL located in a certain row of the memory device MINT. K1-1] is determined, and a current according to the number of switches that are turned on flows from the circuit WCS2 to the wiring IL.

[0156] 5 as the semiconductor device SDV1, data can be read from the memory device MINT and written to the multiplication cell of the calculation unit CLP in the same manner as in FIG. 3. Also, by performing this operation at regular intervals, data degraded by leakage current (absolute value of the reduced charge amount) can be periodically rewritten to the original data (absolute value of the original charge amount) in the multiplication cell of the calculation unit CLP. In other words, by applying the configuration shown in FIG. 5 as the semiconductor device SDV1, the rewriting operation of the data held in the memory element of the multiplication cell of the calculation unit CLP can be easily performed.

[0157] 3 to 5 has a configuration including three transistors and one capacitor, but one embodiment of the present invention is not limited thereto. In one embodiment of the present invention, for example, the memory cell MCL included in the memory device MINT may have two transistors and one capacitor. An example of such a configuration is shown in FIG. 6. The memory cell MCL of the memory device MINT shown in FIG. 6 differs from the memory cell MCL of the memory device MINT shown in FIG. 3 to 5 in that it does not include a transistor F3 and that a second terminal of the capacitor CI is electrically connected to the wiring RWL.

[0158] In the memory cells MCL[1] to MCL[m] shown in Fig. 6, the second terminal of the transistor F1 is electrically connected to the wiring RBL[u]. The second terminal of the capacitance CI of the memory cell MCL[1] in Fig. 6 is electrically connected to the wiring RWL[1], and the second terminal of the capacitance CI of the memory cell MCL[m] in Fig. 6 is electrically connected to the wiring RWL[m].

[0159] When writing information read from the memory device MEXT to the first terminal of the capacitance CI of each of the memory cells MCL[1] to MCL[m], a high-level potential is preferably input to the wirings RWL[1] to RWL[m]. Also, while information is held in the first terminal of the capacitance CI of the memory cells MCL[1] to MCL[m], a low-level potential is preferably input to the wirings RWL[1] to RWL[m]. In particular, in this case, it is preferable that the transistor F1 is turned off by applying a low-level potential to the wirings RWL[1] to RWL[m]. Also, when reading information written to the first terminal of the capacitance CI from any one of the memory cells MCL[1] to MCL[m], it is preferable that a high-level potential is input to the wirings RWL[1] to RWL[m]. In particular, in this case, it is preferable that the transistor F1 is turned on by applying a high-level potential to the wirings RWL[1] to RWL[m].

[0160] 3 to 6, for example, one embodiment of the present invention may be configured such that the wirings WBL[u] and RBL[u] are combined into one common wiring. Fig. 7 shows a configuration in which the wirings WBL[u] and RBL[u] are combined into one common wiring RBL[u] in the memory device MINT of Fig. 3. The wiring RBL[u] of the memory device MINT of Fig. 7 functions not only as a read data line but also as a write data line, so that the memory device MINT has, in addition to the switch RSW, a switch WSW and a switch RSW2 for switching between a write operation and a read operation.

[0161] In the memory device MINT of FIG. 7, the switch WSW is provided in the electrical path between the wiring WBL[u] and the wiring RBL[u], and the switch RSW2 is provided in the electrical path between the wiring RBL[u] and the wiring DIL[u].

[0162] As the switch WSW and the switch RSW2, for example, a switch applicable to the switch RSW described above can be used.

[0163] When writing information read from the memory device MEXT to the first terminal of the capacitance CI of each of the memory cells MCL[1] to MCL[m] of the memory device MINT in FIG. 7, the switch WSW is turned on, and the switches RSW and RSW2 are turned off. For the subsequent operation of the memory cells MCL[1] to MCL[m], refer to the description of the write operation of the memory device MINT in FIG. 3. Also, when reading information written to the first terminal of the capacitance CI from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT in FIG. 7, the switch WSW is first turned off. For the subsequent operation of the memory cells MCL[1] to MCL[m], refer to the description of the read operation of the memory device MINT in FIG. 3.

[0164] <<Configuration example 4 of memory device MINT and circuit ILD>> 3 to 7 has a circuit configuration including NOSRAM (registered trademark), the memory device MINT of the semiconductor device of one embodiment of the present invention is not limited to this. The memory device MINT may have a circuit configuration including, for example, a dynamic random access memory (DRAM).

[0165] 8 is a circuit configuration example showing a memory device MINT and a part of the circuit ILD described above, in which the memory device MINT has memory cells MCL[1] to MCL[m], a circuit SA, and a circuit WRD. Each of the memory cells MCL[1] to MCL[m] included in the memory device MINT is configured as a DRAM having a transistor F4 and a capacitance CI2.

[0166] As the transistor F4, for example, a transistor applicable to the transistor F2 shown in Figures 3 to 7 can be used. Therefore, for the configuration of the transistor F4, the description of the transistor F2 in this specification and the like should be referred to.

[0167] In particular, when an OS transistor is applied as the transistor F4, the memory device MINT in FIG. 8 may be called a Dynamic Oxide Semiconductor Random Access Memory (DOSRAM) (registered trademark).

[0168] As an example, the memory device MINT can be configured to have memory cells MCL arranged in a matrix. For example, the memory device MINT can be configured to have multiple columns of memory cells MCL[1] to MCL[m] arranged in one column. Note that in the memory device MINT of FIG. 8, the memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are illustrated here.

[0169] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to a wiring RBL[u]. The circuit SA is electrically connected to a wiring WBL[u], a wiring RBL[u], and a wiring DIL[u].

[0170] In each of the memory cells MCL[1] to MCL[m], a first terminal of the transistor F4 is electrically connected to a first terminal of the capacitor CI2, a second terminal of the capacitor CI2 is electrically connected to the wiring VEA, and a second terminal of the transistor F4 is electrically connected to the wiring RBL[u].

[0171] In the memory cell MCL[1], the gate of the transistor F4 is electrically connected to the wiring WRL[1]. In the memory cell MCL[m], the gate of the transistor F4 is electrically connected to the wiring WRL[m].

[0172] In addition, the wirings WRL[1] to WRL[m] are electrically connected to the circuit WRD.

[0173] The wirings WRL[1] to WRL[m] each function as a word line for performing a write operation and a read operation in the memory cells MCL[1] to MCL[m]. The circuit WRD is a driver circuit that selects a memory cell to be written to or read from, and has a function of transmitting a write or read selection signal to any one of the wirings WRL[1] to WRL[m].

[0174] The wiring RBL[u] functions as a data line for performing write and read operations in the memory cells MCL[1] to MCL[m].

[0175] The wiring VEA functions as a wiring that applies a constant voltage, similar to the wiring VEA shown in Fig. 3 to Fig. 7. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0176] The circuit SA has a function of amplifying information (such as a voltage or a current) read from the memory device MEXT and transmitted to the wiring WBL[u], and supplying the information to the wiring RBL[u]. The circuit SA also has a function of amplifying information read from any one of the memory cells MCL[1] to MCL[m] and transmitted to the wiring RBL[u], and transmitting the information to the wiring DIL[u]. For this reason, the circuit SA included in the memory device MINT in FIG. 8 can have a configuration including a circuit for switching between a write operation and a read operation, an amplifier circuit (such as a sense amplifier), and the like. For this reason, the circuit SA may be referred to as a read circuit. The circuit SA may also have a function of writing back data to any one of the memory cells MCL[1] to MCL[m] in which data destruction has occurred due to reading.

[0177] 8, in a configuration in which a memory circuit of DRAM (or DOSRAM (registered trademark)) is provided in the memory device MINT, the read signal (voltage) from the memory cell MCL to the wiring RBL[u] during reading can be increased by increasing the capacitance value of the capacitance C1 provided in the memory cell MCL. As a means for increasing the capacitance value of the capacitance C1, for example, a trench type capacitance may be applied to the capacitance C1.

[0178] Note that one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 8. One embodiment of the present invention may be modified from the circuit configuration shown in Fig. 8 depending on the case or situation. For example, the memory device MINT shown in Fig. 8 can be combined with the configuration of the memory device MINT having a memory circuit of NOSRAM (registered trademark) shown in Figs. 3 to 7.

[0179] For example, one embodiment of the present invention may have a configuration in which a decoder DEC is added to the circuit configuration in Fig. 8, as in Fig. 5. As a specific example, Fig. 9 shows a configuration in which a memory device MINT is electrically connected to the decoder DEC through wirings DIL[1] to DIL[K], and a circuit ILD is electrically connected to the decoder DEC through wirings DEL[1] to DEL[L].

[0180] The memory device MINT in Fig. 9 has memory cells similar to the memory cells MCL[1] to MCL[m] shown in Fig. 8 arranged in a matrix of m rows and K columns. In Fig. 9, the memory cells arranged in the matrix are described as memory cells MCL[1,1] to MCL[m,K]. The memory device MINT in Fig. 9 also has circuits SA[1] to SA[K] corresponding to the circuit SA shown in Fig. 8.

[0181] The memory cells MCL[1,1] to MCL[m,1] located in the first column are electrically connected to the wiring RBL[1]. The memory cells MCL[1,K] to MCL[m,K] located in the Kth column are electrically connected to the wiring RBL[K]. The memory cells MCL[1,1] to MCL[1,K] located in the first row are electrically connected to the wiring WRL[1]. The memory cells MCL[m,1] to MCL[m,K] located in the mth row are electrically connected to the wiring WRL[m].

[0182] The circuit SA[1] is electrically connected to the wiring WBL[1], the wiring RBL[1], and the wiring DIL[1]. The circuit SA[K] is electrically connected to the wiring WBL[K], the wiring RBL[K], and the wiring DIL[K].

[0183] For the electrical connection between the decoder DEC and the circuit ILD, please refer to the explanation of FIG. 2B.

[0184] In the memory device MINT of Figure 9, by performing a data read operation in the same manner as the memory device MINT shown in Figure 8, information read from multiple memory cells MCL in any one of the first row to the mth row can be input to the decoder DEC.

[0185] 9 as the semiconductor device SDV1, data can be read from the memory device MINT and written to the multiplication cell of the calculation unit CLP in the same manner as in FIG. 3. Also, by performing this operation at regular time intervals, data degraded by leakage current (absolute value of the reduced charge amount) can be periodically rewritten to the original data (absolute value of the original charge amount) in the multiplication cell of the calculation unit CLP. In other words, by applying the configuration shown in FIG. 9 as the semiconductor device SDV1, the rewriting operation of the data held in the memory element of the multiplication cell of the calculation unit CLP can be easily performed.

[0186] <<Configuration example 5 of memory device MINT and circuit ILD>> 3 to 7 have a circuit configuration including NOSRAM (registered trademark), and the memory device MINT shown in FIGS. 8 and 9 have a circuit configuration including DRAM (or DOSRAM (registered trademark)), but the memory device MINT of the semiconductor device of one embodiment of the present invention is not limited thereto. The memory device MINT may have a circuit configuration including, for example, a load circuit LC.

[0187] 10A is a circuit configuration example showing a memory device MINT and a part of the circuit ILD described above, in which the memory device MINT includes memory cells MCL[1] to MCL[m], a circuit IVC, a switch WSW, a switch RSW2, and a circuit WRD. Each of the memory cells MCL[1] to MCL[m] included in the memory device MINT includes a transistor F4 and a load circuit LC.

[0188] As the transistor F4, for example, a transistor applicable to the transistor F2 shown in Figures 3 to 7 can be used. Therefore, for the configuration of the transistor F4, the description of the transistor F2 in this specification and the like should be referred to.

[0189] As for the switch WSW and the switch RSW2, the description of the switch WSW and the switch RSW2 shown in FIG. 7 should be referred to.

[0190] As for the circuit WRD, the description of the circuit WRD shown in FIG. 8 should be referred to.

[0191] As an example, the load circuit LC is a circuit that can change the resistance between the first terminal and the second terminal of the load circuit LC. By changing the resistance between the first terminal and the second terminal of the load circuit LC, the amount of current flowing between the first terminal and the second terminal of the load circuit LC can be changed.

[0192] In Fig. 10A, the configuration of each of the memory cells MCL[1] to MCL[m] included in the memory device MINT is such that the capacitance CI2 in the memory cells MCL shown in Fig. 8 and Fig. 9 is replaced with a load circuit. Specifically, a first terminal of the load circuit LC is electrically connected to a first terminal of the transistor F4, and a second terminal of the load circuit LC is electrically connected to the wiring VEA.

[0193] As an example, the memory device MINT can be configured to have memory cells MCL arranged in a matrix. For example, the memory device MINT can be configured to have multiple columns of memory cells MCL[1] to MCL[m] arranged in one column. Note that in the memory device MINT of FIG. 10A, the memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are illustrated here.

[0194] 10A, the switch WSW is provided in the electrical path between the wiring WBL[u] and the wiring RBL[u], and the switch RSW2 is provided in the electrical path between the wiring RBL[u] and the input terminal of the circuit IVC. The output terminal of the circuit IVC is electrically connected to the wiring DIL[u].

[0195] The memory cells MCL[1] to MCL[m] in the u-th column of the memory device MINT are electrically connected to the wiring RBL[u]. The circuit IVC is electrically connected to the wiring RBL[u] through the switch RSW2. The circuit IVC is electrically connected to the wiring DIL[u].

[0196] The wiring VEA functions as a wiring that applies a constant voltage, similar to the wiring VEA shown in Figures 3 to 7. The magnitude of the constant voltage may be appropriately determined according to, for example, the configuration of the load circuit LC.

[0197] The circuit IVC has a function of converting a current flowing through the wiring RBL[u] or the like according to information read from any one of the memory cells MCL[1] to MCL[m] into a voltage and supplying the voltage to the wiring DIL[u]. The circuit IVC may also have a function of applying a predetermined voltage to the wiring RBL[u] in order to read information from any one of the memory cells MCL[1] to MCL[m]. As described above, the circuit IVC included in the memory device MINT in FIG. 10A has a function as a read circuit.

[0198] When writing information read from the memory device MEXT to the memory cells MCL[1] to MCL[m] included in the memory device MINT of FIG. 10A, the transistor F4 and the switch WSW of the memory cell MCL to be written are turned on, and the switch RSW is turned off. After that, the information read from the memory device MEXT may be input to the load circuit LC of the memory cell MCL to be written via the wiring WBL[u], the switch WSW, and the wiring RBL[u]. Also, when reading information written to the load circuit LC from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT of FIG. 10A, the switch WSW is first turned off, and the switch RSW2 is turned on. Next, if necessary, a desired potential is applied to the wiring RBL[u] by the circuit IVC. After that, by turning on the transistor F4 of the memory cell MCL to be read, an amount of current corresponding to the information flows from the load circuit LC to the circuit IVC (depending on the information held in the load circuit LC, there may be cases where no current flows). Then, the circuit IVC can output a voltage according to the amount of the current to the wiring DIL[u], and turn on or off the switch SW[u] included in the circuit WCS1 of the circuit ILD.

[0199] As the load circuit LC, for example, a resistance change element VR included in a ReRAM (Resistive Random Access Memory) or the like can be used as shown in Fig. 10B. Also, as the load circuit LC, for example, a load circuit LC including a MTJ (Magnetic Tunnel Junction) element MR included in a MRAM (Magnetoresistive Random Access Memory) or the like can be used as shown in Fig. 10C. Also, as the load circuit LC, for example, a resistance element including a phase change material used in a phase change memory (PCM) or the like (for convenience, referred to as a phase change memory PCM in this specification and the like) can be used as shown in Fig. 10D.

[0200] As the load circuit LC, for example, as shown in Fig. 10E, a ferroelectric capacitor FEC sandwiched between a pair of electrodes used in a FeRAM (Ferroelectric Random Access Memory) can be used. In Fig. 10E, a first terminal of the ferroelectric capacitor FEC is electrically connected to a first terminal of the transistor F4, and a second terminal of the ferroelectric capacitor FEC is electrically connected to the wiring VEA.

[0201] In this case, the wiring VEA does not function as a wiring for supplying a constant voltage, but functions as a plate line for polarizing the ferroelectric film of the ferroelectric capacitor or for inverting the polarization of the ferroelectric film.

[0202] For example, the operation of writing information from the memory device MEXT to the ferroelectric capacitor FEC is performed by turning on the transistor F4, applying a voltage corresponding to the information to the wiring RBL, and applying a predetermined voltage to the wiring VEA, thereby polarizing the ferroelectric film included in the ferroelectric capacitor FEC. The operation of reading the written information from the ferroelectric capacitor FEC is performed by turning on the transistor F4 and then applying a pulse voltage to the wiring VEA. The height of the pulse voltage applied to the wiring VEA may be the same as the voltage applied to the wiring VEA during writing. The ferroelectric capacitor FEC determines whether the information held is "0" or "1" depending on whether polarization reversal occurs due to the pulse voltage from the wiring VEA. When polarization reversal occurs in the ferroelectric film of the ferroelectric capacitor FEC, a current flows through the wiring RBL via the transistor F4. The amount of current flowing through the wiring RBL can be obtained by using a circuit IVC having the configuration of, for example, an integrating circuit (or a current-charge (IQ) conversion circuit) and a current-voltage conversion circuit. The amount of current determines the on or off state of the switch SW[u] included in the circuit WCS1 of the circuit ILD. As a result, the amount of current flowing through the wiring IL is determined by the on / off state of each of the switches SW[1] to SW[K] included in the circuit WCS1.

[0203] 10 is configured such that the memory cell MCL includes a load circuit LC, but one embodiment of the present invention is not limited to this. In one embodiment of the present invention, for example, the memory cell MCL included in the memory device MINT may include a static random access memory (SRAM).

[0204] In this case, the memory device MINT has a configuration as shown in FIG. 11. As an example, the memory device MINT in FIG. 11 can have memory cells MCL arranged in a matrix. For example, the memory device MINT can have a configuration in which memory cells MCL[1] to MCL[m] are arranged in multiple columns. In the memory device MINT in FIG. 11, memory cells MCL[1] to MCL[m] are arranged in K columns, and only the memory cells MCL[1] to MCL[m] in the u-th column are shown here.

[0205] In the memory device MINT of Fig. 11, each of the memory cells MCL[1] to MCL[m] includes a transistor F4, an inverter circuit INV1, and an inverter circuit INV2. A first terminal of the transistor F4 is electrically connected to an output terminal of the inverter circuit INV1 and an input terminal of the inverter circuit INV2, and the input terminal of the inverter circuit INV1 is electrically connected to an output terminal of the inverter circuit INV2. That is, in each of the memory cells MCL[1] to MCL[m], an inverter loop circuit is formed by each of the inverter circuits INV1 and INV2.

[0206] The gate of the transistor F4 in the memory cell MCL[1] is electrically connected to the wiring WRL[1], the gate of the transistor F4 in the memory cell MCL[m] is electrically connected to the wiring WRL[m], and the second terminals of the transistors F4 in the memory cells MCL[1] to MCL[m] are electrically connected to the wiring RBL[u].

[0207] For the circuit WRD and the wirings WRL[1] to WRL[m] included in the memory device MINT in FIG. 11, the description of the memory device MINT in FIG. 10 can be referred to.

[0208] The memory device MINT in Fig. 11 has a switch WSW, a switch RSW, and a switch RSW2. Note that the functions and connection configurations of the switches WSW, RSW, RSW2, wiring WBL[u], wiring VDL2, wiring RBL[u], and wiring DIL[u] shown in Fig. 11 should be referred to the description of the memory device MINT in Fig. 7.

[0209] When writing information read from the memory device MEXT to the memory cells MCL[1] to MCL[m] included in the memory device MINT of FIG. 11, the transistor F4 and the switch WSW of the memory cell MCL to be written are turned on, and the switches RSW and RSW2 are turned off. After that, the information read from the memory device MEXT may be input to the inverter loop circuit of the memory cell MCL to be written via the wiring WBL[u], the switch WSW, and the wiring RBL[u]. When reading information written to the inverter loop circuit from any one of the memory cells MCL[1] to MCL[m] of the memory device MINT of FIG. 11, first, the switches WSW and RSW2 are turned off, the switch RSW is turned on, and the wiring RBL[u] is given the potential of the wiring VDL2 (for example, a high-level potential) to initialize it. After that, the transistor F4 of any one of the memory cells MCL[1] to MCL[m] to be read is turned on, and the switch RSW2 is turned on. This allows the read data to be input from the memory cell MCL to be read to the circuit ILD via the wiring RBL[u], the switch RSW2, and the wiring DIL. Since the potential of the wiring DIL is determined according to the data, the on or off state of the switch SW[u] included in the circuit WCS1 of the circuit ILD is determined. As a result, the amount of current flowing through the wiring IL is determined according to the on or off state of each of the switches SW[1] to SW[K] included in the circuit WCS1.

[0210] In addition to the above, examples of memory devices that can be used in the memory device MINT include flash memories.

[0211] 10, 11, etc., can be applied to the semiconductor device SDV1 to read data from the memory device MINT and write the data to the multiplication cell of the calculation unit CLP, as in the case of FIG. 3. Also, by performing this operation at regular time intervals, data degraded by leakage current (absolute value of the reduced charge amount) can be periodically rewritten to the original data (absolute value of the original charge amount) in the multiplication cell of the calculation unit CLP. In other words, by applying the configurations illustrated in FIGS. 10, 11, etc., to the semiconductor device SDV1, the rewrite operation of the data held in the memory element of the multiplication cell of the calculation unit CLP can be easily performed.

[0212] <<Configuration Example 6 of Memory Device MINT and Circuit ILD>> Here, we will explain the electrical connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP that is applicable to the semiconductor device SDV1, which differs from the electrical connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP shown in Figures 3 to 10.

[0213] Fig. 12 shows a modified example of the electrical connection configuration between the memory device MINT, the circuit ILD, and the operation unit CLP in Fig. 3. The connection configuration shown in Fig. 12 differs from the connection configuration in Fig. 3 in that the memory device MINT does not have a circuit RWD. In addition, the wirings RWL[1] to RWL[m] electrically connected to the memory cells MCL[1] to MCL[m] of the memory device MINT are electrically connected to the wirings WL[1] to WL[m] of the operation unit CLP.

[0214] Specifically, the wirings WL[1] to WL[m] function as write data lines for writing information to the multiplication cells (referred to as circuits MP[1] to MP[m] in FIG. 12) in the calculation unit CLP. The wirings WL[1] to WL[m] will be described in embodiment 2. Each of the wirings WL[1] to WL[m] is electrically connected to a circuit WLD. The circuit WLD functions as a driver circuit for transmitting a selection signal for selecting a multiplication cell (circuit MP) in which information is to be written in the calculation unit CLP.

[0215] 12, the wirings RWL[1] to RWL[m] functioning as read word lines of the memory device MINT and the wirings WL[1] to WL[m] functioning as write data lines of the operation unit CLP are shared with each other. By transmitting a selection signal to any one of the wirings RWL[1] (wiring WL[1]) to RWL[m] (wiring WL[m]) by the circuit WLD of the operation unit CLP, information can be read from a specific memory cell MCL in the memory device MINT.

[0216] In addition, since the read word line (wire RWL) of the memory device MINT and the write data line (wire WL) of the calculation unit CLP are integrated into a single wire, when information is read from a specific memory cell MCL in the memory device MINT, a selection signal is also input to the multiplication cell (circuit MP) of the calculation unit CLP located in the same row as the memory cell MCL. In other words, when information is read from a specific memory cell MCL in the memory device MINT, the write transistor included in the multiplication cell (circuit MP) is also turned on.

[0217] For example, when information is read from K memory cells MCL[1] located in the first row of the memory device MINT, a selection signal is sent from the circuit WLD to the wiring RWL[1] (wiring WL[1]). At this time, potentials corresponding to the information stored in each of the K memory cells MCL[1] located in the first row are read, and each potential is input to the circuit WCS1 of the circuit ILD. In the circuit WCS1, the on / off states of the switches SW[1] to SW[K] are determined according to each potential. That is, the amount of current flowing from the circuit WCS1 to the wiring IL is determined by a combination of the on / off states of the switches SW[1] to SW[K]. Furthermore, since a selection signal is sent to the wiring WL[1] (wiring RWL[1]) in the arithmetic unit CLP, the write transistor included in the multiplication cell (circuit MP) located in the first row is turned on. Therefore, the current of the amount of current output by the circuit ILD flows to the multiplication cell (circuit MP) located in the first row via the wiring IL. This makes it possible to write the information held in the memory cell MCL of the memory device MINT to the multiplication cell (circuit MP) of the calculation unit CLP.

[0218] Moreover, by applying the configuration of FIG. 12 to the semiconductor device SDV1, the memory device MINT can be configured not to include the circuit RWD which is a drive circuit during reading, and therefore the area of ​​the memory device MINT can be reduced.

[0219] Furthermore, the connection configuration of the memory device MINT, the circuit ILD, and the calculation unit CLP according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 12. The connection configuration of the memory device MINT, the circuit ILD, and the calculation unit CLP may change the included circuit elements, connection configuration, and the like depending on the case or situation.

[0220] For example, the connection configuration between the memory device MINT, the circuit ILD, and the calculation unit CLP may be such that the circuit BF described with reference to FIG. 4 is provided between the memory device MINT and the circuit ILD in FIG. 12, as shown in FIG.

[0221] In the connection configuration of the memory device MINT, the circuit ILD, and the calculation unit CLP in Fig. 13, a circuit BF is provided between the electrical path of the wiring RBL[u] and the wiring DIL[u]. In addition, the circuit BF may be configured to include an amplifier circuit such as a buffer circuit, an inverter circuit, and a latch circuit, as in the description of Fig. 4.

[0222] In particular, by making the circuit BF have a latch circuit configuration that temporarily holds the potential of the wiring RBL[u], the speed of writing information to the multiplication cell (circuit MP) of the calculation unit CLP may be increased. In this case, for example, as shown in the connection configuration of the memory device MINT, the circuit ILD, and the calculation unit CLP in FIG. 14A, a wiring WL[0] is provided in the calculation unit CLP, the wiring WL[0] and the wiring RWL[1] are electrically connected, and the wiring WL[1] and the wiring RWL[2] are electrically connected. In other words, the wiring RWL[i] (where i is 1 or more and m or less) of the memory device MINT and the wiring WL[i-1] of the calculation unit CLP are electrically connected. Note that the wiring WL[0] in the calculation unit CLP does not need to be provided with a multiplication cell (circuit MP).

[0223] As an example, the circuit BF may have the configuration shown in FIG. 14B. The circuit BF has a latch circuit LAT1, a latch circuit LAT2, and an inverter circuit INV. An input terminal of the latch circuit LAT1 is electrically connected to a wiring RBL[u], an output terminal of the latch circuit LAT1 is electrically connected to an input terminal of the latch circuit LAT2, and an output terminal of the latch circuit LAT2 is electrically connected to a wiring DIL[u]. An enable signal input terminal (sometimes called a clock signal input terminal) of the latch circuit LAT1 is electrically connected to a wiring CLK, an input terminal of the inverter circuit INV is electrically connected to a wiring CLK, and an output terminal of the inverter circuit INV is electrically connected to an enable signal input terminal of the latch circuit LAT2.

[0224] An operation example in the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP in FIG. 14A will be described. First, a selection signal is sent from the circuit WLD to the wiring WL[0] to read information stored in the memory cell MCL[1] located in the first row of the memory device MINT. The read information is input as a potential to the input terminal of the circuit BF via the wiring RBL[u]. At this time, in the circuit BF, a first potential (e.g., one of a high-level potential or a low-level potential) is input to the wiring CLK, so that the latch circuit LAT1 holds the potential input from the wiring RBL[u] and outputs it to the output terminal of the latch circuit LAT1. Furthermore, a second potential (e.g., the other of a high-level potential or a low-level potential) is input to the wiring CLK, so that the latch circuit LAT2 holds the potential from the output terminal of the latch circuit LAT1 and outputs it to the output terminal of the latch circuit LAT2. Also, at the timing when a second potential (for example, the other of the high-level potential or the low-level potential) is input to the wiring CLK, a selection signal is sent from the circuit WLD to the wiring WL[1] to read out information held in the memory cell MCL[1] located in the first row of the memory device MINT. As a result, the read out information is input as a potential to the input terminal of the circuit BF via the wiring RBL[u]. Meanwhile, in the arithmetic unit CLP, since the selection signal is sent to the wiring WL[1], the write transistor of the multiplication cell (circuit MP) in the first row is turned on. At this time, the output terminal of the latch circuit LAT2 of the circuit BF outputs a potential corresponding to the information read out from the memory cell MCL[1] of the memory device MINT, so that the circuit ILD passes a current corresponding to the potential to the wiring IL. Then, the current passes from the wiring IL to the multiplication cell (circuit MP), and the information is written to the multiplication cell (circuit MP).

[0225] In the semiconductor device SDV1, by applying the connection configuration of the memory device MINT, the circuit ILD, and the arithmetic unit CLP of FIG. 14A, the speed at which information held in the memory device MINT is written to the multiplication cell of the arithmetic unit CLP can be increased in the rewrite operation of the data held in the memory element of the multiplication cell of the arithmetic unit CLP.

[0226] In the above operation example, the circuit BF has been described as having a configuration in which the latch circuits LAT1 and LAT2 are connected in series, but the circuit BF may have a configuration in which two latch circuits are connected in parallel instead of in series (not shown). For example, one latch circuit may be configured to obtain information (voltage) sent from the memory device MINT, and the other latch circuit may be configured to transmit information (voltage) obtained in advance to the circuit ILD.

[0227] The configuration of the semiconductor device SDV1 may be selected from the configurations of FIGS. 3 to 9, 10A, 11 to 13, and 14A described above, and may be a combination of these configurations.

[0228] <Configuration Example 2 of Semiconductor Device> Next, a semiconductor device capable of supplementing data held in an arithmetic circuit, which is different from the semiconductor device SDV1 in FIG. 1, will be described.

[0229] 15 is a block diagram showing a configuration example of a semiconductor device SDV2 according to one embodiment of the present invention. As an example, the semiconductor device SDV2 includes a circuit ILD, a calculation unit CLP, and a circuit LMNT. In addition, in order to show the configuration of electrical connections with the semiconductor device SDV2, a memory device MEXT is also shown in FIG.

[0230] The semiconductor device SDV2 can be fabricated by forming circuit elements and the like on one substrate BSE in the same manner as the semiconductor device SDV1.

[0231] For example, by using a semiconductor substrate containing silicon as the substrate BSE, the transistors included in the calculation unit CLP, the transistors included in the circuit ILD, and the transistors included in the circuit LMNT can each be formed as Si transistors on the substrate BSE.

[0232] The circuit ILD provided in the semiconductor device SDV2, for example, acquires information read by a memory device MEXT provided outside the semiconductor device SDV2, and provides a current, voltage, etc. according to the information to a calculation unit CLP described later. The information is treated as data for calculation by the calculation unit CLP.

[0233] Since the semiconductor device SDV2 does not have a memory device MINT, the semiconductor device SDV2 is configured to directly input information read by the memory device MEXT to the circuit ILD, unlike the semiconductor device SDV1. Therefore, when the circuit ILD functions as a current source circuit, the circuit ILD directly supplies a current corresponding to the information read from the memory device MEXT to a circuit included in the calculation unit CLP. Note that the circuit ILD may not be provided as a current source circuit for supplying a current to the calculation unit CLP, but may be provided as a voltage source circuit (voltage generation circuit) for inputting a voltage corresponding to the information read from the memory device MEXT to the calculation unit CLP.

[0234] When the circuit ILD functions as a current source circuit, the specific configuration of the circuit ILD should be referred to the description of the circuit ILD in FIGS. 2A to 2C.

[0235] The arithmetic unit CLP has a plurality of circuits that function as multiplication cells. For the arithmetic unit CLP, please refer to the description of the arithmetic unit CLP included in the semiconductor device SDV1 in FIG. 1A. The circuit configuration of the arithmetic unit CLP and the principle of the product-sum operation in the arithmetic unit CLP will be described in detail in the second embodiment.

[0236] The circuit LMNT has a function of monitoring information (e.g., current, voltage, etc.) held in a multiplication cell (or a memory element included in the circuit LMNT) included in the calculation unit CLP. Specifically, for example, when the information (e.g., current, voltage, etc.) held in the multiplication cell fluctuates due to charge leakage or the like, the circuit LMNT transmits a command signal to the memory device MEXT and the like. Upon receiving the command signal, the memory device MEXT reads out the information from the memory device MEXT, transmits the information to the circuit ILD, and rewrites the information from the circuit ILD to the multiplication cell (replenishes charge to the memory element). At this time, the memory element included in the circuit LMNT is also rewritten to the original information in the same way. This makes it possible to prevent deterioration of the data held in the multiplication cell of the calculation unit CLP.

[0237] <<Example 1 of circuit LMNT and circuit ILD configuration>> Next, a configuration example of the circuit LMNT included in the semiconductor device SDV2 of FIG. 15 will be described.

[0238] The circuit LMNT shown in FIG. 16 includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). The circuit LMC[i] also includes a memory cell DC and a switch DSW1. The memory cell DC also includes a transistor M1d, a transistor M2d, and a capacitance C1d. In addition to the circuit LMNT, FIG. 16 also illustrates a semiconductor device SDV2 including a circuit ILD and an arithmetic unit CLP, as well as a memory device MEXT and a circuit EXMNT.

[0239] In the circuit LMNT, a plurality of circuits LMC[i] may be provided. Specifically, the circuit LMNT may be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row. For example, if the number of wirings IL is 2m, the circuit LMNT may be configured such that the circuits LMC[1] to LMC[2m] are arranged in one row.

[0240] As the switch DSW1, for example, a switch applicable to the above-mentioned switch RSW can be used.

[0241] The memory device MEXT is electrically connected to the circuit ILD. The circuit ILD is electrically connected to the wiring IL. The circuit EXMNT is electrically connected to the memory device MEXT.

[0242] The wiring IL is electrically connected to a first terminal of the switch DSW1, and a second terminal of the switch DSW1 is electrically connected to a wiring DLd. The wiring DLd is also electrically illustrated in the circuit EXMNT and the memory cell DC.

[0243] In the memory cell DC, the first terminal of the transistor M1d is electrically connected to the wiring VEd, the second terminal of the transistor M1d is electrically connected to the wiring DLd, and the gate of the transistor M1d is electrically connected to the first terminal of the capacitor C1d and the first terminal of the transistor M2d. The second terminal of the transistor M2d is electrically connected to the wiring DLd, and the gate of the transistor M2d is electrically connected to the wiring WLd. The second terminal of the capacitor C1d is electrically connected to the wiring VEd. In FIG. 16, the electrical connection point between the gate of the transistor M1d, the first terminal of the capacitor C1d, and the first terminal of the transistor M2d is referred to as a node n1d.

[0244] For example, the wiring DLd functions as a wiring for transmitting data to be written to the first terminal of the capacitance C1d of the memory cell DC. Also, for example, the wiring DLd functions as a wiring for passing a current according to the potential of the first terminal of the capacitance C1d of the memory cell DC.

[0245] For example, the line WLd functions as a write word line in the memory cell DC.

[0246] The wiring VEd functions as, for example, a wiring that applies a constant voltage, which may be, for example, a low-level potential or a ground potential.

[0247] The transistor M1d preferably has a structure similar to that of the transistor M1 described in the second embodiment, which is included in the multiplication cell (circuit MC) of the calculation unit CLP. The transistor M2d preferably has a structure similar to that of the transistor M2 described in the second embodiment, which is included in the multiplication cell (circuit MC) of the calculation unit CLP. For example, when the transistor M1 is a Si transistor and the transistor M2 is an OS transistor, the transistor M1d is preferably a Si transistor, and the transistor M2d is preferably an OS transistor. The capacitance C1d preferably has a structure similar to that of the capacitance C1 described in the second embodiment, which is included in the multiplication cell (circuit MC) of the calculation unit CLP.

[0248] As the transistor M1d, for example, a transistor applicable to the transistor F1 can be used, and as the transistor M2d, for example, a transistor applicable to the transistor F2 can be used.

[0249] The circuit EXMNT is provided outside the semiconductor device SDV2, for example. The circuit EXMNT has a function of monitoring the potential (or charge amount) held at the first terminal of the capacitance C1d of the memory cell DC included in the circuit LMC[i], for example. Specifically, for example, the circuit EXMNT acquires the amount of current input from the wiring DLd and compares the amount of current with a desired amount of current. When the amount of current becomes equal to or less than the desired amount of current, the circuit EXMNT determines that the voltage held in the memory cell DC and the multiplication cell included in the arithmetic unit CLP has become lower (or the absolute value of the charge amount has become smaller), and transmits a command signal to the external memory device MEXT, circuit ILD, etc. to rewrite the same data as the data originally held in the memory cell DC and the multiplication cell included in the arithmetic unit CLP.

[0250] Next, an example of the operation of the circuit LMNT in FIG. 16 will be described.

[0251] First, in the circuit LMC[i], the switch DSW1 is turned on and the transistor M2d is turned on. When the transistor M2d is turned on, the node n1d and the second terminal of the transistor M1d are electrically connected, and the potentials of the node n1d and the second terminal of the transistor M1d become approximately equal.

[0252] At this time, for example, when the circuit ILD is a current source circuit, the amount of current I is supplied from the circuit ILD to the wiring DLd via the wiring IL. 0 The initialization current may be, for example, a current output from the circuit WCS1 or the circuit WCS2 included in the circuit ILD shown in FIGS. 2A to 2C. In this case, for example, the initialization current amount I 0 is the minimum amount of current that the circuit WCS1 or the circuit WCS2 can generate. ut or the maximum value (2 K -1)×I ut It is also possible to use the following.

[0253] Since the transistor M2d is turned on, the first terminal of the capacitor C1d is charged with electric charge flowing from the wiring DLd. Eventually, a current amount I 0 A current of flows, and the potential of the node n1d is a current of I 0 At this time, the potential of the node n1d is V nd Let us assume that.

[0254] In addition, for example, when the circuit ILD is a voltage source circuit, a voltage is written from the circuit ILD to the first terminal of the capacitor C1d via the wiring IL and the transistor M2d. In this case, the voltage written from the circuit ILD to the first terminal of the capacitor C1d is V nd At this time, a current I flows between the first terminal and the second terminal of the transistor M1d (between the wiring DLd and the wiring VEd). 0It is assumed here that the line VED is at a low level potential or a ground potential, and a positive current flows from the line DLd to the line VEd.

[0255] Whether the circuit ILD is a current source circuit or a voltage source circuit, the potential of the first terminal of the capacitance C1d is V nd When the potential V nd At this time, the first terminal of the capacitor C1d of the memory cell DC is supplied with a potential V nd By holding the current I 0 After the transistor M2d is turned off, the switch DSW1 may be turned off.

[0256] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW1 is turned off. This causes a current amount I 0 Specifically, a positive current flows from the circuit EXMNT to the memory cell DC via the wiring DLd.

[0257] Here, the potential V held at the first terminal of the capacitance C1d is nd When the capacitance of the transistor M1d decreases due to leakage of electric charge, the amount of current flowing between the first terminal and the second terminal of the transistor M1d is I 0 When the amount of current flowing from the memory cell DC through the wiring DLd to the circuit EXMNT becomes equal to or less than the desired amount of current, the circuit EXMNT determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (e.g., a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the arithmetic unit CLP and transmit the data to the circuit ILD.

[0258] The desired amount of current here is the amount of current I flowing from the circuit ILD through the wiring IL to the wiring DLd. 0 The current amount here is I 0 For example, the current amount I 0 It can be 0.95 times, 0.90 times, 0.80 times, etc.

[0259] When the command signal is input to the memory device MEXT, the memory device MEXT reads out the information stored in the memory device MEXT and transmits it to the semiconductor device SDV2. The semiconductor device SDV2 then writes the information to the multiplication cell included in the calculation unit CLP by the circuit ILD, and also writes the original voltage (or current) to the memory cell DC. This makes it possible to rewrite data (replenish charge) to the degraded data stored in the multiplication cell of the calculation unit CLP and the memory cell DC.

[0260] 16 is applied to the semiconductor device SDV2, it is possible to easily detect the deterioration of data held in the memory element of the multiplication cell of the operation unit CLP (reduction in the absolute value of the charge amount due to leakage current). In addition, by detecting the deterioration, it is possible to rewrite data (replenish charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0261] <<Configuration example 2 of circuit LMNT and circuit ILD>> Next, a configuration example of the circuit LMNT that is different from the configuration of the circuit LMNT in FIG. 16 and can be applied to the semiconductor device SDV2 in FIG. 15 will be described.

[0262] The circuit LMNT shown in FIG. 17A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL). The circuit LMC[i] also includes a memory cell DC, a circuit DTC, a switch DSW1, and a switch DSW2. The memory cell DC also includes a transistor M1d, a transistor M2d, and a capacitance C1d. In addition to the circuit LMNT, FIG. 17A also illustrates a semiconductor device SDV2 including a circuit ILD and an arithmetic unit CLP, and a memory device MEXT.

[0263] Also, the memory cell DC shown in Fig. 17A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 17A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 17A, refer to the description of the circuit LMNT in Fig. 16.

[0264] The circuit LMNT in Fig. 17A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0265] As the switches DSW1 and DSW2, similar to the switch DSW1 in FIG. 16, for example, a switch applicable to the above-mentioned switch RSW can be used.

[0266] The memory device MEXT is electrically connected to the circuit ILD. The circuit ILD is electrically connected to the wiring IL.

[0267] The wiring IL is electrically connected to a first terminal of a switch DSW1, and the second terminal of the switch DSW1 is electrically connected to a wiring DLd. The wiring DLd is also electrically connected to a first terminal of a switch DSW2, and the second terminal of the switch DSW2 is electrically connected to a first input terminal of a circuit DTC, and the second input terminal of the circuit DTC is electrically connected to a wiring IRFE, and the output terminal of the circuit DTC is electrically connected to the memory device MEXT. The wiring IRFE is also electrically connected to the circuit ILD, as an example.

[0268] The circuit DTC has a function of monitoring the current input to the first input terminal of the circuit DTC. Specifically, for example, the circuit DTC has a function of comparing the amount of current input to the first input terminal of the circuit DTC with the amount of current input to the second input terminal of the circuit DTC (hereinafter referred to as the amount of reference current), and when the current input to the first input terminal of the circuit DTC becomes equal to or less than the amount of the reference current, the circuit DTC has a function of outputting, for example, a command signal (for example, a pulse voltage, etc.) to the memory device MEXT from the output terminal of the circuit DTC. That is, the circuit DTC can be configured to have a current comparator, etc. When the circuit DTC is configured to have a current comparator, for example, the configuration of the circuit ACTF[j] described later in the second embodiment can be applied as the circuit DTC. Therefore, the circuit DTC can be used in common with the circuit ACTF[j] described in the second embodiment.

[0269] Strictly speaking, in the circuit LMNT in Fig. 17A, a positive current flows from the first terminal of the circuit DTC to the memory cell DC via the switch DSW2 and the wiring DLd. For this reason, it is preferable that the current input to the second terminal of the circuit DTC is a positive current that flows from the second terminal of the circuit DTC to the wiring IRFE.

[0270] For this reason, the wiring IRFE functions as, for example, a wiring that provides a constant current as a reference current. In addition, as will be described later in detail, the first input terminal of the circuit DTC is connected to the first terminal and the second terminal of the transistor M1d. 0The constant current to be used as the reference current is, for example, a current amount I 0 Specifically, the current amount I 0 For example, the current amount I 0 It can be 0.95 times, 0.90 times, 0.80 times, etc.

[0271] The reference current may be generated by the circuit ILD. For example, in FIG. 17A, the circuit ILD is electrically connected to the wiring IRFE, so that the circuit ILD can supply the reference current generated by the circuit ILD to the wiring IRFE.

[0272] Moreover, the memory device MEXT reads out rewrite data (data originally written in the multiplication cell) from the memory device MEXT by receiving a command signal from the circuit DTC. The read out data is input to the calculation unit CLP via the circuit ILD.

[0273] An example of the configuration of the circuit ILD in this case is shown in Fig. 17B. The circuit ILD shown in Fig. 17B includes, as an example, a circuit WCS1 and a circuit WCSA.

[0274] The circuit WCS1 in Fig. 17B is a part of the circuit WCS1 in Fig. 2A, and shows only circuit elements related to writing to the memory cell DC. Specifically, the circuit WCS1 in Fig. 17B shows only the current source CC[u] and the switch SW[u]. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are set to the off state, and the current generated by the current sources CC[1] to CC[K] other than the current source CC[u] does not flow through the wiring IL.

[0275] 17B includes a current source CCA, a transistor F6A, and a transistor F6B. An input terminal of the current source CCA is electrically connected to the wiring VDL, an output terminal of the current source CCA is electrically connected to a first terminal of the transistor F6B, a gate of the transistor F6B, and a gate of the transistor F6A, and a second terminal of the transistor F6B is electrically connected to the wiring VSE. A first terminal of the transistor F6A is electrically connected to the wiring IRFE, and a second terminal of the transistor F6A is electrically connected to the wiring VSE.

[0276] The wiring VSE functions as, for example, a wiring that applies a constant voltage, which may be, for example, a low-level potential or a ground potential.

[0277] The transistors F6A and F6B are preferably, for example, Si transistors. In addition to Si transistors, OS transistors, transistors including Ge or the like in a channel formation region, transistors including a compound semiconductor in a channel formation region, transistors including a carbon nanotube in a channel formation region, transistors including an organic semiconductor in a channel formation region, and the like can be used.

[0278] It is also assumed that the amounts of current generated by the current source CC[u] and the current source CCA are equal to each other.

[0279] The transistors F6A and F6B of the circuit WCSA are configured as a current mirror circuit. Therefore, when the sizes (e.g., channel length, channel width, structure, etc.) of the transistors F6A and F6B are equal, ideally, the amount of current flowing between the first and second terminals of the transistor F6B is equal to the amount of current flowing between the first and second terminals of the transistor F6A. In other words, the amount of current generated by the current source CCA is equal to the amount of current flowing between the first and second terminals of the transistor F6A.

[0280] In addition, since the circuit LMNT in FIG. 17A is configured so that a positive current flows from the second terminal of the circuit DTC to the wiring IRFE, the circuit WCSA of the circuit ILD shown in FIG. 17B is configured so that a positive current flows from the wiring IRFE to the first terminal of the transistor F6A.

[0281] Here, by making the ratio W / L of the W length to the L length of transistor F6A smaller than the ratio W / L of the W length to the L length of transistor F6B, the amount of current flowing between the first terminal and the second terminal of transistor F6A can be made smaller than the amount of current flowing between the first terminal and the second terminal of transistor F6B (i.e., the amount of current generated by current source CCA).

[0282] 17B, ​​the amount of current flowing through the wiring IRFE can be made smaller than the amount of current flowing through the wiring IL, as described above. Note that the ratio W / L of the width to the length of the transistor F6A and the ratio W / L of the width to the length of the transistor F6B are made the same, and the amount of current generated by the current source CC[u] is increased to make the amount of current I 0 A difference may be made between the current and the reference current.

[0283] Next, an example of the operation of the circuit LMNT in FIG. 17A will be described.

[0284] First, in the circuit LMC[i], the switch DSW1 is turned on, the switch DSW2 is turned off, and the transistor M2d is turned on. Next, similarly to the circuit LMNT of FIG. 16, a voltage V nd is written, turning off the transistor M2d and holding the voltage of the node n1d.

[0285] At this time, a current I 0 Then, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0286] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW1 is turned off and the switch DSW2 is turned on. This causes the amount of current I flowing from the first input terminal of the circuit DTC to the wiring VEd via the switch DSW2 and the wiring DLd and between the first terminal and the second terminal of the transistor M1d. 0 A current of flows.

[0287] Here, the potential V held at the first terminal of the capacitance C1d is nd When the capacitance of the transistor M1d decreases due to leakage of electric charge, the amount of current flowing between the first terminal and the second terminal of the transistor M1d is I 0 When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IRFE, or when it becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal from the output terminal of the circuit DTC to the memory device MEXT to read data to be rewritten from the memory device MEXT (data that was originally written in the multiplication cell). As a result, the data read from the memory device MEXT is input to the calculation unit CLP via the circuit ILD, and the deteriorated data is overwritten with that data. At this time, the potential held in the memory cell DC is also restored to the data before deterioration (potential V nd ) is preferable.

[0288] 17A as the semiconductor device SDV2, it is possible to easily detect the deterioration of the data held in the memory element of the multiplication cell of the operation unit CLP (reduction in the absolute value of the charge amount due to leakage current). In addition, by detecting the deterioration, it is possible to rewrite the data (replenish the charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0289] <<Configuration example 3 of circuit LMNT and circuit ILD>> Here, a configuration example of a circuit LMNT that is different from the circuit LMNT in FIG. 16 and FIG. 17A and that can be applied to the semiconductor device SDV2 will be described.

[0290] The circuit LMNT shown in Fig. 18A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL) like the circuit LMNT in Fig. 16. However, the circuit LMC[i] in Fig. 18A differs from the circuit LMC[i] in Fig. 16 in that it includes a memory cell DC, a circuit CMPD, and a switch DSW1. Note that Fig. 18A also illustrates a circuit ILD.

[0291] Also, the memory cell DC shown in Fig. 18A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 18A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 18A, refer to the description of the circuit LMNT in Fig. 16.

[0292] The circuit LMNT in Fig. 18A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0293] As the switch DSW1, like the switch DSW1 in FIG. 16, for example, a switch applicable to the above-mentioned switch RSW can be used.

[0294] The wiring IL is electrically connected to a first terminal of the switch DSW1, and a second terminal of the switch DSW1 is electrically connected to a wiring DLd. A first input terminal of the circuit CMPD is electrically connected to a gate of the transistor M1d, a second terminal of the transistor M2d, and a first terminal of the capacitor C1. A second input terminal of the circuit CMPD is electrically connected to a wiring VRFE. An output terminal of the circuit CMPD is electrically connected to a wiring RSUL. The wiring VRFE is electrically connected to the circuit ILD. Although not shown, the wiring RSUL is electrically connected to the memory device MEXT.

[0295] The wiring VRFE functions as a wiring that applies a constant voltage, for example. The constant voltage is, for example, a voltage V written to the node n1d by a circuit ILD (current source circuit or voltage source circuit). nd Specifically, the voltage V nd For example, a voltage lower than V nd It can be 0.95 times, 0.90 times, 0.80 times, etc. Hereinafter, the constant voltage provided by the wiring VRFE is called the reference potential.

[0296] The reference potential may be generated by the circuit ILD. For example, in FIG. 18A, the circuit ILD is electrically connected to the wiring IRFE, and therefore the circuit ILD can supply the reference current generated by the circuit ILD to the wiring IRFE.

[0297] An example of the configuration of the circuit ILD in this case is shown in Fig. 19. The circuit ILD shown in Fig. 19 includes, as an example, a circuit WCS1 and a circuit WCSA.

[0298] The circuit WCS1 shown in Fig. 19 is a part of the circuit WCS1 in Fig. 2A, and shows circuit elements related to writing to the memory cell DC. Specifically, in the circuit WCS1 in Fig. 19, for example, the current source CC[u] and the switch SW[u] are shown. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are set to the off state, and the current generated by the current sources CC[1] to CC[K] other than the current source CC[u] does not flow through the wiring IL.

[0299] 19 includes a current source CCB and a transistor F7. An input terminal of the current source CCB is electrically connected to a first terminal of the transistor F7, a gate of the transistor F7, and a wiring VRFE, and a second terminal of the transistor F7 is electrically connected to a wiring VSE.

[0300] As the transistor F7, for example, a transistor applicable to the transistor F6A or the transistor F6B illustrated in FIG. 17B, or the transistor M1d illustrated in FIG. 17A can be used.

[0301] It is also assumed that the amounts of current generated by the current source CC[u] and the current source CCB are equal to each other.

[0302] The transistor F7 of the circuit WCSB is configured as a diode connection. In addition, when focusing on the memory cell DC of FIG. 18A, the connection configuration of the transistor F7 and the current source CCB is approximately the same as the connection configuration of the transistor M1d and the current source CC[u] when the transistor M2d is in the on state. In this case, if the size (e.g., channel length, channel width, structure, etc.) of the transistor F7 and the transistor M1d is the same, ideally, the potential of the first terminal (gate) of the transistor F7 and the potential of the node n1d are the same.

[0303] Here, by making the ratio W / L of the width to the length of the transistor F7 larger than the ratio W / L of the width to the length of the transistor M1d, the potential of the first terminal (gate) of the transistor F7 is set to the potential V nd In addition, by making the ratio W / L of the width and length of the transistor F7A and the ratio W / L of the width and length of the transistor M1d the same and increasing the amount of current generated by the current source CC[u], the V held at the node n1d can be reduced. nd and the reference potential may be differentiated.

[0304] By configuring the circuit ILD as shown in FIG. 19, as described above, the potential given to the wiring VRFE is set to the potential V nd can be made smaller than

[0305] The circuit CMPD has a function of comparing a voltage input to a first input terminal of the circuit CMPD with a voltage input to a second input terminal of the circuit CMPD and outputting the comparison result to an output terminal of the circuit CMPD. Therefore, the circuit CMPD can be configured to have, for example, a voltage comparator.

[0306] Next, an example of the operation of the circuit LMNT in FIG. 18A will be described.

[0307] First, in the circuit LMC[i], the switch DSW1 is turned on and the transistor M2d is turned on. Next, similarly to the circuit LMNT of FIG. 16, a voltage V nd is written, turning off the transistor M2d and holding the voltage of the node n1d.

[0308] At this time, the first input terminal of the circuit CMPD is connected to the voltage V nd The second input terminal of the circuit CMPD is connected to V nd A reference potential lower than the reference potential is input.

[0309] Next, for example, the voltage V nd When the potential of the node n1d becomes lower than the reference potential due to leakage or the like, the signal (voltage) output from the output terminal of the circuit CMPD changes. For example, if the circuit CMPD outputs a low level potential from the output terminal when the potential of the node n1d is higher than the reference potential, and outputs a high level potential from the output terminal when the potential of the node n1d is lower than the reference potential, when the voltage of the node n1d becomes lower than the reference potential, the potential output from the output terminal of the circuit CMPD changes from a low level potential to a high level potential. In other words, the circuit CMPD determines that the data held in the memory cell DC has deteriorated, and changes the signal (voltage) output from the output terminal of the circuit CMPD. For this reason, the signal (voltage) can be used as a trigger signal for a rewrite operation for the data held in the multiplication cell of the calculation unit CLP and the potential held in the memory cell DC.

[0310] When a change in the signal (voltage) from the circuit CMPD is input to the memory device MEXT, the memory device MEXT reads out the data held in the memory device MEXT (the data originally written in the multiplication cell) and transmits it to the semiconductor device SDV2. As a result, the data read out from the memory device MEXT is input to the arithmetic unit CLP via the circuit ILD, and the degraded data is overwritten with the data. At this time, the potential held in the memory cell DC is also restored to the data before degradation (potential V nd ) is preferable.

[0311] 18A illustrates the configuration of the circuit LMNT that monitors the potential of the node n1d of the memory cell DC and detects the potential when the potential becomes lower than the reference potential, but the circuit included in the semiconductor device of one embodiment of the present invention is not limited to this. For example, the circuit included in the semiconductor device of one embodiment of the present invention may be a circuit obtained by changing the configuration of the circuit LMNT in FIG. 18A depending on the case or situation.

[0312] For example, since the circuit LMNT in Fig. 18A monitors the potential of the node n1d, the memory cell DC may not have the transistor M1d. Specifically, the circuit LMNT may be configured such that the memory cell DC does not have the transistor M1d, as shown in Fig. 18B.

[0313] Also, for example, as in the circuit LMNT shown in Fig. 18C, a circuit BF2 functioning as a buffer circuit may be provided instead of the circuit CMPD. Specifically, the circuit LMNT in Fig. 18C is configured such that the first terminal of the capacitance C1d, the gate of the transistor M1d, and the first terminal of the transistor M2d are electrically connected to the input terminal of the circuit BF2, and the wiring RSUL is electrically connected to the output terminal of the circuit BF2. The circuit BF2 may be configured to include, for example, a source follower circuit, a voltage follower circuit using an operational amplifier, or the like.

[0314] Also, for example, a configuration may be used that includes a circuit CMPD and a circuit BF2, as in the circuit LMNT shown in Fig. 18D. Specifically, the circuit LMNT in Fig. 18D is configured such that a first terminal of a capacitance C1d, a gate of a transistor M1d, and a first terminal of a transistor M2d are electrically connected to an input terminal of a circuit BF2, a first input terminal of a circuit CMPD is electrically connected to an output terminal of the circuit BF2, a second input terminal of the circuit CMPD is electrically connected to a wiring VRFE, and an output terminal of the circuit CMPD is electrically connected to a wiring RSUL.

[0315] <<Configuration example 4 of circuit LMNT and circuit ILD>> Next, a configuration example of the circuit LMNT that can be applied to the semiconductor device SDV2, which is different from those in FIG. 16, FIG. 17A, and FIG. 18A to FIG. 18D, will be described.

[0316] The circuit LMNT shown in Fig. 20A includes a circuit LMC[i] (i is an integer equal to or greater than 1 and equal to or less than the number of wirings IL) like the circuit LMNT in Fig. 16. However, the circuit LMC[i] in Fig. 20A differs from the circuit LMC[i] in Fig. 16 in that it includes a memory cell DC, a circuit DTC, a switch DSW2, a switch DSW3, and a switch DSW4. Note that Fig. 20 also illustrates a circuit ILD.

[0317] Also, the memory cell DC shown in Fig. 20A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 16, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 20A, refer to the description of the circuit LMNT in Fig. 16.

[0318] The circuit LMNT in Fig. 20A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0319] As the switches DSW2 to DSW4, similar to the switch DSW1 in FIG. 16, for example, switches applicable to the above-mentioned switch RSW can be used.

[0320] The wiring IL is electrically connected to a first terminal of the switch DSW4, and the second terminal of the switch DSW4 is electrically connected to the wiring DLd. Also, the first terminal of the switch DSW2 is electrically connected to the wiring DLd, and the first input terminal of the circuit DTC is electrically connected to the second terminal of the switch DSW2. Also, the first terminal of the switch DSW3 is electrically connected to the wiring IL, and the second input terminal of the circuit DTC is electrically connected to the second input terminal of the switch DSW3. The output terminal of the circuit DTC is electrically connected to the wiring RSUL. Although not shown, the wiring RSUL is electrically connected to the memory device MEXT.

[0321] For the circuit DTC, please refer to the explanation of the circuit DTC included in the circuit LMNT shown in FIG.

[0322] Next, a configuration example of the circuit ILD when the circuit LMNT in FIG. 20A is applied will be described.

[0323] FIG. 20B shows a configuration example of a circuit ILD in the case where the circuit LMNT in FIG. 20A is applied, and includes a circuit WCS1 and a circuit WCSD.

[0324] The circuit WCS1 shown in Fig. 20B is a part of the circuit WCS1 in Fig. 2A, and shows only circuit elements related to writing to the memory cell DC. Specifically, the circuit WCS1 in Fig. 20B shows only the current source CC[u] and the switch SW[u]. At this time, the switches SW[1] to SW[K] other than the switch SW[u] are set to the off state, and the current generated by the current sources CC[1] to CC[K] other than the current source CC[u] does not flow through the wiring IL.

[0325] 20B includes a current source CCD and a switch SWN. A first terminal of the switch SWN is electrically connected to a second terminal of the switch SW[u] and a line IL, the second terminal of the switch SWN is electrically connected to an input terminal of the current source CCD, and an output terminal of the current source CCD is electrically connected to a line VSE.

[0326] The switch SWN may be any switch that can be used for the switch RSW described above. If a transistor is used as an electrical switch for the switch SWN, it is preferable that the transistor be an n-channel transistor.

[0327] Moreover, the current source CCD preferably has, as an example, an n-channel transistor having a gate to which a bias voltage is applied and a source to which a low-level potential or a ground potential (a potential applied by a wiring VSE) is applied.

[0328] In addition, the amount of current generated by the current source CCD is smaller than the amount of current generated by the current source CC[u]. 0 Then, the amount of current generated by the current source CCD is I 0 It can be 0.95 times, 0.90 times, 0.80 times, etc. Hereinafter, the current generated by the current source CCD is called the reference current.

[0329] Next, an example of the operation of the circuit LMNT in FIG. 20A will be described.

[0330] First, in the circuit LMC[i], the switch DSW4 is turned on, the switches DSW2 and DSW3 are turned off, and the transistor M2d is turned on. At this time, in FIG. 20B, the switch SW[u] is turned on, and the switch SWN is turned off. As a result, a current amount I flows from the circuit ILD to the memory cell DC via the wiring IL. 0 Next, a current of V flows to the first terminal of the capacitor C1d of the memory cell DC, similar to the circuit LMNT of FIG. ndis written, turning off the transistor M2d and holding the voltage of the node n1d.

[0331] At this time, a current I 0 Then, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0332] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW4 is turned off and the switch DSW2 is turned on. This causes the amount of current I flowing from the first input terminal of the circuit DTC to the wiring VEd via the switch DSW2 and the wiring DLd and between the first terminal and the second terminal of the transistor M1d. 0 A current of flows.

[0333] At the same time that the switch DSW2 is turned on, the switch DSW3 is turned on. In addition, in FIG. 20B, the switch SW[u] is turned off, and the switch SWN is turned on. This causes a reference current to flow from the second input terminal of the circuit DTC to the line VSE via the switch DSW3, the line IL, and the switch SWN.

[0334] Here, the potential V held at the first terminal of the capacitance C1d is nd When the capacitance of the transistor M1d decreases due to leakage of electric charge, the amount of current flowing between the first terminal and the second terminal of the transistor M1d is I 0 When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IL, or becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the arithmetic unit CLP and transmit the data to the circuit ILD.

[0335] Thereafter, similar to the circuit LMNT in Fig. 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. The semiconductor device SDV2 then writes the information to the multiplication cell included in the arithmetic unit CLP by the circuit ILD, and writes the original voltage (or current) to the memory cell DC. This makes it possible to rewrite data (replenish charge) to the degraded data stored in the multiplication cell of the arithmetic unit CLP and the memory cell DC.

[0336] 20A as the semiconductor device SDV2, it is possible to easily detect the deterioration of the data held in the memory element of the multiplication cell of the operation unit CLP (reduction in the absolute value of the charge amount due to leakage current). In addition, by detecting the deterioration, it is possible to rewrite the data (replenish the charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0337] <<Configuration example 5 of circuit LMNT and circuit ILD>> Next, a configuration example of the circuit LMNT that can be applied to the semiconductor device SDV2 in FIG. 15, which differs from the configurations of the circuit LMNT shown in the circuit 15, FIGS. 17A, 18A to 18D, and FIG. 20A, will be described.

[0338] The circuit LMNT shown in Fig. 21A includes a circuit LMC[i] (where i is an integer greater than or equal to 1 and less than or equal to the number of wirings IL) and a circuit LMCr[i]. The circuit LMC[i] also includes a memory cell DC, a memory cell DCr, a circuit DTC, a switch DSW1, a switch DSW2, a switch DSW3, a switch DSW4, and a switch DSW4r. Note that Fig. 21A also illustrates a circuit ILD.

[0339] The memory cell DC has a transistor M1d, a transistor M2d, and a capacitance C1d. The memory cell DCr can have the same configuration as the memory cell DC, or a different configuration from the memory cell DC. In FIG. 21A, the memory cell DCr has the same configuration as the memory cell DC. Therefore, the memory cell DCr is marked with "r" to distinguish it from the memory cell DC. Also, the reference characters of the circuit elements included in the circuit MCr, which will be described later, are marked with "r". For example, the transistor M1dr, the transistor M2dr, and the capacitance C1dr included in the memory cell DCr shown in FIG. 21A correspond to the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC, respectively. Also, for example, the wiring VEdr and the wiring DLdr electrically connected to the memory cell DCr shown in FIG. 21A correspond to the wiring VEd and the wiring DLd electrically connected to the memory cell DC.

[0340] Also, the memory cell DC shown in Fig. 21A has the same configuration as the memory cell DC shown in Fig. 16. Therefore, for the transistor M1d, the transistor M2d, and the capacitance C1d included in the memory cell DC in Fig. 21A, and the wiring VEd, the wiring WLd, and the wiring DLd shown in Fig. 21A, refer to the description of the circuit LMNT in Fig. 16.

[0341] The circuit LMNT in Fig. 21A can have a plurality of circuits LMC[i], similar to the circuit LMNT in Fig. 16. Specifically, for example, the circuit LMNT can be configured such that the same number of circuits LMC[i] as the number of wirings IL electrically connected to the circuit ILD are arranged in one row.

[0342] As the switches DSW2, DSW3, and DSW4, similar to the switch DSW1 in FIG. 16, for example, the switches applicable to the above-mentioned switch RSW can be used.

[0343] The circuit ILD is electrically connected to the wiring IL and the wiring ILB.

[0344] The wiring IL is electrically connected to a first terminal of the switch DSW4, and the second terminal of the switch DSW4 is electrically connected to the wiring DLd. The wiring DLd is electrically connected to a first terminal of the switch DSW2, and the second terminal of the switch DSW2 is electrically connected to a first input terminal of the circuit DTC, and the output terminal of the circuit DTC is electrically connected to the wiring RSUL. The wiring ILB is electrically connected to a first terminal of the switch DSW3 and a first terminal of the switch DSW4r, and the second terminal of the switch DSW4r is electrically connected to the wiring DLdr. The second input terminal of the circuit DTC is electrically connected to the second terminal of the switch DSW3. The output terminal of the circuit DTC is electrically connected to the wiring RSUL. Although not shown, the wiring RSUL is electrically connected to the memory device MEXT.

[0345] For the circuit DTC, please refer to the explanation of the circuit DTC shown in FIG. 17A.

[0346] Next, a configuration example of the circuit ILD when the circuit LMNT in FIG. 21A is applied will be described.

[0347] FIG. 21B shows a configuration example of a circuit ILD in the case where the circuit LMNT in FIG. 21A is applied, and includes a circuit WCS1, a circuit WCS1r, a circuit WCSD, and a circuit WCSDr.

[0348] The circuit WCS1 and the circuit WCSD shown in Fig. 21B have the same configuration as the circuit WCS1 and the circuit WCSD shown in Fig. 20B, respectively. Therefore, for the circuit WCS1 and the circuit WCSD in Fig. 21B, the description of the circuit WCS1 and the circuit WCSD in Fig. 20B should be referred to.

[0349] Also, the circuit WCS1r and the circuit WCSDr shown in FIG. 21B have the same configuration as the circuit WCS1 and the circuit WCSD shown in FIG. 21B. Therefore, the circuit WCS1r and the circuit WCSDr are marked with "r" to distinguish them from the circuit WCS1 and the circuit WCSD. For example, the current source CCr[u] and the switch SWr[u] included in the circuit WCS1r shown in FIG. 21B correspond to the current source CC[u] and the switch SWr[u] included in the circuit WCS1. Also, for example, the current source CCDr[u] and the switch SWNr[u] included in the circuit WCSDr shown in FIG. 21B correspond to the current source CCD[u] and the switch SWN[u] included in the circuit WCSD.

[0350] The wiring IL is electrically connected to the second terminal of the switch SW[u] and the first terminal of the switch SWN. The wiring ILB is electrically connected to the second terminal of the switch SWr[u] and the first terminal of the switch SWNr.

[0351] Next, an example of the operation of the circuit LMNT in FIG. 21A will be described.

[0352] First, in the circuit LMC[i], the switch DSW4 is turned on, the switches DSW2 and DSW3 are turned off, and the transistor M2d is turned on. At this time, in FIG. 21B, the switch SW[u] is turned on, and the switch SWN is turned off. As a result, a current amount I flows from the circuit ILD to the memory cell DC via the wiring IL. 0 Next, a current of V flows to the first terminal of the capacitor C1d of the memory cell DC, similar to the circuit LMNT of FIG. nd is written, turning off the transistor M2d and holding the voltage of the node n1d.

[0353] At this time, a current I 0Then, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0354] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW4 is turned off and the switch DSW2 is turned on. This causes a current amount I 0 A current of flows.

[0355] At the timing when the switch DSW2 is turned on, the switch DSW3 is turned on and the switch DSW4r is turned off. In addition, in FIG. 21B, the switch SWr[u] is turned off and the switch SWNr is turned on. This causes a reference current to flow from the second input terminal of the circuit DTC to the line VSE via the switch DSW3, the line ILB, and the switch SWNr.

[0356] Here, the potential V held at the first terminal of the capacitance C1d is nd When the capacitance of the transistor M1d decreases due to leakage of electric charge, the amount of current flowing between the first terminal and the second terminal of the transistor M1d is I 0 When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of the reference current flowing from the wiring IL, or becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the arithmetic unit CLP and transmit the data to the circuit ILD.

[0357] Thereafter, similar to the circuit LMNT in Fig. 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. The semiconductor device SDV2 then writes the information to the multiplication cell included in the arithmetic unit CLP by the circuit ILD, and writes the original voltage (or current) to the memory cell DC. This makes it possible to rewrite data (replenish charge) to the degraded data stored in the multiplication cell of the arithmetic unit CLP and the memory cell DC.

[0358] 21A as the semiconductor device SDV2, it is possible to easily detect the deterioration of the data held in the memory element of the multiplication cell of the operation unit CLP (reduction in the absolute value of the charge amount due to leakage current). In addition, by detecting the deterioration, it is possible to rewrite the data (replenish the charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0359] <<Configuration example 6 of circuit LMNT and circuit ILD>> Next, as a modification of the circuit LMNT shown in FIG. 21A, a configuration example of the circuit LMNT that can be applied to the semiconductor device SDV2 in FIG. 15 will be described.

[0360] The circuit LMNT shown in Fig. 22A is a modified example of the circuit LMNT shown in Fig. 21A, and has a configuration in which the gate of the transistor M2d included in the memory cell DC is electrically connected to the wiring WLd, and the gate of the transistor M2dr included in the memory cell DCr is electrically connected to the wiring WLdr. That is, the circuit LMNT in Fig. 22A has a configuration in which the gate of the transistor M2d and the gate of the transistor M2dr are not directly connected. Therefore, for the parts of the circuit LMNT shown in Fig. 22A that are common to the circuit LMNT in Fig. 21A, please refer to the description of the circuit LMNT in Fig. 21A.

[0361] Also, as the circuit ILD in the circuit LMNT in Fig. 22A, for example, the circuit ILD shown in Fig. 21B can be applied. Hereinafter, the circuit ILD in Fig. 22A will be described on the assumption that the circuit ILD in Fig. 21B is applied.

[0362] Next, an example of the operation of the circuit LMNT in FIG. 22A will be described.

[0363] First, in the circuit LMC[i], the switch DSW4 is turned on and the switch DSW2 is turned off. Next, a high-level potential is applied to the wiring WLd to turn on the transistor M2d. At this time, in FIG. 21B, the switch SW[u] is turned on and the switch SWN is turned off. As a result, a current amount I flows from the circuit ILD to the memory cell DC via the wiring IL. 0 Next, a current of V flows to the first terminal of the capacitor C1d of the memory cell DC, similar to the circuit LMNT of FIG. nd , a low-level potential is applied to the wiring WLd to turn off the transistor M2d, and the voltage of the node n1d is held.

[0364] At this time, a current I 0 Then, the switch DSW1 is turned off to stop the current flowing between the first terminal and the second terminal of the transistor M1d.

[0365] When starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d, the switch DSW4r is turned on and the switch DSW3 is turned off. Next, a high-level potential is applied to the wiring WLdr to turn on the transistor M2dr. At this time, in FIG. 21B, the switch SWr[u] is turned off and the switch SWNr is turned on. This causes a reference current to flow from the circuit ILD through the wiring ILB to the transistor M1dr of the memory cell DCr. The potential of the node n1dr at this time is set to V REFThen, a low-level potential is applied to the wiring WLdr to turn off the transistor M2dr, and the voltage V REF is retained.

[0366] After that, the switch DSW4 is turned off and the switch DSW2 is turned on. As a result, a current of an amount I 0 A reference current flows from the second input terminal of the circuit DTC to the wiring VEdr via the switches DSW3 and DSW4r, the wiring DLdr, and the transistor M1dr.

[0367] Here, the potential V held at the first terminal of the capacitance C1d is nd When the capacitance of the transistor M1d decreases due to leakage of electric charge, the amount of current flowing between the first terminal and the second terminal of the transistor M1d is I 0 When the amount of current flowing from the first input terminal of the circuit DTC to the wiring VEd becomes equal to or less than the amount of a reference current flowing from the second input terminal of the circuit DTC to the wiring VEdr, or becomes less than the amount of the reference current, the circuit DTC determines that the data held in the memory cell DC has deteriorated, and transmits a command signal (for example, a pulse signal) to the memory device MEXT to read data to be rewritten in the multiplication cell of the arithmetic unit CLP and transmit the data to the circuit ILD.

[0368] Thereafter, similar to the circuit LMNT in Fig. 16, the memory device MEXT receives the command signal, reads out the information stored in the memory device MEXT, and transmits it to the semiconductor device SDV2. The semiconductor device SDV2 then writes the information to the multiplication cell included in the arithmetic unit CLP by the circuit ILD, and writes the original voltage (or current) to the memory cell DC. This makes it possible to rewrite data (replenish charge) to the degraded data stored in the multiplication cell of the arithmetic unit CLP and the memory cell DC.

[0369] 22A as the semiconductor device SDV2, it is possible to easily detect the deterioration of the data held in the memory element of the multiplication cell of the operation unit CLP (reduction in the absolute value of the charge amount due to leakage current). In addition, by detecting the deterioration, it is possible to rewrite the data (replenish the charge) to the multiplication cell of the operation unit CLP and the memory cell DC.

[0370] In the above operation example, the memory cell DCr is supplied with a voltage V REF In order to retain the data, the deterioration of data in the memory cell DCr (voltage V REF In this case, the memory cell DCr may have a potential V REF By starting to monitor the current flowing between the first terminal and the second terminal of the transistor M1d immediately after holding the data, it is possible to reduce the influence of deterioration of the data.

[0371] Moreover, the configuration of the circuit LMNT according to one embodiment of the present invention is not limited to the circuit configuration shown in Fig. 22A. The configuration of the circuit LMNT may change the included circuit elements, connection configuration, and the like depending on the case or situation.

[0372] For example, the circuit LMNT may be configured such that the memory cells DC and the memory cells DCr are arranged in one column, not in one row, as shown in Fig. 22B. Also, in Fig. 22B, the wiring VEd is electrically connected to the memory cells DCr instead of the wiring VEdr. Therefore, the wiring VEd and the wiring VEdr shown in Fig. 22A can be combined into one wiring by changing the configuration to that of Fig. 22B.

[0373] The memory cells DC described above may be included in, for example, the arithmetic unit CLP, not in the circuit LMNT. In this case, it is preferable that the memory cells DC are fabricated together with the multiplication cells (such as the circuit MC and the circuit MCr described in the second embodiment). Alternatively, the multiplication cells (such as the circuit MC and the circuit MCr described in the second embodiment) of the arithmetic unit CLP may be used as the memory cells DC.

[0374] The configuration of the semiconductor device SDV2 may be a combination of the configurations selected from those shown in Figures 16, 17A, 18A to 18D, 20A, 21A, 22A, and 22B.

[0375] 1A to 1C and the semiconductor device shown in FIG. 15 have been described in this embodiment, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention may have a configuration in which the semiconductor device SDV1 includes the circuit LMNT included in the semiconductor device SDV2 as the semiconductor device SDV3 as shown in FIG. 23. That is, the configuration example of the semiconductor device SDV1 described in this embodiment can be appropriately combined with the configuration example of the semiconductor device SDV2.

[0376] Incidentally, when information (e.g., current, voltage, etc.) held in a circuit included in the calculation unit CLP changes due to leakage or the like, it is preferable to periodically perform a refresh operation or a rewrite operation on the circuit. Specifically, for example, when information (e.g., current, voltage, etc.) held in a circuit included in the calculation unit CLP changes, information read from the memory device MINT is transmitted again to the circuit ILD, and the circuit ILD supplies a current (or sometimes a voltage) according to the information to the circuit.

[0377] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0378] (Embodiment 2) In this embodiment, an example of the calculation unit CLP described in the above embodiment will be described.

[0379] <Hierarchical neural network> Before describing the arithmetic circuit, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 24A shows an example, and the neural network 100 has a first layer to an Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 24A illustrates the (k-1)th layer and the kth layer (where k is an integer of 3 or more and R-1 or less) as intermediate layers, and does not illustrate the other intermediate layers.

[0380] Each layer of the neural network 100 has one or more neurons. In FIG. 24A, the first layer has neurons N 1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N 1 (k-1) Neuron N m (k-1) (where m is an integer equal to or greater than 1), and the kth layer has neurons N 1 (k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer has neurons N 1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0381] In addition, in FIG. 24A, neuron N 1 (1) , neuron N p (1) , neuron N 1 (k-1) , neuron N m (k-1) , neuron N 1 (k), neuron N n (k) , neuron N 1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0382] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output to and from each neuron. j (k) Focus on.

[0383] FIG. 24B shows the kth layer of neurons N j (k) and neuron N j (k) The input signal to neuron N j (k) 4 shows a signal output from the

[0384] Specifically, the (k-1)th layer neuron N 1 (k-1) Neuron N m (k-1) The output signals of each 1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z 1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k)is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0385] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse that connects those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the kth layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the kth layer neuron N j (k) The signal input to can be expressed by equation (2.1).

[0386]

number

[0387] In other words, the (k-1)th layer of neurons N 1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to z 1 (k-1) ~z m (k-1) The weighting coefficients w 1 (k-1) j (k) Or even w m (k-1) j (k) Then, the kth layer neuron N j (k) For w 1 (k-1) j(k) z 1 (k-1) Or even w m (k-1) j (k) z m (k-1) At this time, the kth layer neuron N j (k) The sum of the signals input to j (k) becomes equation (2.2).

[0388]

number

[0389] In addition, the weighting factor w 1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron's signal z 1 (k-1) ~z m (k-1) The result of the multiplication and accumulation of and can be biased. When the bias is b, equation (2.2) can be rewritten as the following equation.

[0390]

number

[0391] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0392]

number

[0393] The function f(u j (k) ) is an activation function in a hierarchical neural network, and may be a step function, a ramp function (ReLU function), a sigmoid function, a tanh function, a softmax function, or the like. The activation function may be the same for all neurons, or may be different. In addition, the activation function of a neuron may be the same for each layer, or may be different.

[0394] Incidentally, the signal, weighting coefficient w, or bias b output by the neuron of each layer may be an analog value or a digital value. The digital value may be, for example, a binary value or a ternary value. It may also be a value with a larger number of bits. For example, in the case of an analog value, a linear ramp function, a sigmoid function, or the like may be used as an activation function. In the case of a binary digital value, for example, a step function with an output of -1 or 1, or 0 or 1 may be used. In addition, the signal output by the neuron of each layer may be three or more values. For example, as an activation function that outputs three values, for example, a step function with an output of -1, 0, or 1, or a step function with an output of 0, 1, or 2 may be used. In addition, as an activation function that outputs five values, for example, a step function with an output of -2, -1, 0, 1, or 2 may be used. By using digital values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to reduce the circuit size, reduce power consumption, increase the calculation speed, etc. Also, by using analog values ​​for at least one of the signals, weighting coefficients w, or biases b output by the neurons in each layer, it is possible to improve the accuracy of calculations.

[0395] In neural network 100, when an input signal is input to the first layer (input layer), each layer from the first layer (input layer) to the last layer (output layer) generates an output signal based on the signal input from the previous layer using formula (2.1), formula (2.2) (or formula (2.3)), and formula (2.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0396] <Arithmetic circuit configuration example 1> Here, an example of a calculation circuit capable of performing the calculations of formula (2.2) (or formula (2.3)) and formula (2.4) in the above-mentioned neural network 100 will be described. In addition, in the calculation circuit, as an example, the weight coefficient of the synapse circuit of the neural network 100 is set to a binary value (a combination of "-1" and "+1", or a combination of "0" and "+1", etc.), a ternary value (a combination of "-1", "0", "1", etc.), or a multi-value of four or more values ​​(in the case of five values, a combination of "2", "-1", "0", "1", "2", etc.), and the activation function of the neuron is set to a function that outputs a binary value (a combination of "-1" and "+1", or a combination of "0", "+1", etc.), a ternary value (a combination of "-1", "0", "1", etc.), or a multi-value of four or more values ​​(in the case of four values, a combination of "0", "1", "2", "3", etc.). In this specification, either the weight coefficient or the value of a signal input from a neuron in a previous layer to a neuron in a next layer (sometimes referred to as a calculated value) may be referred to as first data, and the other may be referred to as second data. Note that the weight coefficient and the calculated value of the synapse circuit of the neural network 100 are not limited to digital values, and at least one of them may be an analog value.

[0397] The arithmetic circuit 110 shown in FIG. 25 is, as an example, a semiconductor device having a circuit ILD and an arithmetic unit CLP. The arithmetic unit CLP has an array unit ALP, a circuit WLD, a circuit XLD, and a circuit AFP. Note that FIG. 25 does not show the circuit LMNT electrically connected to the wiring IL and the wiring ILB, and the wirings electrically connecting the wiring IL and the wiring ILB to the circuit LMNT. The arithmetic circuit 110 corresponds to the neuron N of the kth layer in FIGS. 24A and 24B. 1 (k) Neuron N n (k) The signal z input to 1 (k-1) ~z m (k-1) Then, neuron N 1 (k) Neuron N n (k) The signal z output from each 1 (k) ~z n (k) This is a circuit that generates the following:

[0398] The entire arithmetic circuit 110 or a part thereof may be used for purposes other than neural networks (including CNNs and RNNs (recurrent neural networks) that perform convolution processing) and AI. For example, when performing multiply-and-accumulate processing, matrix calculation processing, etc. in graphics calculations or scientific calculations, the entire arithmetic circuit 110 or a part thereof may be used to perform the processing. In other words, the entire arithmetic circuit 110 or a part thereof may be used not only for AI calculations but also for general calculations.

[0399] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and wirings ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0400] <<Array section ALP>> The array section ALP has, for example, m×n circuits MP. For example, the circuits MP are arranged in a matrix of m rows and n columns in the array section ALP. In addition, in FIG. 25, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as circuit MP[i,j]. However, in FIG. 25, the circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1,n], and circuit MP[m,n] are selectively illustrated.

[0401] As an example, the circuit MP[i,j] is electrically connected to a wiring IL[j], a wiring ILB[j], a wiring WLS[i], a wiring XLS[i], a wiring OL[j], and a wiring OLB[j].

[0402] A circuit MP[i,j] is, for example, a network of neurons N i (k-1) and neuron N j (k) Specifically, the circuit MP[i,j] holds information (such as a potential, a resistance value, or a current value) corresponding to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j]. The circuit MP[i,j] also holds information corresponding to the first data (weighting coefficient) input from the neuron N i (k-1) The signal z output from i (k-1)(sometimes called the other of the first data and the second data. Here, called the second data) and the first data. As a specific example, the circuit MP[i,j] receives the second data z i (k-1) When the first data and the second data are input, information corresponding to the product of the first data and the second data (e.g., a current, a voltage, etc.) or information related to the product of the first data and the second data (e.g., a current, a voltage, etc.) is output to the wiring OL[j] and the wiring OLB[j]. Note that although an example in which the wiring IL[j] and the wiring ILB[j] are provided is shown in FIG. 25, one embodiment of the present invention is not limited to this. One embodiment of the present invention may be configured such that only one of the wiring IL[j] and the wiring ILB[j] is provided in the arithmetic circuit 110 in FIG. 25.

[0403] A specific example of the configuration of the circuit MP will be described later.

[0404] <<Circuit ILD>> For example, the circuit ILD transmits the first data w 1 (k-1) 1 (k) Or even w m (k-1) n (k) As a specific example, the circuit ILD has a function of inputting information (e.g., potential, resistance value, current value, etc.) corresponding to the circuit MP[i,j]. i (k-1) j (k) The information (for example, potential, resistance value, or current value) corresponding to the first data w is supplied via the wiring IL[j] and the wiring ILB[j]. 1 (k-1) 1 (k) Or even w m (k-1)n (k) is stored, and the first data is transmitted from the memory device MINT or the memory device MEXT to the circuit ILD, whereby the circuit ILD receives one data w i (k-1) j (k) Information corresponding to the circuit ILD (for example, a potential, a resistance value, or a current value) is supplied via the wiring IL[j] and the wiring ILB[j]. Note that a specific circuit configuration of the circuit ILD is described in the first embodiment and the like.

[0405] <<Circuit XLD>> For example, the circuit XLD transmits second data z 1 (k-1) ~z m (k-1) Specifically, the circuit XLD has a function of supplying second data z i (k-1) The wiring XLS[i] supplies information (for example, a potential, a current value, and the like) corresponding to the second data z i (k-1) The information (for example, potential, current value, etc.) corresponding to the input may be supplied through a plurality of wirings.

[0406] <<Circuit WLD>> For example, the circuit WLD has a function of selecting a circuit MP to which information (e.g., potential, resistance, current, etc.) corresponding to the first data input from the circuit ILD is to be written. For example, when writing information (e.g., potential, resistance, current, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WLS[i], and may supply a potential for turning off the write switching elements included in the circuits MP other than the i-th row to the wiring WLS. Note that although an example in which the wiring WLS[i] is provided has been shown, one embodiment of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring WLS[i] may be provided separately.

[0407] 25 shows a configuration example in which the wiring WLS[i] is provided in the arithmetic circuit 110, but one embodiment of the present invention is not limited to this. For example, the wiring WLS[i] may be replaced with a plurality of wirings. For example, the wiring XLS[i] may be replaced with a plurality of wirings, and some of the wirings XLS[i] may also be used as selection signal lines for writing information to the circuits MP[i,1] to MP[i,n]. Specifically, as in the arithmetic circuit 130 shown in FIG. 26, the wiring XLS[i] of the arithmetic circuit 110 may be replaced with wirings WX1L[i] and X2L[i], and the wiring WX1L[i] may be electrically connected to the circuits WLD and XLD. In addition, when a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] is supplied to the wiring WX1L[i] from the circuit WLD, the circuit XLD preferably has a function of turning off the electrical continuity between the circuit XLD and the wiring WX1L. 1 (k-1) ~z m (k-1)When the signal is supplied from the circuit WLD to the circuits MP[i,1] to MP[i,n], the circuit WLD preferably has a function of bringing the circuit WLD and the wiring WX1L into a non-conductive state.

[0408] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is electrically connected to each of the wirings OL[j] and OLB[j]. For example, the circuit ACTF[j] generates a signal according to each piece of information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. For example, the circuit ACTF[j] compares each piece of information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j] and generates a signal according to the comparison result. That is, for example, the circuits ACTF[1] to ACTF[n] function as circuits that perform the above-described activation function of the neural network. However, one embodiment of the present invention is not limited thereto. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting output impedance. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of converting a current or a charge into a voltage. Alternatively, for example, the circuits ACTF[1] to ACTF[n] may have a function of initializing the potentials of the wiring OL[j] and the wiring OLB[j].

[0409] 25 illustrates an example in which the circuit ACTF is provided in the arithmetic circuit 110; however, one embodiment of the present invention is not limited to this. For example, the circuit ACTF does not necessarily have to be provided in the circuit AFP.

[0410] An example of the configuration of the circuit ACTF will be described later.

[0411] <<Circuit MP>> FIG. 27A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110. As an example, the circuit MP[i,j] has a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of a weighting coefficient and an input signal (operation value) of a neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr, or a different configuration from the circuit MCr. Therefore, the circuit MCr is given the symbol "r" to distinguish it from the circuit MC. In addition, the symbols of the circuit elements included in the circuit MCr, which will be described later, are also given the symbol "r".

[0412] For example, the circuit MC includes a circuit HC, and the circuit MCr includes a circuit HCr. The circuit HC and the circuit HCr each have a function of retaining information (e.g., potential, resistance, current, etc.). Note that the first data w i (k-1) j (k) is determined according to information (e.g., potential, resistance value, current value, etc.) held in each of the circuits HC and HCr. Therefore, each of the circuits HC and HCr is determined according to the first data w i (k-1) j (k) The wiring IL[j] and the wiring ILB[j] are electrically connected to each other and supply information (for example, a potential, a resistance value, a current value, or the like) according to the input signal.

[0413] In FIG. 27A, the circuit MP[i,j] is electrically connected to the wiring VE[j] and the wiring VAr[j]. The circuit MC and the circuit MCr are electrically connected to the wiring OL[j] and the wiring OLB[j], respectively. The wiring VE[j] and the wiring VAr[j] function as wirings that supply a constant voltage. The wiring VE[j] also functions as a wiring that drains a current from the wiring OL through the circuit MC. The wiring VAr[j] also functions as a wiring that drains a current from the wiring OLB through the circuit MCr. That is, the wiring VE[j] and the wiring VAr[j] each function as a wiring that provides a constant voltage. The constant voltage can be, for example, a ground potential or a low-level potential.

[0414] The wiring WL[i] shown in FIG. 27A corresponds to the wiring WLS[i] in FIG. 25. The wiring WL[i] is electrically connected to each of the circuit HC and the circuit HCr. i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, etc.) according to the first data w, a predetermined potential is supplied to the wiring WL[i] to bring the wiring IL[j] and the circuit HC into electrical continuity, and also bring the wiring ILB[j] and the circuit HCr into electrical continuity. i (k-1) j (k) By supplying a potential according to the data w, the potential can be input to each of the circuits HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to bring the wiring IL[j] and the circuit HC into a non-conductive state and bring the wiring ILB[j] and the circuit HCr into a non-conductive state. Then, the first data w is input to each of the circuits HC and HCr. i (k-1) j (k) Each current according to the above is maintained.

[0415] For example, the first data i(k-1) j (k) Consider the case where the first data w can take one of the three values ​​"-1", "0", or "1". i (k-1) j (k) is "1", for example, a predetermined potential is held in the circuit HC so that a current corresponding to "1" flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MC, and a potential V 0 The first data w i (k-1) j (k) When is "-1", for example, a potential V 0 A predetermined potential is held in the circuit HCr so that a current corresponding to "-1" flows from the wiring OL[j] or the wiring OLB[j] to the wiring VEl[j] via the circuit MCr. Then, the first data w i (k-1) j (k) When is "0", for example, a potential V 0 is maintained, and a potential V 0 The potential V 0 For example, the potential V can be set to be equal to the potential applied by the wiring VE and / or the wiring VEr. 0 It is preferable that the power supply circuit 100 has a function of supplying the same to the wirings IL and ILB.

[0416] Therefore, the circuit ILD may be applied by changing the configuration of FIG. 2A to the configuration shown in FIG. 28. The circuit ILD of FIG. 28 is configured such that the circuit LGC is provided in the circuit ILD of FIG. 2A, and the circuit WCS1 has a switch SW[0]. A first terminal of the switch SW[0] is electrically connected to the wiring IL (wiring ILB), and a second terminal of the switch SW[0] is electrically connected to the wiring VEG. Wirings DIL[1] to DIL[K] are electrically connected to the input terminals of the circuit LGC, respectively, and an output terminal of the circuit LGC is electrically connected to the control terminal of the switch SW[0] via a wiring DAL. The wiring VEG functions as a wiring that applies a potential (for example, a low-level potential, a ground potential, etc.) equal to the potential applied by the wiring VE and / or the wiring VEl.

[0417] Note that, for example, a transistor that can be used for the switches SW[1] to SW[K] is preferably used as the switch SW[0].

[0418] The circuit LGC has a function of transmitting a signal to turn on the switch SW[0] from an output terminal of the circuit LGC when each of the wirings DIL[1] to DIL[K] transmits a signal to turn off the switches SW[1] to SW[K]. In other words, the circuit LGC has a function of transmitting a signal to turn off the switch SW[0] from an output terminal of the circuit LGC when each of the wirings DIL[1] to DIL[K] transmits a signal to turn on any one of the switches SW[1] to SW[K]. Therefore, the circuit LGC can be, for example, a logic circuit having a NAND gate when the switches SW[0] to SW[K] are p-channel transistors, or a logic circuit having a NOR gate when the switches SW[0] to SW[K] are n-channel transistors.

[0419] Also, the first data i (k-1) j (k)Let us consider a case where the first data w is not a multi-value such as "-1", "0", or "1" but an analog value, specifically, a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) is a "positive analog value", for example, a predetermined potential is held in the circuit HC so that an analog current corresponding to the "positive analog value" flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and a potential V 0 The first data w i (k-1) j (k) is a "negative analog value", for example, the circuit HC is connected to a potential V 0 A predetermined potential is held in the circuit HCr so that an analog current corresponding to a "negative analog value" flows from the wiring OLB[j] to the wiring VEl[j] via the circuit MCr. Then, the first data w i (k-1) j (k) When is "0", for example, a potential V 0 is maintained, and a potential V 0 The potential V 0 As in the previous example, it is preferable that the signal is supplied from the circuit ILD via the wiring IL and the wiring ILB.

[0420] Also, as an example, the circuit MC has a function of outputting a current corresponding to information (e.g., potential, resistance, or current) held in the circuit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current corresponding to information (e.g., potential, resistance, or current) held in the circuit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when a first potential is held in the circuit HC, the circuit MC flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the circuit HC, the circuit MC flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when a first potential is held in the circuit HCr, the circuit MCr flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the circuit HCr, the circuit MCr flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. The magnitudes of the first current value and the second current value are respectively represented by the first data w i (k-1) j (k) The first current value is determined by the value of the second current value. For example, the first current value may be greater than or less than the second current value. For further example, one of the first current value and the second current value may be zero current, i.e., the current value is 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions.

[0421] In particular, for example, the first data w i (k-1) j (k) It is preferable to configure the circuit MC and the circuit MCr so that when the first data w takes one of the three values ​​of "-1", "0", and "1", either the first current value or the second current value becomes zero. i (k-1) j (k)takes an analog value, for example, a “negative analog value”, “0”, or a “positive analog value”, the first current value or the second current value can also take an analog value, for example.

[0422] Incidentally, when the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC is made equal to the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MCr, the potential held in the circuit MC may not be equal to the potential held in the circuit MCr because the characteristics of the transistor may vary due to the manufacturing process of the transistor, etc. The arithmetic circuit described in this embodiment can make the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC approximately equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MCr, even if there is variation in the characteristics of the transistor.

[0423] In this specification, the current or voltage corresponding to the information (e.g., potential, resistance value, or current value) held in the circuit HC and the circuit HCr may be a positive current or voltage, a negative current or voltage, a zero current or zero voltage, or a mixture of positive, negative, and zero. In other words, for example, the above description "the circuit HC has a function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current or voltage corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr to the other of the wiring OL[j] or the wiring OLB[j]" can be rephrased as "the circuit HC has a function of discharging a current, voltage, etc. corresponding to information (e.g., potential, resistance, or current value) held in the circuit HC from one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of discharging a current, voltage, etc. corresponding to information (e.g., potential, resistance, or current value) held in the circuit HCr from the other of the wiring OL[j] or the wiring OLB[j]."

[0424] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 27A correspond to the wiring XLS[i] in FIG. 25. Note that the second data z i (k-1) For example, the second data z i (k-1) Each potential according to the above is input.

[0425] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j], and the circuit MCr is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MC and the circuit MCr transmit the first data w i (k-1) j (k) and the second data z i (k-1) A current or potential according to the product of x and x is output. As a specific example, the output destination of the current from the circuit MC and the circuit MCr is determined by the potential of the wiring X1L[i] and the wiring X2L[i]. For example, the circuit MC and the circuit MCr are configured such that the current output from the circuit MC flows to one of the wiring OL[j] and the wiring OLB[j], and the current output from the circuit MCr flows to the other of the wiring OL[j] and the wiring OLB[j]. In other words, the currents output from the circuit MC and the circuit MCr do not flow to the same wiring, but to different wirings. Note that, as an example, there are cases where the current does not flow from the circuit MC and the circuit MCr to either the wiring OL[j] or the wiring OLB[j].

[0426] For example, the second data z i (k-1) Consider the case where the second data z can take one of the three values ​​"-1", "0", or "1".i (k-1) When the second data z i (k-1) When the second data z i (k-1) When is "0", in order to prevent the currents output by the circuits MC and MCr from flowing through either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state.

[0427] Here is an example of the above operations. i (k-1) j (k) When the first data w is "1", a current may flow from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MC, and a current does not flow from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the second data z i (k-1) When the second data z is “1”, the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1) When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1)j (k) and the second data z i (k-1) When the product of the first data w is a positive value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a negative value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. i (k-1) j (k) and the second data z i (k-1) When the product is zero, no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VE[j], and no current flows from the wiring OL[j] or the wiring OLB[j] to the wiring VEr[j].

[0428] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero.i (k-1) j (k) is "0", and the second data z i (k-1) When is "1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero.

[0429] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. At this time, the magnitude of the second current value is, for example, zero.

[0430] In addition, the second data z i (k-1)When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1) j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0431] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is a positive value, a current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is negative, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. i (k-1) j (k) When the value is positive, a current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k)When is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OL[j] flows to the wiring OL[j]. That is, a current having a value obtained by summing up the positive values ​​flows in the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or the circuit MCr connected to the wiring OLB[j] flows to the wiring OLB[j]. That is, a current having a value obtained by summing up the negative values ​​flows in the wiring OLB[j]. As a result of the above operation, the total current value flowing in the wiring OL[j], that is, the sum of the positive values, and the total current value flowing in the wiring OLB[j], that is, the sum of the negative values, are used to perform a product-sum operation. For example, when the total current value flowing in the wiring OL[j] is greater than the total current value flowing in the wiring OLB[j], it can be determined that the product-sum operation results in a positive value. When the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the product-sum operation is a negative value. When the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same value, it can be determined that the result of the product-sum operation is zero.

[0432] In addition, the second data z i (k-1) The same operation can be performed when the first data w is one of two values ​​of "-1", "0", and "1", for example, the two values ​​of "-1" and "1", or the two values ​​of "0" and "1". i (k-1) j (k) The same operation can be performed when the value is any one of two values ​​"-1", "0", or "1", for example, when the value is "-1" or "1", or when the value is "0" or "1".

[0433] In addition, the first data i (k-1) j (k)may take a multi-bit (multi-value) digital value. As a specific example, the first data w i (k-1) j (k) The first data w may take five values: "-2", "-1", "0", "1", and "2". i (k-1) j (k) When "+2" is set, the magnitude of the current flowing from the circuit MC is the first data w i (k-1) j (k) The voltages of the circuits HC and HCr of the circuit MP are held so that the current flow is twice as large as when the first data w is "+1" and the current flowing from the circuit MCr is zero. i (k-1) j (k) When "-2" is set, the magnitude of the current flowing from the circuit MCr is the first data w i (k-1) j (k) is "-1", and the amount of current flowing from the circuit MC is set to zero.

[0434] Also, the first data i (k-1) j (k) may take an analog value. As a specific example, a "negative analog value" may be taken instead of "-1", and a "positive analog value" may be taken instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may be, for example, the first data w i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0435] In addition, the second data z i (k-1) If the second data zi (k-1) In this case, the input time is determined according to the value of the second data z i (k-1) When is a positive value, the second data z i (k-1) A high-level potential may be applied to the wiring X1L[i] and a low-level potential may be applied to the wiring X2L[i] for a period of time corresponding to the second data z i (k-1) When is negative, the second data z i (k-1) A low-level potential is applied to the wiring X1L[i] and a high-level potential is applied to the wiring X2L[i] for a period of time corresponding to the first data w i (k-1) j (k) The integration circuit converts the amount of charge flowing through the wiring OL[j] or the wiring OLB[j] into a voltage, thereby obtaining the first data w i (k-1) j (k) and the second data z i (k-1) In other words, by applying the above configuration, the voltage corresponding to the product of the first data w i (k-1) j (k) is a multi-value or analog value, and the second data z i (k-1) It is possible to perform a multiplication operation with multi-valued or analog values.

[0436] Moreover, the circuit MC may have not only one circuit HC, but also two or more circuits HCr. By having two or more circuits HC (circuits HCr) in the circuit MC (circuit MCr), two or more first data can be held in the circuit MP. Furthermore, by providing a driving circuit for selecting one of the two or more circuits HC (circuits HCr) in the calculation unit CLP, the first data to be calculated in the calculation unit CLP can be selected. Therefore, by configuring such a circuit MP, the circuit MP can perform a multiplication of one selected from the two or more first data and the input second data by switching the two or more circuits HC (circuits HCr) provided in the circuit MC (circuit MCr). Furthermore, by applying such a circuit MP to the entire array unit ALP, when performing a product-sum operation between a plurality of first data and a plurality of second data, each of the plurality of first data can be switched to another plurality of first data.

[0437] Next, a specific example of the circuit configuration of Fig. 27A will be described. The circuit configuration shown in Fig. 27B is an example of the circuit configuration of the circuit MP of Fig. 27A, and the circuit MC included in the circuit MP of Fig. 27B has, as an example, transistors M1 to M5, which are n-channel transistors, and a capacitance C1. For example, a circuit HC is formed by a transistor M2 and a capacitance C1.

[0438] In the circuit MP of Fig. 27B, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are marked with "r" to distinguish them from the circuit elements of the circuit MC. For this reason, the transistors M1r to M5r, the capacitance C1r, and the node n1r are described below with reference to the transistors M1 to M5, the capacitance C1, and the node n1.

[0439] In addition, in this specification and the like, unless otherwise specified, the transistor M1 includes a case where it finally operates in the saturation region when it is in the on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors include a case where they are appropriately biased to a voltage within the range in which they operate in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude value of the voltage supplied, the transistor M1 may operate in a linear region. In addition, in order to reduce the amount of current flowing through the transistor M1, the transistor M1 may operate in a subthreshold region. Alternatively, the transistor M1 may operate near the boundary between the saturation region and the subthreshold region. In addition, when the first data (weighting coefficient) is an analog value, for example, the transistor M1 may operate in a linear region, a saturation region, and a subthreshold region depending on the magnitude of the first data (weighting coefficient). Alternatively, the transistor M1 may operate in a linear region and in a saturation region, or may operate in a saturation region and in a subthreshold region, or may operate in a linear region and in a subthreshold region.

[0440] In this specification and the like, unless otherwise specified, the transistors M2 to M5 are assumed to finally operate in a linear region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are assumed to include a case where the transistors are appropriately biased to a voltage within a range in which the transistors operate in a linear region. However, one embodiment of the present invention is not limited to this. For example, the transistors M2 to M5 may operate in a saturation region or a subthreshold region when they are on. Alternatively, the transistors M2 to M5 may operate near the boundary between the saturation region and the subthreshold region. Alternatively, the transistors M2 to M5 may operate in a linear region and a saturation region in a mixed state, or may operate in a saturation region and a subthreshold region in a mixed state, or may operate in a linear region and a subthreshold region in a mixed state, or may operate in a linear region, a saturation region, and a subthreshold region in a mixed state.

[0441] Moreover, it is preferable that the sizes, for example, the channel length and the channel width, of the transistor M3 and the transistor M4 shown in FIG. 27B are equal to each other. By using such a circuit configuration, it is possible to efficiently perform layout. It is also possible to make the currents flowing through the transistors M3 and M4 uniform. Similarly, it is preferable that the sizes of the transistors M1 and M1r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M2 and M2r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M5 and M5r shown in FIG. 27B are equal to each other. Similarly, it is preferable that the sizes of the transistors M3 and M3r, and the sizes of the transistors M4 and M4r shown in FIG. 27B are equal to each other.

[0442] Although each of the transistors M1 to M5 is illustrated as an n-channel transistor in FIG. 27B, each of the transistors M1 to M5 may be replaced with a p-channel transistor. In this case, a p-channel transistor having an SOI (Silicon On Insulator) structure may be used as each of the transistors. The constant voltage applied to the wirings VE and VEr is preferably a high-level potential. Incidentally, in order to reduce the amplitude of the voltage applied to the gate of the transistor M2 (for example, an OS transistor), the transistor M1 (for example, a Si transistor) is preferably an n-channel transistor.

[0443] 27B, each of the transistors M2 to M5 may be replaced with an analog switch, a mechanical switch, etc. The analog switch may have a CMOS configuration using, for example, an n-channel transistor and a p-channel transistor.

[0444] The transistors M1 to M5 shown in FIG. 27B are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M5 has a first gate and a second gate. However, in this specification and the like, for convenience, the first gate is described as a gate (sometimes referred to as a front gate) and the second gate is described as a back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification and the like, the term "gate" can be interchanged with the term "back gate". Similarly, the term "back gate" can be interchanged with the term "gate". As a specific example, a connection configuration in which "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring".

[0445] Furthermore, the semiconductor device according to one embodiment of the present invention does not depend on the connection configuration of the backgate of the transistor. Although the backgates of the transistors M1 to M5 illustrated in FIG. 27B are illustrated, and the connection configuration of the backgates is not illustrated, the electrical connection destination of the backgates can be determined at the design stage. For example, in a transistor having a backgate, the gate and the backgate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the backgate of the transistor M2 may be electrically connected. For example, in a transistor having a backgate, a wiring electrically connected to an external circuit or the like may be provided to change the threshold voltage of the transistor or reduce the off-current of the transistor, and a fixed potential or a variable potential may be applied to the backgate of the transistor by the external circuit or the like. Note that this is true not only for FIG. 27B but also for transistors described in other parts of the specification or transistors illustrated in other drawings.

[0446] The semiconductor device of one embodiment of the present invention does not depend on the structure of the transistors included in the semiconductor device. For example, each of the transistors M1 to M5 illustrated in FIG. 27B may have a structure without a backgate, that is, a single-gate transistor. Some of the transistors may have a backgate, and other transistors may have a structure without a backgate.

[0447] In addition, in this specification and the like, transistors with various structures can be used as the transistor. Therefore, the type of the transistor used is not limited. As an example of the transistor, a transistor having single crystal silicon, or a transistor having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon, or the like can be used. Alternatively, a thin film transistor (TFT) in which such a semiconductor is thinned can be used. There are various advantages in using a TFT. For example, since the TFT can be manufactured at a lower temperature than the case of single crystal silicon, the manufacturing cost can be reduced or the manufacturing equipment can be enlarged. Since the manufacturing equipment can be enlarged, the TFT can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, the display devices can be manufactured at low cost. Alternatively, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, the transistor can be manufactured on a substrate having light-transmitting properties. Alternatively, the light transmission in the display element can be controlled by using a transistor on a substrate having light-transmitting properties. Alternatively, since the film thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0448] As an example of the transistor, a transistor having a compound semiconductor (e.g., SiGe, GaAs, etc.) or an oxide semiconductor (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.) can be used. Alternatively, a thin film transistor in which these compound semiconductors or these oxide semiconductors are thinned can be used. This allows the manufacturing temperature to be lowered, so that it is possible to manufacture a transistor at room temperature, for example. As a result, a transistor can be formed directly on a substrate with low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistor elements, pixel electrodes, or electrodes having light-transmitting properties. Since they can be formed or deposited simultaneously with the transistor, costs can be reduced.

[0449] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, since manufacturing is possible without using a mask (reticle), the layout of the transistor can be easily changed. Alternatively, since manufacturing is possible without using a resist, material costs can be reduced and the number of steps can be reduced. Alternatively, since a film can be applied only to a necessary portion, materials are not wasted and costs can be reduced compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0450] As an example of a transistor, a transistor having an organic semiconductor, a carbon nanotube, or the like can be used. This allows a transistor to be formed on a substrate that can be bent. A device using a transistor having an organic semiconductor, a carbon nanotube, or the like can be made resistant to impact.

[0451] It should be noted that transistors of various other structures can be used as the transistors. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistors. By using MOS transistors as the transistors, the size of the transistors can be reduced. Thus, a large number of transistors can be mounted. By using bipolar transistors as the transistors, a large current can be passed. Thus, the circuit can be operated at high speed. It should be noted that MOS transistors and bipolar transistors may be mixed and formed on one substrate. This allows low power consumption, miniaturization, high speed operation, etc. to be realized.

[0452] As an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below an active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below an active layer, a circuit configuration in which multiple transistors are connected in parallel is obtained. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below an active layer, it becomes easier to form a depletion layer, making it possible to improve the S value.

[0453] As an example of a transistor, a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a positive staggered structure, an inverted staggered structure, a structure in which a channel region is divided into a plurality of regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series can be used. Alternatively, the transistor can have various configurations, such as a planar type, a FIN type, a TRI-GATE type, a top gate type, a bottom gate type, and a double gate type (gates are disposed above and below the channel).

[0454] As an example of a transistor, a transistor having a structure in which a source electrode and a drain electrode overlap an active layer (or a part thereof) can be used. By using a structure in which a source electrode and a drain electrode overlap an active layer (or a part thereof), it is possible to prevent the operation from becoming unstable due to accumulation of electric charges in a part of the active layer.

[0455] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-current or improve the breakdown voltage (improve reliability) of the transistor. In addition, by providing the LDD region, even if the voltage between the drain and source changes when operating in the saturation region, the drain current does not change much, and it is possible to obtain voltage-current characteristics with a flat slope.

[0456] In addition, the above-mentioned modified examples of the connections and configurations of each terminal of the transistors can be applied not only to the circuit diagram shown in FIG. 27B but also to transistors described in other parts of the specification or transistors shown in other drawings.

[0457] In the circuit MP of FIG. 27B, a first terminal of the transistor M1 is electrically connected to the wiring VE. A second terminal of the transistor M1 is electrically connected to a first terminal of the transistor M3, a first terminal of the transistor M4, and a first terminal of the transistor M5. A gate of the transistor M1 is electrically connected to a first terminal of the capacitor C1 and a first terminal of the transistor M2. A second terminal of the capacitor C1 is electrically connected to the wiring VE. A second terminal of the transistor M2 is electrically connected to a second terminal of the transistor M5 and a wiring IL. A gate of the transistor M2 is electrically connected to a wiring WL. A second terminal of the transistor M3 is electrically connected to a wiring OL, and a gate of the transistor M3 is electrically connected to a wiring X1L. A second terminal of the transistor M4 is electrically connected to a wiring OLB, and a gate of the transistor M4 is electrically connected to a wiring X2L.

[0458] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. A second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and a second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. A first terminal of the transistor M1r and a first terminal of the capacitor C1r are electrically connected to the wiring VEl.

[0459] The first terminal of the transistor M1 may be electrically connected to another wiring instead of the wiring VE. Similarly, the first terminal of the transistor M1r may be electrically connected to another wiring instead of the wiring VE. The wiring VE may be the same wiring as the wiring VEl. In the circuit diagrams of the other drawings, the first terminal of the transistor M1 may be electrically connected to another wiring instead of the wiring VE, and / or the first terminal of the transistor M1r may be electrically connected to another wiring instead of the wiring VEl.

[0460] In the circuit HC shown in FIG. 27B, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as a node n1.

[0461] As described above, the circuit HC has a function of holding a potential corresponding to the first data, for example. The potential is held in the circuit HC included in the circuit MC of FIG. 27B by inputting a potential from the wiring IL and writing it in the capacitor C1 when the transistors M2 and M5 are turned on, and then turning off the transistor M2. This allows the potential of the node n1 to be held as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and a potential having a magnitude corresponding to the magnitude of the current can be held in the capacitor C1. This makes it possible to reduce the influence of variations in the current characteristics of the transistor M1.

[0462] In order to hold the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current as the transistor M1. For example, an OS transistor can be used as the transistor with low off-state current. Alternatively, a transistor having a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side and reduce the off-state current.

[0463] The circuit configuration applicable to the circuit MP of FIG. 27A is not limited to the configuration of the circuit MP of FIG. 27B. For example, the circuit MP of FIG. 27A can be applied with the configuration of the circuit MP of FIG. 27C. The circuit MP of FIG. 27C is a modified example of the circuit MP of FIG. 27B, and has a configuration in which the electrical connections of the first terminals of the transistor M5 and the transistor M5r are modified. Specifically, in the circuit MP of FIG. 27C, the first terminal of the transistor M5 is electrically connected to the first terminal of the transistor M2, the gate of the transistor M1, and the first terminal of the capacitor C1. By configuring the circuit MP shown in FIG. 27C, the circuit MP of FIG. 27C can operate almost similarly to the circuit MP of FIG. 27B.

[0464] <<Circuit ACTF>> Next, the circuits ACTF[1] to ACTF[n] will be described. The circuits ACTF[1] to ACTF[n] can have the circuit configuration shown in FIG. 29A, for example. FIG. 29A shows an example in which a signal z j (k) Specifically, FIG. 29A shows a circuit that generates a signal z j (k) 4 shows an example of an activation function calculation circuit that outputs

[0465] In FIG. 29A, the circuit ACTF[j] has, as an example, a resistor RE, a resistor REB, and a comparator CMP. The resistors RE and REB have a function of converting a current into a voltage. Therefore, as long as the element or circuit has a function of converting a current into a voltage, it is not limited to a resistor. The wiring OL[j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. In addition, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor RE and the second terminal of the resistor REB may be connected to the same wiring. Or, they may be connected to different wirings having the same potential.

[0466] The resistance values ​​of the resistors RE and REB are preferably equal to each other. For example, it is desirable that the difference between the resistance values ​​of the resistors RE and REB is within 10% of the resistance value of the resistor RE, more preferably within 5%. However, one aspect of the present invention is not limited to this. In some cases or depending on the situation, the resistance values ​​of the resistors RE and REB may be different from each other.

[0467] For example, the wiring VAL functions as a wiring that provides a constant voltage. The constant voltage can be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential (GND), or the like. It is preferable that the constant voltage is appropriately set according to the configuration of the circuit MP. For example, a pulse signal may be supplied to the wiring VAL instead of a constant voltage.

[0468] The voltage between the first and second terminals of the resistor RE is determined according to the current flowing from the wiring OL[j]. Therefore, a voltage corresponding to the resistance value of the resistor RE and the current is input to the first input terminal of the comparator CMP. Similarly, the voltage between the first and second terminals of the resistor REB is determined according to the current flowing from the wiring OLB[j]. Therefore, a voltage corresponding to the resistance value of the resistor REB and the current is input to the second input terminal of the comparator CMP.

[0469] As an example, the comparator CMP has a function of comparing the voltages input to the first input terminal and the second input terminal, and outputting a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP can output a high-level potential from the output terminal of the comparator CMP when the voltage input to the second input terminal is higher than the voltage input to the first input terminal, and can output a low-level potential from the output terminal of the comparator CMP when the voltage input to the first input terminal is higher than the voltage input to the second input terminal. In other words, the potentials output from the output terminal of the comparator CMP are two, a high-level potential and a low-level potential, so that the signal z output by the circuit ACTF[j] j (k) For example, the high level potential and the low level potential output from the output terminal of the comparator CMP are expressed as the signal z j (k) In some cases, the high level potential and the low level potential output from the output terminal of the comparator CMP correspond to the signal z j (k) may correspond to "+1" and "0".

[0470] In addition, in the circuit ACTF[j] of FIG. 29A, the resistors RE and REB are used, but they are not limited to resistors as long as they are elements or circuits having a function of converting a current into a voltage. Therefore, the resistors RE and REB of the circuit ACTF[j] of FIG. 29A can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 29B is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 29A are replaced with capacitors CE and CEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 29A. Note that the capacitance values ​​of the capacitors CE and CEB are preferably equal to each other. For example, it is desirable that the difference between the capacitance values ​​of the capacitors CE and CEB is within 10% of the capacitance value of the capacitor CE, more preferably within 5%. However, one embodiment of the present invention is not limited to this. Note that a circuit for initializing the charge stored in the capacitors CE and CEB may be provided. For example, a switch may be provided in parallel with the capacitor CE. That is, the second terminal of the switch may be connected to the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance CE, the wiring OL[j], and the first input terminal of the comparator CMP. Alternatively, the second terminal of the switch may be connected to a wiring different from the wiring VAL, and the first terminal of the switch may be connected to the first terminal of the capacitance CE, the wiring OL[j], and the first input terminal of the comparator CMP. In addition, the circuit ACTF[j] shown in FIG. 29C is a circuit in which the resistors RE and REB included in the circuit ACTF[j] of FIG. 29A are replaced with diode elements DE and DEB, and can perform substantially the same operation as the circuit ACTF[j] of FIG. 29A. It is desirable to appropriately change the orientation (the connection point between the anode and the cathode) of the diode elements DE and DEB depending on the magnitude of the potential of the wiring VAL.

[0471] Also, the comparator CMP included in the circuit ACTF[j] in Figures 29A to 29C can be replaced with an operational amplifier OP, for example. The circuit ACTF[j] shown in Figure 29D is a circuit diagram in which the comparator CMP of the circuit ACTF[j] in Figure 29A is replaced with an operational amplifier OP.

[0472] Also, the circuit ACTF[j] of FIG. 29B may be provided with switches S01a and S01b. This allows the circuit ACTF[j] to hold potentials corresponding to the currents input from the wiring OL[j] and wiring OLB[j] to the capacitance CE and capacitance CEB, respectively. As an example of a specific circuit, as shown in FIG. 29E, the wiring OL[j] is electrically connected to the first terminal of the switch S01a, the first terminal of the capacitance CE and the first input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01a, the wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the first terminal of the capacitance CEB and the second input terminal of the comparator CMP are electrically connected to the second terminal of the switch S01b. In the circuit ACTF[j] of FIG. 29E, when the potentials of the wiring OL[j] and wiring OLB[j] are input to the first input terminal and the second input terminal of the comparator CMP, respectively, this can be done by turning on the switches S01a and S01b. Then, by turning off the switches S01a and S01b, the potentials input to the first and second input terminals of the comparator CMP can be held in the capacitors CE and CEB. The switches S01a and S01b can be, for example, electrical switches such as analog switches and transistors. The switches S01a and S01b can be, for example, mechanical switches. When transistors are used as the switches S01a and S01b, the transistors can be OS transistors or transistors having silicon in their channel formation regions (hereinafter, referred to as Si transistors). Alternatively, the voltage values ​​of the capacitors CE and CEB can be controlled by controlling the period during which the switches S01a and S01b are kept on. For example, when the current values ​​flowing through the capacitors CE and CEB are large, the voltage values ​​of the capacitors CE and CEB can be prevented from becoming too large by shortening the period during which the switches S01a and S01b are kept on.

[0473] 29A to 29C and 29E, the comparator CMP included in the circuit ACTF[j] may be, for example, a chopper type comparator. The comparator CMP shown in FIG. 29F is a chopper type comparator, and the comparator CMP has switches S02a, S02b, and S03, a capacitance CC, and an inverter circuit INV3. The switches S02a, S02b, and S03 may be mechanical switches, OS transistors, Si transistors, or other transistors, similar to the above-mentioned switches S01a and S01b.

[0474] A first terminal of the switch S02a is electrically connected to the terminal VinT, a first terminal of the switch S02b is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the second terminal of the switch S02b and the first terminal of the capacitor CC. The second terminal of the capacitor CC is electrically connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3 and the second terminal of the switch S03.

[0475] The terminal VinT functions as a terminal for inputting an input potential to the comparator CMP, the terminal VrefT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal VoutT functions as a terminal for outputting an output potential from the comparator CMP. The terminal VinT can correspond to one of the first terminal or the second terminal of the comparator CMP in Figures 29A to 29C and 29E, and the terminal VrefT can correspond to the other of the first terminal or the second terminal of the comparator CMP in Figures 29A to 29C and 29E.

[0476] The circuit ACTF[j] in FIG. 29A to FIG. 29E converts a signal z j (k) The activation function ACTF[j] outputs the signal z j (k) Alternatively, the circuit ACTF[j] in FIG. 29A to FIG. 29E may be configured to output zj (k) The configuration is such that one signal is output, but z j (k) may be output as two or more signals.

[0477] 29A to 29E is a circuit that compares two currents and outputs the result, and therefore can be applied to the circuit DTC described in embodiment 1. Alternatively, the circuit ACTF[j] may be configured to be shared with the circuit DTC described in embodiment 1.

[0478] <Example of operation of the calculation circuit> Next, an example of the operation of the arithmetic circuit 110 in Fig. 25 will be described. In the description of this example of the operation, the arithmetic circuit 110 shown in Fig. 30 will be used as an example.

[0479] The arithmetic circuit 110 in Fig. 30 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in Fig. 25. In other words, the arithmetic circuit 110 in Fig. 30 is a circuit that corresponds to the neuron N j (k) The input to neuron N 1 (k-1) Neuron N m (k-1) Signal z from 1 (k-1) ~z m (k-1) and the weighting factor w 1 (k-1) j (k) Or even w m (k-1) j (k) 27B is applied to the circuit MP included in the array unit ALP of the arithmetic circuit 110 in Fig. 30. Also, the circuit ILD of Fig. 28 is applied to the circuit ILD of the arithmetic circuit 110 in Fig. 30.

[0480] First, in the arithmetic circuit 110, the first data w 1 (k-1) j (k) Or even w m (k-1) j (k) The first data w i (k-1) j (k) The method of setting the first data is as follows: a predetermined potential is input to the wirings WLS[1] to WLS[m] by the circuit WLD, the circuits MP[1,j] to MP[m,j] are selected in order, and a potential, a current, or the like according to the first data is supplied from the circuit ILD to the circuits HC and HCr of the circuits MC and MCr included in the selected circuit MP via the wirings IL[j] and ILB[j]. After the potential, current, or the like is supplied, the circuits MP[1,j] to MP[m,j] are deselected by the circuit WLD, so that the first data w is supplied to the circuits MC and MCr included in each of the circuits MP[1,j] to MP[m,j], and the circuits HC and HCr included in each of the circuits MP[1,j] to MP[m,j]. 1 (k-1) j (k) Or even w m (k-1) j (k) As an example, the first data w 1 (k-1) j (k) Or even w m (k-1) j (k) When each of the first data w takes a positive value, a value corresponding to the positive value is input to the circuit HC, and a value corresponding to zero is input to the circuit HCr. 1 (k-1) j (k) Or even w m (k-1) j (k)When each of the above takes a negative value, a value equivalent to zero is input to the circuit HC, and a value corresponding to the absolute value of the negative value is input to the circuit HCr. Note that, in the above, the value equivalent to zero can be, for example, the voltage provided by the wiring VEG described in FIG.

[0481] Next, the circuit XLD supplies second data z 1 (k-1) ~z m (k-1) As a specific example, the second data z 1 (k-1) is supplied.

[0482] The second data z input to each of the circuits MP[1,j] to MP[m,j] 1 (k-1) ~z m (k-1) In accordance with the second data z i (k-1) Depending on the second data z, the state may be one of the following: "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j] are electrically connected," "the circuit MC and the wiring OLB[j] are electrically connected, and the circuit MCr and the wiring OL[j] are electrically connected," and "the circuit MC and the circuit MCr are not electrically connected to the wiring OL[j] and the wiring OLB[j], respectively." 1 (k-1) When the second data z1 (k-1) When the second data z 1 (k-1) When the value of zero is taken for , a value that can bring about a non-conductive state between the circuit MC and the wiring OLB[j] and a non-conductive state between the circuit MCr and the wiring OL[j] is input to the wiring X1L[1]. Then, a value that can bring about a non-conductive state between the circuit MC and the wiring OL[j] and a non-conductive state between the circuit MCr and the wiring OLB[j] is input to the wiring X2L[1].

[0483] The second data z input to the circuit MP[i,j] i (k-1) In response to the first data w set in the circuit MP[i,j], a conductive state or a non-conductive state is determined between the circuit MC and the circuit MCr included in the circuit MP[i,j] and the wiring OL[j] and the wiring OLB[j], thereby inputting and outputting a current between the circuit MC and the wiring OL[j] and the wiring OLB[j]. Furthermore, the amount of the current is determined based on the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or second data z i (k-1) It depends on.

[0484] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Let I be the current flowing from the circuit ACTF[j] to the wiring OL[j]. out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout [j], then Iout [j] and I Bout [j] can be expressed by the following formula:

[0485]

number

[0486] In the circuit MP[i,j], for example, the first data w i (k-1) j (k) When the first data w is "+1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). i (k-1) j (k) When the first data w is "-1", the circuit MC outputs I(-1) and the circuit MCr outputs I(+1). i (k-1) j (k) When is "0", the circuit MC outputs I(-1) and the circuit MCr outputs I(-1).

[0487] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is “+1”, a state is taken in which “the circuit MC and the wiring OL[j] are conductive, the circuit MCr and the wiring OLB[j] are conductive, the circuit MC and the wiring OLB[j] are non-conductive, and the circuit MCr and the wiring OL[j] are non-conductive”, and the second data z i (k-1) is “−1”, a state is taken in which “the circuit MC and the wiring OLB[j] are electrically connected, the circuit MCr and the wiring OL[j] are electrically connected, the circuit MC and the wiring OL[j] are not electrically connected, and the circuit MCr and the wiring OLB[j] are not electrically connected” and the second data z i (k-1)is "0", the state is such that "there is no conduction between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j]."

[0488] At this time, in the circuit MP[i,j], a current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and a current I B [i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the amount of current I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0489] [Table 1]

[0490] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [j] and I Bout By inputting each of the inputs I[j] to the circuit ACTF[j], the circuit ACTF[j] can be configured as follows: out [j] and I Bout [j]. The circuit ACTF[j] may, for example, select neurons N j (k) The signal z sent to the (k+1)th layer neuron j (k) Output.

[0491] As an example, the arithmetic circuit 110 in FIG. j (k) The input to neuron N 1 (k-1) Neuron N m(k-1) Signal z from 1 (k-1) ~z m (k-1) and the weighting factor w 1 (k-1) j (k) Or even w m (k-1) j (k) 30, by providing n rows of circuits MP, a circuit equivalent to the arithmetic circuit 110 of FIG. 25 can be configured. In other words, the arithmetic circuit 110 of FIG. 25 can perform a multiplication and accumulation operation of the above and an activation function operation using the result of the multiplication and accumulation operation. 1 (k) Neuron N n (k) In each of the above, the product-sum operation and the operation of the activation function using the result of the product-sum operation can be performed simultaneously.

[0492] <<Example 1 of changing the circuits included in the arithmetic circuit>> Each of the above-mentioned arithmetic circuits 110 and 130 can be changed to a circuit that performs the calculation of formula (2.3) instead of the calculation of formula (2.2). Formula (2.3) corresponds to the calculation in which a bias is applied to the product-sum result of formula (2.2). Therefore, each of the arithmetic circuits 110 and 130 may be provided with a circuit that applies a bias value to the wiring OL and the wiring OLB.

[0493] The arithmetic circuit 170 shown in Fig. 31 has a circuit configuration in which circuits BS[1] to BS[n] are added to the array unit ALP of the arithmetic circuit 110 in Fig. 25. Note that, as the circuits BS[1] to BS[n], for example, the same circuit configurations as those in Fig. 27A to Fig. 27C may be applied.

[0494] The circuit BS[j] is electrically connected to the wiring OL[j], the wiring OLB[j], the wiring WBS, and the wiring XBS.

[0495] The wiring WBS functions as a wiring for supplying a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n], similar to the wirings WLS[1] to WLS[m] of the arithmetic circuit 110 in Fig. 25. Therefore, the wiring WBS is electrically connected to the circuit WLD, so that the signal can be supplied from the circuit WLD to the wiring WBS.

[0496] The wire XBS is connected to the neuron N in the same manner as the wires XLS[1] to XLS[m] of the arithmetic circuit 110 in FIG. i (k-1) The second data z output from i (k-1) The wiring XBS functions as a wiring that supplies information (for example, a potential, a current value, and the like) corresponding to the circuit BS[1] to the circuit BS[n]. Therefore, the wiring XBS is electrically connected to the circuit XLD, so that the information can be supplied from the circuit XLD to the wiring XBS.

[0497] The wiring XBS may also serve as a selection signal line for writing information to the circuits BS[1] to BS[n], similar to the wirings WX1L[1] to WX1L[m] of the arithmetic circuit 130 in Fig. 26. In such a configuration, the circuit WLD can supply a signal for turning on or off the write switching elements included in the circuits BS[1] to BS[n] to the wiring WBS and the wiring XBS, respectively.

[0498] In the jth column of the array portion ALP of the arithmetic circuit 170, the amount of current flowing from the circuits MP[1,j] to MP[m,j] to the wiring OL[j] or the wiring OLB[j] can be expressed by formula (2.5) and formula (2.6), respectively. Since each of the wiring OL[j] and the wiring OLB[j] is electrically connected to the circuit BS[j], the current flowing from the circuit BS[j] to the wiring OL[j] is expressed by I BIAS [j], the current flowing from circuit BS[j] to wiring OLB[j] is I BIASB When [j], equations (2.5) and (2.6) can be rewritten as the equations below.

[0499]

number

[0500] This allows the calculation of equation (2.3) to include the bias I out [j] and I Bout [j] can be generated. Also, I out [j] and I Bout [j] is input to the circuit ACTF[j], which biases the neuron N j (k) Signal z from j (k) can be generated.

[0501] 31, the circuits BS[1] to BS[n] are provided in one row in the array portion ALP, but one embodiment of the present invention is not limited to this. For example, the circuits BS[1] to BS[n] may be provided in two or more rows in the array portion ALP.

[0502] <<Example 2 of changing circuits included in the arithmetic circuit>> Here, a configuration of a circuit MP that is different from the circuit MP shown in FIGS. 27B and 27C and that can be applied to the arithmetic circuit 110 and the like will be described.

[0503] The circuit MP shown in Fig. 32 has a configuration including a memory circuit called NOSRAM (registered trademark). Note that Fig. 32 shows the entire circuit MP in order to show the electrical connection configuration of the circuit elements of the circuit HC and the circuit HCr.

[0504] The circuit MP in Fig. 32 has a configuration in which the transistor M5 and the transistor M5r are not provided in the configuration in Fig. 27B or Fig. 27C. Therefore, the circuit MP in Fig. 32 has a configuration in which a voltage is written to the first terminal of the capacitance C1 of the circuit HC and the first terminal of the capacitance C1r of the circuit HCr.

[0505] For example, if the potential provided by the wiring VE is set to a low-level potential and a high-level potential is held at the first terminal of the capacitance C1 of the circuit HC, the transistor M1 is turned on, or if a low-level potential is held at the first terminal of the capacitance C1 of the circuit HC, the transistor M1 is turned off.

[0506] Here, for example, consider a case where values ​​of "-1", "0", and "+1" are written as the first data to the circuit MP. When "+1" is written as the first data to the circuit MP, the potentials held in the circuits HC and HCr may be a combination of a high-level potential and a low-level potential. When "-1" is written as the first data to the circuit MP, the potentials held in the circuits HC and HCr may be a combination of a low-level potential and a high-level potential. When "0" is written as the first data to the circuit MP, the potentials held in the circuits HC and HCr may be a combination of a low-level potential and a low-level potential. The circuits HC and HCr may hold three or more potentials, analog values, etc., instead of the two values ​​of the high-level potential and the low-level potential.

[0507] Next, after writing the first data to the circuit MP as described above, by inputting voltages corresponding to the second data to the wiring X1L and the wiring X2L as in the previous operation example, as a result of the product of the first data and the second data, a current flows (or may not flow) from the wiring OL or the wiring OLB to the wiring VE via the circuit MC, and a current flows (or may not flow) from the wiring OL or the wiring OLB to the wiring VE through the circuit MCr.

[0508] Next, a configuration of a circuit MP that is different from the circuit MP shown in FIG. 27B, FIG. 27C, and FIG. 32 and that can be applied to the arithmetic circuit 110 and the like will be described.

[0509] The circuit MP shown in Fig. 33A has a configuration including a memory circuit including elements similar to those of the load circuit LC described in Fig. 10. Note that Fig. 33 shows the entire circuit MP in order to show the electrical connection configuration of the circuit elements of the circuit HC and the circuit HCr.

[0510] 33A, the circuit MC includes a circuit HC, a transistor M3, and a transistor M4, and also includes a load circuit LC2 and a transistor M8.

[0511] For the transistor M8, for example, a transistor applicable to the transistor M2 can be used. Therefore, for the transistor M8, the description of the transistor M2 can be referred to.

[0512] In addition, for the configurations of the transistors M3, M4, M3r, and M4r, please refer to the descriptions of the transistors M3, M4, M3r, and M4r described elsewhere.

[0513] In the circuit MC of the circuit MP of FIG. 33A, a first terminal of the load circuit LC2 is electrically connected to a first terminal of the transistor M8, a first terminal of the transistor M3, and a first terminal of the transistor M4, and a second terminal of the load circuit LC2 is electrically connected to the wiring VL. Also, a second terminal of the transistor M8 is electrically connected to the wiring IL, a second terminal of the transistor M3 is electrically connected to the wiring OL, and a second terminal of the transistor M4 is electrically connected to the wiring OLB. Also, a gate of the transistor M8 is electrically connected to the wiring WLS, a gate of the transistor M3 is electrically connected to the wiring X1L, and a gate of the transistor M4 is electrically connected to the wiring X2L.

[0514] The circuit MCr of the circuit MP in Fig. 33A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are marked with "r" to distinguish them from the circuit elements of the circuit MC. The first terminal of the transistor M8r is electrically connected to the wiring ILB, the second terminal of the transistor M3r is electrically connected to the wiring OLB, and the second terminal of the transistor M4r is electrically connected to the wiring OL.

[0515] The wiring VL and the wiring VLr function as wirings for supplying a constant voltage. The constant voltage can be, for example, a ground potential (GND) or a low potential within a range that allows the load circuits LC2 and LC2r to operate normally.

[0516] As an example, the load circuits LC2 and LC2r are circuits that can change the resistance value between the first terminal and the second terminal, similar to the load circuit LC in Fig. 10. By changing the resistance value between the first terminal and the second terminal of the load circuits LC2 and LC2r, the amount of current flowing between the first terminal and the second terminal of the load circuits LC2 and LC2r can be changed.

[0517] Here, a method of changing the resistance value between the first terminal and the second terminal of the load circuit LC2 and the load circuit LC2r in the circuit MP of FIG. 33A will be described. First, a low-level potential is input to each of the wiring X1L and the wiring X2L to turn off the transistor M3, the transistor M3r, the transistor M4, and the transistor M4r. Next, a high-level potential is input to the wiring WL to turn on the transistor M8 and the transistor M8r, and the potential of the wiring IL (wiring ILB) is changed to set the resistance value between the first terminal and the second terminal of the load circuit LC2 (load circuit LC2r). For example, there is a method of inputting a potential to the wiring IL (wiring ILB) for resetting the resistance value between the first terminal and the second terminal of the load circuit LC2 (load circuit LC2r), and then inputting a potential to the wiring IL (wiring ILB) so that the resistance value between the first terminal and the second terminal of the load circuit LC2 (load circuit LC2r) becomes a desired value. After the resistance value between the first terminal and the second terminal of the load circuit LC2 (load circuit LC2r) is set to a desired value, a low-level potential is input to the wiring WL to turn off the transistor M8 and the transistor M8r.

[0518] As the load circuit LC2 and the load circuit LC2r, for example, a resistance change element VR2 included in a ReRAM or the like can be used as shown in Fig. 33B. Also, as the load circuit LC2 and the load circuit LC2r, for example, a load circuit LC2 including an MTJ element MR2 included in an MRAM or the like can be used as shown in Fig. 33C. Also, as the load circuit LC2 and the load circuit LC2r, for example, a resistance element including a phase change material used in a phase change memory (PCM) or the like (here, for convenience, referred to as a phase change memory PCM2) can be used as shown in Fig. 33D.

[0519] Also, as the load circuit LC2 and the load circuit LC2r, for example, as shown in Fig. 33E, a ferroelectric capacitor FEC sandwiched between a pair of electrodes used in FeRAM etc. can be used. In this case, the wiring VL functions as a plate line, not as a wiring that applies a constant voltage.

[0520] Next, a configuration of a circuit MP that is different from the circuits MP shown in FIGS. 27B, 27C, 32, and 33A and that can be applied to the arithmetic circuit 110 and the like will be described.

[0521] Fig. 34A shows a circuit MP in which the circuit HC in Fig. 32 is provided with an inverter loop circuit IVR instead of the transistor M1 and the capacitance C1, and the circuit HCr in Fig. 32 is provided with an inverter loop circuit IVRr instead of the transistor M1r and the capacitance C1r. That is, the circuit MP in Fig. 34A has a configuration having an SRAM memory circuit. Note that the wiring VE and wiring VEr are omitted in the circuit MP in Fig. 34A.

[0522] The inverter loop circuit IVR has an inverter circuit IV1 and an inverter circuit IV2, and the inverter loop circuit IVRr has an inverter circuit IV1r and an inverter circuit IV2r.

[0523] The output terminal of the inverter circuit IV1 is electrically connected to the input terminal of the inverter circuit IV2, the first terminal of the transistor M3, the first terminal of the transistor M4, and the first terminal of the transistor M1, and the output terminal of the inverter circuit IV2 is electrically connected to the input terminal of the inverter circuit IV1. The second terminal of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring X1L. The second terminal of the transistor M4 is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L. The second terminal of the transistor M2 is electrically connected to the wiring IL, and the gate of the transistor M2 is electrically connected to the wiring WLS. The output terminal of the inverter circuit IV1r is electrically connected to the input terminal of the inverter circuit IV2r, the first terminal of the transistor M3r, the first terminal of the transistor M4r, and the first terminal of the transistor M2r, and the output terminal of the inverter circuit IV2r is electrically connected to the input terminal of the inverter circuit IV1r. A second terminal of the transistor M3r is electrically connected to the wiring OLB, and a gate of the transistor M3r is electrically connected to the wiring X1L. A second terminal of the transistor M4r is electrically connected to the wiring OL, and a gate of the transistor M4r is electrically connected to the wiring X2L. A second terminal of the transistor M2r is electrically connected to the wiring ILB, and a gate of the transistor M2r is electrically connected to the wiring WLS.

[0524] The circuit HC has a function of holding either a high level potential or a low level potential at the output terminal of the inverter circuit IV1 by the inverter loop circuit IVR, and the circuit HCr has a function of holding either a high level potential or a low level potential at the output terminal of the inverter circuit IV1 by the inverter loop circuit IVRr. Therefore, as an example, when the first data (weighting coefficient) set in the circuit MP is set to "+1", a high level potential is held at the output terminal of the inverter circuit IV1 and a low level potential is held at the output terminal of the inverter circuit IV1r, when the first data (weighting coefficient) set in the circuit MP is set to "-1", a low level potential is held at the output terminal of the inverter circuit IV1 and a high level potential is held at the output terminal of the inverter circuit IV1r, and when the first data (weighting coefficient) set in the circuit MP is set to "0", a low level potential is held at the output terminal of the inverter circuit IV1 and a low level poten...

Claims

1. A first circuit, a second circuit, and a third circuit, the first circuit includes a current source and a first switch; the second circuit includes a first transistor, a third transistor, a fourth transistor, and a first capacitance; the third circuit includes a second transistor and a second capacitance; the third circuit has a function of performing a product-sum operation; a first terminal of the first transistor electrically connected to a control terminal of the first switch; a second terminal of the first transistor electrically connected to a first terminal of the fourth transistor; a second terminal of the fourth transistor is electrically connected to a first terminal of the first capacitance; a gate of the fourth transistor is electrically connected to a second terminal of the first capacitor and a first terminal of the third transistor; a second terminal of the third transistor electrically connected to a write data line; a first terminal of the first switch electrically connected to an output terminal of the current source; a second terminal of the first switch electrically connected to a first terminal of the second transistor; a second terminal of the second transistor electrically connected to a first terminal of the second capacitor; a second terminal of the second capacitor is electrically connected to a wiring to which a constant voltage is supplied; Semiconductor device.

2. In claim 1, A fourth circuit is provided. the fourth circuit includes a latch circuit; the electrical connection between the first terminal of the first transistor and the control terminal of the first switch is established by electrically connecting a first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting a second terminal of the fourth circuit to the control terminal of the first switch. Semiconductor device.

3. a first circuit, a second circuit, a third circuit, and a sense amplifier; the first circuit includes a current source and a first switch; the second circuit includes a first transistor and a first capacitance; the third circuit includes a second transistor and a second capacitance; the third circuit has a function of performing a product-sum operation; a first terminal of the first transistor is electrically connected to a control terminal of the first switch via the sense amplifier; a second terminal of the first transistor electrically connected to a first terminal of the first capacitance; a first terminal of the first switch electrically connected to an output terminal of the current source; a second terminal of the first switch electrically connected to a first terminal of the second transistor; a second terminal of the second transistor electrically connected to a first terminal of the second capacitor; a second terminal of the second capacitor is electrically connected to a wiring to which a constant voltage is supplied; Semiconductor device.

4. In any one of claims 1 to 3, The gate of the first transistor is electrically connected to the gate of the second transistor. Semiconductor device.

5. A first circuit, a second circuit, and a third circuit, the first circuit includes a current source and a first switch; the second circuit includes a first transistor, a third transistor, and a first capacitance; the third circuit includes a second transistor and a second capacitance; the third circuit has a function of performing a product-sum operation; a first terminal of the first transistor electrically connected to a control terminal of the first switch; a first terminal of the third transistor is electrically connected to a first terminal of the first capacitor and to a gate of the first transistor; a second terminal of the third transistor electrically connected to a write data line; a first terminal of the first switch electrically connected to an output terminal of the current source; a second terminal of the first switch electrically connected to a first terminal of the second transistor; a second terminal of the second transistor electrically connected to a first terminal of the second capacitor; a second terminal of the second capacitor is electrically connected to a wiring to which a constant voltage is supplied; Semiconductor device.

6. In claim 5, A fourth circuit is provided. the fourth circuit includes a latch circuit; the electrical connection between the first terminal of the first transistor and the control terminal of the first switch is established by electrically connecting a first terminal of the fourth circuit to the first terminal of the first transistor and electrically connecting a second terminal of the fourth circuit to the control terminal of the first switch. Semiconductor device.

7. In claim 5 or claim 6, a second terminal of the first capacitance is electrically connected to a gate of the second transistor; Semiconductor device.

8. In any one of claims 1 to 7, A semiconductor device, wherein a transistor included in the second circuit has a metal oxide in a channel formation region.

9. In claim 8, The semiconductor device, wherein the metal oxide is indium oxide.

10. A semiconductor device comprising: a semiconductor device according to any one of claims 1 to 9; and a housing. electronic equipment.

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