Memory precharge circuit

Abstract

The present disclosure relates to a precharge circuit for bit lines of a memory cell array, the precharge circuit comprising a precharge and limit unit configured to precharge a first bit line and a second bit line, the precharge and limit unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and / or write operation of any of the memory cells, the precharge and limit unit configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay.

Description

Technical Field

[0001] The present disclosure relates to a power - efficient pre - charge circuit for bit lines of a memory cell array. The present disclosure further relates to a memory such as a static random access memory comprising at least one pre - charge circuit.

Background Art

[0002] Static random access memories are widely used in integrated circuits and can account for a significant portion of the power consumption of a circuit. A typical memory cell of an SRAM is a six - transistor (6T) memory cell composed of six MOSFETs. Each bit is stored in four transistors that form two cross - coupled inverters. In addition to the four transistors, the two cross - coupled inverters are connected to the bit line and the inverted bit line via two additional access transistors, which are controlled by a common word line of a standard single - port 6T SRAM cell. There are other types of SRAMs.

[0003] In an example of a standard 6T memory cell, access to the cell is enabled by a word line, which controls access transistors that control whether the cell is connected to the bit line. The bit line is used to transfer data for read and write operations. Before accessing the memory cell, a pre - charge circuit is used to initialize the bit line, i.e., in a standard operation, load the supply voltage onto the bit line. The bit line has a large capacitance due to its length and the diffusion capacitance of the access transistors. As a result of this structure and process, a large portion of the memory access energy can be consumed by pre - charging the bit line. Usually, the only way to reduce it is by voltage scaling, which brings other problems including speed and stability issues. Thus, a more power - efficient solution, particularly an improved pre - charge circuit, and a memory comprising such an improved pre - charge circuit are needed.

[0004] In content addressable memories (CAMs) and ternary content addressable memories (TCAMs), instead of reading data, the retrieved data is supplied to the memory as input, and a series of output lines, usually called match lines, output information as to whether a match has been found in the input data. In these memories, since the entire memory is accessed, the switching energy in the match lines can be very high.

[0005] U.S. Patent No. 5,771,190 discloses a static random access memory cell that can store data bits supplied from a bit line pair through two p-channel enhancement access transistors gate-controlled by word lines in a two-stable latch circuit powered by a positive high power supply voltage and a positive low power supply voltage, where the positive low power supply voltage is higher than the active level of the word lines, so that the two-stable latch circuit surely changes its state according to the logic level of the write data bits.

[0006] U.S. Patent Application Publication No. 2017 / 243633 discloses a memory cell arrangement configuration of an SRAM cell group, in which, in each of the groups, a plurality of SRAM cells are connected to the input of a local read amplifier by at least one common local bit line. The output of the amplifier is connected to a shared global bit line. The global bit line is connected to a precharge circuit, and the precharge circuit is adapted to precharge the global bit line with a programmable precharge voltage before reading data. The precharge circuit includes a limiter circuit having a precharge adjustment circuit connected to the global bit line for precharging the global bit line with the programmable precharge voltage, and an evaluation and conversion circuit connected to the precharge adjustment circuit and the global bit line for compensating for the leakage current of the global bit line without changing the voltage level.

[0007] U.S. Patent Application Publication No. 2007 / 247885 discloses an entry coupled to a match line, which includes a plurality of bits of unit cells each storing a data bit. A charging current having a limit current value smaller than the match line current flowing in a one-bit error state in one entry and larger than the match line current flowing in an all-bit match state in one entry is supplied to the match line. The precharge voltage level of the match line is limited to a voltage level equal to or lower than half of the power supply voltage.

[0008] European Patent Application Publication No. 2211352 discloses a semiconductor memory device including a first memory circuit connected to a first bit line, a second bit line, and a word line, a first precharge control circuit connected to a first precharge control line, the first bit line, and the second bit line and performing precharge of the first bit line and the second bit line based on an input from the first precharge control line, and a read control circuit having a first transistor, a second transistor, a third transistor, and a fourth transistor. The fourth transistor conducts based on an input from a charged global bit line driver control line, a column having the first bit line and the second bit line is selected accordingly, and information held in the memory circuit connected to the word line driven among the memory circuits is output to a third bit line. SUMMARY OF THE INVENTION

[0009] Accordingly, a first aspect of the present disclosure relates to reduction of dynamic power in a static random access memory or an associative memory or a ternary associative memory, and more particularly, to a precharge circuit of the memory. According to a first embodiment, the precharge circuit for the bit lines of a memory cell array A precharge and limit unit configured to precharge a first bit line and a second bit line, and further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of a memory cell. The precharge and limit unit is preferably configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle with substantially no delay.

[0010] The precharge and limit unit is preferably configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle with substantially no delay.

[0011] The precharge circuit of the present disclosure provides a compact and fast solution for limiting the precharge level of bit lines for read and write operations. This solution limits the precharge level from a floating level in a single precharge cycle and functions without significantly affecting cell stability or memory performance without significant delay.

[0012] Memory cells and precharge circuits in a memory typically operate at a common supply voltage (VDD). A precharge circuit including a precharge and limit unit can thus operate at a common supply voltage equal to the voltage level of the memory cells. However, as demonstrated in the present disclosure, it is possible to select some dimensions and types of transistors such that the transistors of the precharge circuit are connected and the voltage level of the bit line during precharge is at a lower level rather than the supply voltage. As an example, the first bit line precharge level and the second bit line precharge level may be 10 - 80% or 20 - 80% lower than the supply voltage (VDD). This implementation can imply significant power savings. This technique can be used for supply voltages within a range with sufficient margin so as not to adversely affect the stability of the memory cells. The inventor recognizes that the precharge circuit can be configured to set the first bit line precharge level from a first floating level and the second bit line precharge level from a second floating level immediately after the start of the precharge cycle. As demonstrated in the present disclosure, there are several possible embodiments including PMOS-based, NMOS-based, or combinations thereof.

[0013] The present disclosure further relates to a memory such as a static random access memory, an associative memory, or a ternary associative memory, comprising a plurality of memory cells arranged in columns and rows, the plurality of memory cells including an arrangement configuration of memory cell transistors defining a first storage node and a first inverted storage node accessed from a first bit line and a second bit line, and at least one precharge circuit, the precharge circuit being connected to the first bit line and the second bit line within a column, each precharge circuit being configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle.

[0014] By limiting the precharge level of the bit lines to a level preferably lower than the common supply voltage (VDD), as shown in FIG. 2, the dynamic power consumption of the memory can be significantly improved. The value of the limited precharge level can be adjusted so that the stability of the bit cells in read and write operations is not affected, which is achievable at the design stage. This solution is fast and applicable within the range of a single precharge operation, and can be configured to function without affecting the cell stability or memory performance.

[0015] In one embodiment of the memory, the memory has both a local precharge circuit and a global precharge circuit. Specifically, the global precharge circuit can be configured to precharge the bit lines to a precharge level that is reduced / limited, for example, a precharge level that is 10 - 80% or 20 - 80% lower than the supply voltage level, while the local precharge circuit can precharge at a sufficient supply voltage level.

Brief Description of the Drawings

[0016]

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DETAILED DESCRIPTION OF THE INVENTION

[0017] The present disclosure relates to a precharge circuit for bit lines of a memory cell array. The precharge circuit includes a precharge unit configured to precharge a first bit line and a second bit line, and a limiting unit configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cells by controlling the operation of the precharge unit. The limiting unit may be regarded as an integral part of the precharge unit. Preferably, the precharge circuit is adapted to limit the first bit line precharge level and the second bit line precharge level without delay during the precharge cycle. The first bit line may be a positive or "true" bit line, and the second bit line may be a negative or "false" bit line having a value opposite to that of the positive or "true" bit line of a column of the memory cell array. In certain situations, a memory having only one bit line instead of two may be implemented. For such a memory, the precharge circuit may be configured to precharge the first bit line and limit the first bit line to the first bit line precharge level during the precharge cycle. In one embodiment, the precharge circuit is a precharge and limiting unit configured to precharge the first bit line and further configured to limit the first bit line precharge level of the first bit line during a precharge cycle of any read and / or write operation of the memory cells, comprising the precharge and limiting unit The precharge and limiting unit is preferably configured to limit the first bit line precharge level in a single precharge cycle without substantial delay.

[0018] By extension, the precharge and limit unit may be configured and applied to any bit cell having a configuration with two or more bit lines where different bit lines are used depending on the operation. This may include, for example, a 2-port 8T bit cell having one read bit line and two read / write bit lines, and a dual-port 8T bit cell having two sets of read / write bit lines.

[0019] The limitation of the precharge level may be considered as related to the conventional precharge level which is the general supply voltage level (VDD). The precharge and limit unit may thus operate at a general voltage level (VDD) equal to the voltage level of the memory cell. This concept is illustrated in FIG. 2. Instead of precharging to VDD as in the normal approach, the bit lines are precharged to a lower VPRE level. Preferably, the precharge circuit is arranged such that precharging occurs substantially immediately when the precharge cycle starts. After access to the memory cells of the memory, the bit lines may have a floating voltage level. Thus, the precharge circuit of the memory is for preparing the bit lines for a new access. Therefore, in one embodiment of the precharge circuit of the present disclosure, the precharge circuit is configured to set the first bit line precharge level from a first floating level and the second bit line precharge level from a second floating level immediately after the start of the precharge cycle.

[0020] According to one embodiment of the precharge circuit of the present disclosure, the first bit line precharge level and the second bit line precharge level are 10 to 80% lower than the supply voltage (VDD), preferably 20 to 70% lower than the supply voltage (VDD), or 10 to 50% lower than the supply voltage (VDD), and preferably, the first bit line precharge level and the second bit line precharge level are 20 to 40% lower than the supply voltage (VDD). The precharge circuit can thereby provide a dynamically reduced precharge voltage on the bit line by precharging through a precharge circuit having a diode-connected transistor. Thereby, the precharge voltage is reduced during both read and write, and due to the square root dependence of the dynamic energy of the voltage, the access energy is reduced. The gain can be important especially for writes in the accessed word, but can also be important for the remaining cells on the accessed word line in read mode for both read and write. As demonstrated in the present disclosure, it can be implemented in various ways by connecting the transistors in a particular way, and by determining the dimensions or selecting the type of the transistors, or by changing the body bias voltage of the precharge transistors if possible.

[0021] As described above, the precharge and limit unit of the present disclosure can be implemented in many implementations. FIGS. 1, 3, and 4 show ways in which a precharge circuit can be supplemented by a precharge limit circuit, and are high-level diagrams with an equalization circuit as an option. FIGS. 5A-5E show examples of transistor-level implementations. If the precharge circuit is based on a PMOS transistor solution, one of ordinary skill in the art will recognize that an implementation can also be realized in a corresponding NMOS solution. This includes using NMOS transistors and connecting the precharge circuit to GND instead of VDD. Therefore, limiting the precharge level can be interpreted, within the scope of the context of the present disclosure, as limiting with respect to the GND level, i.e., precharging to a precharge level that is 10-80% higher than GND, 20-80% higher than GND, or 20-70% higher than GND, etc., or 10-50% higher than GND, preferably 20-40% higher than GND, etc., a precharge level higher than ground.

[0022] One embodiment of the precharge and limit unit of the present disclosure includes a PMOS transistor-based or NMOS transistor-based precharge portion configured to precharge a first bit line and a second bit line, and a PMOS transistor-based or NMOS transistor-based limit portion configured to limit the first bit line precharge level and the second bit line precharge level with respect to a supply voltage (VDD) or a ground reference level (GND) with substantially no delay by shorting the first bit line to a first limited precharge level node of the PMOS transistor-based or NMOS transistor-based limit portion and shorting the second bit line to a second limited precharge level node of the PMOS transistor-based or NMOS transistor-based limit portion.

[0023] More specifically, the precharge circuit is A first PMOS transistor, a second PMOS transistor, and a third PMOS transistor connected in series to provide a precharge portion, A fourth PMOS transistor and a fifth PMOS transistor connected between the precharge portion and a supply voltage (VDD) to provide a limiting portion, The first bit line is connected to either the fourth gate terminal of the fourth PMOS transistor or the second gate terminal of the second PMOS transistor, thereby limiting the first bit line precharge level, The second bit line is connected to either the fifth gate terminal of the fifth PMOS transistor or the third gate terminal of the third PMOS transistor, thereby limiting the second bit line precharge level.

[0024] The same structure is possible using NMOS transistors. In this embodiment, the precharge circuit A first NMOS transistor, a second NMOS transistor, and a third NMOS transistor connected in series to provide a precharge portion, A fourth NMOS transistor and a fifth NMOS transistor connected between the precharge portion and a ground reference point (GND) to provide a limiting portion with respect to the ground reference point, The first bit line is connected to either the fourth gate terminal of the fourth NMOS transistor or the second gate terminal of the second NMOS transistor, thereby limiting the first bit line precharge level with respect to the ground reference point, The second bit line is connected to either the fifth gate terminal of the fifth NMOS transistor or the third gate terminal of the third NMOS transistor, thereby limiting the second bit line precharge level with respect to the ground reference point.

[0025] According to one embodiment, the precharge circuit A first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal, A second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal, and a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, The connection between the first PMOS transistor and the second PMOS transistor defines a first bit line node connected to the first bit line, The connection between the first PMOS transistor and the second PMOS transistor defines a second bit line node connected to the second bit line, The precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal.

[0026] The limiting part is a fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth PMOS is connected between the second PMOS transistor and the supply voltage (VDD), and a fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth PMOS is connected between the third PMOS transistor and the supply voltage (VDD), The fourth gate terminal is connected to the first bit line node, and the fifth gate terminal is connected to the second bit line node.

[0027] According to one embodiment, the second PMOS transistor and the third PMOS transistor are connected to a ground reference point (GND). In this embodiment, three PMOS transistors may be sufficient to implement a ground precharge and limiting unit.

[0028] The fourth PMOS transistor and the fifth PMOS transistor can be sized such that the first bit line precharge level and the second bit line precharge level are limited as compared to the supply voltage (VDD), and / or the transistor type of the fourth PMOS transistor and the fifth PMOS transistor is selected such that the first bit line precharge level and the second bit line precharge level are limited as compared to the supply voltage (VDD). As can be seen, the combination of connecting the gate signals of the fourth transistor and the fifth transistor to the bit line and selecting the fourth transistor and the fifth transistor having the characteristic of limiting the precharge value of the bit line can be done in a way that provides the required precharge level without substantial delay. Similarly, in an NMOS implementation, the fourth NMOS transistor and the fifth NMOS transistor can be sized such that the first bit line precharge level and the second bit line precharge level are higher than the ground reference point (GND), and / or the fourth NMOS transistor and the fifth NMOS transistor are selected such that the first bit line precharge level and the second bit line precharge level are higher than the ground reference point (GND).

[0029] The PMOS transistor in this embodiment can be an NMOS transistor, and the supply voltage VDD can be GND.

[0030] According to a further embodiment, the precharge section a first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; A fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth PMOS is connected between the second PMOS transistor and the supply voltage (VDD), the fourth PMOS transistor; A fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth PMOS is connected between the third PMOS transistor and the supply voltage (VDD), the fifth PMOS transistor; and The connection between the first PMOS transistor and the second PMOS transistor defines a first bit line node connected to the first bit line. The connection between the first PMOS transistor and the third PMOS transistor defines a second bit line node connected to the second bit line. The precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal.

[0031] In this embodiment, the second gate terminal may be connected to the first bit line node, and the third gate terminal is connected to the second bit line node.

[0032] The fourth PMOS transistor and the fifth PMOS transistor can be sized such that the first bit line precharge level and the second bit line precharge level are limited as compared to the supply voltage (VDD), and / or the transistor type of the fourth PMOS transistor and the fifth PMOS transistor is selected such that the first bit line precharge level and the second bit line precharge level are limited as compared to the supply voltage (VDD).

[0033] The PMOS transistor in this embodiment can be an NMOS transistor, and the supply voltage VDD can be GND.

[0034] In a further embodiment, the precharge circuit A first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; A second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal, A third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, and, The connection between the first NMOS transistor and the second NMOS transistor defines a first bit line node connected to the first bit line, The connection between the first NMOS transistor and the third NMOS transistor defines a second bit line node connected to the second bit line, The precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal.

[0035] The limiting portion is A fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth NMOS is connected between the second NMOS transistor and a ground reference point (GND), the fourth NMOS transistor, A fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth NMOS is connected between the third NMOS transistor and a ground reference point (GND), the fifth NMOS transistor, and may further include, The fourth gate terminal is connected to the first bit line node, and the fifth gate terminal is connected to the second bit line node.

[0036] In a further embodiment, the precharge circuit is A first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal, A second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal, A third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, A fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth NMOS is connected between the second NMOS transistor and a ground reference point (GND), the fourth NMOS transistor, A fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth NMOS is connected between the third NMOS transistor and a ground reference point (GND), the fifth NMOS transistor, are provided. The connection between the first NMOS transistor and the second NMOS transistor defines a first bit line node connected to the first bit line. The connection between the first NMOS transistor and the third NMOS transistor defines a second bit line node connected to the second bit line. The precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal.

[0037] The second gate terminal may be connected to the first bit line node, and the third gate terminal may be connected to the second bit line node. The fourth NMOS transistor and the fifth NMOS transistor may be sized and / or selected such that the first bit line precharge level and the second bit line precharge level are higher than the ground reference point (GND).

[0038] From the examples of the present disclosure, it can be understood that within the scope of the precharge circuit of the present disclosure, the bit lines can be limited by a VDD limiter based on PMOS, NMOS, or a combination thereof, and by a corresponding GND limiter based on PMOS, NMOS, or a combination thereof.

[0039] The precharge circuit may further include an equalization circuit connected between the first bit line and the second bit line. The equalization circuit may be an integral part of the precharge circuit. Examples of the equalization circuit can be found in FIGS. 7A - 7C.

[0040] In one embodiment, the equalization circuit includes an NMOS transistor for equalization or a PMOS transistor for equalization connected between the first bit line and the second bit line, and the precharge signal is connected to the gate terminal of the NMOS transistor for equalization or the PMOS transistor for equalization. In an alternative embodiment, the equalization circuit includes an NMOS transistor for equalization and a PMOS transistor for equalization connected in parallel, and the NMOS transistor for equalization and the PMOS transistor for equalization are connected between the first bit line and the second bit line.

[0041] The present disclosure further relates to a memory such as a static random access memory, a plurality of memory cells arranged in columns and rows, each memory cell including an arrangement of memory cell transistors that define a first storage node and a first inverted storage node accessed from the first bit line and the second bit line, at least one precharge circuit, the precharge circuit being connected to the first bit line and the second bit line within a column, and each precharge circuit being configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle.

[0042] The precharge circuit can be any embodiment of the precharge circuit of the present disclosure. The memory cell can be, for example, a 4T, 5T, 6T, 7T, 8T, or any suitable memory cell. The memory may be a static random access memory or an associative memory or a ternary associative memory.

[0043] When the memory is an associative memory or a ternary associative memory, the precharge circuit of the present disclosure may be used to limit the match line of the memory. Accordingly, the present disclosure further provides a precharge circuit for a match line of a memory cell array, a precharge and limiting unit configured to precharge the match line, and further configured to limit the match line precharge level of the match line during a precharge cycle of any read and / or write operation of the memory cell, comprising the precharge and limiting unit, The precharge and limiting unit relates to a precharge circuit configured to limit the match line precharge level in a single precharge cycle with substantially no delay.

[0044] As an example, the arrangement configuration of the memory cell transistors is a first memory cell transistor, a second memory cell transistor, a third memory cell transistor, and a fourth memory cell transistor forming a first cross-coupled inverter and a second cross-coupled inverter defining a first storage node and a first inverted storage node; a fifth memory cell transistor connected between the first storage node and the first bit line, and / or a sixth transistor connected between the first inverted storage node and the second bit line.

[0045] The precharge circuit may include a precharge and limiting unit configured to precharge the first bit line and the second bit line, and further configured to limit the first bit line precharge level of the first bit line and the second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cell. The precharge and limit unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay.

[0046] The memory may further include, without limitation, a row decoder, a column decoder, and any additional peripheral components for operating the memory, such as sense amplifiers.

[0047] The precharge circuit of the present disclosure can be utilized in various ways in a memory structure. In the partitioning of the memory, both a local precharge circuit and a global precharge circuit can be used, or a single precharge circuit can be connected to global bit lines. Thus, in one embodiment, memory cells arranged in each column are connected to a first local bit line and a second local bit line, at least one local precharge circuit is connected to each local bit line, the first global bit line can be configured to be connected to any first local bit line, the second global bit line can be configured to be connected to any second local bit line, and the global precharge circuit is connected to the first global bit line and the second global bit line.

[0048] The local bit line and the global bit line are separated by switch elements that can be configured to enable voltage transfer from the local bit line to the global bit line during reading and from the global bit line to the local bit line during writing. According to one embodiment, the local bit line and the global bit line are separated by switch elements such as NMOS transistors. An example of this configuration is shown in FIG. 11. In this implementation, the local bit line may be precharged to full VDD, while the global bit line is precharged to a limited voltage. In one embodiment, during a write operation, one of the global bit lines is pulled down to "0" and the switch element is opened by activating the "sel" signal. The NMOS switch element limits the propagation of the limited precharge voltage to the local bit line, thereby limiting the impact of this scheme on the stability of the bit cell.

[0049] In one embodiment, during a read operation, the "sel" signal is activated simultaneously on both sides. In this embodiment, on one side, the global bit line remains constant or only the voltage increases according to the charge sharing principle with the local bit line, depending on the type of switch element used. On the opposite side, as soon as the local bit line falls below the limited precharge voltage of the global bit line, the global bit line is pulled down via the local bit line. An alternative embodiment includes discharging the local bit line below the global bit line precharge voltage and then activating the "sel" signal.

[0050] More specifically, the local precharge circuit can be the unrestricted precharge circuit of the present disclosure, and the global precharge circuit can include the restriction unit of the present disclosure. In one embodiment, the global precharge circuit is configured to precharge the bit line to a precharge level that is 10% to 80% lower than the supply voltage level (VDD) or a precharge level that is 10% to 50% lower than the supply voltage level (VDD), and the local precharge circuit is configured to precharge the bit line to the supply voltage level. Also, in this case, the precharge circuit can be a PMOS-based variant, an NMOS-based variant, or a combination thereof.

[0051] Detailed Description of the Drawings The present invention will be described in more detail with reference to the accompanying drawings. The drawings are illustrative and are intended to show some of the features of the precharge circuit and memory of the present disclosure and should not be construed as limiting the invention of the present disclosure.

[0052] FIG. 1 shows an exemplary embodiment of a precharge circuit (100) of the present disclosure for bit lines (BLT, BLF) of a memory cell array. The precharge circuit (100) includes two precharge restriction circuits (101) and an equalization circuit (110). The connection between one of the precharge and restriction circuits (101) and the equalization circuit (110) defines a first bit line node (BLT). The connection between the other of the precharge and restriction circuits (101) and the equalization circuit (110) defines a second bit line node (BLF).

[0053] Figure 2 shows an example of signal levels of memory access using the precharge circuit of the present disclosure. It can be seen that the bit lines are precharged to VPRE during the precharge cycle. During the write cycle, one of the bit lines goes to GND while there is access to the word line. In the idle cycle, the bit lines are in a virtually floating state. Next, the read access is started by the precharge cycle. During the read cycle, the word line is accessed and the cell slowly discharges one of the bit lines. The SA+ idle cycle is an idle mode where the bit lines are in a floating state again after the end of the read operation where the word line is closed and the sense amplifier is triggered.

[0054] Figure 3 shows a further embodiment of the precharge circuit (100) of the present disclosure. The precharge circuit (100) includes two limiting portions (101) configured to limit the first bit line precharge level of the first bit line and the second bit line precharge level of the second bit line during the precharge cycle, and two PMOS transistors (103, 104) constituting the precharge portion of the precharge and limiting unit, wherein the precharge signal (nPRE) is connected to the gate terminals, and an equalization circuit (110) disposed between the first bit line (BLT) and the second bit line (BLF). Figure 4 shows a similar precharge circuit (100) in which the two limiting portions (101) are disposed between the bit lines (BLT, BLF) and the two PMOS transistors (103, 104), rather than between the supply voltage (VDD) and the two PMOS transistors (103, 104). Instead of PMOS transistors, NMOS transistors may be used.

[0055] Figures 5A - 5E show transistor - level implementations of an embodiment of the pre - charge circuit (100) of the present disclosure. In the example of Figure 5A, the pre - charge circuit (100) includes a first PMOS transistor (102), a second PMOS transistor (103), and a third PMOS transistor (104). The connection between the source terminal of the first PMOS transistor (102) and the drain terminal of the second PMOS transistor (103) defines a first bit - line node (BLT). The connection between the drain terminal of the first PMOS transistor (102) and the drain terminal of the third PMOS transistor (104) defines a second bit - line node (BLF). The pre - charge signal (nPRE) is connected to the gate terminals of the first PMOS transistor (102), the second PMOS transistor (103), and the third PMOS transistor (104). A fourth PMOS transistor (105) is connected between the source terminal of the second PMOS transistor (103) and the supply voltage (VDD). A fifth PMOS transistor (106) is connected between the source terminal of the third PMOS transistor (104) and the supply voltage (VDD). The gate terminal of the fourth PMOS transistor (105) is connected to the first bit - line node (BLT). The gate terminal of the fifth PMOS transistor (106) is connected to the second bit - line node (BLF). The source terminal of the fourth PMOS transistor (105) is connected to the supply voltage (VDD). The drain terminal of the fourth PMOS transistor (105) is connected to the source terminal of the second PMOS transistor (103). The source terminal of the fifth PMOS transistor (106) is connected to the supply voltage (VDD). The drain terminal of the fifth PMOS transistor (106) is connected to the source terminal of the third PMOS transistor (104). In the example of Figure 5B, which is similar to Figure 5A, the pre - charge signal (NPRE) is connected to the gate terminals of the first PMOS transistor (102), the fourth PMOS transistor (105), and the fifth PMOS transistor (106), while the gate terminal of the second PMOS transistor (103) is connected to the first bit - line node (BLT), and the gate terminal of the third PMOS transistor (104) is connected to the second bit - line node (BLF).In the example of FIG. 5C, the precharge circuit (100) includes a first NMOS transistor (113), a second NMOS transistor (114), and a third NMOS transistor (115). The connection between the drain terminal of the first NMOS transistor (113) and the source terminal of the second NMOS transistor (114) defines a first bit line node (BLT). The connection between the source terminal of the first NMOS transistor (113) and the source terminal of the third NMOS transistor (115) defines a second bit line node (BLF). The precharge signal (PRE) is connected to the gate terminals of the first NMOS transistor (113), the second NMOS transistor (114), and the third NMOS transistor (115). The drain terminal of the second NMOS transistor is connected to the supply voltage (VDD). The drain terminal of the third NMOS transistor is connected to the supply voltage (VDD). In the example of FIG. 5D, the precharge circuit (100) includes a first NMOS transistor (113), a second NMOS transistor (114), a third NMOS transistor (115), a fourth NMOS transistor (116), and a fifth NMOS transistor (117). The connection between the source terminal of the first NMOS transistor (113) and the drain terminal of the second NMOS transistor (114) defines a first bit line node (BLT). The connection between the drain terminal of the first NMOS transistor (113) and the drain terminal of the third NMOS transistor (115) defines a second bit line node (BLF). The source terminal of the fourth NMOS transistor (116) is grounded (GND). The drain terminal of the fourth NMOS transistor (116) is connected to the source terminal of the second NMOS transistor (114). The source terminal of the fifth NMOS transistor (117) is grounded (GND). The drain terminal of the fifth NMOS transistor (117) is connected to the source terminal of the third NMOS transistor (115). The precharge signal (PRE) is connected to the gate terminals of the first NMOS transistor (113), the second NMOS transistor (114), and the third NMOS transistor (115).The gate terminal of the fourth NMOS transistor (116) is connected to the first bit line node (BLT). The gate terminal of the fifth NMOS transistor (117) is connected to the second bit line node (BLF). In the example of FIG. 5E, the precharge circuit (100) includes the first NMOS transistor (113), the second NMOS transistor (114), the third NMOS transistor (115), the fourth NMOS transistor (116), and the fifth NMOS transistor (117). The connection between the source terminal of the first NMOS transistor (113) and the drain terminal of the second NMOS transistor (114) defines the first bit line node (BLT). The connection between the drain terminal of the first NMOS transistor (113) and the drain terminal of the third NMOS transistor (115) defines the second bit line node (BLF). The source terminal of the fourth NMOS transistor (116) is grounded (GND). The drain terminal of the fourth NMOS transistor (116) is connected to the source terminal of the second NMOS transistor (114). The source terminal of the fifth NMOS transistor (117) is grounded (GND). The drain terminal of the fifth NMOS transistor (117) is connected to the source terminal of the third NMOS transistor (115). The precharge signal (PRE) is connected to the gate terminals of the first NMOS transistor (113), the fourth NMOS transistor (116), and the fifth NMOS transistor (117). The gate terminal of the second NMOS transistor (114) is connected to the first bit line node (BLT). The gate terminal of the third NMOS transistor (115) is connected to the second bit line node (BLF).

[0056] FIG. 6A shows an NMOS-based precharge and limit circuit including a first NMOS transistor (113), a second NMOS transistor (114), and a third NMOS transistor (115). For this embodiment, the equalization circuit (110) of FIG. 6B may be used to further improve the speed and reliability of the limited precharge circuit as an alternative to 113 of FIG. 6A or as an additional parallel circuit. When EQ is low and nEQ is high, BLT and BLF are effectively shorted. In one embodiment, the precharge and limit unit is configured to set EQ low and nEQ high when a memory access is initiated, i.e., at least shortly before precharge occurs, and to keep EQ low and nEQ high for at least some time after the memory access is completed. For the remaining time, EQ is high and nEQ is kept low.

[0057] FIGS. 7A-7C show embodiments of an equalization circuit for the precharge circuit of the present disclosure. Preferably, the equalization circuit (110) is an integral part of the precharge circuit and is disposed, for example, between a first bit line and a second bit line as shown in FIGS. 3 and 4. FIG. 7A shows an example where the equalization circuit (110) is implemented as a PMOS transistor (111) for equalizing. FIG. 7B shows an example where the equalization circuit (110) is implemented as an NMOS transistor (112) for equalizing. FIG. 7C shows an example where the equalization circuit (110) is implemented as an NMOS transistor (112) for equalizing and a PMOS transistor (111) for equalizing connected in parallel.

[0058] FIG. 8 shows a further embodiment of the precharge circuit (100) of the present disclosure using a mixed PMOS / NMOS implementation. In this embodiment, the precharge and limit unit (101) is divided into a first NMOS precharge and limit unit disposed and connected between VDD and the first bit line node (BLT), and a second NMOS precharge and limit unit disposed and connected between VDD and the second bit line node (BLF). The precharge and limit unit (101) further includes a first PMOS precharge and limit unit disposed and connected between VDD and the first bit line node (BLT), and a second PMOS precharge and limit unit disposed and connected between VDD and the second bit line node (BLF).

[0059] FIG. 9 shows an example of an implementation that mixes PMOS / NMOS. In this embodiment, the precharge circuit (100) includes a first PMOS transistor (102), a second PMOS transistor (103), and a third PMOS transistor (104). The connection between the first PMOS transistor (102) and the second PMOS transistor (103) defines a first bit line node (BLT). The connection between the first PMOS transistor (102) and the third PMOS transistor (104) defines a second bit line node (BLF). The precharge signal (PRE) is connected to the gate terminals of the first PMOS transistor (102), the second PMOS transistor (103), and the third PMOS transistor (104). A fourth PMOS transistor (105) is connected between the second PMOS transistor (103) and the supply voltage (VDD). A fifth PMOS transistor (106) is connected between the third PMOS transistor (104) and the supply voltage (VDD). The gate terminal of the fourth PMOS transistor (105) is connected to the first bit line node (BLT). The gate terminal of the fifth PMOS transistor (106) is connected to the second bit line node (BLF). The precharge circuit (100) further includes a sixth (NMOS) transistor (107) and a seventh (NMOS) transistor (108) connected between the bit lines (BLT, BLF) and the supply voltage (VDD). The inverted precharge signal (nPRE) is connected to the gate terminals of the sixth transistor (107) and the seventh transistor (108).

[0060] FIG. 10 shows an embodiment of a memory (200) of the present disclosure that includes a plurality of memory cells (203) and includes a local precharge circuit (201) and a global precharge circuit (202). The switch element (204) is used to control the connection between the local bit lines (lbl_l, lbl_r) and the global bit lines (gbl_l, gbl_r). In FIG. 11, the switch element (204) is implemented as an NMOS transistor (204).

[0061] FIG. 12 shows an example of a standard 6T memory cell (300). The memory (200) of the present disclosure includes a plurality of memory cells arranged in columns and rows. The memory cells may be, for example, 6T memory cells, but may also be other types of memory cells. In the example of FIG. 12, the memory cell includes a first memory cell transistor (301), a second memory cell transistor (302), a third memory cell transistor (303), and a fourth memory cell transistor (304) that form a first cross-coupled inverter and a second cross-coupled inverter that define a first storage node and a first inverted storage node. The memory cell further includes a fifth memory cell transistor (305) connected between the first storage node and the first bit line, and a sixth memory cell transistor (306) connected between the first inverted storage node and the second bit line.

[0062] Further details of the present invention 1. A precharge circuit for bit lines of a memory cell array, a precharge and limiting unit configured to precharge a first bit line and a second bit line, and further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cell, the precharge circuit comprising the precharge and limiting unit, the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay, the precharge circuit.

[0063] 2. The precharge circuit according to item 1, wherein the precharge and limiting unit operates at a voltage level equal to the voltage level of the memory cell.

[0064] 3. The precharge circuit is configured to set the first bit line precharge level from the first floating level and the second bit line precharge level from the second floating level immediately after the start of the precharge cycle, according to any one of the preceding items.

[0065] 4. The precharge part includes a first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; a third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, the connection between the first PMOS transistor and the second PMOS transistor defines a first bit line node connected to the first bit line, the connection between the first PMOS transistor and the third PMOS transistor defines a second bit line node connected to the second bit line, The precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal, according to any one of the preceding items.

[0066] 5. The limiting part includes a fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth PMOS is connected between the second PMOS transistor and the supply voltage (VDD), a fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth PMOS is connected between the third PMOS transistor and the supply voltage (VDD), The fourth gate terminal is connected to the first bit line node, and the fifth gate terminal is connected to the second bit line node. The precharge circuit according to item 4.

[0067] 6. The second PMOS transistor and the third PMOS transistor are connected to a ground reference point (GND). The precharge circuit according to item 4.

[0068] 7. The precharge circuit is A first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; A second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; A third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; A fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth PMOS is connected between the second PMOS transistor and a supply voltage (VDD); the fourth PMOS transistor; A fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth PMOS is connected between the third PMOS transistor and the supply voltage (VDD); the fifth PMOS transistor, and is provided with The connection between the first PMOS transistor and the second PMOS transistor defines a first bit line node connected to the first bit line; The connection between the first PMOS transistor and the third PMOS transistor defines a second bit line node connected to the second bit line; The precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal. The precharge circuit according to any one of items 1 to 3.

[0069] 8. The second gate terminal is connected to the first bit line node, and the third gate terminal is connected to the second bit line node. The precharge circuit according to item 7.

[0070] 9. The fourth PMOS transistor and the fifth PMOS transistor are sized such that the first bit line precharge level and the second bit line precharge level are limited when compared with the supply voltage (VDD), and / or the transistor types of the fourth PMOS transistor and the fifth PMOS transistor are selected such that the first bit line precharge level and the second bit line precharge level are limited when compared with the supply voltage (VDD). The precharge circuit according to any one of items 5 to 8.

[0071] 10. The precharge portion a first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; a second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; a third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal, and the connection between the first NMOS transistor and the second NMOS transistor defines a first bit line node connected to the first bit line; the connection between the first NMOS transistor and the third NMOS transistor defines a second bit line node connected to the second bit line; The precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal. The precharge circuit according to any one of items 1 to 3.

[0072] 11. The limiting portion A fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth NMOS is connected between the second NMOS transistor and a ground reference point (GND), the fourth NMOS transistor, A fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth NMOS is connected between the third NMOS transistor and the ground reference point (GND), the fifth NMOS transistor, and The precharge circuit according to item 10, wherein the fourth gate terminal is connected to the first bit line node and the fifth gate terminal is connected to the second bit line node.

[0073] 12. The precharge circuit is A first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; A second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; A third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; A fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth NMOS is connected between the second NMOS transistor and a ground reference point (GND), the fourth NMOS transistor; A fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth NMOS is connected between the third NMOS transistor and the ground reference point (GND), the fifth NMOS transistor, and The connection between the first NMOS transistor and the second NMOS transistor defines a first bit line node connected to the first bit line; The connection between the first NMOS transistor and the third NMOS transistor defines a second bit line node connected to the second bit line. The precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal, and is the precharge circuit according to any one of Items 1 to 3.

[0074] 13. The precharge circuit according to Item 12, wherein the second gate terminal is connected to the first bit line node, and the third gate terminal is connected to the second bit line node.

[0075] 14. The precharge circuit according to any one of Items 11 to 13, wherein the fourth NMOS transistor and the fifth NMOS transistor are sized such that the first bit line precharge level and the second bit line precharge level are higher than the ground reference point (GND).

[0076] 15. The precharge circuit according to any one of the preceding items, wherein the first bit line precharge level and the second bit line precharge level are 10% to 50% lower than the supply voltage (VDD), and preferably, the first bit line precharge level and the second bit line precharge level are 20% to 40% lower than the supply voltage (VDD).

[0077] 16. The precharge circuit according to any one of the preceding items, further comprising an equalization circuit connected between the first bit line and the second bit line.

[0078] 17. The precharge circuit according to Item 16, wherein the equalization circuit includes an NMOS transistor for equalization or a PMOS transistor for equalization connected between the first bit line and the second bit line, and the precharge signal is connected to the gate terminal of the NMOS transistor for equalization or the PMOS transistor for equalization.

[0079] 18. The equalization circuit includes an NMOS transistor for equalization and a PMOS transistor for equalization connected in parallel, and the NMOS transistor for equalization and the PMOS transistor for equalization are connected between the first bit line and the second bit line. The precharge circuit according to item 16.

[0080] 19. The precharge circuit according to any one of the preceding items, wherein the first bit line is a "true" bit line and the second bit line is a "false" bit line of a column of the memory cell array.

[0081] 20. A memory such as a static random access memory, A plurality of memory cells arranged in columns and rows, each memory cell including an arrangement of memory cell transistors that define a first storage node and a first inverted storage node accessed from a first bit line and a second bit line. The plurality of memory cells, At least one precharge circuit, the precharge circuit being connected to the first bit line and the second bit line within a column, and each precharge circuit being configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle. The at least one precharge circuit, the memory comprising.

[0082] 21. The arrangement of the memory cell transistors is A first memory cell transistor, a second memory cell transistor, a third memory cell transistor, and a fourth memory cell transistor that form a first cross-coupled inverter and a second cross-coupled inverter that define the first storage node and the first inverted storage node. A fifth memory cell transistor connected between the first memory node and the first bit line, and / or a sixth memory cell transistor connected between the first inverted memory node and the second bit line, the memory according to item 20, comprising:

[0083] 22. The precharge circuit is A precharge and limit unit configured to precharge the first bit line and the second bit line, and further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cell, the memory comprising the precharge and limit unit, The memory according to any one of items 20 to 21, wherein the precharge and limit unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay.

[0084] 23. The memory according to any one of items 20 to 22, wherein the precharge circuit is the precharge circuit according to any one of items 1 to 19.

[0085] 24. A row decoder, A column decoder, A sense amplifier, the memory according to any one of items 20 to 23, further comprising:

[0086] 25. The memory according to any one of items 20 to 24, wherein the memory is a static random access memory or an associative memory or a ternary associative memory.

[0087] 26. The memory cells arranged in each column are connected to a first local bit line and a second local bit line, at least one local precharge circuit is connected to each local bit line, a first global bit line can be configured to be connected to any first local bit line, a second global bit line can be configured to be connected to any second local bit line, and a global precharge circuit is connected to the first global bit line and the second global bit line, the memory according to any one of items 20 to 25.

[0088] 27. The memory according to item 26, wherein the local bit line and the global bit line are separated by a switching element such as an NMOS transistor.

[0089] 28. The memory according to any one of items 26 to 27, wherein the global precharge circuit is configured to precharge the bit line to a precharge level that is 10 to 50% lower than the supply voltage level (VDD), and the local precharge circuit is configured to precharge the bit line to the supply voltage level.

[0090] 29. A precharge circuit for a match line of a memory cell array, a precharge and restriction unit configured to precharge the match line, and further configured to restrict the match line precharge level of the match line during a precharge cycle of any read and / or write operation of the memory cell, the precharge and restriction unit is provided, the precharge and restriction unit is configured to restrict the match line precharge level in a single precharge cycle, preferably without substantial delay, the precharge circuit for a match line of the memory cell array.

[0091] 30. A precharge circuit for a bit line of a memory cell array, A precharge and limit unit configured to precharge a first bit line, further configured to limit a first bit line precharge level of the first bit line during a precharge cycle of a read and / or write operation of any of the memory cells, comprising the precharge and limit unit, The precharge and limit unit is a precharge circuit for a bit line of the memory cell array, configured to limit the first bit line precharge level in a single precharge cycle, preferably without substantial delay.

Claims

1. A global precharge circuit for global bit lines of an array of memory cells, the global precharge circuit comprising: - A precharge and limit unit configured to precharge a first bit line and a second bit line, the precharge and limit unit being further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cells, the precharge and limit unit comprising: The precharge and limit unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay. The precharge part comprises: - A first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; - A second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; - A third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; comprising: A connection between the first source terminal of the first PMOS transistor and the second drain terminal of the second PMOS transistor defines a first bit line node connected to the first bit line. A connection between the first drain terminal of the first PMOS transistor and the third drain terminal of the third PMOS transistor defines a second bit line node connected to the second bit line. A precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal. The limit part comprises: - A fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal connected to the second source terminal, and a fourth source terminal connected to a supply voltage (VDD); - A fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal connected to the third source terminal, and a fifth source terminal connected to the supply voltage (VDD); comprising: The fourth gate terminal is connected to the first bit line node, and the fifth gate terminal is connected to the second bit line node. The first bit line and the second bit line are global bit lines of the array of memory cells, and further include a local precharge circuit configured to precharge local bit lines of the array of memory cells, each global bit line can be connected to a plurality of local bit lines, the local bit lines and the global bit lines are separated by switch elements, the global precharge circuit is configured to precharge and limit the global bit lines to a limited voltage, and the local precharge circuit is configured to precharge the local bit lines to the supply voltage, a global precharge circuit. **Claim 2** A global precharge circuit for global bit lines of an array of memory cells, the global precharge circuit comprising: - A precharge and limit unit configured to precharge a first bit line and a second bit line, the precharge and limit unit being further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cells, a precharge and limit unit comprising the precharge and limit unit is preferably configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle without substantial delay, the global precharge circuit comprising: - A first PMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; - A second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; - A third PMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; - A fourth PMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the fourth PMOS transistor being connected between the second PMOS transistor and the supply voltage (VDD), a fourth PMOS transistor A fifth PMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth PMOS is connected between the third PMOS transistor and the supply voltage (VDD), the fifth PMOS transistor; Comprising; The connection between the first source terminal and the second drain terminal defines a first bit line node connected to the first bit line; The connection between the first drain terminal and the third drain terminal defines a second bit line node connected to the second bit line; The precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal; The second gate terminal is connected to the first bit line node, and the third gate terminal is connected to the second bit line node; The first bit line and the second bit line are global bit lines of the array of memory cells; Further comprising a local precharge circuit configured to precharge the local bit lines of the array of memory cells; Each global bit line can be connected to a plurality of local bit lines; The local bit line and the global bit line are separated by a switch element; The global precharge circuit is configured to precharge and limit the global bit line to a limited voltage, and the local precharge circuit precharges the local bit line to the supply voltage, the global precharge circuit.

3. A global precharge circuit for global bit lines of an array of memory cells, the global precharge circuit comprising: - A precharge and limit unit configured to precharge the first bit line and the second bit line, the precharge and limit unit being configured to limit the first bit line precharge level of the first bit line and the second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cell, the precharge and limit unit Comprising; The precharge and limit unit is preferably configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle without substantial delay. The precharge portion includes - a first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; - a second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; - a third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; and the connection between the first source terminal and the second drain terminal defines a first bit line node connected to the first bit line; the connection between the first drain terminal and the third drain terminal defines a second bit line node connected to the second bit line; the precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal; The limit portion includes - a fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal connected to the second source terminal, and a fourth source terminal connected to a ground reference point (GND); - a fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal connected to the third source terminal, and a fifth source terminal connected to the ground reference point (GND); and the fourth gate terminal is connected to the first bit line node, and the fifth gate terminal is connected to the second bit line node; the first bit line and the second bit line are global bit lines of the memory cell array; further comprising a local precharge circuit configured to precharge the local bit lines of the memory cell array; each global bit line can be connected to a plurality of local bit lines; the local bit lines and the global bit lines are separated by switch elements; the global precharge circuit is configured to precharge and limit the global bit lines to a limited voltage, and the local precharge circuit precharges the local bit lines to the supply voltage. Global precharge circuit.

4. A global precharge circuit for global bit lines of an array of memory cells, the global precharge circuit comprising: - A precharge and limit unit configured to precharge a first bit line and a second bit line, the precharge and limit unit being further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cell; comprising The precharge and limit unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay; The global precharge circuit further comprises: - A first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; - A second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; - A third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; - A fourth NMOS transistor having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the fourth NMOS transistor being connected between the second NMOS transistor and a ground reference point (GND); - A fifth NMOS transistor having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, the fifth NMOS transistor being connected between the third NMOS transistor and the ground reference point (GND); comprising A connection between the first source terminal and the second drain terminal defines a first bit line node connected to the first bit line; A connection between the first drain terminal and the third drain terminal defines a second bit line node connected to the second bit line; A precharge signal is connected to the first gate terminal, the fourth gate terminal, and the fifth gate terminal; The second gate terminal is connected to the first bit line node, and the third gate terminal is connected to the second bit line node; The first bit line and the second bit line are global bit lines of the array of memory cells, and further include a local precharge circuit configured to precharge local bit lines of the array of memory cells, each global bit line can be connected to a plurality of local bit lines, the local bit lines and the global bit lines are separated by switch elements, the global precharge circuit is configured to precharge and limit the global bit lines to a limited voltage, and the local precharge circuit precharges the local bit lines to the supply voltage, a global precharge circuit. **Claim 5** A global precharge circuit for global bit lines of an array of memory cells operating at a supply voltage (VDD), the global precharge circuit comprising: - A precharge and limit unit configured to precharge a first bit line and a second bit line, the precharge and limit unit being further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of any read and / or write operation of the memory cells, a precharge and limit unit comprising, the precharge and limit unit is preferably configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle without substantial delay, the global precharge circuit comprising: - A first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal; - A second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal; - A third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal; comprising, a connection between the drain terminal of the first NMOS transistor and the source terminal of the second NMOS transistor defines a first bit line node connected to the first bit line, The connection between the source terminal of the first NMOS transistor and the source terminal of the third NMOS transistor defines a second bit line node connected to the second bit line. The drain terminal of the second NMOS transistor is connected to the supply voltage (VDD), and the drain terminal of the third NMOS transistor is connected to the supply voltage (VDD). The precharge signal is connected to the first gate terminal, the second gate terminal, and the third gate terminal. The first bit line and the second bit line are global bit lines of the array of memory cells. It further includes a local precharge circuit configured to precharge the local bit lines of the array of memory cells. Each global bit line can be connected to a plurality of local bit lines. The local bit lines and the global bit lines are separated by switch elements. The global precharge circuit is configured to precharge and limit the global bit lines to a limited voltage, and the local precharge circuit precharges the local bit lines to the supply voltage, global precharge circuit. **Claim 6** The global precharge circuit according to any one of claims 1 to 5, wherein the global precharge circuit is configured to set the first bit line precharge level from a first floating level and the second bit line precharge level from a second floating level immediately after the start of the precharge cycle. **Claim 7** A PMOS transistor-based or NMOS transistor-based precharge portion configured to precharge the first bit line and the second bit line, and a PMOS transistor-based or NMOS transistor-based limiting portion, wherein the first bit line precharge level and the second bit line precharge level are set with respect to a supply voltage (VDD) or a ground reference level (GND). The first bit line is short-circuited to a first limited precharge level node of the PMOS transistor-based or NMOS transistor-based limiting portion, and the second bit line is short-circuited to a second limited precharge level node of the PMOS transistor-based or NMOS transistor-based limiting portion, so as to be limited substantially without delay. The global precharge circuit according to any one of claims 1 to 6, comprising the PMOS transistor-based or NMOS transistor-based limiting portion.

8. The fourth PMOS transistor and the fifth PMOS transistor are sized such that the first bit line precharge level and the second bit line precharge level are limited as compared with the supply voltage (VDD), and / or the transistor types of the fourth PMOS transistor and the fifth PMOS transistor are selected such that the first bit line precharge level and the second bit line precharge level are limited as compared with the supply voltage (VDD). The global precharge circuit according to any one of claims 1 to 2.

9. The fourth NMOS transistor and the fifth NMOS transistor are sized such that the first bit line precharge level and the second bit line precharge level are higher than the ground reference point (GND). The global precharge circuit according to any one of claims 3 to 4.

10. The first bit line precharge level and the second bit line precharge level are 10 to 80% lower than the supply voltage (VDD), preferably, the first bit line precharge level and the second bit line precharge level are 20 to 80% lower than the supply voltage (VDD), more preferably, the first bit line precharge level and the second bit line precharge level are 20 to 70% lower than the supply voltage (VDD), the global precharge circuit according to any one of claims 1 to 9.

11. A memory comprising at least one global precharge circuit according to any one of claims 1 to 10.

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