Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes: a first transistor including a channel formation region provided for a substrate including a semiconductor material, impurity regions provided to have the channel formation region therebetween, a first gate insulating layer on the channel formation region, a first gate electrode on the first gate insulating layer, and a first source electrode and a first drain electrode electrically connected to the impurity regions; and a second transistor including a second gate electrode on the substrate including the semiconductor material, a second gate insulating layer on the second gate electrode, an oxide semiconductor layer on the second gate insulating layer, and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field of the invention relates to a semiconductor device and a method for manufacturing the same. Here, the semiconductor device refers to elements and devices in general that function by utilizing semiconductor characteristics.

Background Art

[0002] Metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as a material for transparent electrodes required for liquid crystal display devices and the like.

[0003] Among metal oxides, some exhibit semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using such metal oxides in the channel formation region are already known (see, for example, Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] By the way, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO 3 (ZnO) m (m: natural number) is known as a multi-component oxide semiconductor having In, Ga, and Zn (see, for example, Non-Patent Documents 2 to 4, etc.).

[0005] And it has been confirmed that an oxide semiconductor composed of an In-Ga-Zn-based oxide as described above is also applicable to the channel formation region of a thin film transistor (see, for example, Patent Document 5, Non-Patent Documents 5 and 6, etc.).

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 60-198861 [Patent Document 2] Japanese Patent Application Laid-Open No. 8-264794 [Patent Document 3] Japanese Patent Application Laid-Open No. Hei 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Non-Patent Document]

[0007] [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m = 3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m = 7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Shinsuke Nakamura, Noboru Kimizuka, Hisahiko Mouri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phases, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] By the way, a field-effect transistor, which is a representative example of a semiconductor device, uses materials such as silicon is generally configured. However, in a semiconductor device using silicon or the like as a material the switching characteristics are not sufficiently high. For example, in the case of configuring a CMOS inverter circuit there has been a problem that the semiconductor device is destroyed by a very large through-current In addition, there has also been a problem that the power consumption increases due to the through-current .

[0009] Also, in a semiconductor device using silicon or the like as a material, the off-current (also called leakage current or the like is not small enough to be substantially zero. For this reason, a slight current flows regardless of the operation of the semiconductor device and when configuring a charge-holding type semiconductor device such as a memory device or a liquid crystal display device it has been difficult to ensure a sufficient charge-holding period. In addition there has also been a problem that the power consumption of the semiconductor device increases due to the off-current

[0010] Therefore, one aspect of the disclosed invention aims to provide a semiconductor device having a new structure that solves the above problems .

Means for Solving the Problem

[0011] One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials . For example, the following configuration can be adopted .

[0012] One aspect of the present invention is a channel formation region provided on a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region , and a first gate insulating layer on the channel formation region and a first gate electrode on the first gate insulating layer, and a first source electrode and a first drain electrode that are electrically connected to the impurity region, a first transistor having the same, and a semiconductor material a second gate electrode on a substrate containing the same, a second gate insulating layer on the second gate electrode, and a second oxide semiconductor layer on the second gate insulating layer, and a second source electrode and a second drain electrode that are electrically connected to the oxide semiconductor layer, a second transistor having the same, and a semiconductor device having the same. are provided. There is.

[0013] In the above, the first gate electrode and the second gate electrode are electrically connected, and the first source electrode or the first drain electrode and the second source electrode or the second drain electrode are preferably electrically connected. Further, the first transistor is a p-type transistor (p-channel type transistor), and the second transistor is preferably an n-type transistor (n-channel type transistor).

[0014] Also, in the above, the first gate electrode and the second source electrode or the second drain electrode are preferably electrically connected.

[0015] Also, in the above, as the substrate containing the semiconductor material, it is preferable to employ a single crystal semiconductor substrate or an SOI substrate . In particular, the semiconductor material is preferably silicon.

[0016] Also, in the above, the oxide semiconductor layer preferably contains an In-Ga-Zn-O-based oxide semiconductor material . In particular, the oxide semiconductor layer is In 2 Ga 2 ZnO 7 crystal It is preferably contained. Further, the hydrogen concentration in the oxide semiconductor layer is 5×10 19 ato ms / cm 3 or less. Also, the off-current of the second transistor is preferably 1× 10 -13 A or less.

[0017] In the above, the second transistor can be configured to be provided in a region overlapping with the first transistor. It can be configured.

[0018] Note that the first source electrode or the first drain electrode and the second source electrode or the second drain electrode may be integrally formed. That is, a part of the second source electrode or the second drain electrode may function as the first source electrode or the first drain electrode, or a part of the first source electrode or the first drain electrode may function as the second source electrode or the second drain electrode.

[0019] In this specification and the like, terms such as "above" and "below" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "the first gate electrode above the gate insulating layer", those including other components between the gate insulating layer and the first gate electrode are not excluded. Also, the terms "above" and "below" are merely expressions used for the convenience of explanation, and unless otherwise specified, those with the above and below swapped are also included.

[0020] In this specification and the like, terms such as "electrode" and "wiring" do not limit these components functionally. For example, an "electrode" may be used as a part of a "wiring". Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes". This also includes cases where "a substrate" or "wiring" are formed integrally.

[0021] In general, an "SOI substrate" is a substrate that has a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is The layer is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is a silicon Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, metal substrates In other words, it includes a conductive substrate having an insulating surface and a semiconductor substrate on an insulating substrate. The term "SOI substrate" broadly includes those having a layer made of a silicon material. In this document, the term "semiconductor substrate" does not only refer to a substrate made of semiconductor material, but also to any semiconductor material. In other words, in this specification, the term "SOI substrate" is also used broadly. "Semiconductor substrate" refers to a semiconductor device that is made of a material other than silicon. Effect of the Invention

[0022] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor is provided in a lower portion, A semiconductor device including a transistor including an oxide semiconductor is provided.

[0023] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor with an oxide semiconductor, Semiconductors that require different electrical properties (e.g., different carriers involved in the operation of the element) The device can be realized.

[0024] In addition, since transistors using oxide semiconductors have good switching characteristics, excellent semiconductor devices utilizing such characteristics can be fabricated. For example, in a CMOS inverter circuit, the through-current can be sufficiently suppressed, thereby reducing the power consumption of the semiconductor device and preventing destruction of the semiconductor device due to a large current. Also, since transistors using oxide semiconductors have an extremely small off-current, using them can reduce the power consumption of the semiconductor device.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

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Figure 5

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Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0026] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0027] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for ease of understanding. Therefore, it is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0028] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0029] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 6.

[0030] <Configuration of Semiconductor Device> FIG. 1(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and FIG. 1(B) shows a plan view of the semiconductor device according to this embodiment. Here, FIG. 1(A) corresponds to the cross-section along lines A1 - A2 and D1 - D2 in FIG. 1(B). The semiconductor device shown in FIGS. 1(A) and 1(B) has a p-type transistor 160 at the lower part and an n-type transistor 162 using an oxide semiconductor at the upper part. The p-type transistor 160 has a channel formation region provided on a substrate 100 containing a semiconductor material

[0031] ​​​​​​​​​ 116, an impurity region 114 and a high-concentration impurity region 120 (collectively also simply referred to as the impurity region) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, a source electrode or drain electrode 130a electrically connected to the impurity region 114 provided on one side of the channel formation region 116, and a source electrode or drain electrode 130b electrically connected to the impurity region 114 provided on the other side of the channel formation region 116. Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Further, the substrate 100 has a high-concentration impurity region 120 provided so as to sandwich the sidewall insulating layer 118 when viewed in plan, and a metal compound region 124 exists on the high-concentration impurity region 120. Also, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the p-type transistor 160, and an interlayer insulating layer 126 and

[0032] an interlayer insulating layer 128 are provided so as to cover the p-type transistor 160. Through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128, the source electrode or drain electrode 130a is electrically connected to the metal compound region 124 provided on one side of the channel formation region 116, and the source electrode or drain electrode 130b is electrically connected to the metal compound region 124 provided on the other side of the channel formation region 116. That is, the source electrode or drain electrode 130a is connected to the channel formation region 116 through the metal compound region 124 provided on one side of the channel formation region 116. 116, and the source electrode or drain electrode 130b is connected to the metal compound region 124 provided on the other side of the channel formation region 116. 116. 116, and the source electrode or drain electrode 130a is electrically connected to the metal compound region 124 provided on one side of the channel formation region 116, and the source electrode or drain electrode 130b is electrically connected to the metal compound region 124 provided on the other side of the channel formation region 116. That is, the source electrode or drain electrode 130a is connected to the metal compound region 124 provided on one side of the channel formation region 116 through the metal compound region 124 provided on one side of the channel formation region 116. The high-concentration impurity region 120 provided on one side of the channel formation region 116 and the channel formation The impurity region 114 provided on one side of the region 116 is electrically connected, and the source electrode Or the drain electrode 130b is provided on the other side of the channel formation region 116 through the metal compound Region 124 and is electrically connected to the high-concentration impurity region 120 provided on the other side of the channel formation region 116 and the impurity region 114 provided on the other side of the channel formation region 116. 120 and the impurity region 114 provided on the other side of the channel formation region 116 are electrically Connected.

[0033] The n-type transistor 162 includes a gate electrode 136c provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136c, an oxide semiconductor layer 140 provided on the gate insulating layer 138, and a source electrode or drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or drain electrode 142b. And a gate insulating layer 138 provided thereon, and an oxide semiconductor layer 140 provided on the gate insulating layer 138. Are provided, and a source electrode or drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or drain electrode 142b. 0 and having a source electrode or drain electrode 142a, a source electrode or Drain electrode 142b.

[0034] Here, the gate electrode 136c of the n-type transistor 162 is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Also, similarly to the gate electrode 136c, electrodes 136a and 136b are formed in contact with the source electrode or drain electrodes 130a and 130b of the p-type transistor 160. And is provided so as to be embedded. Also, similarly to the gate electrode 136c, electrodes 136a and 136b are formed in contact with the source electrode or drain electrodes 130a and 130b of the p-type transistor 160. On the source electrode or drain electrodes 130a and 130b of the p-type transistor 160. Are formed.

[0035] Also, on the n-type transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, in the protective insulating layer 144 and the interlayer insulating layer 146, a source electrode or a drain Insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, in the protective insulating layer 144 and the interlayer insulating layer 146, a source electrode or a drain Electrode, or the drain An opening reaching the drain electrode 142a and the source electrode or drain electrode 142b is provided. Through the opening, the electrodes 150c and 150d are formed in contact with the drain electrode 142a and the source electrode or drain electrode 142b. Also, similar to the electrodes 150c and 150d, the electrodes 150a and 150b in contact with the electrodes 136a and 136b are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Here, it is desirable that the oxide semiconductor layer 140 is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 atoms / cm or less, desirably 5×10

[0036] atoms / cm or less, more desirably 5×10 19 atoms / cm 3 or less. Also, by using the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified, the n-type transistor 162 can obtain extremely excellent off-current characteristics. For example, when the drain voltage Vd is +1V or 18 +10V, and the gate voltage Vg is in the range of -5V to -20V, the off-current is 3 1×10 A or less. In this way, by applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off-current of the n-type transistor 162, a semiconductor device with excellent characteristics can be obtained. Note that the hydrogen concentration in the above-described oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS:Secondary Ion Mass S 17 atoms / cm 3 or less. Furthermore, by using the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified, the n-type transistor 162 can obtain extremely excellent off-current characteristics. For example, when the drain voltage Vd is +1V or +10V, and the gate voltage Vg is in the range of -5V to -20V, the off-current is 1×10 A or less. In this way, by applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off-current of the n-type transistor 162, a semiconductor device with excellent characteristics can be obtained. Note that the hydrogen concentration in the above-described oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS:Secondary Ion Mass S -13 A or less. In this way, by applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off-current of the n-type transistor 162, a semiconductor device with excellent characteristics can be obtained. Note that the hydrogen concentration in the above-described oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS:Secondary Ion Mass S By applying the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified and reducing the off-current of the n-type transistor 162, a semiconductor device with excellent characteristics can be obtained. Note that the hydrogen concentration in the above-described oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS:Secondary Ion Mass S pectrometry). It is measured by [[spectroscopy]].

[0037] An insulating layer 152 is provided on the interlayer insulating layer 146, and electrodes 154a, 154b, and 154c are provided so as to be embedded in the insulating layer 152. Here, electrode 154a is in contact with electrode 150a, electrode 154b is in contact with electrode 150b and electrode 150 c, and electrode 154c is in contact with electrode 150d. That is, in the semiconductor device shown in FIG. 1, the source electrode or drain

[0038] electrode 130b of the p-type transistor 160 and the source electrode or drain electrode 142 a of the n-type transistor 162 are electrically connected via electrodes 136b, 150b, 154b, and 150c. That is, in the semiconductor device shown in FIG. 1, the source electrode or drain electrode 130b of the p-type transistor 160 and the source electrode or drain electrode 142 a of the n-type transistor 162 are electrically connected via electrodes 136b, 150b, 154b, and 150c.

[0039] Also, the gate electrode 110a of the p-type transistor 160 and the gate electrode 136c of the n-type transistor 162 are also electrically connected via electrodes formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. electrically connected.

[0040] Note that the source electrode or drain electrode 130a of the p-type transistor 160 is electrically connected to a power supply line that supplies a first potential via electrodes 154 a, 150a, and 136a. Also, the source electrode or drain electrode 142b of the n-type transistor 162 is electrically connected to a power supply line that supplies a second potential via electrodes 154 c and 150d. connected. .

[0041] An equivalent circuit of a CMOS inverter circuit in which the p-type transistor 160 and the n-type transistor 162 are complementarily connected is shown in FIG. 2. FIG. 2 shows the semiconductor device shown in FIGS. 1(A) and 1(B). An equivalent circuit of a CMOS inverter circuit in which the p-type transistor 160 and the n-type transistor 162 are complementarily connected is shown in FIG. 2. FIG. 2 shows the semiconductor device shown in FIGS. 1(A) and 1(B). In the case where the electrode 154a is set to a positive potential VDD and the electrode 154c is set to a ground potential GND, In addition, instead of the ground potential, a negative potential VDL may be used.

[0042] Next, an n-type transistor or a p-type transistor is formed on the same substrate as the above-mentioned semiconductor device. The configuration when the capacitor is used alone will be described with reference to FIG. 3. FIG. 3(A) shows the lower Cross-sections of a p-type transistor 164 and an n-type transistor 166 using an oxide semiconductor thereon FIG. 3(A) is a plan view of the line B1 in FIG. 3(B). 3 corresponds to a cross-sectional view taken along line C1-C2 in FIG. The configurations of the above will be described using the same reference numerals.

[0043] First, the configuration and electrical connection relationship of p-type transistor 164 will be described. The source or drain electrode 130c of the transistor 164 The electrode 130d includes an electrode 136d formed to be embedded in the insulating layer 132, an electrode 1 Electrodes 136d and 136e are electrically connected to each other. The gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146 are embedded in the insulating layer 138. The electrodes 150e and 150f are electrically connected to each other. 50e, and the electrode 150f includes an electrode 154d formed to be embedded in the insulating layer 152. , and electrodes 154e are electrically connected to each other. The source or drain electrode 130c of 64 is connected to the electrode 136d, the electrode 150e, and the electrode 1 54d, and the source electrode or drain electrode 130d is electrically connected to a predetermined wiring. is electrically connected to a predetermined wiring via the electrode 136e, the electrode 150f, and the electrode 154e Therefore, the p-type transistor 164 can be used alone.

[0044] Next, the configuration and electrical connection relationship of the n-type transistor 166 will be described. On the element isolation insulating layer 106, a gate insulating layer 108b is provided. Also, on the gate insulating layer 108b, a gate wiring 110b is provided. An electrode 130e formed so as to be embedded in the interlayer insulating layer 126 and the interlayer insulating layer 128 is electrically connected to the gate wiring 110b. An electrode 130e is electrically connected to a gate electrode 136f formed so as to be embedded in the insulating layer 132. As a result, the gate electrode 136f of the n-type transistor 166 is electrically connected to the gate wiring 110b via the electrode 130e, so that the n-type transistor 166 can be used alone.

[0045] <Method for manufacturing a semiconductor device> Next, an example of the method for manufacturing the semiconductor device will be described. Hereinafter, first, the method for manufacturing the lower p-type transistor will be described, and then the method for manufacturing the upper n-type transistor will be described.

[0046] <Method for manufacturing a p-type transistor> First, a substrate 100 including a semiconductor material is prepared (see FIG. 4(A)). As the substrate 100 including a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, when a single crystal silicon substrate is used as the substrate 100 including a semiconductor material, ​​​​​​​​In general, an "SOI substrate" is a substrate that has a silicon semiconductor on an insulating surface. A substrate having a conductor layer formed thereon is referred to as a substrate having a silicon layer formed on an insulating surface. The term "substrate" is used as a concept including a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes those that are made up of

[0047] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 is made of, for example, silicon oxide, silicon nitride, An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0048] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor device is not attached (the exposed area) is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0049] Next, an insulating layer is formed to cover the semiconductor region 104, and the insulating layer in the region superimposed on the semiconductor region 104 is selectively removed to form the element isolation insulating layer 106 (see Fig. 4(B)). ) The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As methods for removing the insulating layer, there are polishing processes such as CMP and etching processes, etc., and any method can be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0050] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer.

[0051] The insulating layer will become the subsequent gate insulating layer, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc., obtained by using the CVD method, sputtering method, etc. Alternatively, the surface of the semiconductor region 104 may be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above insulating layer. The high-density plasma treatment can be performed using, for example, a mixed gas of a rare gas such as He, Ar, Kr, Xe, etc., and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer is not particularly limited, but can be, for example, 1 nm or more and 10 0 nm or less.

[0052] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, a semiconductor material such as polycrystalline silicon containing a conductive material ​​​​Using this, a layer containing a conductive material may be formed. The forming method is not particularly limited, and various film forming methods such as vapor deposition, C VD method, sputtering method, spin coating method, etc. can be used. In addition, in this embodiment, an example of forming a layer containing a conductive material using a metal material is shown.

[0053] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a and the gate electrode 110a (see FIG. 4(C)). At this time, the gate wiring 110b shown in FIG. 3 can be formed together.

[0054] Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 4(C)). Then, Boron (B), aluminum (Al), etc. are added to the semiconductor region 104 to form an impurity region 114 with a shallow junction depth (see FIG. 4(C)). By forming the impurity region 114, the lower part of the gate insulating layer 108a of the semiconductor region 104 becomes the channel formation region 116 (see FIG. 4(C)). Here, the concentration of the impurity to be added can be set as appropriate, but it is desirable to increase the concentration in accordance with the degree of miniaturization of the semiconductor element. Also, here, a process of forming the impurity region 114 after forming the insulating layer 112 is adopted, but it may be a process of forming the insulating layer 112 after forming the impurity region 114.

[0055] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The sidewall insulating layer 118 can be formed self-alignedly by forming an insulating layer so as to cover the insulating layer 112 and then applying an anisotropic high etching process to the insulating layer. Also, at this time Partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114.

[0056] Next, form an insulating layer so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, in the region where the insulating layer contacts the impurity region 114, add boron (B), aluminum (Al), etc. to form a high-concentration impurity region 120 (see Fig. 4(E)). After that, remove the above insulating layer and form a metal layer 122 so as to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 4(E ). The metal layer 122 can be formed using various film formation methods such as vapor deposition, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metal compound . Examples of such metal materials include titanium, tantalum, tungsten, nickel , cobalt, platinum, etc.

[0057] Next, perform a heat treatment to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see Fig. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, a metal compound region is also formed at the portion where the metal layer 12 2 contacts.

[0058] As the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used . Of course, other heat treatment methods may be used, but the chemical reaction related to the formation of the metal compound In order to improve controllability, it is desirable to use a method that can achieve a very short heat treatment. Note that since the above metal compound region is formed by the reaction between the metal material and the semiconductor material, it is a region with sufficiently enhanced conductivity. By forming the metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. After forming the metallization compound region 124, the metal layer 122 is removed.

[0059] Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each component formed by the above-described process (see FIG. 4(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. Alternatively, they may be formed using an organic insulating material such as polyimide or acrylic. Here, although a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is adopted, the configuration of the interlayer insulating layer is not limited thereto. After forming the interlayer insulating layer 128, it is desirable to planarize its surface by a method such as CMP or etching.

[0060] Thereafter, an opening reaching the metal compound region 124 is formed in the above interlayer insulating layer, and a source electrode or a drain electrode 130a and a source electrode or a drain electrode 130b (both can be called a source wiring or a drain wiring) are formed in the opening (see FIG. 4(H)). The source electrode or the drain electrode 130a and the source electrode or the drain electrode 130 b are formed, for example, by forming a conductive layer in the region including the opening using a PVD method, a CVD method, or the like, and then etching. It can be formed by removing a part of the conductive layer using methods such as etching and CMP. It can be done.

[0061] When forming the source electrode or drain electrode 130a or the source electrode or drain electrode 130b by removing a part of the conductive layer, it is desirable to process it so that its surface becomes flat. For example, when a titanium film or a titanium nitride film is thinly formed in a region including an opening and then a tungsten film is formed so as to be embedded in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface of the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. It is desirable to process it so that its surface becomes flat. For example, when a titanium film or a titanium nitride film is thinly formed in a region including an opening and then a tungsten film is formed so as to be embedded in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface of the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. For example, when a titanium film or a titanium nitride film is thinly formed in a region including an opening and then a tungsten film is formed so as to be embedded in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. When forming a tungsten film so as to be embedded in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. When forming a tungsten film so as to be embedded in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface of the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. In this way, by planarizing the surface of the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. In this way, by planarizing the surface of the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0062] Here, only the source electrode or drain electrode 130a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this process, wirings in contact with the gate electrode 110a, etc. can be formed together. Also, at this time, the connection electrode 130e in contact with the gate wiring 110b shown in FIG. 3 can be formed. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Here, only the source electrode or drain electrode 130a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this process, wirings in contact with the gate electrode 110a, etc. can be formed together. Also, at this time, the connection electrode 130e in contact with the gate wiring 110b shown in FIG. 3 can be formed. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Here, only the source electrode or drain electrode 130a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this process, wirings in contact with the gate electrode 110a, etc. can be formed together. Also, at this time, the connection electrode 130e in contact with the gate wiring 110b shown in FIG. 3 can be formed. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Also, at this time, the connection electrode 130e in contact with the gate wiring 110b shown in FIG. 3 can be formed. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used.

[0063] As described above, a p-type transistor is formed using a substrate 100 containing a semiconductor material. The above After the process, wiring or the like may be further formed. By adopting a multilayer wiring structure composed of a stacked structure of an interlayer insulating layer and a conductive layer, a highly integrated semiconductor device can be provided.

[0064] <Method for manufacturing an n-type transistor> Next, the process of manufacturing an n-type transistor on the interlayer insulating layer 128 will be described with reference to FIGS. 5 and 6. Note that FIGS. 5 and 6 show the manufacturing process of the n-type transistor in the cross section of line A1 - A2 and the cross section of line D1 - D2 shown in FIG. 1. Therefore, the p-type transistor formed below the n-type transistor is omitted.

[0065] First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130b (see FIG. 5(A)). The insulating layer 132 can be formed using methods such as PVD method or CVD method. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0066] Next, openings reaching the source electrode or drain electrode 130a and openings reaching the source electrode or drain electrode 130b are formed in the insulating layer 132. At this time, openings are also formed in the region where the gate electrode 136c will be formed later. Then, a conductive layer 134 is formed so as to be embedded in the above openings (see FIG. 5(B)). The above openings can be formed by methods such as etching using a mask The mask can be a photomask. It can be formed by methods such as exposure. As for etching, either wet etching or dry etching can be used. However, from the perspective of microfabrication, it is preferable to use dry etching. The formation of the conductive layer 134 can be carried out using a film formation method such as PVD method or CVD method. As the materials that can be used for the formation of the conductive layer 134, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., and their alloys, compounds (such as nitrides), etc. can be cited. Specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD method in a region including an opening, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to be embedded in the opening. Here, the titanium film formed by PVD method has a function of reducing the oxide film at the interface with the lower electrode (here, the source electrode or drain electrode 130a, or the source electrode or drain electrode 130b) and reducing the contact resistance with the lower electrode. Also, the subsequently formed titanium nitride film has a barrier function of suppressing the diffusion of the conductive material. After forming the conductive layer 134, a part of the conductive layer 134 is removed using methods such as etching or CMP to expose the insulating layer 132, and the electrodes 136a, 136b, and gate electrode 136c are formed (see Fig. 5(C)). Note that when removing a part of the conductive layer 134 to form the electrodes 136a, 136b, and gate electrode 136c, it is desirable to process it so that the surface becomes flat. In this way, the insulating layer 132, electrodes 136a, 136b,

[0067] It can be formed by methods such as exposure. As for etching, either wet etching or dry etching can be used. However, from the perspective of microfabrication, it is preferable to use dry etching. The formation of the conductive layer 134 can be carried out using a film formation method such as PVD method or CVD method. As the materials that can be used for the formation of the conductive layer 134, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., and their alloys, compounds (such as nitrides), etc. can be cited. Specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD method in a region including an opening, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to be embedded in the opening. Here, the titanium film formed by PVD method has a function of reducing the oxide film at the interface with the lower electrode (here, the source electrode or drain electrode 130a, or the source electrode or drain electrode 130b) and reducing the contact resistance with the lower electrode. Also, the subsequently formed titanium nitride film has a barrier function of suppressing the diffusion of the conductive material. After forming the conductive layer 134, a part of the conductive layer 134 is removed using methods such as etching or CMP to expose the insulating layer 132, and the electrodes 136a, 136b, and gate electrode 136c are formed (see Fig. 5(C)). Note that when removing a part of the conductive layer 134 to form the electrodes 136a, 136b, and gate electrode 136c, it is desirable to process it so that the surface becomes flat. In this way, the insulating layer 132, electrodes 136a, 136b,

[0068] After forming the conductive layer 134, a part of the conductive layer 134 is removed using methods such as etching or CMP to expose the insulating layer 132, and the electrodes 136a, 136b, and gate electrode 136c are formed (see Fig. 5(C)). Note that when removing a part of the conductive layer 134 to form the electrodes 136a, 136b, and gate electrode 136c, it is desirable to process it so that the surface becomes flat. In this way, the insulating layer 132, electrodes 136a, 136b, and gate electrode 136c are formed. When removing a part of the conductive layer 134 to form the electrodes 136a, 136b, and gate electrode 136c, it is desirable to process it so that the surface becomes flat. In this way, the insulating layer 132, electrodes 136a, 136b, ​​By planarizing the surface of the gate electrode 136c, in subsequent processes, it becomes possible to form good electrodes, wir es, insulating layers, semiconductor layers, etc.

[0069] Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrodes 136a, 136b, and the gate electrode 136c (see Fig. 5(D)). The gate insulating layer 138 can be formed using a CVD method, a sputtering method, or the like. Further, the gate insulating layer 138 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Note that the gate insulating layer 138 may have a single-layer structure or a stacked structure. For example, using silane (SiH 4 ), oxygen, and nitrogen as source gases, a gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD method. The thickness of the gate insulating layer 138 is not particularly limited, but can be, for example, 20 nm or more and 500 nm or less. In the case of a stacked structure, for example, it is preferable to form a stacked structure of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. 4 ), oxygen, and nitrogen as source gases, a gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD method. The thickness of the gate insulating layer 138 is not particularly limited, but can be, for example, 20 nm or more and 500 nm or less. In the case of a stacked structure, for example, it is preferable to form a stacked structure of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. 1 gate insulating layer and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer.

[0070] Note that an oxide semiconductor (purified oxide semiconductor) that has been i-type or substantially i-type by removing impurities is extremely sensitive to interface states and interface charges. Therefore, when such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the purified oxide semiconductor layer is required to be of high quality.

[0071]

[0071] For example, the high-density plasma CVD method using μ waves (2.45 GHz) is suitable in that it can form a dense gate insulating layer 138 with a high breakdown voltage. Since the highly purified oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, the interface level can be reduced and the interface characteristics can be improved. Of course, as long as a high-quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering and plasma CVD can be applied even when a highly purified oxide semiconductor layer is used. Also, an insulating layer whose film quality and interface characteristics with the oxide semiconductor layer are modified by heat treatment after film formation may be formed. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. By closely contacting the highly purified oxide semiconductor layer and the high-quality gate insulating layer, the interface level can be reduced and the interface characteristics can be made favorable. This is because it is possible to reduce the interface level and improve the interface characteristics.

[0072] Of course, as long as a high-quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering and plasma CVD can be applied even when a highly purified oxide semiconductor layer is used. Also, an insulating layer whose film quality and interface characteristics with the oxide semiconductor layer are modified by heat treatment after film formation may be formed. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. When using a highly purified oxide semiconductor layer, other methods such as sputtering and plasma CVD can be applied. Also, an insulating layer whose film quality and interface characteristics with the oxide semiconductor layer are modified by heat treatment after film formation may be formed. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. After film formation, heat treatment can be used to modify the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor layer to form an insulating layer. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable. In any case, as long as the film quality as the gate insulating layer is good and the interface level density with the oxide semiconductor layer can be reduced to form a good interface, it is acceptable.

[0073] Furthermore, in a gate bias thermal stress test (BT test) at 85 °C, 2 × 10 6 V / cm for 12 hours, when impurities are added to the oxide semiconductor, the bond between the impurities and the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated unbonded hands induce a shift in the threshold voltage (Vth). When impurities are added to the oxide semiconductor, the bond between the impurities and the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated unbonded hands induce a shift in the threshold voltage (Vth). The bond between the impurities and the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated unbonded hands induce a shift in the threshold voltage (Vth). This results in a shift in the threshold voltage (Vth).

[0074] In contrast, in one aspect of the disclosed invention, impurities in the oxide semiconductor, particularly hydrogen and water, are excluded as much as possible, and by improving the interface characteristics with the gate insulating layer as described above, it is possible to obtain a stable transistor even for the BT test. By excluding impurities in the oxide semiconductor, particularly hydrogen and water, as much as possible, and improving the interface characteristics with the gate insulating layer as described above, it is possible to obtain a stable transistor even for the BT test. This makes it possible to obtain a stable transistor even for the BT test.

[0075] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching using a mask is performed. The oxide semiconductor layer is processed by a method such as this to form an island-shaped oxide semiconductor layer 140 (see Fig. 5(E)). (See Fig. 5(E)).

[0076] As the oxide semiconductor layer, an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-A l-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn -O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn- O-based, Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer, is preferably used. In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target as the oxide semiconductor layer. Note that by adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, a target containing 2 wt% or more and 10 wt% or less of SiO can be used to form the oxide semiconductor layer. Since it can be suppressed, for example, a target containing 2 wt% or more and 10 wt% or less of SiO can be used to form the oxide semiconductor layer. 2 can be used to form the oxide semiconductor layer. semiconductor layer may be formed.

[0077] As a target for producing the oxide semiconductor layer by sputtering, for example, an oxide semiconductor film-forming target mainly composed of zinc oxide can be used. Also, an oxide semiconductor film-forming target containing In, Ga, and Zn (as a composition ratio, In O 2 O 3 :G a 2 O 3 :ZnO = 1:1:1 [mole ratio]) etc. can also be used. Also, as an oxide semiconductor film-forming target containing In, Ga, and Zn, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio], or In 2 O3 :Ga 2 O 3 :ZnO = 1: A target having a composition ratio of 1:4 [mole ratio] may also be used. For forming an oxide semiconductor film The filling rate of the target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less There is. By using a target for forming an oxide semiconductor film with a high filling rate, a dense oxide semi- conductor layer is formed.

[0078] The film formation atmosphere is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas ( typically argon) and oxygen. Specifically, for example , high-purity gas in which the concentrations of impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to about several ppm (desirably about several ppb level) is preferably used.

[0079] When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the film while heating the substrate , the impurity concentration contained in the formed oxide semiconductor layer can be reduced . Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and a metal oxide is used as a tar get to form an oxide semiconductor layer. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium subliimation pump. Also, as the evacuation means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump is, for example, hydrogen atoms, water (H ). After evacuation using a cryopump, the film formation chamber is, for example, hydrogen atoms, water (H ), and water (H 2(O) and other hydrogen atom-containing compounds (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced.

[0080] As the formation conditions, for example, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC (direct current) power is 0.5 kW, the atmosphere is an oxygen (oxygen flow ratio 100%) atmosphere, and the like conditions can be applied. When using a pulsed DC (direct current) power supply, the powdery substances (also called particles, dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform which is preferable. The oxide semiconductor layer has a thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied so the thickness may be appropriately selected according to the material used.

[0081] Before forming the oxide semiconductor layer by sputtering, it is preferable to introduce argon gas and perform reverse sputtering to generate plasma to remove the dust adhering to the surface of the gate insulating layer 138 . Here, reverse sputtering means that in normal sputtering, ions collide with the sputtering target, but conversely, it refers to a method of modifying the surface by colliding ions with the processing surface . As a method of colliding ions with the processing surface , there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate . Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used .

[0082] For the etching of the above oxide semiconductor layer, either dry etching or wet etching It may also be used. Of course, both can be used in combination. To be able to etch into a desired shape, the etching conditions (etching gas, etching liquid, etching time, temperature, etc.) are appropriately set according to the material. As the etching gas used for dry etching, for example, a gas containing chlorine (chlorine-based gas, such as chlorine (Cl ), boron trichloride (BCl

[0083] ), silicon tetrachloride (SiCl ), carbon tetrachloride (CCl 2 ), etc.) can be used. Also, a gas containing fluorine (fluorine-based gas, such as carbon tetrafluoride (CF 3 ), sulfur hexafluoride (SF 4 ), nitrogen trifluoride (NF ), trifluoromethane (CHF 4 ), etc.), hydrogen bromide (HBr), oxygen (O ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. may be used. 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF ), etc.), hydrogen bromide (HBr), oxygen (O 3 ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. may be used. 2 ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. may be used. As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. To be able to etch into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set.

[0084] As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. To be able to etch into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set. ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. To be able to etch into a desired shape, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set. As the etching liquid used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) etc. may be used.

[0085] As the etching liquid used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) etc. may be used.

[0086] Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented. Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented. Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented. Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented. Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented. Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be carried out. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heater or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere, and re-mixing of water or hydrogen is prevented.

[0087] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used.

[0088] For example, as the first heat treatment, the substrate is moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is moved and placed in an inert gas heated to a high temperature. For example, as the first heat treatment, the substrate is moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is moved and placed in an inert gas heated to a high temperature. GRTA processing may be performed to emit from. When GRTA processing is used, high-temperature heat treatment in a short time becomes possible. Also, since it is a short-time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate is.

[0089] In addition, the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example it is desirable that the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0090] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, there may be a case where the crystallization rate is 90% or more, or a microcrystalline oxide semiconductor layer of 80% or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer containing no crystal components may be obtained.

[0091] In addition, there may be a case where a microcrystal (particle size 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) is mixed in an amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer) to form an oxide semiconductor layer is. For example, when an oxide semiconductor layer is formed using an In-Ga-Zn-O-based oxide semiconductor film-forming target, In having electrical anisotropy By providing a microcrystalline portion in which the crystal 2 Ga 2 ZnO 7 grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed ​ It is possible. Thus, In 2 Ga 2 ZnO 7 By forming a microcrystalline portion in which the crystal grains of are oriented on the surface of the oxide semiconductor layer, for example, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved and the insulation in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Further, such a microcrystalline portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer . Note that the above-described oxide semiconductor layer can be formed by surface heating of the oxide semiconductor layer by GRTA treatment . Also, by using a sputtering target in which the Zn content is smaller than the In or Ga content , it is possible to form more suitably

[0092] The first heat treatment for the oxide semiconductor layer 140 can also be performed on the oxide semiconductor layer before it is processed into an island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed .

[0093] Note that since the above-described first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140, it can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such a dehydration treatment , dehydrogenation treatment can be performed at timings such as after forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer, or after forming a protective insulating layer on the source electrode or the drain electrode . Also, such a dehydration treatment , dehydrogenation treatment may be performed not only once but a plurality of times .

[0094] Next, a source electrode or a drain electrode 142a is provided in contact with the oxide semiconductor layer 140 ​​​​​Form the source electrode or drain electrode 142b (see Fig. 5(F)). The source electrode or drain electrode 142a, and the source electrode or drain electrode 142b can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 1 40 and then selectively etching the conductive layer.

[0095] The conductive layer can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Also, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or alloys containing the above-described elements can be used. One or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Also, materials obtained by combining a single or a plurality of elements selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used. The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer

[0096] structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. Here, for the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. The channel length (L) of the transistor is determined by the interval between the lower end of the source electrode or drain When performing exposure with a channel length (L) of less than 25 nm, exposure for mask pattern formation is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. Exposure using extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is possible to set the channel length (L) of the transistor to be formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit. Furthermore, since the off-current value is extremely small, miniaturization does not cause an increase in power consumption. In addition, during the etching of the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 140 is not removed. Depending on the materials and etching conditions, in this process, a part of the oxide semiconductor layer 140 may be etched, resulting in an oxide semiconductor layer having a groove (recess).

[0097] Moreover, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region, thereby realizing high-speed operation of the transistor.

[0098] In addition, in order to reduce the number of masks used and the number of processes, exposure in which the transmitted light has multiple intensities is performed. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region, thereby realizing high-speed operation of the transistor. In addition, in order to reduce the number of masks used and the number of processes, exposure in which the transmitted light has multiple intensities

[0099] is performed. An etching process may be performed using a resist mask formed by a multi-tone mask which is a mask. The resist mask formed using the multi-tone mask has a shape with a plurality of film thicknesses and can be further deformed in shape by ashing, so it can be used in a plurality of etching processes for processing different patterns. That is, with a single multi-tone mask it is possible to form a resist mask corresponding to at least two or more different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0100] Note that after the above process, plasma treatment 2 using a gas such as NO, N 2 , or Ar is preferably performed. By this plasma treatment, water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0101] Next, without exposing to the atmosphere, a protective insulating layer 14 4 in contact with a part of the oxide semiconductor layer 140 is formed (see FIG. 5(G)).

[0102] The protective insulating layer 144 has a film thickness of 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Materials that can be used for the protective insulating layer 14 4 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300°C or lower. The atmosphere is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method.

[0103] When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method. When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method. When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method. When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method. When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method.

[0104] Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being contained in the oxide semiconductor layer 140 and the protective insulating layer 144. Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being contained in the oxide semiconductor layer 140 and the protective insulating layer 144. Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being contained in the oxide semiconductor layer 140 and the protective insulating layer 144.

[0105] To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting the film-forming chamber using a cryopump, since compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) are removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting the film-forming chamber using a cryopump, since compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) are removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting the film-forming chamber using a cryopump, since compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) are removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. 2 For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting the film-forming chamber using a cryopump, since compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) are removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting the film-forming chamber using a cryopump, since compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) are removed, the concentration of impurities contained in the protective insulating layer 144 formed in the film-forming chamber can be reduced.

[0106] As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is removed to about several ppm (desirably about several ppb). As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is removed to about several ppm (desirably about several ppb). As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is removed to about several ppm (desirably about several ppb).

[0107] Next, a second heat treatment (preferably at 2 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is preferably performed in an inert gas atmosphere or an oxygen gas atmosphere. For example a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor.

[0108] Alternatively, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating the temperature increase from room temperature to a heating temperature of 10 0°C or higher and 200°C or lower and the temperature decrease from the heating temperature to room temperature a plurality of times. Further, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. Note that the heat treatment may be performed instead of the second heat treatment described above, or may be performed after the second heat treatment.

[0109] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 6(A)). The interlayer insulating layer 146 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to planarize its surface by a method such as CMP or etching.

[0110] Next, with respect to the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138, an electrode 1 36a, electrode 136b, source electrode or drain electrode 142a, source electrode or drain An opening reaching the electrode 142a or the drain electrode 142b is formed, and the conductive layer 148 is formed so as to be embedded in the opening (see Fig. 6(B)). The above opening can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, it is preferable to use dry etching. The formation of the conductive layer 148 can be carried out using a film formation method such as PVD method or CVD method. Examples of the material that can be used for the formation of the conductive layer 148 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., and alloys and compounds (e.g., nitrides) thereof. Specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD method in a region including the opening, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to be embedded in the opening. Here, the titanium film formed by PVD method reduces the oxide film at the interface with the lower electrode (here, electrode 136a, electrode 136b, source electrode or drain electrode 142a,

[0111] source electrode or drain electrode 142b), and has a function of reducing the contact resistance with the lower electrode. Further, the subsequently formed titanium nitride has a barrier function of suppressing the diffusion of the conductive material. After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148. After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148. After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148. After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148. After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148.

[0112] After forming the conductive layer 148, methods such as etching or CMP are used to process the conductive layer 148. ​Remove a part of it to expose the interlayer insulating layer 146, and form electrodes 150a, 150b, electrode 1 50c, and 150d (see Fig. 6(C)). When forming electrodes 150a, 150b, 150c, and 150d by removing a part of the conductive layer 148, it is desirable to process so that the surface becomes flat. Thus, by planarizing the surfaces of the interlayer insulating layer 146, electrodes 150a, 150b, 150c, and 150d, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0113] Furthermore, form an insulating layer 152, form openings in the insulating layer 152 that reach electrodes 150a, 150b, electrode 1 50c, and 150d, form a conductive layer so as to fill the openings, and then remove a part of the conductive layer using methods such as etching or CMP to expose the insulating layer 15 2 and form electrodes 154a, 154b, and 154c (see Fig. 6(D)). Since this process is the same as the case of forming electrodes 150a, etc., details are omitted.

[0114] When manufacturing the n-type transistor 162 by the method as described above, the hydrogen concentration of the oxide semiconductor layer 140 is 5×10 atoms / cm 19 or less, and the off-current of the n-type transistor 162 is 1×10 3 A or less, preferably 100 zA / μm or less. By applying such an oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration and high purity, an n-type transistor 162 with excellent characteristics can be obtained. Also, having a p-type transistor at the lower part and an n-type transistor using an oxide semiconductor at the upper part, a semiconductor with excellent characteristics -13 A conductor device can be fabricated.

[0115] Thus, by adopting a configuration that integrally includes a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor, a semiconductor device with different electrical characteristics (for example, different carriers involved in the operation of the element) can be realized. Since the transistor using an oxide semiconductor has good switching characteristics, an excellent semiconductor device can be fabricated by utilizing such characteristics. For example, in a CMOS inverter circuit, the through current can be sufficiently suppressed, thereby reducing the power consumption of the semiconductor device and preventing the destruction of the semiconductor device by a large current. Also, since the transistor using an oxide semiconductor has an extremely small off-current, the power consumption of the semiconductor device can be reduced by using it. For example, in a CMOS inverter circuit, since the through current can be sufficiently suppressed, the power consumption of the semiconductor device can be reduced, and the destruction of the semiconductor device by a large current can be prevented. In addition, since the off-current of the transistor using an oxide semiconductor is extremely small, the power consumption of the semiconductor device can be reduced by using it.

[0116] In the present embodiment, an example in which the p-type transistor 160 and the n-type transistor 162 are stacked and formed has been described, but the present invention is not limited to this, and the p-type transistor 160 and the n-type transistor 162 may be formed on the same substrate. Also, in the present embodiment, an example in which the channel length directions of the p-type transistor 160 and the n-type transistor 162 are orthogonal to each other has been described, but the positional relationship between the p-type transistor 160 and the n-type transistor 162 is not limited to this. Furthermore, the p-type transistor 160 and the n-type transistor 162 may be provided in a superimposed manner. For example, in a CMOS inverter circuit, since the through current can be sufficiently suppressed, the power consumption of the semiconductor device can be reduced, and the destruction of the semiconductor device by a large current can be prevented. In addition, since the off-current of the transistor using an oxide semiconductor is extremely small, the power consumption of the semiconductor device can be reduced by using it. In the present embodiment, an example in which the p-type transistor 160 and the n-type transistor 162 are stacked and formed has been described, but the present invention is not limited to this, and the p-type transistor 160 and the n-type transistor 162 may be formed on the same substrate. Also, in the present embodiment, an example in which the channel length directions of the p-type transistor 160 and the n-type transistor 162 are orthogonal to each other has been described, but the positional relationship between the p-type transistor 160 and the n-type transistor 162 is not limited to this. Furthermore, the p-type transistor 160 and the n-type transistor 162 may be provided in a superimposed manner.

[0117] In the present embodiment, an example in which the p-type transistor 160 and the n-type transistor 162 are stacked and formed has been described, but the present invention is not limited to this, and the p-type transistor 160 and the n-type transistor 162 may be formed on the same substrate. Also, in the present embodiment, an example in which the channel length directions of the p-type transistor 160 and the n-type transistor 162 are orthogonal to each other has been described, but the positional relationship between the p-type transistor 160 and the n-type transistor 162 is not limited to this. Furthermore, the p-type transistor 160 and the n-type transistor 162 may be provided in a superimposed manner. In the present embodiment, an example in which the channel length directions of the p-type transistor 160 and the n-type transistor 162 are orthogonal to each other has been described, but the positional relationship between the p-type transistor 160 and the n-type transistor 162 is not limited to this. Furthermore, the p-type transistor 160 and the n-type transistor 162 may be provided in a superimposed manner. In the present embodiment, an example in which the channel length directions of the p-type transistor 160 and the n-type transistor 162 are orthogonal to each other has been described, but the positional relationship between the p-type transistor 160 and the n-type transistor 162 is not limited to this. Furthermore, the p-type transistor 160 and the n-type transistor 162 may be provided in a superimposed manner.

[0118] The configurations, methods, etc. shown in the present embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments. They can be used in combination.

[0119] (Embodiment 2) In this embodiment, the configuration of a semiconductor device according to another aspect of the disclosed invention will be described with reference to FIGS. 7 and 8. Note that in this embodiment, the configuration of a semiconductor device that can be used as a memory element is shown.

[0120] FIG. 7(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and FIG. 7(B) shows a plan view of the semiconductor device according to this embodiment. Here, FIG. 7(A) corresponds to the cross-section along lines E1-E2 and F1-F2 in FIG. 7(B). FIGS. 7(A) and 7(B) The semiconductor device shown in FIGS. 7(A) and 7(B) has a transistor 260 using a material other than an oxide semiconductor at the lower part and a transistor 262 using an oxide semiconductor at the upper part.

[0121] The transistor 260 using a material other than an oxide semiconductor includes a channel formation region 216 provided in a substrate 200 containing a semiconductor material, and impurity regions 214 and a high-concentration impurity region 220 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 216, a gate insulating layer 208a provided on the channel formation region 216, a gate electrode 210a provided on the gate insulating layer 208a, a source electrode or drain electrode 230a electrically connected to the impurity region 214 provided on one side of the channel formation region 216, and a source electrode or drain electrode 230b electrically connected to the impurity region 214 provided on the other side of the channel formation region 216. Note that the source electrode or drain electrode 230a is a metal compound region 224 provided on one side of the channel formation region 216. ​ is electrically connected to the impurity region 214 provided on one side of the channel formation region 216 through Subsequently, the source electrode or drain electrode 230b is provided on the other side of the channel formation region 216 through the metal compound region 224 provided on the other side of the channel formation region 216, and is preferably electrically connected to the impurity region 214 provided on the other side of the channel formation region 216. Thus, the configuration of the transistor 260 is the same as that of the p-type transistor 160 described in the previous embodiment, so other details can be referred to the previous embodiment. Note that the polarity of the transistor 260 does not necessarily have to be limited to p-type, and it may be n-type. The transistor 260 is the same as that of the p-type transistor 160 described in the previous embodiment, so other details can be referred to the previous embodiment. Note that the polarity of the transistor 260 does not necessarily have to be limited to p-type, and it may be n-type. For the polarity of the transistor 260, it is not necessary to be limited to p-type, and it may be n-type.

[0122] The transistor 262 using an oxide semiconductor includes a gate electrode 236c provided on the insulating layer 228, a gate insulating layer 238 provided on the gate electrode 236c, an oxide semiconductor layer 240 provided on the gate insulating layer 238, and a source electrode or drain electrode 242a and a source electrode or drain electrode 242b provided on the oxide semiconductor layer 240 and electrically connected to the oxide semiconductor layer 240. Thus, the configuration of the transistor 262 is the same as that of the n-type transistor 162 described in the previous embodiment, so other details can be referred to the previous embodiment. On the other hand, for the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type. 36c, a gate insulating layer 238 provided on the gate electrode 236c, an oxide semiconductor layer 240 provided on the gate insulating layer 23 8, and a source electrode or drain electrode 242a and a source electrode or drain electrode 242b provided on the oxide semiconductor layer 240 and electrically connected to the oxide semiconductor layer 240. Thus, the configuration of the transistor 262 is the same as that of the n-type transistor 162 described in the previous embodiment, so other details can be referred to the previous embodiment. On the other hand, for the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type. 8, and a source electrode or drain electrode 242a and a source electrode or drain electrode 242b provided on the oxide semiconductor layer 240 and electrically connected to the oxide semiconductor layer 240. Thus, the configuration of the transistor 262 is the same as that of the n-type transistor 162 described in the previous embodiment, so other details can be referred to the previous embodiment. On the other hand, for the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type. has a source electrode or drain electrode 242a and a source electrode or drain electrode 242b provided on the oxide semiconductor layer 240 and electrically connected to the oxide semiconductor layer 240. Thus, the configuration of the transistor 262 is the same as that of the n-type transistor 162 described in the previous embodiment, so other details can be referred to the previous embodiment. On the other hand, for the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type. is the same as that of the n-type transistor 162 described in the previous embodiment, so other details can be referred to the previous embodiment. For other details, the previous embodiment can be referred to. On the other hand, for the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type. For the polarity of the transistor 262, it is not necessary to be limited to n-type, and it may be p-type.

[0123] Next, the electrical connection relationship between the transistor 260 and the transistor 262 will be described. The source electrode or drain electrode 230a of the transistor 260 is electrically connected to a predetermined wiring through electrodes 236a, electrodes 250a, electrodes 254a, etc. Also, the transistor The source electrode or drain electrode 230b of the transistor 260 is electrically connected to a predetermined wiring via the electrode 236b, the electrode 25 0b, the electrode 254b, etc.

[0124] The source electrode or drain electrode 242a of the transistor 262 is connected to the gate electrode 210a of the transistor 260 via the electrode 250d, the electrode 2 54c, the electrode 250c, the electrode 236b, and the electrode 230c. Also, the source electrode or drain electrode 242b of the transistor 262 is connected to a predetermined wiring via the electrode 250e, the electrode 254d, etc. and is electrically connected. In addition, the source electrode or drain electrode 242b of the transistor 262 is electrically connected to a predetermined wiring via the electrode 250e, the electrode 254d, etc. and is electrically connected.

[0125] Note that in FIG. 7, the element isolation insulating layer 206 corresponds to the element isolation insulating layer 106 of Embodiment 1, the sidewall insulating layer 218 corresponds to the sidewall insulating layer 118 of Embodiment 1, the interlayer insulating layer 226 corresponds to the interlayer insulating layer 126 of Embodiment 1, the insulating layer 232 corresponds to the insulating layer 1 32 of Embodiment 1, the protective insulating layer 244 corresponds to the protective insulating layer 144 of Embodiment 1, the interlayer insulating layer 246 corresponds to the interlayer insulating layer 146 of Embodiment 1, and the insulating layer 252 corresponds to the insulating layer 152 of Embodiment 1. layer 226 corresponds to the interlayer insulating layer 126 of Embodiment 1, the insulating layer 232 corresponds to the insulating layer 1 32 of Embodiment 1, the protective insulating layer 244 corresponds to the protective insulating layer 144 of Embodiment 1, the interlayer insulating layer 246 corresponds to the interlayer insulating layer 146 of Embodiment 1, and the insulating layer 252 corresponds to the insulating layer 152 of Embodiment 1. Note that in FIG. 7, the element isolation insulating layer 206 corresponds to the element isolation insulating layer 106 of Embodiment 1, the sidewall insulating layer 218 corresponds to the sidewall insulating layer 118 of Embodiment 1, the interlayer insulating layer 226 corresponds to the interlayer insulating layer 126 of Embodiment 1, the insulating layer 232 corresponds to the insulating layer 1 32 of Embodiment 1, the protective insulating layer 244 corresponds to the protective insulating layer 144 of Embodiment 1, the interlayer insulating layer 246 corresponds to the interlayer insulating layer 146 of Embodiment 1, and the insulating layer 252 corresponds to the insulating layer 152 of Embodiment 1.

[0126] FIG. 8 shows an example of a circuit diagram when the above semiconductor device is used as a memory element.

[0127] The source electrode of the transistor 260 using a material other than an oxide semiconductor is electrically connected to the first source wiring (Source1). Also, the drain electrode of the transistor 260 using a material other than an oxide semiconductor is electrically connected to the drain wiring (Drain) . Also, the gate electrode of the transistor 260 using a material other than an oxide semiconductor is an acid oxide semiconductor. It is electrically connected to the drain electrode of the transistor 262 using an oxide semiconductor.

[0128] The source electrode of the transistor 262 using an oxide semiconductor is electrically connected to the second source wiring (Source2). Also, the gate electrode of the transistor 262 using an oxide semiconductor is electrically connected to the gate wiring (Gate).

[0129] Here, the transistor 262 using an oxide semiconductor has the characteristic that the off-current is extremely small. Therefore, by turning off the transistor 262, it is possible to hold the potential of the gate electrode of the transistor 260 for an extremely long time.

[0130] By taking advantage of the characteristic of holding the potential of the gate electrode, for example, it can function as a memory element by the following operation. First, the potential of the gate wiring (Gate) is set to a potential at which the transistor 262 is turned on, and the transistor 262 is turned on. As a result, the potential of the second source wiring (Source2) is applied to the gate electrode of the transistor 260 (write operation). After that, the potential of the gate wiring (Gate) is set to a potential at which the transistor 262 is turned off, and the transistor 262 is turned off.

[0131] Since the off-current of the transistor 262 is extremely small, the potential of the gate electrode of the transistor 260 is held for a long time. More specifically, for example, if the potential of the gate electrode of the transistor 260 is a potential that turns on the transistor 260, the on-state of the transistor 260 will be held for a long time. If the potential of the gate electrode turns off the transistor 260, the off state of the transistor 26 0 is maintained for a long time.

[0132] Therefore, according to the potential held at the gate electrode of the transistor 260, the potential of the drain wiring (Drain) takes different values. For example, if the potential of the gate electrode of the transistor 260 turns on the transistor 260, the on state of the transistor 260 is maintained, so the potential of the drain wiring (Drain) is equal to the potential of the first source wiring (Source1). In this way, the potential of the drain wiring (Drain) takes different values according to the potential held at the gate electrode of the transistor 260, or by reading this (read operation), it functions as a memory element.

[0133] The semiconductor device according to this embodiment can hold information for an extremely long time due to the off-current characteristics of the transistor 262, so it can be used as a practical non-volatile memory element.

[0134] Note that in this embodiment, for simplicity of understanding, only the minimum unit of the memory element is described, but the configuration of the semiconductor device is not limited to this. By appropriately connecting a plurality of memory elements, a more advanced semiconductor device can also be configured. For example, using a plurality of the above memory elements, it is possible to configure NAND-type or NOR-type semiconductor devices. The configuration of the wiring is not limited to FIG. 8

[0135] As described above, in one aspect of the invention, using the off-current characteristics of the transistor 262, It constitutes a substantial non-volatile memory element. Thus, according to one aspect of the invention, a new semiconductor device with a novel configuration is provided.

[0136] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0137] (Embodiment 3) In this embodiment, the configuration of a semiconductor device according to another aspect of the disclosed invention will be described with reference to FIGS. 9 and 10. Note that in this embodiment, the configuration of a semiconductor device that can be used as a memory element is shown.

[0138] FIG. 9(A) shows a cross-sectional view of the semiconductor device according to this embodiment, and FIG. 9(B) shows a plan view of the semiconductor device according to this embodiment. Here, FIG. 9(A) corresponds to the cross-section along lines G1 - G2 and H1 - H2 in FIG. 9(B). FIGS. 9(A) and 9(B) show a semiconductor device having a p-type transistor 460 and an n-type transistor 464 using a material other than an oxide semiconductor at the lower part, and a transistor 46 2 using an oxide semiconductor at the upper part. The configurations of the p-type transistor 460 and the n-type transistor 464 using a material other than an oxide semiconductor are the same as those of the p-type transistor 160, the transistor 260, etc. in the previous embodiment. Also, the configuration of the transistor 462 using an oxide semiconductor is the same as those of the n-type transistor 162, the transistor 262, etc. in the previous embodiment. Therefore, each component of the transistor also conforms to the transistor in the previous embodiment.

[0139] The configurations of the p-type transistor 460 and the n-type transistor 464 using a material other than an oxide semiconductor are the same as those of the p-type transistor 160, the transistor 260, etc. in the previous embodiment. Also, the configuration of the transistor 462 using an oxide semiconductor is the same as those of the n-type transistor 162, the transistor 262, etc. in the previous embodiment. Thus, each component of the transistor also conforms to the transistor in the previous embodiment. and becomes similar to the transistors in the previous embodiment. ​​​​​It exists. For details, the previous embodiments can be referred to.

[0140] In FIG. 9, the substrate 400 corresponds to the substrate 100 of Embodiment 1, the element isolation insulating layer 406 corresponds to the element isolation insulating layer 106 of Embodiment 1, the gate insulating layer 408a corresponds to the gate insulating layer 108a of Embodiment 1, the gate electrode 410a corresponds to the gate electrode 110a of Embodiment 1, the gate wiring 410b corresponds to the gate wiring 110b of Embodiment 1, the impurity region 414 corresponds to the impurity region 114 of Embodiment 1, the channel formation region 416 corresponds to the channel formation region 1 16 of Embodiment 1, the sidewall insulating layer 418 corresponds to the sidewall insulating layer 118 of Embodiment 1, the high-concentration impurity region 420 corresponds to the high-concentration impurity region 120 of Embodiment 1, the metal compound region 4 24 corresponds to the metal compound region 124 of Embodiment 1, the interlayer insulating layer 426 corresponds to the interlayer insulating layer 126 of Embodiment 1, the interlayer insulating layer 428 corresponds to the interlayer insulating layer 128 of Embodiment 1, the source electrode or drain electrode 430a corresponds to the source electrode or drain electrode 130a of Embodiment 1, the source electrode or drain electrode 430b corresponds to the source electrode or drain electrode 130b of Embodiment 1, the source electrode or drain electrode 430c corresponds to the electrode 130e of Embodiment 2, and they respectively correspond.

[0141] Also, the insulating layer 432 corresponds to the insulating layer 132 of Embodiment 1, the electrode 436a corresponds to the electrode 136a of Embodiment 1, the electrode 436b corresponds to the electrode 136b of Embodiment 1, the gate electrode 436c corresponds to the gate electrode 136c of Embodiment 1, the gate insulating layer 438 corresponds to the gate insulating layer 138 of Embodiment 1, the oxide semiconductor layer 440 corresponds to the oxide semiconductor layer 140 of Embodiment 1, the source electrode Alternatively, the drain electrode 442a is the source electrode or drain electrode 142a of Embodiment 1 , the source electrode or drain electrode 442b is the source electrode or drain electrode 142b of Embodiment 1, the protective insulating layer 444 is the protective insulating layer 144 of Embodiment 1, the interlayer insulating layer 44 6 is the interlayer insulating layer 146 of Embodiment 1, the electrode 450a is the electrode 150a of Embodiment 1 , the electrode 450b is the electrode 150b of Embodiment 1, the electrode 450c is the electrode 1 50b of Embodiment 1, the electrode 450d is the electrode 150c of Embodiment 1, the electrode 450e is the electrode 1 50d of Embodiment 1, the insulating layer 452 is the insulating layer 152 of Embodiment 1, the electrode 454a is the electrode 154a of Embodiment 1, the electrode 454b is the electrode 154b of Embodiment 1, the electrode 454 c is the electrode 154b of Embodiment 1, the electrode 454d is the electrode 154c of Embodiment 1, and they respectively correspond.

[0142] The semiconductor device according to this embodiment is different from the semiconductor device according to the previous embodiment in that the drain electrode of the transistor 462, the gate electrode of the p-type transistor 460, and the gate electrode of the n-type transistor 464 are electrically connected to each other (see FIG 9). With such a configuration, it is possible to temporarily hold the input signal (INPUT T) of the CMOS inverter circuit.

[0143] The configurations, methods, etc. shown in this embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments and used.

[0144] (Embodiment 4) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment will be described This will be described with reference to FIG. 11. The semiconductor device obtained in the previous embodiment has a transistor using an oxide semiconductor with good switching characteristics, so the power consumption of each electronic device can be reduced. Also, since a new semiconductor device (for example, a memory element, etc.) utilizing the characteristics of the oxide semiconductor is provided, it is possible to provide an electronic device with a new configuration. In addition, the semiconductor device according to the previous embodiment will be mounted on a circuit board, etc., either singly or in an integrated manner, and will be incorporated inside each electronic device. Since it has a transistor using an oxide semiconductor with good switching characteristics, the power consumption of each electronic device can be reduced. In addition, since a new semiconductor device (for example, a memory element, etc.) utilizing the characteristics of the oxide semiconductor is provided, it is possible to provide an electronic device with a new configuration. Furthermore, since a new semiconductor device (for example, a memory element, etc.) utilizing the characteristics of the oxide semiconductor is provided, it is possible to provide an electronic device with a new configuration. Moreover, the semiconductor device according to the previous embodiment will be mounted on a circuit board, etc., either singly or in an integrated manner, and will be incorporated inside each electronic device. Moreover, the semiconductor device according to the previous embodiment will be mounted on a circuit board, etc., either singly or in an integrated manner, and will be incorporated inside each electronic device.

[0145] An integrated circuit in which the semiconductor device is incorporated and integrated is often configured by incorporating various circuit elements such as resistors, capacitors, and coils in addition to the semiconductor device described in the previous embodiment. Examples of integrated circuits include those in which an arithmetic circuit, a conversion circuit, an amplification circuit, a memory circuit, and circuits related to combinations thereof are highly integrated. MPU, CPU, etc. can be said to be the most typical ones. An integrated circuit in which the semiconductor device is incorporated and integrated is often configured by incorporating various circuit elements such as resistors, capacitors, and coils in addition to the semiconductor device described in the previous embodiment. Examples of integrated circuits include those in which an arithmetic circuit, a conversion circuit, an amplification circuit, a memory circuit, and circuits related to combinations thereof are highly integrated. Examples of integrated circuits include those in which an arithmetic circuit, a conversion circuit, an amplification circuit, a memory circuit, and circuits related to combinations thereof are highly integrated. MPU, CPU, etc. can be said to be the most typical ones.

[0146] Also, it is possible to use the above semiconductor device as a switching element of a display device, etc. In this case, it is preferable to provide a drive circuit on the same substrate. Of course, the above semiconductor device can also be used only for the drive circuit of the display device. In this case, it is preferable to provide a drive circuit on the same substrate. Of course, the above semiconductor device can also be used only for the drive circuit of the display device.

[0147] FIG. 11(A) shows a notebook personal computer including the semiconductor device according to the previous embodiment, which is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. FIG. 11(A) shows a notebook personal computer including the semiconductor device according to the previous embodiment, which is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. FIG. 11(A) shows a notebook personal computer including the semiconductor device according to the previous embodiment, which is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc.

[0148] FIG. 11(B) shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. , the main body 311 is provided with a display unit 313, an external interface 315, operation buttons 314, etc. There is also a stylus 312 as an accessory for operation.

[0149] FIG. 11(C) shows, as an example of an electronic paper including the semiconductor device according to the previous embodiment, an electronic book 320. The electronic book 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337, and can perform an opening and closing operation around the shaft portion 337. With such a configuration, it can be used like a paper book.

[0150] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By adopting a configuration to display different screens, for example, a text can be displayed on the right display unit (display unit 325 in FIG. 11(C)), and an image can be displayed on the left display unit (display unit 327 in FIG. 11 (C)). (C)).

[0151] Also, FIG. 11(C) shows an example in which the housing 321 is provided with an operation unit or the like. For example, in the housing 321, a power supply 331, operation keys 333, a speaker 335, etc. are provided. Pages can be turned by the operation keys 333. In addition, a configuration may be adopted in which a keyboard or a pointing device or the like is provided on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (terminals that can be connected to various cables such as earphone terminals, USB terminals, or an AC adapter and a USB cable etc.), a recording medium insertion portion, etc. may be provided. ​This is also acceptable. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. .

[0152] Also, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is also possible to purchase and download desired book data and the like from an electronic book server.

[0153] Note that the electronic paper can be applied to any field as long as it can display information. For example, in addition to electronic books, it can be applied to posters, in-vehicle advertisements on vehicles such as trains, and displays on various cards such as credit cards.

[0154] FIG. 11(D) shows a mobile phone including the semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, a housing 340 and a housing 341. The housing 341 is provided with a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 is provided with a solar cell 349 for charging the mobile phone and an external memory slot 350. Further, the antenna is built into the housing 341.

[0155] The display panel 342 has a touch panel, and FIG. 11(D) shows a plurality of operation keys 345 where video is displayed by a dotted line. Note that the mobile phone is equipped with a boost circuit for boosting the voltage output by the solar cell 349 to the voltage required for each circuit. Also, in addition to the above configuration, it is also possible to have a configuration with a built-in non-contact IC chip, a small recording device, etc.

[0156] The display direction of the display panel 342 changes appropriately depending on the usage mode. A camera lens 347 is provided on the same surface as the camera 42, making video calling possible. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can be slid to each other, as shown in FIG. It can be folded up from the unfolded state like this, making it compact and easy to carry. It is possible.

[0157] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. It is possible to charge the battery and to communicate with a personal computer. A recording medium can be inserted into the slot 350 to accommodate the storage and transfer of larger amounts of data. In addition to the above functions, it may also have infrared communication functions, television reception functions, etc. stomach.

[0158] FIG. 11E shows a digital camera including the semiconductor device according to the above embodiment. The digital camera is comprised of a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc.

[0159] FIG. 11F illustrates a television set including the semiconductor device according to the above embodiment. The vision device 370 has a display unit 373 built into a housing 371. In addition, the stand 375 supports the housing 3. This shows the configuration that supported 71.

[0160] The operation of the television device 370 can be performed by operation switches provided in the housing 371 or a separate remote controller. The operation can be carried out by the operation unit 380. By means of the operation keys 379 provided in the remote control operation unit 380, operations such as changing channels and adjusting the volume can be performed, and the video displayed on the display unit 373 can be operated. In addition, the remote control operation unit 380 may be configured to be provided with a display unit 377 for displaying information output from the remote control operation unit 380.

[0161] It should be noted that the television device 370 is preferably configured to include a receiver, a modem, and the like. The receiver can be used to receive general television broadcasts. Also, by connecting to a wired or wireless communication network via the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between receivers) information communication can be performed.

[0162] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

Explanation of Reference Numerals

[0163] 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108a Gate insulating layer 108b Gate insulating layer 110a Gate electrode 110b Gate wiring 110c Wiring 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c Source electrode or drain electrode 130d Source electrode or drain electrode 130e Electrode 132 Insulating layer 134 Conductive layer 136a Electrode 136b Electrode 136c Gate electrode 136d Electrode 136e Electrode 136f Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a Electrode 150b Electrode 150c Electrode 150d Electrode 150e Electrode 150f Electrode 152 Insulating layer 154a Electrode 154b Electrode 154c Electrode 154d Electrode 154e Electrode 160 p-type transistor 162 n-type transistor 164 p-type transistor 166 n-type transistor 200 Substrate 206 Element isolation insulating layer 208a Gate insulating layer 210a Gate electrode 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High-concentration impurity region 224 Metal compound region 226 Interlayer insulating layer 228 Insulating layer 230a Source electrode or drain electrode 230b Source electrode or drain electrode 230c Electrode 232 Insulating layer 236a Electrode 236b Electrode 236c Gate electrode 238 Gate insulating layer 240 Oxide semiconductor layer 242a Source electrode or drain electrode 242b Source electrode or drain electrode 244 Protection insulating layer 246 Interlayer insulating layer 250a Electrode 250b Electrode 250c Electrode 250d Electrode 250e Electrode 252 Insulating layer 254a Electrode 254b Electrode 254c Electrode 254d Electrode 260 Transistor 262 Transistor 301 Body 302 Housing 303 Display unit 304 Keyboard 311 Body 312 Stylus 313 Display unit 314 Operation button 315 External interface 320 E-book 321 Housing 323 Housing 325 Display unit 327 Display unit 331 Power supply 333 Operation key 335 Speaker 337 Shaft portion 340 Housing 341 Housing 342 Display panel 343 Speaker 344 Microphone 345 Operation key 346 Pointing device 347 Camera lens 348 External connection terminal 349 Solar cell 350 External memory slot 361 Main body 363 Eyepiece portion 364 Operation switch 365 Display unit (B) 366 Battery 367 Display unit (A) 370 Television apparatus 371 Housing 373 Display unit 375 Stand 377 Display unit 379 Operation key 380 Remote control operation unit 400 Substrate 406 Element isolation insulating layer 408a Gate insulating layer 410a Gate electrode 410b Gate wiring 414 Impurity region 416 Channel formation region 418 Sidewall insulating layer 420 High-concentration impurity region 424 Metal compound region 426 Interlayer insulating layer 428 Interlayer insulating layer 430a Source electrode or drain electrode 430b Source electrode or drain electrode 430c Source electrode or drain electrode 432 Insulating layer 436a Electrode 436b Electrode 436c Gate electrode 438 Gate insulating layer 440 Oxide semiconductor layer 442a Source electrode or drain electrode 442b Source electrode or drain electrode 444 Protective insulating layer 446 Interlayer insulating layer 450a Electrode 450b Electrode 450c Electrode 450d Electrode 450e Electrode 452 Insulating layer 454a Electrode 454b Electrode 454c Electrode 454d Electrode 460 p-type transistor 462 Transistor 464 n-type transistor

Claims

1. A semiconductor device having a first transistor and a second transistor, wherein a potential corresponding to information is written to a gate of the first transistor via the second transistor, the semiconductor device comprising: a silicon semiconductor layer in which a channel formation region of the first transistor is provided; a first insulating layer disposed above the silicon semiconductor layer; an oxide semiconductor layer disposed above the first insulating layer and in which a channel formation region of the second transistor is provided; a second insulating layer disposed above the oxide semiconductor layer; and a first conductive layer disposed above the second insulating layer, wherein the oxide semiconductor layer does not overlap with the gate of the first transistor, and the gate of the first transistor is electrically connected to one of a source and a drain of the second transistor via the first conductive layer. Semiconductor device.

2. A semiconductor device having a first transistor and a second transistor, wherein a potential corresponding to information is written to a gate of the first transistor via the second transistor, the semiconductor device comprising: a silicon semiconductor layer in which a channel formation region of the first transistor is provided; a first insulating layer disposed above the silicon semiconductor layer; an oxide semiconductor layer disposed above the first insulating layer and in which a channel formation region of the second transistor is provided; a second insulating layer disposed above the oxide semiconductor layer; and a first conductive layer disposed above the second insulating layer, wherein the oxide semiconductor layer does not overlap with the gate of the first transistor, and the gate of the first transistor is electrically connected to one of a source and a drain of the second transistor via the first conductive layer. The second transistor has an off-current of 1 × 10 －１３ A or less, Semiconductor device.

3. A semiconductor device having a first transistor and a second transistor, wherein a potential corresponding to information is written to a gate of the first transistor via the second transistor, the semiconductor device comprising: a silicon semiconductor layer in which a channel formation region of the first transistor is provided; a first insulating layer disposed above the silicon semiconductor layer; an oxide semiconductor layer disposed above the first insulating layer and in which a channel formation region of the second transistor is provided; a second insulating layer disposed above the oxide semiconductor layer; a first conductive layer disposed above the second insulating layer the oxide semiconductor layer has no overlap with the gate of the first transistor the gate of the first transistor is electrically connected to one of the source or drain of the second transistor via the first conductive layer The second transistor has an off-current of 1 × 10 －１３ A or less, after a potential is applied to the gate of the first transistor when the second transistor is turned on, the potential of the gate of the first transistor is held when the second transistor is turned off a semiconductor device

4. a semiconductor device having a first transistor and a second transistor a semiconductor device in which a potential corresponding to information is written to the gate of the first transistor via the second transistor a silicon semiconductor layer in which a channel formation region of the first transistor is provided a first insulating layer disposed above the silicon semiconductor layer a second conductive layer disposed above the first insulating layer and having a function as a gate of the second transistor a third conductive layer disposed above the first insulating layer and electrically connected to the silicon semiconductor layer an oxide semiconductor layer disposed above the second conductive layer and in which a channel formation region of the second transistor is provided a second insulating layer disposed above the oxide semiconductor layer a first conductive layer disposed above the second insulating layer the oxide semiconductor layer has no overlap with the gate of the first transistor the second conductive layer and the third conductive layer have a region in contact with the upper surface of the first insulating layer the gate of the first transistor is electrically connected to one of the source or drain of the second transistor via the first conductive layer a semiconductor device

5. a semiconductor device having a first transistor and a second transistor a semiconductor device in which a potential corresponding to information is written to the gate of the first transistor via the second transistor a silicon semiconductor layer in which a channel formation region of the first transistor is provided a first insulating layer disposed above the silicon semiconductor layer a second conductive layer disposed above the first insulating layer and having a function as a gate of the second transistor a third conductive layer disposed above the first insulating layer and electrically connected to the silicon semiconductor layer An oxide semiconductor layer that is disposed above the second conductive layer and in which a channel formation region of the second transistor is provided; A second insulating layer disposed above the oxide semiconductor layer; A first conductive layer disposed above the second insulating layer, and having: The oxide semiconductor layer does not overlap with the gate of the first transistor; The second conductive layer and the third conductive layer have a region in contact with the upper surface of the first insulating layer; The gate of the first transistor is electrically connected to one of the source or drain of the second transistor via the first conductive layer; The second transistor has an off-current of 1 × 10 －１３ A or less, A semiconductor device.

6. A semiconductor device having a first transistor and a second transistor, wherein a potential corresponding to information is written to the gate of the first transistor via the second transistor, A silicon semiconductor layer in which a channel formation region of the first transistor is provided; A first insulating layer disposed above the silicon semiconductor layer; A second conductive layer that is disposed above the first insulating layer and functions as a gate of the second transistor; A third conductive layer that is disposed above the first insulating layer and is electrically connected to the silicon semiconductor layer; An oxide semiconductor layer that is disposed above the second conductive layer and in which a channel formation region of the second transistor is provided; A second insulating layer disposed above the oxide semiconductor layer; A first conductive layer disposed above the second insulating layer, and having: The oxide semiconductor layer does not overlap with the gate of the first transistor; The second conductive layer and the third conductive layer have a region in contact with the upper surface of the first insulating layer; The gate of the first transistor is electrically connected to one of the source or drain of the second transistor via the first conductive layer; The second transistor has an off-current of 1×10 －１３ A or less, After a potential is applied to the gate of the first transistor by turning on the second transistor, the potential of the gate of the first transistor is held by turning off the second transistor; A semiconductor device.

7. In any one of Claims 1 to 6, The silicon semiconductor layer is crystallized; A semiconductor device.

8. In any one of Claims 1 to 7, The oxide semiconductor layer is any one of In—Ga—Zn—O-based, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn—Al—Zn—O-based, In—Zn—O-based, Sn—Zn—O-based, Al—Zn—O-based, In—O-based, Sn—O-based, and Zn—O-based. Semiconductor device.

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