Clock disable circuit

Abstract

The present invention suppresses an unnecessary circuit operation caused by a toggle operation of a clock signal in a clock enabler circuit.　A state holding unit performs a holding operation of a state of whether an output clock signal is to be outputted, in accordance with an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held by the state holding unit. A control unit supplies, on the basis of a clock signal and a clock enable signal from the outside, to the state holding unit, an internal clock signal and a value of the state necessary for the holding operation by the state holding unit.

Description

Technical Field

[0001] The present technology relates to a clock enable circuit. Specifically, it relates to a clock enable circuit that controls the transmission of a clock signal.

Background Art

[0002] A clock enable circuit (also referred to as a clock gating cell) is a circuit that outputs a clock signal when a clock enable signal indicates an enabled state. This clock enable circuit is often used to reduce the power consumption of a semiconductor integrated circuit by avoiding unnecessary operations caused by the clock signal. As such a clock enable circuit, for example, a circuit that captures an asynchronous clock enable signal into an internal latch in synchronization with the clock signal is known as a conventional technique (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described conventional technology, synchronization with the clock signal is achieved by capturing the clock enable signal into the latch during the period when the clock signal is at the L level. However, in this conventional technology, there is a problem that the internal circuit operates and consumes power every time the clock signal toggles, regardless of the value of the clock enable signal.

[0005] The present technology has been created in view of such a situation, and an object thereof is to suppress unnecessary circuit operations associated with the toggle operation of the clock signal in the clock enable circuit.

Means for Solving the Problems

[0006] This technology is made to solve the above problems. Its first aspect is a clock inenable circuit comprising a state holding unit that performs a holding operation of a state of whether to output an output clock signal according to an internal clock signal, a clock signal output unit that controls the output of the output clock signal according to the state held by the state holding unit, and a control unit that supplies the internal clock signal and the value of the state necessary for the holding operation to the state holding unit based on an external clock signal and a clock enable signal. This brings about an effect of stopping the toggle operation of the internal clock signal that is unnecessary for the holding operation of the state of whether to output the output clock signal.

[0007] Also, in this first aspect, the control unit may operate the internal clock signal when the clock enable signal indicates an enabled state, and stop the internal clock signal when the clock enable signal does not indicate an enabled state. This brings about an effect of stopping the toggle operation of the internal clock signal according to the state of the clock enable signal.

[0008] Also, in this first aspect, the control unit may supply, as the value of the state, a state of outputting the output clock signal when the clock enable signal indicates an enabled state, and supply, as the value of the state, a state of not outputting the output clock signal when the clock enable signal does not indicate an enabled state. This brings about an effect of supplying the value of the state held by the state holding unit according to the clock enable signal.

[0009] Also, in this first aspect, the state holding unit may include a delay unit that delays the timing of holding the value of the state. This provides the effect of preventing malfunction by adjusting the timing for the state holding unit to hold the state. In this case, the delay unit may be a clock inverter that operates according to the internal clock signal, or may be a transmission gate that operates according to the internal clock signal.

[0010] Also, in this first aspect, the clock signal output unit may generate the output clock signal based on the external clock signal. On the other hand, the clock signal output unit may generate the output clock signal based on the internal clock signal. This provides the effect of separating the external clock signal from the clock signal output unit and reducing the load capacitance of the external clock signal.

[0011] Also, in this first aspect, the control unit may include a reception circuit that receives the external clock signal. This provides the effect of making the reception process of the external clock signal independent. In this case, the reception circuit may be a small amplitude signal reception circuit or a differential small amplitude signal reception circuit. This provides the effect of consolidating processes such as level conversion in one place.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. Embodiments 2. Modification Examples

[0014] <1. Embodiments> [Semiconductor Integrated Circuit] FIG. 1 is a diagram showing an example of the connection relationship between the clock enable circuit 10 and the flip-flop circuit 20 in an embodiment of the present technology.

[0015] In a semiconductor integrated circuit, pipeline control is performed to increase the operating speed. A combinational circuit 30 is arranged in each stage of the pipeline, and a plurality of flip-flop circuits 20 are arranged in parallel at its input stage and output stage.

[0016] Each of the flip-flop circuits 20 is supplied with a clock signal CKO from the clock enable circuit 10. As a result, each of the flip-flop circuits 20 in the first stage latches the input signals IN1 to INn in synchronization with the clock signal CKO and outputs them to the first-stage combinational circuit 30. The output of the combinational circuit 30 is latched by each of the flip-flop circuits 20 in the next stage in synchronization with the clock signal CKO. Then, each of the flip-flop circuits 20 in the final stage latches the output of the previous-stage combinational circuit 30 in synchronization with the clock signal CKO and outputs it as output signals OUT1 to OUTn.

[0017] The clock enable circuit 10 takes an external clock signal CK, an enable signal E, and a test signal TE as inputs and outputs a clock signal CKO that is to be supplied to the flip-flop circuit 20. The enable signal E is a signal for enabling the output of the clock signal CKO in the system mode. The test signal TE is a signal for performing a forced operation in the test mode. In the clock enable circuit 10, since the enable signal E and the test signal TE are treated equally, they may be collectively referred to as "clock enable signals" hereinafter.

[0018] [Clock Enable Circuit] FIG. 2 is a diagram showing a configuration example of the clock enable circuit 10 in the embodiment of the present technology.

[0019] This clock enable circuit 10 includes a clock enable signal generation unit 100, a control unit 200, a state holding unit 300, and a clock signal output unit 400.

[0020] The clock enable signal generation unit 100 detects that at least one of the enable signal E or the test signal TE indicates an enabled state, and generates a clock enable signal. Considering the ease of logic configuration in the subsequent control unit 200, negative logic is adopted. Therefore, this clock enable signal generation unit 100 is composed of a NOR (Negative OR) gate 110. Accordingly, the output ETNR of the clock enable signal generation unit 100 becomes the L (Low) level when at least one of the enable signal E or the test signal TE indicates an enabled state, and becomes the H (High) level when neither indicates an enabled state. Note that the test signal TE is not limited to one, and there may be multiple.

[0021] The control unit 200 supplies the internal clock CKB and the state value LE necessary for the holding operation in the state holding unit 300 to the state holding unit 300 based on the external clock signal CK and the clock enable signal (negative logic) ETNR. Thereby, the control unit 200 performs control to reduce the circuits that operate in conjunction with the toggle operation of the clock signal CK when both the enable signal E and the test signal TE are at the L level. This control unit 200 is composed of an RS latch circuit consisting of two NAND (Negative AND) gates 210 and 220 that take the clock signal CK and ETNR as inputs. Accordingly, this control unit 200 does not require the output signal of the state holding unit 300 as an input.

[0022] In this control unit 200, when LE is at the H level, the internal clock CKB, which is the inverted signal of the clock signal CK, propagates to the subsequent state holding unit 300 through the negative AND gate 210. On the other hand, when LE is at the L level, the clock signal CK is blocked by the negative AND gate 210, and the internal clock CKB is fixed at the H level.

[0023] In this way, by adopting the structure using the RS latch circuit in the control unit 200, it operates correctly even when the enable signal E or the test signal TE changes while the clock signal CK is at the H level. For example, if the negative AND gate 220 were simply an inverter that inverts ETNR, when the enable signal E or the test signal TE changes while the clock signal CK is at the H level, the clock signal CKO changes at the timing when the enable signal E or the test signal TE changes. Therefore, there is a risk of malfunction. On the other hand, in this embodiment, by appropriately generating LE, when both the enable signal E and the test signal TE are at the L level, that is, when there is no need to propagate the clock signal CK to the clock signal CKO, the toggle operation of the internal clock CKB can be stopped.

[0024] The state holding unit 300 performs the state holding operation of whether to output the clock signal CK as the clock signal CKO according to the internal clock CKB. This state holding unit 300 functions as a low active latch that takes the internal clock CKB and LE as inputs, and includes a latch 330, an input buffer 320, and an inverted clock generation unit 310.

[0025] The latch 330 holds the state of whether to output the clock signal CK as the clock signal CKO, and outputs the value LAT of the state to be held to the clock signal output unit 400. This latch 330 is composed of an inverter 331 and a clocked inverter 332, and holds the value in the loop connecting these. The clocked inverter 332 is controlled by the internal clock CKB and its inverted clock CKBB.

[0026] The input buffer 320 is a buffer for writing a value to the latch 330, and is a clocked inverter controlled by the internal clock CKB and its inverted clock CKBB.

[0027] The inversion clock generation unit 310 generates its inverted clock CKBB from the internal clock CKB. The input internal clock CKB of the inversion clock generation unit 310 and the output inverted clock CKBB of the inversion clock generation unit 310 are both supplied to the input buffer 320 and the clock inverter 332.

[0028] As a result, when the internal clock CKB is at the H level, LE is written to LATB in the latch 330.

[0029] The clock signal output unit 400 controls the output of the clock signal CKO according to the state held by the state holding unit 300. This clock signal output unit 400 performs an operation of propagating the clock signal CK to the output or blocking it at the L level according to the output LAT of the latch 330. This clock signal output unit 400 includes a negative logical product (NAND) gate 410 and an inverter 420, and generates the clock signal CKO by generating the logical product of the clock signal CK and the output LAT of the latch 330 as a whole.

[0030] [Operation] FIG. 3 is a diagram showing an example of the state transition of the control unit 200 in the embodiment of the present technology. FIG. 4 is a table showing an example of the state transition of the control unit 200 in the embodiment of the present technology.

[0031] Here, in the control unit 200, it is regarded as an RS latch in which one input of the negative logical product gate 210 is the reset input R and one input of the negative logical product gate 210 is the set input S, and its state transition is analyzed. That is, the clock signal CK is input to the reset input R, and ETNR is input to the set input S. Then, LE is output from the output Q, and the inverted clock CKB is output from the output QB.

[0032] In the initial operation of a standard integrated circuit, since the initial value of the clock is at the L level, the clock signal CK also starts from "0" in this state transition diagram.

[0033] As a first case, when the enable signal E and the test signal TE are at the L level and the clock enable signal is in the disabled state (ETNR is "1"), states #1 and #2 are repeated. In this case, since the inverted clock CKB and LE, which are the outputs of the control unit 200, do not change, the toggle operation of the clock in the state holding unit 300 does not occur. Therefore, power consumption can be suppressed.

[0034] As a second case, when at least one of the enable signal E or the test signal TE is at the H level and the clock enable signal is in the enabled state (ETNR is "0"), states #3 and #7 are repeated. In this case, the waveform of the inverted clock CKB is the inverted clock signal CK, and a toggle operation occurs.

[0035] As a third case, when the clock signal CK is at the L level and at least one of the enable signal E or the test signal TE transitions from the L level to the H level, the clock signal CK propagates as the clock signal CKO. In this case, by transitioning from state #1 to state #7, a high-level value is held in the latch 330. Then, due to the change in the clock signal CK, a transition occurs between state #7 and state #3, and the clock signal CK propagates as the clock signal CKO. At this time, only the inverted clock CKB performs a toggle operation while the value held in the latch 330 and LE maintain the same value.

[0036] As a fourth case, when the clock signal CK is at the L level and at least one of the enable signal E or the test signal TE transitions from the H level to the L level and both become the L level, the clock signal CK is blocked. In this case, a transition occurs from state #7 to state #1. At this time, a low level is written to the latch 330.

[0037] As a fifth case, when at least one of the enable signal E or the test signal TE transitions from the L level to the H level with the clock signal CKO at the L level and the clock signal CK at the H level, the clock signal CK must not propagate to the clock signal CKO. That is, the clock signal CKO must not transition from the L level to the H level. Specifically, it is a transition from state #2 to state #4. At this time, first LE transitions from the L level to the H level, and then the internal clock CKB transitions from the H level to the L level. When propagating to the latch 330 in this order of change, the H level will be written to the latch 330, and the clock signal CKO will transition from the L level to the H level. In order to avoid this malfunction and prevent the H level from being written to the latch 330, it is necessary to insert a delay into the path on the LE side so that the transition of the internal clock CKB from the H level to the L level propagates to the latch 330 first, and then the transition of LE from the L level to the H level propagates. In this embodiment, the input buffer 320 serves this role. For example, by using a type of transistor with a high threshold voltage as the transistor constituting the input buffer 320, the timing of passing LE can be delayed. Thereby, the L level can be held in the latch 330 even in state #4, preventing malfunction.

[0038] As a sixth case, when the clock signal CKO and the clock signal CK are at the H level, and at least one of the enable signal E or the test signal TE transitions from the H level to the L level, and after both become the L level, if the clock signal CK transitions to the L level, first, when both change to the L level, the clock signal CKO must not transition from the H level to the L level. Specifically, it is a transition from state #3 to state #5. At this time, since neither LE nor the internal clock CKB changes, the latch 330 continues to hold the H level, and the clock signal CKO is not set to the L level. After that, when the clock signal CK transitions to the L level, it transitions from state #5 to state #1. At this time, first, the internal clock CKB transitions from the L level to the H level, and then LE transitions from the H level to the L level. If it reaches the latch 330 in this order, the correct operation of writing the L level to the latch 330 is performed.

[0039] As a seventh case, pay attention to the situation where the clock signal CKO is at the L level and the clock signal CK is at the H level, and at least one of the enable signal E or the test signal TE transitions from the L level to the H level, then transitions back to the L level, and then the clock signal CK transitions to the L level. Specifically, it is the case of transitioning from state #4 to state #6 and further transitioning to state #1. In this case, the output state as an RS latch does not change. When transitioning from state #6 to state #1, first, the internal clock CKB transitions from the L level to the H level, and then LE transitions from the H level to the L level. If it reaches the latch 330 in this order, the correct operation of writing the L level to the latch 330 is performed.

[0040] As an eighth case, pay attention to the situation where the clock signal CKO and the clock signal CK are at the L level, and at least one of the enable signal E or the test signal TE transitions from the L level to the H level and then transitions back to the L level. In this case, it goes back and forth between state #1 and state #7. At this time, the correct L level or H level is written to the latch 330. On the other hand, the internal clock CKB does not transition and remains at the H level, so no useless toggling operation occurs, and power consumption can be suppressed.

[0041] FIG. 5 is a diagram showing an example of input / output waveforms of the clock enable circuit 10 in the embodiment of the present technology.

[0042] In this example, it is assumed that the test signal TE is at the L level and the enable signal E changes. The enable signal E transitions between the L level and the H level asynchronously with the clock signal CK, but since the clock signal CKO changes in synchronization with the clock signal CK, it does not transition in a state midway between the L level or the H level. That is, if the enable signal E is at the H level at the rising timing of the clock signal CK, the clock signal CK is propagated as the clock signal CKO, and if the enable signal E is at the L level at the rising timing of the clock signal CK, the clock signal CKO becomes the L level.

[0043] As described above, according to the embodiment of the present technology, by grasping a state in which the toggling operation of the internal clock CKB is unnecessary in the state holding unit 300 and appropriately generating LE, the unnecessary toggling operation of the internal clock CKB can be stopped. Also, the influence due to the change in the enable signal E or the test signal TE when the clock signal CK is at the L level can be suppressed. Thereby, the power consumption in the clock enable circuit 10 can be suppressed.

[0044] <2. Modification Example> [First Modification Example] FIG. 6 is a diagram showing a first modification example of the clock enable circuit 10 in the embodiment of the present technology.

[0045] In this first modification example, instead of the input buffer 320 in the above-described embodiment, a transmission gate 340 is provided. This transmission gate 340 is controlled by the internal clock CKB and its inverted clock CKBB, and passes the input LE to the latch 330.

[0046] In the above-described embodiment, the timing of the transition from state #2 to state #4 was adjusted by adjusting the delay amount of the input buffer 320. However, in this first modification example, by controlling the timing at which LE passes through the transmission gate 340, the same effect can be obtained, and at the same time, the number of transistors can be reduced. For example, by using a transistor with a high threshold voltage as the transistor constituting the transmission gate 340, the timing at which LE passes through can be delayed.

[0047] [Second Modification Example] FIG. 7 is a diagram showing a second modification example of the clock enable circuit 10 in the embodiment of the present technology.

[0048] In this second modification example, the output of the inverter 230 instead of LE is connected as the input of the input buffer 320. This inverter 230 generates an inverted signal of the output ETNR of the negative logical sum gate 110.

[0049] [Third Modification Example] FIG. 8 is a diagram showing a third modification example of the clock enable circuit 10 in the embodiment of the present technology.

[0050] In this third modification example, an example is shown in which the number of stacked stages of the transistors 321 to 326 is changed in order to adjust the delay amount of the input buffer 320. The internal clock CKB is connected to the gate of the transistor 321, and the inverted clock CKBB is connected to the gate of the transistor 322. As a result, it has the function of an inverter. By stacking the transistors 323 and 324, and further the transistors 325 and 326 outside the transistors 321 and 322, the delay amount of the input buffer 320 can be increased.

[0051] [Fourth Modification Example] FIG. 9 is a diagram showing a fourth modification example of the clock enable circuit 10 in the embodiment of the present technology.

[0052] In this fourth modification example, the function of the clock enable signal generation unit 100 in the above-described embodiment is incorporated into the control unit 200. Along with this, the configuration as an RS latch circuit is realized by a circuit configuration different from the two NAND gates. That is, a three-input NOR gate 120 is provided, and in addition to the enable signal E and the test signal TE, the clock CKBB is input. Therefore, the inverted clock generation unit 310 in the above-described embodiment is incorporated into the control unit 200 as the inverted clock generation unit 240. Also, an inverter 230 is provided to generate LE from the output of the NOR gate 120.

[0053] This fourth modification example is logically equivalent to the above-described embodiment. Thus, in consideration of the layout in the integrated circuit, a logically transformed one may be appropriately adopted.

[0054] [Fifth Modification Example] FIG. 10 is a diagram showing a fifth modification example of the clock enable circuit 10 in the embodiment of the present technology.

[0055] In this fifth modification example, as the clock signal input to the NAND gate 410 of the clock signal output unit 400, instead of directly inputting the clock signal CK as in the above-described embodiment, the internally generated clock CKBB is input. Even in this case, the logic of the clock signal CKO does not change.

[0056] By separating the clock signal CK from the clock signal output unit 400 in this way, the fan-out number of the clock signal CK can be reduced by half, and the load capacitance of the clock signal CK can be reduced. Also, by increasing the locations where the operation can be stopped when the clock enable signal is in the disabled state, the power consumption due to the toggle operation of the clock can be reduced.

[0057] [Sixth Modification Example] FIG. 11 is a diagram showing a sixth modification of the clock enable circuit 10 in the embodiment of the present technology.

[0058] In this sixth modification, a reception circuit 250 is provided instead of the negative AND gate 210 in the above-described embodiment. This reception circuit 250 generates the logical product CKBB and the negative logical product CKB of the clock signal CK and LE. That is, in terms of generating the negative logical product CKB, the logic is equivalent to the negative AND gate 210 in the above-described embodiment. Also, in terms of generating CKBB, the logic is equivalent if up to the inverted clock generation unit 310 in the above-described embodiment is included.

[0059] Also, in this sixth modification, similar to the above-described fifth modification, the internally generated clock CKBB is input to the clock signal output unit 400. Therefore, the clock signal CK can be separated from the clock signal output unit 400 to reduce the load capacitance of the clock signal CK.

[0060] The reception circuit 250 may implement a level shift circuit that shifts the level from small swing to full swing. At this time, this level shift circuit is configured to operate only when LE is at the H level and not to operate when LE is at the L level. Thereby, even a level shift circuit that normally incurs an operating cost can be made into a circuit that stops and does not consume unnecessary power when the enable signal E or the test signal TE is in the disabled state.

[0061] FIG. 12 is a diagram showing an example of the reception circuit 250 in the sixth modification of the clock enable circuit 10 in the embodiment of the present technology.

[0062] The receiving circuit 250 in the figure is an example when a level shift circuit is implemented. This receiving circuit 250 includes transistors 251 to 257 and an inverter 258. Among them, transistors 251 to 253 are standard threshold voltage (SVT) transistors, and transistors 254 to 257 are low threshold voltage (LVT) transistors. Thereby, the threshold value on the high level side of the clock signal CK can be lowered to correspond to a small amplitude signal.

[0063] In this example of the receiving circuit 250, an example where the clock signal CK is a small amplitude signal is shown. However, in addition to this, for example, when other low power technologies such as the clock signal CK being a differential small amplitude signal are implemented, the receiving circuit 250 can similarly handle them. That is, by receiving the clock signal CK in the receiving circuit 250 in a batch and then distributing it in the circuit, processes such as level conversion can be grouped together in one place.

[0064] Note that the above-described embodiments show an example for embodying the present technology, and there is a corresponding relationship between the matters in the embodiments and the matters specifying the invention in the claims. Similarly, there is a corresponding relationship between the matters specifying the invention in the claims and the matters in the embodiments of the present technology with the same name. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist thereof.

[0065] Note that the effects described in this specification are merely examples and are not limiting, and there may be other effects.

[0066] Note that the present technology can also have the following configuration. (1) A state holding unit that performs a state holding operation of whether to output an output clock signal according to an internal clock signal, A clock signal output unit that controls the output of the output clock signal according to the state held by the state holding unit; A control unit that supplies the internal clock signal and the value of the state required for the holding operation to the state holding unit based on an external clock signal and a clock enable signal; A clock inabler circuit comprising: (2) When the clock enable signal indicates an enabled state, the control unit operates the internal clock signal, and when the clock enable signal does not indicate an enabled state, the control unit stops the internal clock signal. The clock inabler circuit according to (1) above. (3) When the clock enable signal indicates an enabled state, the control unit supplies, as the value of the state, a state in which the output clock signal is output, and when the clock enable signal does not indicate an enabled state, the control unit supplies, as the value of the state, a state in which the output clock signal is not output. The clock inabler circuit according to (1) or (2) above. (4) The state holding unit includes a delay unit that delays the timing of holding the value of the state. The clock inabler circuit according to any one of (1) to (3) above. (5) The delay unit is a clock inverter that operates according to the internal clock signal. The clock inabler circuit according to (4) above. (6) The delay unit is a transmission gate that operates according to the internal clock signal. The clock inabler circuit according to (4) above. (7) The clock signal output unit generates the output clock signal based on the external clock signal. The clock inabler circuit according to any one of (1) to (6) above. (8) The clock signal output unit generates the output clock signal based on the internal clock signal. The clock inabler circuit according to any one of (1) to (6) above. (9) The control unit includes a receiving circuit that receives a clock signal from the outside. The clock enable circuit according to any one of (1) to (8) above. (10) The receiving circuit is a small-amplitude signal receiving circuit. The clock enable circuit according to (9) above. (11) The receiving circuit is a differential small-amplitude signal receiving circuit. The clock enable circuit according to (9) above.

Explanation of symbols

[0067] 10 Clock enable circuit 20 Flip-flop circuit 30 Combinational circuit 100 Clock enable signal generation unit 110, 120 NOR gates 200 Control unit 210, 220 NAND gates 230 Inverter 240 Inverted clock generation unit 250 Receiving circuit 251 to 257 Transistors 258 Inverter 300 State holding unit 310 Inverted clock generation unit 320 Input buffer 321 to 326 Transistors 330 Latch 331 Inverter 332 Clocked inverter 340 Transmission gate 400 Clock signal output unit 410 NAND gate 420 Inverter

Claims

1. A state holding unit that performs a holding operation of an output state of whether to output an output clock signal according to an internal clock signal, A clock signal output unit that controls the output of the output clock signal according to the output state held by the state holding unit, A control unit that supplies the internal clock signal and the value of the output state required for the holding operation to the state holding unit based on an external reference clock signal and an external clock enable signal comprising: When the clock enable signal indicates an enabled state, the control unit supplies an output enabled state as the value of the output state and supplies a signal linked to the reference clock signal as the internal clock signal. When the clock enable signal indicates a disabled state, the control unit supplies an output disabled state as the value of the output state and supplies a fixed signal as the internal clock signal A clock enable circuit.

2. The control unit is constituted by an RS latch circuit that is set by the clock enable signal and reset by the reference clock signal The clock enable circuit according to Claim 1.

3. The signal linked to the reference clock signal is an inverted signal of the reference clock signal The clock enable circuit according to Claim 1.

4. The clock signal output unit generates the output clock signal based on the reference clock signal The clock enable circuit according to Claim 1.

5. The clock signal output unit generates the output clock signal based on the internal clock signal The clock enable circuit according to Claim 1.

6. The control unit includes a receiving circuit that receives the reference clock signal The clock enable circuit according to Claim 1.

7. The receiving circuit is a small amplitude signal receiving circuit The clock enable circuit according to Claim 6.

8. The receiving circuit is a differential small amplitude signal receiving circuit The clock enable circuit according to Claim 6.

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