Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, a semiconductor device with high reliability, and a semiconductor device consuming less power.SOLUTION: A semiconductor device includes a gate electrode, a first insulating layer on the gate electrode, a metal oxide layer on the first insulating layer, a pair of electrodes on the metal oxide layer, and a second insulating layer on the pair of electrodes. The first insulating layer includes a first region and a second region. The first region is in contact with the metal oxide layer and includes a region containing more oxygen than the second region. The second region includes a region containing more nitrogen than the first region. The metal oxide layer has at least an oxygen concentration gradient in a film thickness direction, and the oxygen concentration is high on the first region side and the second insulating layer side.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. TECHNICAL FIELD One embodiment of the present invention relates to a display device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices The vessel may include a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, etc. Examples of the present invention include a memory device, a driving method thereof, or a manufacturing method thereof. can. [Background technology]

[0004] Oxide semiconductors have been attracting attention as semiconductor materials that can be used for transistors. In Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, The oxide semiconductor layer serving as a channel contains indium and gallium, and the ratio of indium By making μF larger than the percentage of gallium, the field effect mobility (simply called mobility, or μFE A semiconductor device is disclosed in which the resistance (which may be called "resistance") is improved.

[0005] An oxide semiconductor that can be used for the semiconductor layer can be formed by a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. It is possible to improve and utilize a part of the production equipment of a transistor using amorphous silicon, so that equipment investment can be suppressed. In addition, since a transistor using an oxide semiconductor has a high field-effect mobility, a high-function display device with an integrated drive circuit can be realized. Moreover, since the transistor using an oxide semiconductor has a high field-effect mobility, a high-function display device with an integrated drive circuit can be realized. Moreover, since the transistor using an oxide semiconductor has a high field-effect mobility, a high-function display device with an integrated drive circuit can be realized.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] With the increasing high definition of display devices or high integration of semiconductor devices, miniaturization of transistors is required. Specifically, as miniaturization of transistors, shortening the channel length can be cited. However, in a transistor with a short channel length, the carrier density and defect levels in the channel region significantly affect the electrical characteristics and reliability. With the increasing high definition of display devices or high integration of semiconductor devices, miniaturization of transistors is required. Specifically, as miniaturization of transistors, shortening the channel length can be cited. However, in a transistor with a short channel length, the carrier density and defect levels in the channel region significantly affect the electrical characteristics and reliability. With the increasing high definition of display devices or high integration of semiconductor devices, miniaturization of transistors is required. Specifically, as miniaturization of transistors, shortening the channel length can be cited. However, in a transistor with a short channel length, the carrier density and defect levels in the channel region significantly affect the electrical characteristics and reliability. With the increasing high definition of display devices or high integration of semiconductor devices, miniaturization of transistors is required. Specifically, as miniaturization of transistors, shortening the channel length can be cited. However, in a transistor with a short channel length, the carrier density and defect levels in the channel region significantly affect the electrical characteristics and reliability.

[0008] In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems. In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems. In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems. In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems. In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems. In view of the above, one aspect of the present invention is to provide a semiconductor device with good electrical characteristics as one of the problems. Or, to provide a highly reliable semiconductor device as one of the problems. Or, to provide a semiconductor device with low power consumption as one of the problems. Or, to provide a novel semiconductor device as one of the problems. Or, to provide a method for manufacturing a highly productive semiconductor device as one of the problems. Or, to provide a method for manufacturing a semiconductor device with a high yield as one of the problems. Or, to provide a novel method for manufacturing a semiconductor device as one of the problems.

[0009] ​​ Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention includes a gate electrode, a first insulating layer on the gate electrode, and on the first insulating layer a metal oxide layer, a pair of electrodes on the metal oxide layer, and a second insulating layer on the pair of electrodes, and the metal oxide layer contains indium, an element M (where M is one or more of gallium, aluminum, silicon , boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium , tantalum, tungsten, or magnesium), and zinc. The first insulating layer has a first region and a second region. The first region is in contact with the metal oxide layer and has a region with a higher oxygen content than the second region. The second region has a region with a higher nitrogen content than the first region. The metal oxide layer has at least an oxygen concentration gradient in the film thickness direction, and the concentration gradient is higher on the first region side and the second insulating layer side, and is a semiconductor device therein.

[0011] In the semiconductor device described above, it is preferable that the first region has a region of 1 nm or more and 10 nm or less in the film thickness direction.

[0012] In the semiconductor device described above, when the atomic ratio of In is 1, the atomic ratio of M is 0.5 or more and 1.5 or less, and the atomic ratio of Zn is 0.1 or more and 2 or less, which is preferable Yes.

[0013] In the semiconductor device described above, when the atomic ratio of In is 4, the atomic number of M is preferably in the range of 1.5 or more and 2.5 or less, and the atomic ratio of Zn is preferably in the range of 2 or more and 4 or less. .

[0014] In the semiconductor device described above, when the atomic ratio of In is 5, the atomic number of M is preferably in the range of 0.5 or more and 1.5 or less, and the atomic ratio of Zn is preferably in the range of 5 or more and 7 or less. .

[0015] In the semiconductor device described above, the metal oxide layer has a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, and the first metal oxide layer preferably has a region with lower crystallinity than the second metal oxide layer. On the first metal oxide layer, there is a second metal oxide layer, and on the lower side of the first metal oxide layer, there is a third metal oxide layer. The first metal oxide layer preferably has a region with lower crystallinity than either one or both of the second metal oxide layer and the third metal oxide layer. .

[0016] In the semiconductor device described above, on the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains silicon and nitrogen. On the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains one or more of elements X (X is aluminum, indium, gallium, or zinc) and oxygen. On the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains one or more of elements X (X is aluminum, indium, gallium, or zinc) and oxygen. .

[0017] In the semiconductor device described above, on the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains silicon and nitrogen. On the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains one or more of elements X (X is aluminum, indium, gallium, or zinc) and oxygen.

[0018] In the semiconductor device described above, on the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains one or more of elements X (X is aluminum, indium, gallium, or zinc) and oxygen. On the second insulating layer, there is further a third insulating layer, and the third insulating layer preferably contains one or more of elements X (X is aluminum, indium, gallium, or zinc) and oxygen. .

[0019] One aspect of the present invention includes a step of forming a gate electrode, a step of forming a first insulating layer on the gate electrode, a step of adding oxygen near the surface of the first insulating layer, a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. a step of forming, a step of adding oxygen near the surface of the first insulating layer, a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. a step of forming a second insulating layer on the pair of electrodes. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in two steps, the first step is performed before the second step, and the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device.

[0020] One aspect of the present invention includes a step of forming a gate electrode, a step of forming a first insulating layer on the gate electrode, a step of adding oxygen near the surface of the first insulating layer, a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. a step of forming a first insulating layer on the gate electrode, a step of adding oxygen near the surface of the first insulating layer, a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. a step of adding oxygen near the surface of the first insulating layer, a step of forming a metal oxide layer on the first insulating layer, a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. a step of forming a pair of electrodes on the metal oxide layer, and a step of forming a second insulating layer on the pair of electrodes. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in three steps, the first step is performed before the second step, the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step, the third step is performed before the first step, and the third step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. In the step of forming the metal oxide layer, the metal oxide layer is continuously formed in a vacuum in three steps, the first step is performed before the second step, the second step has a higher oxygen flow rate ratio in the total film-forming gas than the first step, the third step is performed before the first step, and the third step has a higher oxygen flow rate ratio in the total film-forming gas than the first step. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device. This is a method for manufacturing a semiconductor device.

Advantages of the Invention

[0021] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, a semiconductor device with high reliability can be provided. Or, a semiconductor device with low power consumption can be provided. Also a semiconductor device with low power consumption can be provided. Also It is possible to provide a novel semiconductor device. Or, it is possible to provide a method for manufacturing a highly productive semiconductor device. Or, it is possible to provide a method for manufacturing a semiconductor device with a high yield. Or, it is possible to provide a method for manufacturing a novel semiconductor device. It is possible. Also, it is possible to provide a method for manufacturing a semiconductor device with a high yield. Or, it is possible to provide a method for manufacturing a novel semiconductor device. It is possible.

[0022] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0023]

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Mode for Carrying Out the Invention

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, there are many embodiments It can be implemented in different modes, and it is easily understood by those skilled in the art that the form, state, and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0025] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematically shown ideal examples and are not limited to the shapes or values shown in the drawings.

[0026] In addition, the ordinal numbers "first", "second", "third", etc. used in this specification are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0027] In this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0028] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel region. In this specification and the like, the channel region refers to the region through which current mainly flows. ​​​​​​​​​​​​

[0029] In addition, the functions of the source and drain may be interchanged when transistors of different polarities are employed, or when the direction of the current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0030] In this specification and the like, "electrically connected" includes cases where connection is made through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0031] In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included.

[0032] In this specification and the like, the term "film" and the term "layer" are interchangeable. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0033] Also, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is off (also referred to as a non-conducting state or a cut-off state). The off-state , unless otherwise specified, for an n-channel transistor, is a state where the voltage V gs between the gate and the source is lower than the threshold voltage Vth, and for a p-channel transistor, is a state where the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vt h.

[0034] The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less. The off-current of a transistor may refer to the off-current in the off-state at a predetermined Vgs, in the off-state within a predetermined range of Vgs, or in the off-state at a Vgs where a sufficiently reduced off-current is obtained, etc.

[0035] As an example, assume an n-channel transistor where the threshold voltage Vth is 0.5V, the drain current at Vgs = 0.5V is 1×10 A, the drain current at Vgs = 0.1V is 1×10 -9 A, the drain current at Vgs = -0.5V is 1×10 -1 3 A, and the drain current at Vgs = -0.8V is 1×10 -19 A. The drain current of the said transistor is at Vgs = -0.5V -22 A. ​​​​​​​Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 A or less Therefore, it may be said that the off-current of the transistor is 1×10 -19 A or less. There exists a Vgs such that the drain current of the transistor becomes 1×10 A or less -22 Therefore, it may be said that the off-current of the transistor is 1×10 A or less. -22

[0036] Also, in this specification and the like, the off-current of a transistor having a channel width W may be represented by the current value flowing per channel width W. Also, it may be represented by the current value flowing through a predetermined channel width (for example, 1μm). In the latter case, the unit of the off-current may be represented by a unit having a unit of current / length (for example, A / μm).

[0037] The off-current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-current may represent the off-current at room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which a semiconductor device including the transistor is used (for example any one temperature from 5°C to 35°C), may represent the off-current. That the off-current of a transistor is I or less means that there exists a value of Vgs such that the off-current of the transistor becomes I or less at room temperature, 60°C, 85°C, 95°C, 125°C the temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which a semiconductor device including the transistor is used (for example any one temperature from 5°C to 35°C).

[0038] The off-current of a transistor may depend on the voltage Vds between the drain and the source. . In this specification, unless otherwise specified, the off-current refers to the off-current at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, it may represent the off-current at Vds that guarantees the reliability of a semiconductor device or the like containing the transistor, or the off-current at Vds used in a semiconductor device or the like containing the transistor. When it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs such that the off-current of the transistor at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds that guarantees the reliability of the semiconductor device containing the transistor, or Vds used in a semiconductor device or the like containing the transistor, is I or less. In the description of the off-current above, the drain and the source may be read interchangeably. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In this specification and the like, the off-current may be described as the leakage current in the same sense. Also, in this specification and the like, the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state. In this specification and the like, the threshold voltage of a transistor refers to the voltage at which a channel is formed in the transistor. In the description of the off-current above, the drain and the source may be read interchangeably. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In the description of the off-current above, the drain and the source may be read interchangeably. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. In the description of the off-current above, the drain and the source may be read interchangeably. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

[0039] In the description of the off-current above, the drain and the source may be read interchangeably. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

[0040] Also, in this specification and the like, the off-current may be described as the leakage current in the same sense. Also, in this specification and the like, the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state. Also, in this specification and the like, the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state. That is, the off-current may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0041] Also, in this specification and the like, the threshold voltage of a transistor refers to the voltage at which a channel is formed in the transistor. Refers to the gate voltage (Vg) when the loop is formed. Specifically, the threshold voltage of the transistor The voltage means that with the gate voltage (Vg) on the horizontal axis and the square root of the drain current (Id) on the vertical axis, a plot In the curve (Vg-√Id characteristic), the gate voltage (Vg ) at the intersection with the straight line obtained by extrapolating the tangent line with the maximum slope and the square root of the drain current (Id) being 0 (Id = 0 A) may be pointed to. Alternatively, the threshold voltage of the transistor may refer to the gate voltage (Vg) when, with the channel length being L and the channel width being W, the value of Id [A] × L [μm] / W [μm] becomes 1×10 ) [A]. -9 Refers to the gate voltage (Vg) when it becomes

[0042] Also, in this specification and the like, even when it is described as "semiconductor", for example, when the conductivity is Sufficiently low, it may have the characteristics of an "insulator". Also, the boundary between "semiconductor" and " Insulator" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification Etc. and the "insulator" may be interchangeable with each other in some cases.

[0043] Also, in this specification and the like, even when it is described as "semiconductor", for example, when the conductivity is Sufficiently high, it may have the characteristics of a "conductor". Also, the boundary between "semiconductor" and " Conductor" is ambiguous and may not be strictly distinguishable. Therefore, the "semiconductor" described in this specification Etc. and the "conductor" may be interchangeable with each other in some cases.

[0044] In this specification and the like, metal oxide refers to the oxide of a metal in a broad sense Of. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors ) Oxide semiconductor (also simply referred to as OS) It is classified into etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplification function, a rectification function , and a switching function, the metal oxide is called a metal oxide semiconductor, abbreviated as OS and can be called so. Also, when described as an OS FET, it can be paraphrased as a transistor having a metal oxide or an oxide semi conductor.

[0045] In this specification etc., a metal oxide having nitrogen may also be generically referred to as a metal oxide (metal ox ide). Also, a metal oxide having nitrogen may be referred to as a metal oxynitride (me tal oxynitride).

[0046] In this specification etc., there are cases where CAAC (c-axis aligned crysta l), and CAC (Cloud-Aligned Composite) are described . Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration .

[0047] In this specification etc., CAC-OS or CAC-metal oxide means that it has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole of the material. Note that when CAC-OS or CAC-metal oxi de is used for the active layer of a transistor, the conductive function is the electrons that become carriers (ma or the function of flowing through a hole), and the insulating function is the function of not allowing electrons serving as carriers to flow. There is. By causing the conductive function and the insulating function to act complementarily, respectively, the function of switching (the function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxi de, by separating the respective functions, both functions can be enhanced to the maximum extent. It can be done.

[0048] Also, in this specification, etc., CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be connected in a blurred cloud-like shape around the periphery.

[0049] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 n m or less, respectively.

[0050] Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps . For example, CAC-OS or CAC-metal ox ide is composed of a component having a wide bandgap due to the insulating region and a component having a narrow bandgap due to the conductive region. In the case of such a configuration, when carriers flow In a component having a narrow gap, carriers mainly flow. Also, the component having a narrow gap acts complementarily to the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when using CAC-OS or CAC-metal oxide in the channel region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor. That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite material, or a metal matrix composite material.

[0051] An example of the crystal structure of a metal oxide will be described. Hereinafter, a metal oxide formed by a sputtering ring method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be described as an example. Using the aforementioned target, with the substrate temperature being 100°C or higher and 130°C or lower, the metal oxide formed by the sputtering method is referred to as sIGZO, and using the aforementioned target, with the substrate temperature being room temperature (R.T.), the metal oxide formed by the sputtering method

[0052] is referred to as tIGZO. For example, sIGZO has a crystal structure of either or both of nc (nano crystal) and CAAC. Also, tIGZO has a crystal structure of nc. Here, the room temperature ( R.T.) includes the temperature when the substrate is not intentionally heated. The CAAC structure is , a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation in the a-b plane is.

[0053] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting ing) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0054] Also, in this specification and the like, a display panel substrate with a connector such as an FPC (Flexible Pr inted Circuit) or a TCP (Tape Carrier Packa ge) attached, or a substrate with an IC mounted by a COG (Chip On Glass) method or the like may be referred to as a display panel module, a display module , or simply a display panel.

[0055] Also, in this specification and the like, a touch sensor has a function of detecting when a detected object such as a finger or a stylus touches, presses, or approaches. It may also have a function of detecting the position information . Therefore, the touch sensor is one aspect of an input device . For example, the touch sensor can be configured to have one or more sensor elements.

[0056] Also, in this specification and the like, a substrate having a touch sensor may be referred to as a touch sensor panel or simply a touch sensor. Also, in this specification and the like, a substrate of a touch sensor panel with a connector such as an FPC or a TCP attached, or a substrate with an IC mounted by a COG method or the like may be referred to as a touch sensor panel module, a touch sensor module, a sensor module, or simply a touch sensor. is.

[0057] In the present specification and the like, a touch panel, which is an aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface, and a function as a touch sensor that detects, presses, or approaches a detection object such as a finger or a stylus on the display surface. Therefore, the touch panel is an aspect of an input / output device. The touch panel can also be called, for example, a display panel (or display device) with a touch sensor, or a display panel (or display device) with a touch sensing function.

[0058] The touch panel can be configured to include a display panel and a touch sensor panel. Or, it can be configured to have a function as a touch sensor inside or on the surface of the display panel.

[0059]

[0060] Also, in the present specification and the like, when a touch panel substrate has a connector such as an FPC or a TCP attached to it, or when an IC is mounted on the substrate by a COG method or the like, it is called a touch panel module, a display module, or simply a touch panel.

[0061] (Embodiment 1) In this embodiment, an aspect of the semiconductor device of the present invention and a method for manufacturing the same will be described. Here, a transistor, which is an aspect of the semiconductor device, will be described.

[0062] A transistor according to an aspect of the present invention includes a first conductive layer having a function as a gate electrode, a first insulating layer having a function as a gate insulating layer, a semiconductor layer, and a source electrode and a drain electrode, respectively. ​​​​​​​​​​a second conductive layer and a third conductive layer having a function as a drain electrode, and a second insulating layer and a third insulating layer having a function as a protective layer.

[0063] The semiconductor layer is preferably a metal oxide film. In particular, indium and element M (M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium , beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lan thanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium ), and zinc is preferably used. In particular, element M is preferably aluminum, gallium, ytt rium or tin.

[0064] By using a metal oxide film with a low impurity concentration and a low defect level density as the semiconductor layer , a transistor having excellent electrical characteristics can be manufactured, which is preferable. Here, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. . Since the semiconductor layer having high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources , the carrier density can be lowered. Therefore, in the transistor in which the channel region is formed in the semiconductor layer , the electrical characteristics in which the threshold voltage becomes negative (also referred to as normally on. ) are suppressed. Further, since the semiconductor layer having high-purity intrinsic or substantially high-purity intrinsic has a low defect level density, the trap level density may also be low. In addition, the semiconductor layer having high-purity true ness or substantially high-purity intrinsic has extremely low off-current.

[0065] The carrier density and defect level in the channel region of the transistor affect the electrical characteristics of the transistor and affects reliability. In particular, in a transistor with a short channel length, the carrier density and defect levels in the channel region significantly affect the electrical characteristics and reliability. Therefore, by reducing the carrier density and defect levels in the channel region, good electrical characteristics and reliability can be obtained even in a transistor with a short channel length.

[0066] Oxygen may desorb from the metal oxide film of the semiconductor layer, and oxygen vacancies (hereinafter sometimes referred to as Vo) may be formed. When a large number of oxygen vacancies exist in the semiconductor layer, the defect level density in the semiconductor layer increases, etc., and in some cases, it may have an adverse effect on the electrical characteristics and reliability of the transistor. Therefore, in the transistor manufacturing process, by introducing a sufficient amount of oxygen into the semiconductor layer and reducing oxygen vacancies, a transistor with good electrical characteristics and high reliability can be manufactured. Also, along with the reduction of oxygen vacancies, it is important to suppress the generation of oxygen vacancies in the transistor manufacturing process.

[0067] When oxygen vacancies and hydrogen exist in the semiconductor layer, a state in which hydrogen enters the oxygen vacancies (hereinafter sometimes referred to as VoH) may be formed. VoH serves as a carrier generation source and may have an adverse effect on the electrical characteristics and reliability of the transistor. Therefore, by reducing hydrogen and VoH in the semiconductor layer, the carrier density can be reduced, and a transistor with good electrical characteristics and high reliability can be manufactured. Also, along with the reduction of hydrogen and VoH, it is important to suppress the diffusion of impurities containing hydrogen into the semiconductor layer from the outside. Examples of impurities containing hydrogen include hydrogen, water, etc.

[0068] As one method for reducing oxygen vacancies in a semiconductor layer, a layer capable of releasing oxygen by heating is placed near the semiconductor layer and heat-treated to supply oxygen from the layer to the semiconductor layer can be used.

[0069] The second insulating layer having a function as a protective layer is in contact with the upper surface of the semiconductor layer. The second insulating layer preferably contains oxygen. The second insulating layer is more preferably an insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. For example, it is preferable to use an insulating film containing silicon and oxygen, or an insulating film containing silicon, oxygen, and nitrogen.

[0070] In this specification and the like, oxygen contained in excess of the stoichiometric composition may be referred to as excess oxygen (exO). Alternatively, excess oxygen refers to, for example, oxygen released from a film or layer containing oxygen when heated. Excess oxygen can move inside a film or layer, for example. The movement of excess oxygen may be a case of moving between atoms of a film or layer, or a case of moving in a jumping manner while replacing oxygen constituting the film or layer. Also, in this specification and the like, excess oxygen (exO) may sometimes be simply referred to as oxygen.

[0071] By performing heat treatment after providing a second insulating film on the semiconductor layer, oxygen diffuses from the second insulating layer to the semiconductor layer, and oxygen is supplied to the semiconductor layer. When the oxygen supplied to the semiconductor layer approaches the oxygen vacancies in the semiconductor layer, the oxygen is trapped by the oxygen vacancies, and the oxygen vacancies are filled. Also, when oxygen approaches the hydrogen in the semiconductor layer, oxygen and hydrogen react to form water (H 2 O ) and desorbs from the semiconductor layer as water molecules. Also, when oxygen approaches VoH in the semiconductor layer ​​​​​​​​​When approaching, oxygen fills the oxygen deficiency of VoH. Also, the hydrogen that VoH had reacts with other oxygen to form water and desorbs as water from the semiconductor layer. In this way, the oxygen in the second insulating layer can reduce the oxygen deficiency, hydrogen, and VoH in the semiconductor layer. The third insulating layer having a function as a protective layer is in contact with the upper surface of the second insulating layer. It is preferable to use a material with a higher nitrogen concentration for the third insulating layer than for the second insulating layer. For example, it is preferable to have an insulating film mainly composed of silicon and nitrogen. The insulating film mainly composed of silicon and nitrogen has the characteristic that water, hydrogen, oxygen, etc. are difficult to diffuse. Therefore, by providing the third insulating layer on the second insulating layer, the diffusion (desorption) of oxygen from the semiconductor layer and the second insulating layer to the outside can be suppressed. Accordingly, an increase in the oxygen deficiency in the semiconductor layer can be suppressed. For the third insulating layer, for example, an oxide having one or more of elements X (X is aluminum, indium, gallium, or zinc) can be used. In particular, it is preferable to use an insulating film mainly composed of a metal and oxygen. For example, aluminum oxide or In-Ga-Zn oxide can be used as the third insulating layer. Also, there may be a case where voids are generated in the aforementioned second insulating layer. When voids exist, impurities such as water and hydrogen may diffuse from the outside to the semiconductor layer through the voids, and the hydrogen in the semiconductor layer may increase. By providing the third insulating layer on the second insulating layer to cover the voids, the diffusion of impurities from the outside to the semiconductor layer through the voids can be suppressed, and an increase in the hydrogen in the semiconductor layer can be suppressed.

[0072] The third insulating layer having a function as a protective layer is in contact with the upper surface of the second insulating layer. It is preferable to use a material with a higher nitrogen concentration for the third insulating layer than for the second insulating layer. For example, it is preferable to have an insulating film mainly composed of silicon and nitrogen. The insulating film mainly composed of silicon and nitrogen has the characteristic that water, hydrogen, oxygen, etc. are difficult to diffuse. Therefore, by providing the third insulating layer on the second insulating layer, the diffusion (desorption) of oxygen from the semiconductor layer and the second insulating layer to the outside can be suppressed. Accordingly, an increase in the oxygen deficiency in the semiconductor layer can be suppressed.

[0073] For the third insulating layer, for example, an oxide having one or more of elements X (X is aluminum, indium, gallium, or zinc) can be used. In particular, it is preferable to use an insulating film mainly composed of a metal and oxygen. For example, aluminum oxide or In-Ga-Zn oxide can be used as the third insulating layer.

[0074] Also, there may be a case where voids are generated in the aforementioned second insulating layer. When voids exist, impurities such as water and hydrogen may diffuse from the outside to the semiconductor layer through the voids, and the hydrogen in the semiconductor layer may increase. By providing the third insulating layer on the second insulating layer to cover the voids, the diffusion of impurities from the outside to the semiconductor layer through the voids can be suppressed. Accordingly, an increase in the hydrogen in the semiconductor layer can be suppressed. ​​​​

[0075] By providing a third insulating layer on the second insulating layer, oxygen vacancies, hydrogen, and Vo in the semiconductor layer H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated.

[0076] Hereinafter, a more specific example of one aspect of the present invention will be described with reference to the drawings. Hereinafter as an example of a semiconductor device, a transistor will be taken as an example for explanation.

[0077] <Configuration Example 1> A top view of a transistor 100A which is a semiconductor device according to one aspect of the present invention is shown in Fig. 1(A), and a cross-sectional view is shown in Figs. 1(B) and 1(C). Fig. 1(B) corresponds to a cross-sectional view of a cut-away view along the dashed-dotted line X1- X2 shown in Fig. 1(A), and Fig. 1(C) corresponds to a cross-sectional view of a cut-away view along the dashed-dotted line Y1- Y2 shown in Fig. 1(A). In Fig. 1(A), in order to avoid complexity, a part of the components of the transistor 100A (such as the gate insulating layer, etc.) is omitted in the illustration and shown. Also, the direction of the dashed-dotted line X1-X2 is sometimes referred to as the channel length direction, and the direction of the dashed-dotted line Y1-Y2 is sometimes referred to as the channel width direction. Also, in the top view of the transistor, in the following drawings as in Fig. 1(A), a part of the components may be omitted in the illustration.

[0078] The transistor 100A includes a conductive layer 104 on a substrate 102, an insulating layer 106 on the substrate 102 and the conductive layer 10 4, a metal oxide layer 108 on the insulating layer 106, and a conductive layer 112a and a conductive layer 1 which are in contact with the upper surface of the metal oxide layer 108 and are provided with a space therebetween on the metal oxide layer 108 112b. Also, on the conductive layer 112a, the conductive layer 112b, and the metal oxide layer 108 ​​It has an insulating layer 114 and an insulating layer 116 on the insulating layer 114.

[0079] A part of the conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer layer. The conductive layer 112a functions as one of the source electrode and the drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. The insulating layers 114 and the insulating layer 116 each function as a protective layer.

[0080] The transistor 100A is a so-called channel etch type, single gate structure transistor.

[0081] As shown in FIGS. 1(A), 1(B) and 1(C), the metal oxide layer 108 preferably has a laminated structure of a first metal oxide layer 108a and a second metal oxide layer 108b on the first metal oxide layer 108a.

[0082] The first metal oxide layer 108a and the second metal oxide layer 108b preferably each contain a metal oxide. The above-described materials can be used for the first metal oxide layer 108a and the second metal oxide layer 108b, respectively.

[0083] When the first metal oxide layer 108a and the second metal oxide layer 108b each have a region where the atomic ratio of In is larger than the atomic ratio of M, the field effect mobility of the transistor can be increased, which is preferable. As an example, it is preferable that the atomic ratio of In, M, and Zn in the first metal oxide layer 108a and the second metal oxide layer 108b is In:M:Zn = 4:2:3 or in the vicinity thereof, or In:M:Zn = 5:1:7 or in the vicinity thereof. ​​​​​. Here, the vicinity means that when In is 4, M is 1.5 or more and 2.5 or less, and Zn is 2 or more and 4 or less, and when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less. By making the first metal oxide layer 108a and the second metal oxide layer 108b have substantially the same composition, they can be formed using the same sputtering target, so the manufacturing cost can be suppressed.

[0084] Also, the first metal oxide layer 108a and the second metal oxide layer 108b can use the ratio of the number of atoms of In, M, and Zn to be In:M:Zn = 1:1:1 or in the vicinity thereof, respectively. Here, the vicinity means that when In is 1, M is 0.5 or more and 1.5 or less, and Zn is 0.1 or more and 2 or less. By making the ratio of the number of atoms of In and M substantially the same, the occurrence of oxygen deficiency in the first metal oxide layer 108a and the second metal oxide layer 108b can be suppressed, which is preferable. Since the occurrence of oxygen deficiency can be suppressed, transistors with good electrical characteristics and high reliability can be fabricated.

[0085] The first metal oxide layer 108a and the second metal oxide layer 108b may each use a film formed using a target with a different composition, but it is particularly preferable to use a laminated film formed continuously using a target with the same composition without exposure to the atmosphere. By forming the film continuously, processing can be performed with one film-forming apparatus, and the remaining impurities between the first metal oxide layer 108a and the second metal oxide layer 108b can be suppressed. Since the impurities in the metal oxide layer can be a carrier source, by suppressing the increase in impurities, transistors with good electrical characteristics and high reliability can be fabricated.

[0086] ​​​​​ The second metal oxide layer 108b preferably has a region with higher crystallinity than the first metal oxide layer 108a. Since the second metal oxide layer 108b has a region with high crystallinity, it can be made into a film with better etching resistance than the first metal oxide layer 108a. Therefore, when forming the conductive layer 112a and the conductive layer 112b, it is possible to prevent the second metal oxide layer 108b from disappearing due to etching. Thus, a transistor with a channel etch structure as shown in FIGS. 1(A), 1(B), and 1(C) can be realized. Furthermore, by using a film with high crystallinity for the second metal oxide layer 108b located on the back channel side of the transistor, impurities that can diffuse into the first metal oxide layer 108a on the conductive layer 104 side can be reduced, so that a transistor with good electrical characteristics and high reliability can be fabricated.

[0087] Also, by using a film containing a region with lower crystallinity than the second metal oxide layer 108b for the first metal oxide layer 108a, oxygen can easily diffuse into the first metal oxide layer 108a, and the ratio of oxygen vacancies in the first metal oxide layer 108a can be lowered. In particular, the first metal oxide layer 108a is located closer to the conductive layer 104 and is mainly a layer where a channel is easily formed. Therefore, by using a film with few oxygen vacancies for the first metal oxide layer 108a, a transistor with good electrical characteristics and high reliability can be fabricated.

[0088] The first metal oxide layer 108a and the second metal oxide layer 108b can be separately formed, for example, by varying the film formation conditions. For example, the first metal oxide layer 108a and the second The flow rate of oxygen gas in the film-forming gas can be varied with the metal oxide layer 108b.

[0089] At this time, as the film-forming conditions of the first metal oxide layer 108a, the ratio of the oxygen gas flow rate in the total gas flow rate (also referred to as the oxygen flow rate ratio or oxygen partial pressure) is 0% or more and 30% or less, preferably 5% or more and 15% or less. By setting the oxygen flow rate ratio as described above, the crystallinity of the first metal oxide layer 10 8a can be lowered.

[0090] On the other hand, as the film-forming conditions of the second metal oxide layer 108b, the oxygen flow rate ratio is more than 30% and 100% or less, preferably 50% or more and 100% or less, more preferably 70% or more and 100 % or less. By setting the oxygen flow rate ratio as described above, the crystallinity of the second metal oxide layer 108b can be increased.

[0091] Note that when the oxygen flow rate ratio is high, a region having a spinel-type crystal structure may occur in the metal oxide layer. When there is a region having a spinel-type crystal structure, the oxygen deficiency density may be high in the region or / and at the interface between the region and other regions. Therefore, an oxygen flow rate ratio at which a region having a spinel-type crystal structure does not occur, for example, an oxygen flow rate ratio of more than 30% and 50% or less may be used.

[0092] As the substrate temperature when forming the first metal oxide layer 108a and the second metal oxide layer 108b, room temperature (25°C) or more and 200°C or less is preferable, and room temperature or more and 130°C or less is more preferable . By setting the substrate temperature within the above range, when using a large-area glass substrate, the bending or distortion of the substrate can be suppressed. Here, between the first metal oxide layer 108a and the second metal oxide layer 1 When the substrate temperature is set to the same temperature with 08b, productivity can be increased. Also, for example In the case where the substrate temperature is made different between the first metal oxide layer 108a and the second metal oxide layer 108b when the substrate temperature during the formation of the second metal oxide layer 108b is increased, the crystallinity of the second metal oxide layer 108b can be further enhanced.

[0093] For example, a CAC-OS (Cloud-Aligned Composite oxide semiconductor) film is used for the first metal oxide layer 108a, and a CAAC-OS (c-axis-aligned crystall ine oxide semiconductor) film is preferably used for the second metal oxide layer 108b.

[0094] As for the crystallinity of the first metal oxide layer 108a and the second metal oxide layer 108b, for example it can be analyzed by X-ray diffraction (XRD), transmission electron microscope (T EM:Transmission Electron Microscope), electron beam diffraction, etc.

[0095] The thickness of the first metal oxide layer 108a may be 1 nm or more and 50 nm or less, preferably 5 nm or more and 30 nm or less. Also, the thickness of the second metal oxide layer 108b should be greater than 10 nm and 100 nm or less, preferably 20 nm or more and 50 nm or less to be appropriate.

[0096] Note that there may be cases where the boundary (interface) between the first metal oxide layer 108a and the second metal oxide layer 108b cannot be clearly confirmed. Therefore, in the drawings for explaining one embodiment of the present invention, these boundaries are indicated by broken lines. are indicated by broken lines.

[0097] In the metal oxide layer 108, when oxygen vacancies in the metal oxide layer 108 react with hydrogen VoH is formed, and the carrier density may increase. Therefore, it is preferable that the metal oxide layer 108 has few oxygen vacancies. Also, it is preferable that the metal oxide layer 108 has few impurities Particularly, it is preferable that the metal oxide layer 108 has few hydrogen-containing impurities By having few oxygen vacancies and impurities, the formation of VoH in the metal oxide layer 108 is suppressed. Therefore, a transistor with a low carrier density, good electrical characteristics, and high reliability can be obtained.

[0098] Note that the metal oxide layer 108 may have a single-layer structure. By applying the same configuration as the metal oxide layer 108a to the metal oxide layer 108, the on-current of the transistor can be increased Also, by applying the same configuration as the metal oxide layer 108b to the metal oxide layer 108, the reliability of the transistor can be improved.

[0099] For the insulating layer 114, an oxygen-containing insulating film formed in an oxygen-containing atmosphere can be used. An insulating film formed in an oxygen-containing atmosphere can be made into a film that easily releases a large amount of oxygen by heating. Also, for the insulating layer 114, it is preferable to use a material with a lower nitrogen concentration than the insulating layer 116. For example, it is preferable to use an insulating film containing silicon and oxygen, an insulating film containing silicon, oxygen, and nitrogen, etc. Particularly, it is more preferable to use a silicon oxide film or a silicon oxynitride film.

[0100] In this specification, etc., silicon oxynitride has silicon, oxygen, and nitrogen, and ​​refers to a film having an oxygen content higher than that of nitrogen in its composition. Silicon oxynitride refers to a film having silicon, oxygen, and nitrogen, and having a nitrogen content higher than that of oxygen in its composition. The composition can be measured using, for example, the Rutherford Backscattering Spectrometry (RBS). When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects. The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided. The insulating layer 114a in contact with the back channel side of the metal oxide layer 108 can be configured to use an oxide film having a lower nitrogen content than the insulating layer 114b. By using an oxide film having a lower nitrogen content as the insulating layer 114a, nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably

[0101] When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects. When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects. When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects. When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects. When using a silicon oxide film, a silicon oxynitride film, etc. as the insulating layer 114, it is preferable to form it using a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The PECVD apparatus is preferable because it has high step coverage of the surface to be formed and can form a dense insulating film with few defects.

[0102] The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided. The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided. The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided. The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided. The insulating layer 114 may have a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. It is preferable that the insulating layer 114a and the insulating layer 114b each have an excess oxygen region. By having the insulating layer 114a and the insulating layer 114b have an excess oxygen region, oxygen can be supplied to the metal oxide layer 108. Since the oxygen vacancies that can be formed in the metal oxide layer 108 can be filled with oxygen, a transistor with good electrical characteristics and high reliability can be provided.

[0103] The insulating layer 114a in contact with the back channel side of the metal oxide layer 108 can be configured to use an oxide film having a lower nitrogen content than the insulating layer 114b. By using an oxide film having a lower nitrogen content as the insulating layer 114a, nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably The insulating layer 114a in contact with the back channel side of the metal oxide layer 108 can be configured to use an oxide film having a lower nitrogen content than the insulating layer 114b. By using an oxide film having a lower nitrogen content as the insulating layer 114a, nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably The insulating layer 114a in contact with the back channel side of the metal oxide layer 108 can be configured to use an oxide film having a lower nitrogen content than the insulating layer 114b. By using an oxide film having a lower nitrogen content as the insulating layer 114a, nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably 14a in contact with the metal oxide layer 108, nitrogen oxides (NOx, where x is greater than 0 and less than or equal to 2, preferably x x is greater than 0 and less than or equal to 2, preferably is 1 or more and 2 or less. Typically, NO 2 or NO) is difficult to form It is possible. For the formation of the insulating layer 114a, a PECVD apparatus can be used. The insulating layer 114 The formation of a can use a film formation condition with lower power and lower chamber pressure than the formation of the insulating layer 114b can be used.

[0104] In addition, the insulating layer 114a is an insulating film that can transmit oxygen. Note that the insulating layer 1 14a also functions as a damage relaxation film for the metal oxide layer 108 when forming the insulating layer 114b formed later

[0105] The insulating layer 114b provided on the insulating layer 114a can be configured to use an oxide film having more excess oxygen (exO) than the insulating layer 114a. For the formation of the insulating layer 114b a PECVD apparatus can be used. The formation of the insulating layer 114b can use a film formation condition with higher power and higher chamber pressure than the formation of the insulating layer 114a. In addition, the substrate temperature when forming the insulating layer 114b is preferably 180°C or more and 280°C or less In the film formed at the above-described substrate temperature, since the bonding force between silicon and oxygen is weak, a part of the oxygen in the film desorbs by the heat treatment in the subsequent process. As a result, an insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of the oxygen desorbed by heating can be formed which is preferable.

[0106] When the same material is used for the insulating layer 114a and the insulating layer 114b, the interface between the insulating layer 114a and the insulating layer 114b may not be clearly confirmed. Therefore, in the present embodiment the interface between the insulating layer 114a and the insulating layer 114b is indicated by a broken line. Note that in the present embodiment ​​​​​​, the two-layer structure of the insulating layer 114a and the insulating layer 114b has been described. However, one aspect of the present invention is not limited to this. For example, it may be a single-layer structure of either the insulating layer 114a or the insulating layer 114b, or a laminated structure of three or more layers.

[0107] Regarding the path of oxygen diffusing from the insulating layer 114 into the metal oxide layer 108, it will be described with reference to FIGS. 2(A) and 2(B). FIGS. 2(A) and 2(B) are conceptual diagrams showing the path of oxygen diffusing into the metal oxide layer 108. FIG. 2(A) is a conceptual diagram in the channel length direction, and FIG. 2(B) is a conceptual diagram in the channel width direction.

[0108] The oxygen contained in the insulating layer 114a and the insulating layer 114b diffuses from the upper side, that is, through the second metal oxide layer 108b, into the first metal oxide layer 108a (Route 1 shown in FIGS. 2(A) and 2(B)).

[0109] Alternatively, the oxygen contained in the insulating layer 114a and the insulating layer 114b diffuses into the metal oxide layer 108 from the side surfaces of the first metal oxide layer 108a and the second metal oxide layer 108b respectively (Route 2 shown in FIG. 2(B)).

[0110] For example, in the case of Route 1 shown in FIGS. 2(A) and 2(B), when the crystallinity of the second metal oxide layer 108b is high, it may inhibit the diffusion of oxygen. On the other hand, in the case of Route 2 shown in FIG. 2(B), from the side surfaces of the first metal oxide layer 108a and the second metal oxide layer 108 b respectively, it becomes possible to diffuse oxygen into the first metal oxide layer 108a and the second metal oxide layer 108b.

[0111] ​​​​In the case of Route 2 shown in Fig. 2(B), when the first metal oxide layer 108a has a region with lower crystallinity than the second metal oxide layer 108b, this region serves as an oxygen diffusion path, and oxygen can also be diffused into the second metal oxide layer 108b, which has higher crystallinity than the first metal oxide layer 108a. Although not shown in Figs. 2(A) and 2(B), when the insulating layer 106 and the region 106a contain oxygen, oxygen can diffuse from the insulating layer 106 and the region 106a into the metal oxide layer 108. As described above, by forming the metal oxide layer 108 as a laminated structure of films with different crystal structures and using the region with lower crystallinity as the oxygen diffusion path, a transistor with good electrical characteristics and high reliability can be provided.

[0112] When the insulating layer 114 is provided on the metal oxide layer 108, the metal oxide layer 1 08 may have an oxygen concentration gradient in the film thickness direction, with a higher oxygen concentration on the insulating layer 114 side. Examples of elemental analysis methods include energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), and others.

[0113] The oxygen diffusing from the insulating layer 114a and the insulating layer 114b into the first metal oxide layer 108a and the second metal oxide layer 108b will be described with reference to Fig. 2(C). Fig. 2(C) shows the case where... ... ... ... ... ...

[0114] Regarding the oxygen diffusing from the insulating layer 114a and the insulating layer 114b into the first metal oxide layer 108a and the second metal oxide layer 108b, an explanation will be given using Fig. 2(C). Fig. 2(C) shows As shown, in the first metal oxide layer 108a and the second metal oxide layer 108b, there may exist oxygen vacancies (Vo), hydrogen (H), and a state where oxygen vacancies and hydrogen are combined (VoH). When the oxygen in the insulating layer 114a and the insulating layer 114b approaches the oxygen vacancies in the first metal oxide layer 108a and the second metal oxide layer 108b, the oxygen is captured by the oxygen vacancies, and the oxygen vacancies are filled. Also, when oxygen approaches hydrogen, oxygen and hydrogen act to form water (H2O), and it desorbs as water molecules from the first metal oxide layer 108a and the second metal oxide layer 108b. Further, when oxygen approaches VoH, the oxygen fills the oxygen vacancies. Also, the hydrogen that the VoH had acts with another oxygen to form water and desorbs as water from the first metal oxide layer 108a and the second metal oxide layer 108b. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated. There may exist oxygen vacancies (Vo), hydrogen (H), and a state where oxygen vacancies and hydrogen are combined (VoH). When the oxygen in the insulating layer 114a and the insulating layer 114b approaches the oxygen vacancies in the first metal oxide layer 108a and the second metal oxide layer 108b, the oxygen is captured by the oxygen vacancies, and the oxygen vacancies are filled. When the oxygen in the insulating layer 114a and the insulating layer 114b approaches the oxygen vacancies in the first metal oxide layer 108a and the second metal oxide layer 108b, the oxygen is captured by the oxygen vacancies, and the oxygen vacancies are filled. Also, when oxygen approaches hydrogen, oxygen and hydrogen act to form water (H2O), and it desorbs as water molecules from the first metal oxide layer 108a and the second metal oxide layer 108b. 2 O) and becomes, and desorbs as water molecules from the first metal oxide layer 108a and the second metal oxide layer 108b. Also, when oxygen approaches VoH, the oxygen fills the oxygen vacancies. Also, the hydrogen that the VoH had acts with another oxygen to form water and desorbs as water from the first metal oxide layer 108a and the second metal oxide layer 108b. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated. In this way, the oxygen in the insulating layer 114a and the insulating layer 114b can reduce the oxygen vacancies, hydrogen, and VoH in the first metal oxide layer 108a and the second metal oxide layer 108b. Therefore, a transistor with good electrical characteristics and high reliability can be fabricated.

[0115] Here, consider the case where hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b without providing the insulating layer 114 having excess oxygen. The hydrogen in the first metal oxide layer 108a and the second metal oxide layer 108b may combine with the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b and desorb as water molecules. In that case, since the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b desorbs, oxygen vacancies are generated, which is not preferable. Here, consider the case where hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b without providing the insulating layer 114 having excess oxygen. The hydrogen in the first metal oxide layer 108a and the second metal oxide layer 108b may combine with the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b and desorb as water molecules. Here, consider the case where hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b without providing the insulating layer 114 having excess oxygen. The hydrogen in the first metal oxide layer 108a and the second metal oxide layer 108b may combine with the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b and desorb as water molecules. Here, consider the case where hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b without providing the insulating layer 114 having excess oxygen. The hydrogen in the first metal oxide layer 108a and the second metal oxide layer 108b may combine with the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b and desorb as water molecules. Here, consider the case where hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b without providing the insulating layer 114 having excess oxygen. The hydrogen in the first metal oxide layer 108a and the second metal oxide layer 108b may combine with the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b and desorb as water molecules. In that case, since the oxygen in the first metal oxide layer 108a and the second metal oxide layer 108b desorbs, oxygen vacancies are generated, which is not preferable.

[0116] On the one hand, as shown in this embodiment, when hydrogen desorbs from the first metal oxide layer 108a and the second metal oxide layer 108b in a state where the insulating layer 114 having excess oxygen is provided, consider it. The hydrogen contained in the first metal oxide layer 108a and the second metal oxide layer 108b reacts with the oxygen supplied from the insulating layer 114 and desorbs as water molecules. By the hydrogen reacting with the oxygen supplied from the insulating layer 114, it is possible to suppress the newly generated oxygen deficiency in the first metal oxide layer 108a and the second metal oxide layer 108b, which is preferable.

[0117] By supplying oxygen from the insulating layer 114a and the insulating layer 114b to the first metal oxide layer 108a and the second metal oxide layer 108b, the oxygen deficiency, hydrogen, and VoH contained in the first metal oxide layer 108a and the second metal oxide layer 108b can be reduced. In addition, it is possible to suppress the generation of oxygen deficiency and VoH in the first metal acid ide layer 108a and the second metal oxide layer 108b. By suppressing the generation of oxygen deficiency and VoH, transistors with good electrical characteristics and high reliability can be fabricated.

[0118] After forming the insulating layer 114a, it is preferable to continuously form the insulating layer 114b in a vacuum without exposing the surface of the insulating layer 114a to the atmosphere. By continuously forming, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 1 14a.

[0119] The insulating layer 116 formed on the insulating layer 114b preferably uses an insulating film that is difficult to diffuse and permeate oxygen. Further, the insulating layer 116 preferably uses an insulating film with little impurity release and difficult to diffuse and permeate impurities. In particular, the insulating layer 116 has impurities containing hydrogen It is preferable that the release is small and impurities are difficult to diffuse and permeate. By providing the insulating layer 116, the carrier density of the metal oxide layer 108 is lowered, the electrical characteristics are good, and a highly reliable transistor can be obtained.

[0120] As the insulating layer 116, an insulating film containing silicon and nitrogen can be used. In particular, it is preferable to use an insulating film mainly containing silicon and nitrogen. For example, silicon nitride, silicon oxynitride, etc. can be used alone or in a laminate.

[0121] Alternatively, as the insulating layer 116, an oxide containing an element X (X is one or more of aluminum, indium, gallium, or zinc) can be used. In particular, it is preferable to use an insulating film mainly containing a metal and oxygen. For example, aluminum oxide or In-Ga-Zn oxide can be used as the insulating layer 116. It is more preferable to form the insulating layer 11 6 using a gas containing oxygen. By using a gas containing oxygen, oxygen can be supplied to the insulating layer 114b which is the layer to be formed of the insulating layer 116, which is preferable. The supplied oxygen in the insulating layer 114b can reduce the oxygen deficiency, hydrogen, and VoH in the metal oxide layer 108 as described above. Therefore, a transistor with good electrical characteristics and high reliability can be provided.

[0122] By performing heat treatment in a state where an oxygen-releasing insulating film is used as the insulating layer 114a and the insulating layer 114b, and an insulating film that is difficult to diffuse and permeate oxygen is laminated as the insulating layer 116, oxygen can be efficiently supplied to the metal oxide layer 108. As a result, the oxygen deficiency in the metal oxide layer 108 and the defects at the interface between the metal oxide layer 108 and the insulating layer 114 are repaired, and the defect levels are reduced. ​​This makes it possible to fabricate a transistor with good electrical characteristics and high reliability.

[0123] The above-described insulating layer 114a and insulating layer 114b may have voids 180 in the insulating layer 114a and insulating layer 114b. As shown in FIG. 3(A), voids 180 are likely to occur particularly at the stepped portions of the insulating layer 114a and insulating layer 114b formed by the conductive layer 112a and conductive layer 112b. When voids 180 are present in the insulating layer 114a and insulating layer 114b, impurities may diffuse from the outside or a later-formed layer into the metal oxide layer 108. As shown in FIG. 3(B), by providing the insulating layer 116 on the insulating layer 114a and insulating layer 114b, diffusion of impurities into the metal oxide layer 108 can be suppressed. In addition, desorption of oxygen from the metal oxide layer 108 and its diffusion to the outside can be suppressed. By suppressing the diffusion of oxygen to the outside, an increase in oxygen vacancies, hydrogen, and VoH in the metal oxide layer 108 can be suppressed, and a transistor with good electrical characteristics and high reliability can be fabricated. After forming the insulating layer 114b, it is preferable to continuously form the insulating layer 116 in a vacuum without exposing the surface of the insulating layer 114b to the atmosphere. By forming continuously, adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114b can be suppressed. In addition, when the insulating layer 114a, insulating layer 114b, and insulating layer 116 are continuously formed in a vacuum, adhesion of impurities derived from atmospheric components to the surfaces of the insulating layer 114a and insulating layer 114b can be suppressed, which is more preferable. This makes it possible to fabricate a transistor with good electrical characteristics and high reliability.

[0124] After forming the insulating layer 114b, it is preferable to continuously form the insulating layer 116 in a vacuum without exposing the surface of the insulating layer 114b to the atmosphere. By forming continuously, adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114b can be suppressed. In addition, when the insulating layer 114a, insulating layer 114b, and insulating layer 116 are continuously formed in a vacuum, adhesion of impurities derived from atmospheric components to the surfaces of the insulating layer 114a and insulating layer 114b can be suppressed, which is more preferable. For the insulating layer 106, an insulating film in which impurities such as hydrogen and oxygen hardly diffuse can be used. For the insulating layer 106, an insulating film in which impurities such as hydrogen and oxygen hardly diffuse can be used.

[0125] For the insulating layer 106, an insulating film in which impurities such as hydrogen and oxygen hardly diffuse can be used. For example, an insulating film with high barrier properties such as a nitride insulating film can be used. In particular, it is preferable to use an insulating film containing silicon and nitrogen as main components.

[0126] The insulating layer 106 has a region 106a located near its upper surface. In FIGS. 1(B) and 1(C), the interface of the region 106a is indicated by a dashed line. The region 106a is a region with a higher oxygen concentration than other regions of the insulating layer 106. Note that it is preferable that the region of the insulating layer 106 other than the region 106a does not contain oxygen as a main component. Also, the region 106a is preferably a region with a lower hydrogen concentration than other regions of the insulating layer 106. The metal oxide layer 108 is provided in contact with the region 106a. (C), the interface of the region 106a is indicated by a dashed line. The region 106a is a region with a higher oxygen concentration than other regions of the insulating layer 106. Note that it is preferable that the region of the insulating layer 106 other than the region 106a does not contain oxygen as a main component. Also, the region 106a is preferably a region with a lower hydrogen concentration than other regions of the insulating layer 106. The metal oxide layer 108 is provided in contact with the region 106a. Note that it is preferable that the region of the insulating layer 106 other than the region 106a does not contain oxygen as a main component. Also, the region 106a is preferably a region with a lower hydrogen concentration than other regions of the insulating layer 106. The metal oxide layer 108 is provided in contact with the region 106a. Note that it is preferable that the region of the insulating layer 106 other than the region 106a does not contain oxygen as a main component. Also, the region 106a is preferably a region with a lower hydrogen concentration than other regions of the insulating layer 106. The metal oxide layer 108 is provided in contact with the region 106a. Note that it is preferable that the region of the insulating layer 106 other than the region 106a does not contain oxygen as a main component. Also, the region 106a is preferably a region with a lower hydrogen concentration than other regions of the insulating layer 106. The metal oxide layer 108 is provided in contact with the region 106a.

[0127] The region 106a can have a thickness of 1 nm or more and 10 nm or less.

[0128] By adopting a configuration in which the region 106a containing a large amount of oxygen is in contact with the metal oxide layer 108, it is possible to suppress the formation of defect energy levels at these interfaces. Therefore, by having a stacked structure of the region 106a and the metal oxide layer 108, the electrical characteristics of the transistor 100A can be made good. By adopting a configuration in which the region 106a containing a large amount of oxygen is in contact with the metal oxide layer 108, it is possible to suppress the formation of defect energy levels at these interfaces. Therefore, by having a stacked structure of the region 106a and the metal oxide layer 108, the electrical characteristics of the transistor 100A can be made good. By adopting a configuration in which the region 106a containing a large amount of oxygen is in contact with the metal oxide layer 108, it is possible to suppress the formation of defect energy levels at these interfaces. Therefore, by having a stacked structure of the region 106a and the metal oxide layer 108, the electrical characteristics of the transistor 100A can be made good. By adopting a configuration in which the region 106a containing a large amount of oxygen is in contact with the metal oxide layer 108, it is possible to suppress the formation of defect energy levels at these interfaces. Therefore, by having a stacked structure of the region 106a and the metal oxide layer 108, the electrical characteristics of the transistor 100A can be made good.

[0129] By adopting a configuration in which the metal oxide layer 108 is provided on the region 106a, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and there is a case where the oxygen concentration becomes high on the region 106a side. Also, as described above, the metal oxide layer 108 may have a high oxygen concentration on the insulating layer 114 side. That is, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration may become high on the region 106a side and on the insulating layer 114 side. Elemental analysis By adopting a configuration in which the metal oxide layer 108 is provided on the region 106a, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and there is a case where the oxygen concentration becomes high on the region 106a side. Also, as described above, the metal oxide layer 108 may have a high oxygen concentration on the insulating layer 114 side. That is, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration may become high on the region 106a side and on the insulating layer 114 side. Elemental analysis By adopting a configuration in which the metal oxide layer 108 is provided on the region 106a, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and there is a case where the oxygen concentration becomes high on the region 106a side. Also, as described above, the metal oxide layer 108 may have a high oxygen concentration on the insulating layer 114 side. That is, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration may become high on the region 106a side and on the insulating layer 114 side. Elemental analysis By adopting a configuration in which the metal oxide layer 108 is provided on the region 106a, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and there is a case where the oxygen concentration becomes high on the region 106a side. Also, as described above, the metal oxide layer 108 may have a high oxygen concentration on the insulating layer 114 side. That is, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration may become high on the region 106a side and on the insulating layer 114 side. Elemental analysis By adopting a configuration in which the metal oxide layer 108 is provided on the region 106a, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and there is a case where the oxygen concentration becomes high on the region 106a side. Also, as described above, the metal oxide layer 108 may have a high oxygen concentration on the insulating layer 114 side. That is, the metal oxide layer 108 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration may become high on the region 106a side and on the insulating layer 114 side. Elemental analysis ​As analysis methods, for example, energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc. are available.

[0130] Furthermore, the transistor 100A has a configuration in which a stacked structure of a region 106a, a metal oxide layer 108, and an insulating layer 114 is sandwiched between an insulating layer 106 and an insulating layer 116. Since the insulating layer 106 and the insulating layer 116 are layers in which water, hydrogen, oxygen, etc. hardly diffuse, it is possible to prevent water and hydrogen from diffusing from the outside into the metal oxide layer 108, and to prevent oxygen from diffusing (desorbing) from the metal oxide layer 108 to the outside. As a result, not only can the electrical characteristics of the transistor 100A be made good, but also the reliability can be enhanced.

[0131] The existence of the region 106a can be confirmed, for example, by performing elemental analysis of a region including the interface with the metal oxide layer 108 in the insulating layer 106. At this time, oxygen can be detected in a larger amount in a region of the insulating layer 106 close to the metal oxide layer 108. In addition, a region with a high oxygen concentration may be observed in the vicinity of the interface between the insulating layer 106 and the metal oxide layer 108. Also, a region with a lower hydrogen concentration than other parts may be observed in a region of the insulating layer 106 close to the metal oxide layer 108. As analysis methods, for example, energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc. are available. Also, the existence of the region 106a may be observed as a region with a contrast different from other parts in a transmission electron microscope (TEM: Transmission Electron Microscopy) image in the cross section, etc. (AES), etc. ​

[0132] The above is the description of Configuration Example 1.

[0133] Hereinafter, a configuration example of a transistor that is different from Configuration Example 1 in part will be described. . Note that hereinafter, the description of the overlapping parts with the aforementioned Configuration Example 1 may be omitted. Also, in the drawings shown below, for parts having the same functions as those in the aforementioned Configuration Example 1, the hatching pattern may be the same, and there may be no reference signs.

[0134] <Configuration Example 2> A top view of a transistor 100B, which is a semiconductor device according to an aspect of the present invention, is shown in Fig. 4(A), and a cross-sectional view is shown in Figs. 4(B) and 4(C). Fig. 4(B) corresponds to a cross-sectional view of a cut-away view along the chain double-dashed line X1- X2 shown in Fig. 4(A), and Fig. 4(C) corresponds to a cross-sectional view of a cut-away view along the chain double-dashed line Y1- Y2 shown in Fig. 4(A).

[0135] The transistor 100B is different from the transistor 100A illustrated in Configuration Example 1 in that the metal oxide layer 108 has a first metal oxide layer 108a, a second metal oxide layer 108b, and a third metal oxide layer 108c.

[0136] As shown in Figs. 4(A), 4(B), and 4(C), the metal oxide layer 108 preferably has a laminated structure of a third metal oxide layer 108c, a first metal oxide layer 108a on the third metal oxide layer 108c, and a second metal oxide layer 108b on the first metal oxide layer 108a.

[0137] The first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 ​​08c preferably contains a metal oxide respectively. As the third metal oxide layer 108c the materials used for the first metal oxide layer 108a and the second metal oxide layer 108b can be applied.

[0138] For the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 08c, films formed using targets with different compositions may be used respectively, but it is particularly preferable to use targets with the same composition and use a laminated film formed continuously without exposure to the atmosphere. By forming the film continuously, not only can the treatment be performed with one film-forming apparatus, but also the residual impurities between the third metal oxide layer 108c and the first metal oxide layer 108a, and between the first metal oxide layer 10 8a and the second metal oxide layer 108b can be suppressed. Since the impurities in the metal oxide layer can be a carrier source, by suppressing the increase of impurities, transistors with good electrical characteristics and high reliability can be fabricated.

[0139] The third metal oxide layer 108c and the second metal oxide layer 108b preferably have a region with higher crystallinity than the first metal oxide layer 108a. Since the third metal oxide layer 108 c has a region with high crystallinity, the diffusion of impurities from the lower layer (for example, the insulating layer 106, the conductive layer 104, the substrate 102) below the third metal oxide layer 108c to the first metal oxide layer 108a can be suppressed.

[0140] For the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 08c, they can be made separately by, for example, varying the film-forming conditions. For example, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c and​​​​ The flow rate of oxygen gas in the film-forming gas can be varied.

[0141] At this time, as the film-forming conditions for the first metal oxide layer 108a, the ratio of the oxygen gas flow rate to the total gas flow rate (also referred to as the oxygen flow rate ratio or oxygen partial pressure) is set to 0% or more and 30% or less, preferably 5% or more and 15% or less. By setting the oxygen flow rate ratio as described above, the crystallinity of the first metal oxide layer 10 8a can be lowered.

[0142] On the other hand, as the film-forming conditions for the second metal oxide layer 108b and the third metal oxide layer 108c, the oxygen flow rate ratio is set to more than 30% and 100% or less, preferably 50% or more and 100% or less, and more preferably 70% or more and 100% or less. By setting the oxygen flow rate ratio as described above, the crystallinity of the second metal oxide layer 108b and the third metal oxide layer 108c can be increased . Note that the same oxygen flow rate ratio may be used for the second metal oxide layer 108b and the third metal oxide layer 108c, or different oxygen flow rate ratios may be used.

[0143] Also, by setting the oxygen flow rate ratio as described above, when the third metal oxide layer 108c is formed, oxygen is added to the insulating layer 106 that becomes the surface to be formed of the third metal oxide layer 108c. The oxygen added to the insulating layer 1 06 can diffuse into the metal oxide layer 108 as excess oxygen. Therefore, oxygen vacancies, hydrogen, and VoH in the metal oxide layer can be reduced.

[0144] As the substrate temperature during the formation of the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 08c, a temperature of room temperature (25°C) or higher and 200°C or lower is preferable, and room temperature or higher and 130°C or lower is more preferable. By setting the substrate temperature within the above range, a large-area glass substrate When using a plate, the bending or distortion of the substrate can be suppressed. Here, with the first metal oxide layer 1 08a, the second metal oxide layer 108b, and the third metal oxide layer 108c, when the substrate temperature is set to the same temperature, productivity can be increased. Also, for example, when the substrate temperature is made different with the first metal oxide layer 10 8a, the second metal oxide layer 108b, and the third metal oxide layer 108c, when the substrate temperature during the formation of the second metal oxide layer 108b and the third metal oxide layer 108c is raised, the crystallinity of the second metal oxide layer 108b and the third metal oxide layer 108c can be further enhanced. For example, it is preferable to use a CAC-OS film for the first metal oxide layer 108a and a CAAC-OS film for the second metal oxide layer 1 08b and the third metal oxide layer 108c.

[0145] For example, it is preferable to use a CAC-OS film for the first metal oxide layer 108a and a CAAC-OS film for the second metal oxide layer 1 08b and the third metal oxide layer 108c.

[0146] The thickness of the third metal oxide layer 108c may be 1 nm or more and 50 nm or less, preferably 1 nm or more and 10 nm or less. Also, the thickness of the first metal oxide layer 108a may be 1 nm or more and 50 nm or less, preferably 5 nm or more and 20 nm or less. Also, the thickness of the second metal oxide layer 108b may be greater than 5 nm and 100 nm or less, preferably 5 nm or more and 30 nm or less.

[0147] Note that there may be cases where the boundaries (interfaces) of the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c cannot be clearly confirmed. Therefore, in the drawings for explaining one embodiment of the present invention these boundaries are shown by broken lines. In the drawings for explaining one embodiment of the present invention, these boundaries are shown by broken lines.

[0148] <Configuration Example 3> The top view of the transistor 100C, which is a semiconductor device according to one aspect of the present invention, is shown in Fig. 5(A), and the cross-sectional views are shown in Figs. 5(B) and 5(C). Fig. 5(B) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line X1- X2 shown in Fig. 5(A), and Fig. 5(C) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line Y1- Y2 shown in Fig. 5(A).

[0149] The transistor 100C is different from the transistor 100A exemplified in Configuration Example 1 in that the conductive layers 112a and 112b have a stacked structure.

[0150] The conductive layer 112a has a stacked structure in which the conductive layer 121a, the conductive layer 122a, and the conductive layer 123a are stacked in this order. The conductive layer 112b has a stacked structure in which the conductive layer 121b, the conductive layer 122b, and the conductive layer 123b are stacked in this order.

[0151] The conductive layers 121a and 121b are provided so as to cover the side surfaces of the first metal oxide layer 108a, and the upper surface and side surfaces of the metal oxide layer 108b. Further, the conductive layers 121a and 121b are provided in contact with the region 106a of the insulating layer 106. The conductive layers 122a and 122b are provided on the conductive layers 121a and 121b, respectively. In plan view, the conductive layers 122a and 122b are located inside the conductive layers 121a and 121b. The conductive layers 123a and 123b are provided on the conductive layers 122a and 122b, respectively. The conductive layers 123a and 123b are provided so as to cover the upper surfaces and side surfaces of the conductive layers 122a and 122b, respectively. Also, a part of the conductive layers 123a and 123b is in contact with the conductive layers 121a and 121, respectively. ​​​​​​​​​​It is provided in contact with the upper surface of 21b. The conductive layer 121a and the conductive layer 123a are processed so that their ends coincide in a plan view. The conductive layer 121b and the conductive layer 123b are processed so that their ends coincide in a plan view.

[0152] With such a configuration, the conductive layer 122a can be configured to be surrounded by the conductive layer 121a and the conductive layer 123a. The conductive layer 122b can be configured to be surrounded by the conductive layer 121b and the conductive layer 123b. In other words, the surfaces of the conductive layer 122a and the conductive layer 122b can be configured not to be exposed. Thereby, a material that is likely to diffuse into the metal oxide layer 108 can be used for the conductive layer 122a and the conductive layer 122b.

[0153] For the conductive layer 122a and the conductive layer 122b, it is preferable to use a material with a lower resistance than the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b, a material that is less likely to diffuse into the metal oxide layer 108 can be used.

[0154] For the conductive layer 122a and the conductive layer 122b, at least a conductive material different from the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b can be used. Note that different conductive materials can also be used for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b, respectively. In particular, using the same conductive material for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b is preferable because the manufacturing equipment can be shared and the contact resistance at these ends can be reduced.

[0155] For example, it is preferable to use a titanium film or a molybdenum film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 122a and the conductive layer 122b, it is preferable to use an aluminum film or a copper film. With such a configuration, while reducing the wiring resistance of the conductive layer 112a and the conductive layer 112b, a transistor with good electrical characteristics can be realized. For example, it is preferable to use a titanium film or a molybdenum film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 122a and the conductive layer 122b, it is preferable to use an aluminum film or a copper film. With such a configuration, while reducing the wiring resistance of the conductive layer 112a and the conductive layer 112b, a transistor with good electrical characteristics can be realized. For example, it is preferable to use a titanium film or a molybdenum film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 122a and the conductive layer 122b, it is preferable to use an aluminum film or a copper film. With such a configuration, while reducing the wiring resistance of the conductive layer 112a and the conductive layer 112b, a transistor with good electrical characteristics can be realized. For example, it is preferable to use a titanium film or a molybdenum film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 122a and the conductive layer 122b, it is preferable to use an aluminum film or a copper film. With such a configuration, while reducing the wiring resistance of the conductive layer 112a and the conductive layer 112b, a transistor with good electrical characteristics can be realized. For example, it is preferable to use a titanium film or a molybdenum film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. Also, for the conductive layer 122a and the conductive layer 122b, it is preferable to use an aluminum film or a copper film. With such a configuration, while reducing the wiring resistance of the conductive layer 112a and the conductive layer 112b, a transistor with good electrical characteristics can be realized.

[0156] The above is the description of Configuration Example 3.

[0157] <Configuration Example 4> The top view of the transistor 100D, which is a semiconductor device according to an aspect of the present invention, is shown in Fig. 6(A), and the cross-sectional views are shown in Fig. 6(B) and Fig. 6(C). Fig. 6(B) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line X1-X2 shown in Fig. 6(A), and Fig. 6(C) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line Y1-Y2 shown in Fig. 6(A). The top view of the transistor 100D, which is a semiconductor device according to an aspect of the present invention, is shown in Fig. 6(A), and the cross-sectional views are shown in Fig. 6(B) and Fig. 6(C). Fig. 6(B) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line X1-X2 shown in Fig. 6(A), and Fig. 6(C) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line Y1-Y2 shown in Fig. 6(A). The top view of the transistor 100D, which is a semiconductor device according to an aspect of the present invention, is shown in Fig. 6(A), and the cross-sectional views are shown in Fig. 6(B) and Fig. 6(C). Fig. 6(B) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line X1-X2 shown in Fig. 6(A), and Fig. 6(C) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line Y1-Y2 shown in Fig. 6(A). The top view of the transistor 100D, which is a semiconductor device according to an aspect of the present invention, is shown in Fig. 6(A), and the cross-sectional views are shown in Fig. 6(B) and Fig. 6(C). Fig. 6(B) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line X1-X2 shown in Fig. 6(A), and Fig. 6(C) corresponds to the cross-sectional view of the cut-away view along the dashed-dotted line Y1-Y2 shown in Fig. 6(A).

[0158] The transistor 100D is different from the transistor 100C exemplified in the above Configuration Example 3 in that it has a conductive layer 120a, a conductive layer 120b, and a conductive layer 112c. The transistor 100D is different from the transistor 100C exemplified in the above Configuration Example 3 in that it has a conductive layer 120a, a conductive layer 120b, and a conductive layer 112c.

[0159] The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping with the metal oxide layer 108. At this time, the conductive layer 104 functions as the first gate, and the conductive layer 120a functions as the second gate. A part of the insulating layer 106 functions as the first gate insulating layer, and a part of the insulating layer 114 and the insulating layer 116 functions as the second gate insulating layer. The transistor 100D is a transistor having a pair of gate electrodes. The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping with the metal oxide layer 108. At this time, the conductive layer 104 functions as the first gate, and the conductive layer 120a functions as the second gate. A part of the insulating layer 106 functions as the first gate insulating layer, and a part of the insulating layer 114 and the insulating layer 116 functions as the second gate insulating layer. The transistor 100D is a transistor having a pair of gate electrodes. The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping with the metal oxide layer 108. At this time, the conductive layer 104 functions as the first gate, and the conductive layer 120a functions as the second gate. A part of the insulating layer 106 functions as the first gate insulating layer, and a part of the insulating layer 114 and the insulating layer 116 functions as the second gate insulating layer. The transistor 100D is a transistor having a pair of gate electrodes. The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping with the metal oxide layer 108. At this time, the conductive layer 104 functions as the first gate, and the conductive layer 120a functions as the second gate. A part of the insulating layer 106 functions as the first gate insulating layer, and a part of the insulating layer 114 and the insulating layer 116 functions as the second gate insulating layer. The transistor 100D is a transistor having a pair of gate electrodes. The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping with the metal oxide layer 108. At this time, the conductive layer 104 functions as the first gate, and the conductive layer 120a functions as the second gate. A part of the insulating layer 106 functions as the first gate insulating layer, and a part of the insulating layer 114 and the insulating layer 116 functions as the second gate insulating layer. The transistor 100D is a transistor having a pair of gate electrodes.

[0160] Transistor 100D is a so-called channel etch type, dual gate structure transistor. It is a transistor.

[0161] Conductive layer 120b is electrically connected to conductive layer 123b of conductive layer 112b by connection portion 142b. In connection portion 142b, conductive layer 120b is electrically connected to conductive layer 123b of conductive layer 112b through an opening provided in insulating layer 116 and insulating layer 114. It is connected. As shown in FIG. 6(C), it is preferable that conductive layer 120a and conductive layer 104 are electrically connected by connection portion 142a.

[0162] In connection portion 142a, conductive layer 121c, conductive layer 122c, and conductive layer 123c are provided. In connection portion 142a, conductive layer 120a is electrically connected to conductive layer 123c through an opening provided in insulating layer 114 and insulating layer 116, and conductive layer 121c is electrically connected to conductive layer 104 through an opening provided in insulating layer 106. It is connected. It is connected. It is connected. It is connected.

[0163] Metal oxide layer 108 in transistor 100D is sandwiched between conductive layer 104 and conductive layer 120a. Conductive layer 104 and conductive layer 120a have lengths in the channel length direction and the channel width direction that are longer than the lengths in the channel length direction and the channel width direction of metal oxide layer 108, respectively. Therefore, metal oxide layer 108 has a configuration in which it is sandwiched between insulating layer 106, insulating layer 114, and insulating layer 116 and covered by conductive layer 104 and conductive layer 120a. In other words, in the channel width direction of transistor 100D, conductive layer 104 and conductive layer 120a have a configuration that surrounds metal oxide layer 108. It has a structure. In other words, in the channel width direction of transistor 100D, conductive layer 104 and conductive layer 120a have a configuration that surrounds metal oxide layer 108. It has a structure.

[0164] By adopting such a configuration, the metal oxide layer 108 of the transistor 100D can be electrically surrounded by the electric fields of the conductive layer 104 and the conductive layer 120a. The channel region can be electrically surrounded by the electric fields of the conductive layer 104 and the conductive layer 120a, such as in the case of the transistor 100D. The device structure of a transistor in which a metal oxide layer in which a channel region is formed is electrically surrounded by the electric fields of a conductive layer 104 and a conductive layer 120a can be called a Surrounded channel (S-channel) structure.

[0165] Since the transistor 100D has an S-channel structure, an electric field for inducing a channel can be effectively applied to the metal oxide layer 108 by the conductive layer 104 and the conductive layer 120a. Therefore, the driving ability of the transistor 100D is improved, and high on-current characteristics can be obtained. Also, since the on-current can be increased, the transistor 100D can be miniaturized. Further, since the transistor 100D has a structure in which the metal oxide layer 108 is surrounded by the conductive layer 104 and the conductive layer 120a, the mechanical strength of the transistor 100D can be increased.

[0166] Also, by adopting the above-described configuration, the regions where carriers flow in the metal oxide layer 108 are formed on both the conductive layer 104 side and the conductive layer 120a side of the metal oxide layer 108, resulting in a wide range. Therefore, the carrier mobility of the transistor 100D increases. As a result, the on-current of the transistor 100D can be increased compared to the case where a predetermined potential is applied to either the conductive layer 104 or the conductive layer 120a.

[0167] Note that, like the transistor 100E shown in FIGS. 7(A), 7(B), and 7(C), ​​​​​​​​​​The metal oxide layer 108 is then covered with a third metal oxide layer 108c. A first metal oxide layer 108a and a second metal oxide layer on the first metal oxide layer 108a. A laminated structure of 108b may also be used.

[0168] Also, as in the transistor 100F shown in FIG. 8(A), FIG. 8(B), and FIG. 8(C), The conductive layer 112c may not be provided. The conductive layer 104 is formed on the insulating layer 106, the insulating layer 114, and the insulating layer 116 through openings. 104 is electrically connected to the

[0169] The above is an explanation of configuration example 4.

[0170] <Configuration Example 5> FIG. 9A is a top view of a transistor 100G which is a semiconductor device of one embodiment of the present invention, and FIG. 9B is a cross-sectional view of the transistor 100G. The diagram is shown in FIG. 9(B) and FIG. 9(C). FIG. 9(B) shows the dashed line X1- 9(C) corresponds to a cross-sectional view taken along the dashed line Y1- This corresponds to the cross-sectional view taken at Y2.

[0171] The transistor 100G includes a metal oxide layer 108, a conductive layer 120a, and a conductive layer 120b. The transistor 100 differs from the transistor 100F illustrated in the above-described configuration example 4 in that an insulating layer 150 is provided between the is doing.

[0172] The insulating layer 150 covers the top and side surfaces of the metal oxide layer 108 and the insulating layer 106. The insulating layer 150 is formed by insulating a metal oxide when the conductive layer 112a and the conductive layer 112b are processed. It functions as a channel protection layer for protecting the oxide layer 108 .

[0173] Transistor 100G is a so-called channel protection type, dual-gate structure transistor. It is a type.

[0174] As the insulating layer 150, the same material as the above-described insulating layer 114a can be used.

[0175] The conductive layer 112a and the conductive layer 112b are respectively provided on the insulating layer 150. The conductive layer 112a is electrically connected to the metal oxide layer 108 by the connection portion 152a. The connection portion 152a, the conductive layer 112a is electrically connected to the metal oxide layer 108 through the opening provided in the insulating layer 150. The conductive layer 112b is electrically connected to the metal oxide layer 108 by the connection portion 152b. In the connection portion 152b, the conductive layer 112b is electrically connected to the metal oxide layer 108 through the opening provided in the insulating layer 150.

[0176] With such a configuration, in the etching process for processing the conductive layer 112a and the conductive layer 112b, since the metal oxide layer 108 is in a state covered by the insulating layer 150, a configuration can be achieved in which the metal oxide layer 108 is less likely to be damaged by etching. Also, with such a configuration, the range of material selection for the conductive layer 112a and the conductive layer 112b is broadened, which is preferable.

[0177] Here, the insulating layer 150 is configured to cover not only the upper surface but also the side surface of the metal oxide layer 108, but it is not limited to this. For example, the insulating layer 150 may be processed into an island shape and located above the channel formation region of the metal oxide layer 1 08.

[0178] The above is the description of Configuration Example 5.

[0179] <Components of the semiconductor device> Hereinafter, the components included in the semiconductor device of the present embodiment will be described in detail.

[0180] 〔Substrate〕 There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Also, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 102. When using a glass substrate as the substrate 102, by using a large area substrate such as the 6th generation (1500 mm × 1850 mm), 7th generation (1870 mm × 22 00 mm), 8th generation (2200 mm × 2400 mm), 9th generation (2400 mm × 28 00 mm), 10th generation (2950 mm × 3400 mm), etc., a large display device can be manufactured. Moreover, a flexible substrate may be used as the substrate 102, and transistors may be directly formed on the flexible substrate.

[0181] Alternatively, a release layer may be provided between the substrate 102 and the transistors. The release layer can be separated from the substrate 102 after partially or completely completing the semiconductor device thereon and transferred to another substrate. At that time, the transistors can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0182] 〔Conductive layer〕 The conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, the conductive layer 120b, and Then, it can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the aforementioned metal element as a component, or an alloy formed by combining the aforementioned metal elements, respectively. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. It can be formed.

[0183] Also, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. It can be formed.

[0184] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As the oxide conductor, for example, when an oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor. Generally, a metal oxide having semiconductor characteristics has a large energy gap and is thus transparent to visible light. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. In addition, for the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 120b, an oxide conductor or an oxide semiconductor such as an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten, and zinc (In-W-Zn oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium, and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin, and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) can also be applied. It has properties. On the other hand, the oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the influence of absorption by the donor level on the oxide conductor is small, and it has transparency comparable to that of a metal oxide having semiconductor properties with respect to visible light.

[0185] Also, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive layer 104, the conductive layer 112a, and the conductive layer 112b. By using the Cu-X alloy film, it can be processed in a wet etching process, so that the manufacturing cost can be controlled.

[0186] Also, among the aforementioned metal elements, the conductive layer 112a and the conductive layer 112b preferably have any one or more selected from among copper, titanium, tungsten, tantalum, and molybdenum. Further, when a copper film or an aluminum film is used as the conductive layer 112a and the conductive layer 112b, it is preferable because the resistance of the conductive layers 112a and 112b can be reduced.

[0187] 〔Insulating Layer〕 For the insulating layer 106 that functions as a gate insulating layer, an insulating layer containing one or more of a silicon oxynitride film, a silicon nitride film, Plasma Enhanced Chemical Vapor Depositio n), a silicon nitride film, an aluminum nitride film, an aluminum oxynitride film, etc., formed by a sputtering method or the like can be used. Note that the insulating layer 106 may have a laminated structure of two or more layers.

[0188] As the insulating layer 114a and the insulating layer 114b provided on the metal oxide layer 108, PE CVD method, sputtering method, ALD (Atomic Layer Deposition n) method, etc. film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, acid Tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film In particular, the insulating layer formed by the PECVD method can be used. It is preferable to use a silicon oxide film or a silicon oxynitride film.

[0189] The insulating layer 114a has a thickness of 5 nm to 150 nm, preferably 5 nm to 500 nm. An insulating film having a thickness of 0 nm or less can be suitably used.

[0190] It is preferable that the insulating layer 114a has a small amount of defects. Typically, the insulating layer 114a has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 due to the silicon dangling bond is 3 ×10 17 spins / cm 3 It is preferable that the number of defects contained in the insulating layer 114a is equal to or less than 1. If the defect density is high, oxygen is bound to the defects, and the oxygen permeability in the insulating layer 114a decreases. It ends up like this.

[0191] In addition, in the insulating layer 114a, all of the oxygen that has entered the insulating layer 114a from the outside is absorbed in the insulating layer 114a. Some oxygen does not move outside the insulating layer 114a and remains in the insulating layer 114a. a, and oxygen contained in the insulating layer 114a moves out of the insulating layer 114a. In some cases, oxygen transfer may occur in the insulating layer 114a. When an insulating film that can transmit oxygen is formed, the insulating layer 114a is provided on the insulating layer 114b. Oxygen that dissociates from the edge layer 114b can be transferred to the metal oxide layers 108a and 108b through the insulating layer 114a and the gold metal.

[0192] In addition, the insulating layer 114a can be formed using an insulating film with a low density of levels caused by nitrogen oxides. The density of levels caused by the nitrogen oxides may be formed between the energy (Ev_os) at the upper end of the valence band of the metal oxide film and the energy (Ec_ os) at the lower end of the conduction band of the metal oxide film. As the aforementioned insulating film, a silicon oxynitride film with a low emission amount of nitrogen oxides, an aluminum oxynitride film with a low emission amount of nitrogen oxides, or the like can be used. The energy at the upper end of the valence band of the metal oxide film and the energy at the lower end of the conduction band of the metal oxide film. formed between the energy (Ev_os) at the upper end of the valence band of the metal oxide film and the energy (Ec_ os) at the lower end of the conduction band of the metal oxide film. As the aforementioned insulating film, a silicon oxynitride film with a low emission amount of nitrogen oxides, an aluminum oxynitride film with a low emission amount of nitrogen oxides, or the like can be used. used.

[0193] A silicon oxynitride film with a low emission amount of nitrogen oxides is a film in which the ammonia emission amount is larger than the nitrogen oxide emission amount in temperature-programmed desorption gas analysis (TD S: Thermal Desorption Spectroscopy). Typically, the ammonia emission amount is 1×10 / cm or more and 5×10 18 / cm 3 or less. The ammonia emission amount is the emission amount by heat treatment when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. 19 / cm 3 emission amount is the emission amount by heat treatment when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. heating treatment. heating treatment.

[0194] Nitrogen oxides (NO x , where x is greater than 0 and less than or equal to 2, preferably 1 or more and 2 or less), typically NO 2 or NO form levels in the insulating layer 114a and the like. The levels are located within the energy gap between the metal oxide layer 108a and the metal oxide layer 108b. Therefore, the energy gap between the metal oxide layer 108a and the metal oxide layer 108b. Therefore, When nitrogen oxides diffuse to the interface between the insulating layer 114a and the metal oxide layer 108b, the level may trap electrons on the insulating layer 114a side. As a result, the trapped electrons stay near the interface between the insulating layer 114a and the metal oxide layer 108b, causing the threshold voltage of the transistor to shift in the positive direction.

[0195] In addition, nitrogen oxides react with ammonia and oxygen during heat treatment. The nitrogen oxides contained in the insulating layer 114 a react with the ammonia contained in the insulating layer 114b during heat treatment, so that the nitrogen oxides contained in the insulating layer 114a are reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating layer 1 14a and the metal oxide layer 108b.

[0196] By using the aforementioned insulating film as the insulating layer 114a, it is possible to reduce the shift of the threshold voltage of the transistor, and it is possible to reduce the variation in the electrical characteristics of the transistor.

[0197] In addition, the aforementioned insulating film has a nitrogen concentration measured by SIMS of 6×10 20 atoms / cm 3 or less.

[0198] When the substrate temperature is 220°C or higher and 350°C or lower, and the aforementioned insulating film is formed by using the PEC VD method using silane and dinitrogen monoxide, a dense and hard film can be formed.

[0199] The insulating layer 114b is an insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. A part of the oxygen in the aforementioned insulating film desorbs upon heating. In TDS, the aforementioned insulating film has an oxygen release amount of 1.0×10​​19 atoms / cm 3 Above, preferably 3.0× 10 20 atoms / cm 3 It has a region of the above. Also, the above-mentioned oxygen release amount is the total amount in the range where the heat treatment temperature in TDS is 50°C or higher and 650°C or lower, or 50°C or higher and 550°C or lower. It is the total amount within the range. Also, the above-mentioned oxygen release amount is the total amount in terms of oxygen atoms in TDS. As the insulating layer 114b, silicon oxide, silicon oxynitride, etc. with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less can be used. Also, the insulating layer 114b preferably has a small defect amount. Typically, from ESR measurement, the spin density of the signal appearing at g = 2.001 derived from silicon dangling bonds is less than 1.5×10

[0200] spins / cm 3

[0201] Furthermore, it is preferably less than 1×10 spins / cm 3 18 18

[0202] Since the insulating layer 114b is separated from the metal oxide layer 108a and the metal oxide layer 108b, it may have a higher defect density than the insulating layer 114a.

[0202] As the insulating layer 116 that functions as a protective layer, the above-mentioned materials can be used. The insulating layer 116 may have a laminated structure of two or more layers. It is preferable to use an insulating film in which oxygen is difficult to diffuse and permeate for the insulating layer 116. Also, it is preferable to use an insulating film in which the release of impurities is small and impurities are difficult to diffuse and permeate for the insulating layer 116. In particular, the insulating layer 116 contains hydrogen. It is preferable that the release of impurities is small and that impurities are difficult to diffuse and permeate.

[0203] As the insulating layer 116, an insulating film having a thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 1 50 nm or less can be preferably used.

[0204] 〔Semiconductor layer〕 As the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 08c, the materials shown above can be used.

[0205] As the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 1 08c is an In-M-Zn oxide, in order to form the In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used is preferably such that In > M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn = 1: 1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Z n = 3:1:2, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In :M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc. may be mentioned. In addition, when the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide

[0206] layer 108c are In-M-Zn oxides, as the sputtering target, it is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing polycrystalline In-M- Zn oxide, a metal oxide layer 108 having crystallinity can be formed Zn oxide. Zn oxide-containing target, a crystalline metal oxide layer 108 can be formed It becomes easier to form. The atomic ratio of the metal oxide layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the formed metal oxide layer 108 may be in the vicinity of In:G a:Zn = 4:2:3 [atomic ratio].

[0207] In addition, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c have an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a wide energy gap, the off current of the transistor can be reduced.

[0208] In addition, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c preferably have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC- OS (C Axis Aligned Crystalline Oxide Semi conductor), polycrystalline structure, microcrystalline structure, or amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0209] <Fabrication method of transistor 1> Hereinafter, an example of a method for manufacturing a transistor according to an aspect of the present invention will be described. Here, the transistor 100C illustrated in the above-described configuration example 3 will be described as an example.

[0210] Note that the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device are formed by sputtering ​Methods such as chemical vapor deposition (CVD), physical vapor deposition, pulse laser deposition (PLD), atomic layer deposition (ALD), etc. can be used for formation. As for CVD methods, there are plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. Also, one type of thermal CVD is metal organic chemical vapor deposition (MOCVD). , vacuum evaporation method, pulse laser deposition (PLD) ion method, atomic layer deposition (ALD) method, etc. can be used for formation. As for CVD methods, there are plasma enhanced chemical vapor deposition (PEC VD) method and thermal CVD method, etc. Also, one type of thermal CVD is metal organic chemical vapor deposition (MOCVD) method.

[0211] In addition, for the formation of thin films (such as insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices, spin coating, dipping, spray coating, droplet ejection methods (such as inkjet methods), printing methods (such as screen printing, offset printing, etc.), and equipment such as doctor knives, roll coaters, curtain coaters, and knife coaters can be used. coating, dipping, spray coating, droplet ejection method (such as inkjet method), printing method (such as screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater , knife coater, etc. can be used.

[0212] In addition, when processing thin films that make up semiconductor devices, methods such as photolithography can be used for processing. In addition to that, the thin film can also be processed by nanoimprint method, sandblasting method, lift-off method, etc. Also, island-shaped thin films can be directly formed by a film formation method using a shielding mask such as a metal mask. film formation method using a shielding mask such as a metal mask. film formation method using a shielding mask such as a metal mask.

[0213] Typically, there are two representative methods for photolithography. One is to form a resist mask on the thin film to be processed, process the thin film by etching, etc., and then remove the resist mask. The other is to form a photosensitive thin film and then perform exposure and development to process the thin film into a desired shape. thin film to be processed, process the thin film by etching, etc., and then remove the resist mask. The other is to form a photosensitive thin film and then perform exposure , development to process the thin film into a desired shape.

[0214] In the photolithography method, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Exposure may also be performed by immersion lithography technology. Also, instead of the light used for exposure, extreme ultraviolet light (EUV) or X-rays can be used. In addition, instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. In addition, when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0215] For the etching of the thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used.

[0216] Each of FIGS. 10 to 13 is a diagram for explaining the manufacturing method of the transistor 100C. In each figure, a cross section in the channel length direction is shown on the left side, and a cross section in the channel width direction is shown on the right side, respectively.

[0217] [Formation of the conductive layer 104] A conductive film is formed on the substrate 102, and the conductive film is processed through a lithography process and an etching process to form a conductive layer 104 that functions as a gate electrode.

[0218] [Formation of the insulating layer 106] An insulating layer 106 that covers the conductive layer 104 and the substrate 102 is formed (FIG. 10(A)). The insulating layer 106 can be formed using, for example, the PECVD method or the like.

[0219] In this embodiment, as the insulating layer 106, a silicon nitride film with a thickness of 400 nm can be used. The aforementioned silicon nitride film has a three-layer laminated structure including a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. As an example of the three-layer laminated structure, it can be formed as follows.

[0220] As the first silicon nitride film, for example, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm are used as source gases and supplied to the reaction chamber of a PE-CVD apparatus. The pressure in the reaction chamber is controlled to 100 Pa, and 2000 W of power is supplied using a 27.12 MHz high frequency power supply to form a film with a thickness of 50 nm. That's fine.

[0221] As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm and ammonia gas with a flow rate of 2000 sccm are used as source gases and supplied to the reaction chamber of a PECVD apparatus. The pressure in the reaction chamber is controlled to 100 Pa, and 2000 W of power is supplied using a 27.12 MHz high-frequency power supply to form a film with a thickness of 300 nm.

[0222] As the third silicon nitride film, the same film formation conditions as those of the first silicon nitride film are used, and the thickness is formed to be 50 nm.

[0223] Note that the substrate temperature during the formation of the aforementioned first silicon nitride film, second silicon nitride film, and third silicon nitride film can be 350°C or lower.

[0224] By forming the silicon nitride film into the three-layer laminated structure described above, for example, the conductive layer 104 can be made of copper. When a conductive film including the first silicon nitride film is used, the following effects are obtained. The second silicon nitride film can suppress the diffusion of copper elements from the first silicon nitride film 104. and improves the withstand voltage of the insulating film that functions as a gate insulating film. The third silicon nitride film has a low hydrogen release rate and The diffusion of hydrogen released from the second silicon nitride film can be suppressed.

[0225] [Formation of region 106a] Next, oxygen 130a is added to the insulating layer 106, and an oxygen-containing region 1 is formed near the surface. It is preferable to form 06a (FIG. 10(B)).

[0226] The oxygen 130a added to the insulating layer 106 may be an oxygen radical, an oxygen atom, or an oxygen atom ion. The methods of addition include ion doping, ion doping, and oxygen molecular ion doping. In addition, a film that suppresses oxygen desorption is formed on the insulating layer 106. After the formation of the film, oxygen 130a may be added to the insulating layer 106 through the film. It is preferable to add 30a and then remove it.

[0227] The above-mentioned oxygen desorption-suppressing films include those made of indium, zinc, gallium, tin, and aluminum. Aluminum, Chromium, Tantalum, Titanium, Molybdenum, Nickel, Iron, Cobalt, or Tungsten A conductive film or a semiconductor film having one or more tenn can be used.

[0228] In addition, when oxygen 130a is added in the plasma treatment, the oxygen is excited by microwaves and By generating dense oxygen plasma, the amount of oxygen added to the insulating layer 106 can be increased. Also, by performing plasma treatment in an atmosphere containing oxygen, water, hydrogen, etc. adsorbed on the surface of the insulating layer 106 can be removed. As a result, water or hydrogen that may be present in the later-formed metal oxide layer 108 or at the interface between the metal oxide layer 108 and the insulating layer 106 can be reduced.

[0229] When silicon nitride, silicon oxynitride, etc. are used as the insulating layer 106, hydrogen may be contained in the insulating layer 106. At this time, by performing plasma treatment or the like as described above, the hydrogen concentration in at least the region 106a in contact with the metal oxide layer 108 can be reduced.

[0230] Also, before adding oxygen 130a, a heat treatment may be performed to desorb water and hydrogen from the surface and inside the film of the insulating layer 106. For example, a heat treatment is performed at a temperature of 300°C or higher and lower than the heat resistance temperature of the conductive layer 104 in a nitrogen atmosphere, preferably at a temperature of 300°C or higher and 450°C or lower.

[0231] 〔Formation of Metal Oxide Layer 108〕 Subsequently, a metal oxide film 128a and a metal oxide film 128b are formed on the insulating layer 106 (Fig. 10(C)).

[0232] The metal oxide film 128a and the metal oxide film 128b are preferably formed by a sputtering method using a metal oxide target respectively.

[0233] Also, when forming the metal oxide film 128a and the metal oxide film 128b, in addition to oxygen gas, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) is mixed. ​​This is also acceptable. Note that the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio) is 0% or more and 100% or less, preferably 5% or more and 20% or less.

[0234] By reducing the oxygen flow rate ratio to form a metal oxide film with relatively low crystallinity, a highly conductive metal oxide film can be obtained. On the other hand, by increasing the oxygen flow rate ratio to form a metal oxide film with relatively high crystallinity, a metal oxide film with high etching resistance and electrical stability can be obtained.

[0235] For example, as the film-forming conditions for the metal oxide film 128a and the metal oxide film 128b, the substrate temperature may be room temperature or higher and 180°C or lower, preferably the substrate temperature may be room temperature or higher and 140°C or lower. If the substrate temperature during the formation of the metal oxide film is, for example, room temperature or higher and less than 140°C, the productivity will be high, which is preferable.

[0236] More specifically, the oxygen flow rate ratio during the formation of the metal oxide film 128a is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10% . The thickness of the metal oxide film 128a may be 1 nm or more and 50 nm or less, preferably 5 nm or more and 30 nm or less.

[0237] Also, the oxygen flow rate ratio during the formation of the metal oxide film 128b is 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, even more preferably 90% or more and 100% or less, and typically 100%. Also, for the metal oxide film 128a and the metal oxide film 128b, the conditions such as pressure, temperature, and power during film formation may be different, but ​​​​By keeping all other conditions the same except for the oxygen flow rate, the time required for the film formation process can be shortened. The thickness of the metal oxide film 128b is preferably greater than 10 nm and less than 100 nm. The thickness is preferably set to 20 nm or more and 50 nm or less.

[0238] The metal oxide film 128a and the metal oxide film 128b are films having different compositions. At this time, both the metal oxide film 128a and the metal oxide film 128b may be formed with In. When Ga-Zn oxide is used, the metal oxide film 128a has a higher luminance than the metal oxide film 128b. It is preferable to use an oxide target having a high In composition.

[0239] Next, a resist mask is formed on the metal oxide film 128b, and the metal oxide film 128a and After processing the metal oxide film 128b by etching, the resist mask is removed. Then, the metal oxide layer 108a and the metal oxide layer 108b are formed (FIG. 11(A)).

[0240] After the metal oxide layer 108a and the metal oxide layer 108b are formed, a heat treatment (hereinafter, The first heat treatment may be performed to form the metal oxide layer 108a and the In addition, hydrogen, water, and the like contained in the metal oxide layer 108b can be reduced. The heat treatment for the purpose of reducing the above-mentioned defects is carried out by dividing the metal oxide film 128a and the metal oxide film 128b into islands. The first heat treatment may be performed before processing the metal oxide layer. It could be said that it is one.

[0241] The first heat treatment is performed at a temperature of, for example, 150° C. or higher and lower than the distortion point of the substrate, preferably 200° C. °C or higher and 450 °C or lower, and more preferably 250 °C or higher and 350 °C or lower.

[0242] In addition, for the first heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using an RTA apparatus, the heat treatment can be performed at a temperature equal to or higher than the distortion point of the substrate in a short time. Therefore, it becomes possible to shorten the heating time. Also, the first heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less of air), or a noble gas (such as argon or helium). That is, it is preferable that hydrogen, water, etc. are not contained in the aforementioned nitrogen, oxygen, ultra-dry air, or noble gas. Further, after heat treatment in a nitrogen or noble gas atmosphere, heat treatment may be performed in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, etc. contained in the metal oxide layer can be desorbed, and oxygen can be supplied to the metal oxide layer. As a result, oxygen deficiency contained in the metal oxide layer can be reduced.

[0243] [Formation of Conductive Layers 112a and 112b] Subsequently, a conductive film 121 that will later become conductive layers 121a and 121b, and a conductive film 122 that will later become conductive layers 122a and 122b are laminated and formed.

[0244] Subsequently, a resist mask 131 is formed on the conductive film 122 (Fig. 11(B)). The resist mask 131 is provided with spaces on the region where channels of the metal oxide layer 108 can be formed.

[0245] Thereafter, the conductive film 122 is processed by etching to form conductive layers 122a and 122b (Fig. 11(C)). At this time, as shown in Fig. 11(C), the ends of the conductive layer 122a and the conductive layer 122b are processed so as to be located inside the ends of the resist mask 131. ​ It is preferable to do so.

[0246] For the etching of the conductive film 122, it is preferable to use an isotropic etching method. Preferably a wet etching method can be used. Thereby, etching can be performed so that the ends of the conductive layer 122a and the conductive layer 122b recede.

[0247] After the formation of the conductive layer 122a and the conductive layer 122b, the resist mask 131 is removed.

[0248] Subsequently, a conductive film 123 is formed covering the conductive layer 121a, the conductive layer 122a, and the conductive layer 122b. The conductive film 123 is a conductive film that will later become the conductive layer 123a and the conductive layer 123b.

[0249] Subsequently, a resist mask 132 is formed on the conductive film 123 (FIG. 12(A)). At this time, the resist mask 132 can be formed using the same photomask as the resist mask 131. Thereby, since the photomask can be made common, the manufacturing cost can be suppressed.

[0250] Subsequently, the conductive film 121 and the conductive film 123 are processed by etching to form the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b. At this time, it is preferable to process so that the ends of the conductive layer 121a and the conductive layer 123a are in contact and the conductive layer 122a is not exposed. At this time, it is preferable to process so that the ends of the conductive layer 121b and the conductive layer 123b are in contact and the conductive layer 122b is not exposed.

[0251] For the etching of the conductive film 121 and the conductive film 123, an anisotropic etching method is used. is preferred. Preferably, a dry etching method can be used. Thereby, the end portions of the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b do not recede so that they can be processed. Thereby, the conductive layer 121a can be formed so as to surround the conductive layer 122a and the conductive layer 123a. The conductive layer 121b and the conductive layer 123b can be formed so as to surround the conductive layer 122b In addition, the variation in the channel length of the transistor can be suppressed.

[0252] Also, by using the same conductive film for the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b, etching can be facilitated. Further, it is preferable because unevenness is less likely to be formed at the end portions of the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b.

[0253] Thereafter, the resist mask 132 is removed. Through the above steps, the conductive layer 112a and the conductive layer 112b can be formed (FIG. 12(B)).

[0254] 〔Formation of Insulating Layers 114 and 116〕 Subsequently, the insulating layer 114 and the insulating layer 116 are formed so as to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, and the like.

[0255] The insulating layer 114 is preferably formed, for example, in an atmosphere containing oxygen. In particular, it is preferably formed by the PEC VD method.

[0256] As the insulating layer 114, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a PECVD apparatus in an atmosphere containing oxygen. Thereby Thus, an insulating layer 114 with few defects can be obtained. In this case, as the source gas, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silicon fluoride, etc. Representative examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc. The insulating layer 114 can have a laminated structure including an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. In forming the insulating layer 114a, the flow rate of the oxidizing gas relative to the aforementioned depositable gas is set to be greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to be less than 100 Pa, preferably 50 Pa or less. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silicon fluoride, etc. Representative examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc. In forming the insulating layer 114a, the flow rate of the oxidizing gas relative to the aforementioned depositable gas is set to be greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to be less than 100 Pa, preferably 50 Pa or less. The insulating layer 114 can have a laminated structure including an insulating layer 114a and an insulating layer 114b on the insulating layer 114a.

[0257] In forming the insulating layer 114a, the flow rate of the oxidizing gas relative to the aforementioned depositable gas is set to be greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to be less than 100 Pa, preferably 50 Pa or less. In forming the insulating layer 114a, the flow rate of the oxidizing gas relative to the aforementioned depositable gas is set to be greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to be less than 100 Pa, preferably 50 Pa or less. In forming the insulating layer 114a, the flow rate of the oxidizing gas relative to the aforementioned depositable gas is set to be greater than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to be less than 100 Pa, preferably 50 Pa or less.

[0258] In this embodiment, as the insulating layer 114a, the temperature for holding the substrate 102 is set to 220 °C, silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (the power density is 1.6×10 In this embodiment, as the insulating layer 114a, the temperature for holding the substrate 102 is set to 220 °C, silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (the power density is 1.6×10 In this embodiment, as the insulating layer 114a, the temperature for holding the substrate 102 is set to 220 °C, silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (the power density is 1.6×10 In this embodiment, as the insulating layer 114a, the temperature for holding the substrate 102 is set to 220 °C, silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (the power density is 1.6×10 -2 W / cm 2 ) and the PECVD method is used to form a silicon oxynitride film. In this embodiment, as the insulating layer 114a, the temperature for holding the substrate 102 is set to 220 °C, silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (the power density is 1.6×10

[0259] As the insulating layer 114b, the substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 180 °C or higher and 280 °C or lower, more preferably 200 °C or higher and 240 °C or lower. Source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. The electrode provided in the processing chamber is supplied with 0.17 As the insulating layer 114b, the substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 180 °C or higher and 280 °C or lower, more preferably 200 °C or higher and 240 °C or lower. Source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. The electrode provided in the processing chamber is supplied with 0.17 As the insulating layer 114b, the substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 180 °C or higher and 280 °C or lower, more preferably 200 °C or higher and 240 °C or lower. Source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. The electrode provided in the processing chamber is supplied with 0.17 As the insulating layer 114b, the substrate placed in the evacuated processing chamber of the PECVD apparatus is held at 180 °C or higher and 280 °C or lower, more preferably 200 °C or higher and 240 °C or lower. Source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. The electrode provided in the processing chamber is supplied with 0.17 W / cm 2 or higher and 0.5 W / cm 2Hereinafter, more preferably 0.25 W / cm 2 or more and 0.3 5 W / cm 2 Under the condition of supplying high-frequency power of the following, a silicon oxide film or a silicon oxynitride film is formed.

[0260] As the film formation condition of the insulating layer 114b, by supplying the high-frequency power of the aforementioned power density in the reaction chamber of the aforementioned pressure, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As a result, the oxidation of the source gas proceeds, so the oxygen content in the insulating layer 114b becomes more than the stoichiometric composition. On the other hand, in the film formed at the aforementioned temperature, the bonding force between silicon and oxygen is weak, so a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result, an insulating film can be formed that contains more oxygen than the oxygen that satisfies the stoichiometric composition and a part of the oxygen desorbs by heating.

[0261] In the formation process of the insulating layer 114b, the insulating layer 114a serves as a protective film for the metal oxide layer 108. Therefore, the insulating layer 114b can be formed using high-frequency power with a high power density while reducing damage to the metal oxide layer 108.

[0262] In addition, in the film formation condition of the insulating layer 114b, by increasing the flow rate of the silicon-containing deposition gas with respect to the oxidizing gas, it is possible to reduce the amount of defects in the insulating layer 114b. As a result, the reliability of the transistor can be improved.

[0263] Although the configuration in which the insulating layer 114 has a two-layer structure of the insulating layer 114a and the insulating layer 114b has been described, one aspect of the present invention is not limited thereto. For example, the insulating layer 114 is the insulating layer 1 ​​​​​​​​​​​Either a single-layer structure of 14a or the insulating layer 114b may be used. The insulating layer 114 being a single layer structure is preferable as it can improve productivity. Also, the insulating layer 114 may have a laminated structure of three or more layers.

[0264] Subsequently, an insulating layer 116 is formed so as to cover the insulating layer 114b. The insulating layer 116 can be formed in the same manner as the insulating layer 106.

[0265] As the insulating layer 116, for example, a silicon nitride film is preferably used. Also, as the insulating layer 116, for example, it can be formed using a sputtering method or a PECVD method. For example, when forming the insulating layer 116 by the PECVD method, the substrate temperature is less than 400 °C, preferably less than 375 °C, and more preferably 180 °C or more and 350 °C or less. By setting the substrate temperature when forming the insulating layer 116 within the above range, a dense film can be formed, which is preferable. Also, by setting the substrate temperature when forming the insulating layer 116 within the above range, oxygen or excess oxygen in the insulating layer 114a and the insulating layer 114b can be moved to the metal oxide layer 108.

[0266] Also, when forming a silicon nitride film as the insulating layer 116 by the PECVD method, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as the source gases. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma and active species are generated. These active species break the bonds between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bond between silicon and nitrogen is promoted, and there are fewer bonds between silicon and hydrogen, fewer defects, and a dense silicon nitride film can be formed. ​​​​​​​​​​ This is possible. On the other hand, when the amount of ammonia relative to nitrogen is large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed, silicon and hydrogen bonds remain, and a silicon nitride film with a large amount of hydrogen and defects and a rough surface is formed. Therefore, in the source gas, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 times or more and 50 times or less, or 10 times or more and 50 times or less. By setting the flow rate ratio as described above, a dense silicon nitride film with less hydrogen and defects can be formed. This is possible. On the other hand, when the amount of ammonia relative to nitrogen is large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed, silicon and hydrogen bonds remain, and a silicon nitride film with a large amount of hydrogen and defects and a rough surface is formed. Therefore, in the source gas, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 times or more and 50 times or less, or 10 times or more and 50 times or less. By setting the flow rate ratio as described above, a dense silicon nitride film with less hydrogen and defects can be formed. For these reasons, in the source gas, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 times or more and 50 times or less, or 10 times or more and 50 times or less. For these reasons, in the source gas, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 times or more and 50 times or less, or 10 times or more and 50 times or less. By setting the flow rate ratio as described above, a dense silicon nitride film with less hydrogen and defects can be formed.

[0267] In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². 2 In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². -1 In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². 2 In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm². In this embodiment, as the insulating layer 116, a 100 nm thick silicon nitride film is formed using a PECVD apparatus with silane, nitrogen, and ammonia as source gases. The flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power source. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm². When the supplied power is converted to the power per unit area (power density), it is 1.7×10² W / cm².

[0268] The film formation temperature of the insulating layer 116 can be set higher than that of the insulating layers 114a and 114b. By setting a higher temperature, impurities such as hydrogen in the insulating layer 116 film can be reduced. Also, the substrate temperature during the formation of the insulating layer 116 can be set to the same temperature as that of the insulating layers 114a and 114b. By setting the same temperature, productivity can be increased. The film formation temperature of the insulating layer 116 can be set higher than that of the insulating layers 114a and 114b. By setting a higher temperature, impurities such as hydrogen in the insulating layer 116 film can be reduced. Also, the substrate temperature during the formation of the insulating layer 116 can be set to the same temperature as that of the insulating layers 114a and 114b. By setting the same temperature, productivity can be increased. The film formation temperature of the insulating layer 116 can be set higher than that of the insulating layers 114a and 114b. By setting a higher temperature, impurities such as hydrogen in the insulating layer 116 film can be reduced. Also, the substrate temperature during the formation of the insulating layer 116 can be set to the same temperature as that of the insulating layers 114a and 114b. By setting the same temperature, productivity can be increased. The film formation temperature of the insulating layer 116 can be set higher than that of the insulating layers 114a and 114b. By setting a higher temperature, impurities such as hydrogen in the insulating layer 116 film can be reduced. Also, the substrate temperature during the formation of the insulating layer 116 can be set to the same temperature as that of the insulating layers 114a and 114b. By setting the same temperature, productivity can be increased. The film formation temperature of the insulating layer 116 can be set higher than that of the insulating layers 114a and 114b. By setting a higher temperature, impurities such as hydrogen in the insulating layer 116 film can be reduced. Also, the substrate temperature during the formation of the insulating layer 116 can be set to the same temperature as that of the insulating layers 114a and 114b. By setting the same temperature, productivity can be increased.

[0269] ​ After forming the insulating layer 114a, without exposing the surface of the insulating layer 114a to the atmosphere, in a vacuum it is preferable to continuously form the insulating layer 114b. By forming continuously, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 1 14a. After forming the insulating layer 114b, without exposing the surface of the insulating layer 114b to the atmosphere, in a vacuum, continuously form the insulating layer 116 it is preferable. By forming continuously, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114b derived. It is more preferable to continuously form the insulating layer 114a, the insulating layer 114b, and the insulating layer 11 6. By forming continuously, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surfaces of the insulating layer 114a and the insulating layer 114b.

[0270] After forming the insulating layer 114a, the insulating layer 114b, and the insulating layer 116, it is preferable to perform a heat treatment (hereinafter referred to as the second heat treatment). By the second heat treatment, it is possible to reduce the nitrogen oxides contained in the insulating layer 114a, the insulating layer 114b, and the insulating layer 116. Or by the second heat treatment, a part of the oxygen contained in the insulating layer 114a and the insulating layer 114b is moved to the metal oxide layer 108, and it is possible to reduce the oxygen deficiency and VoH contained in the metal oxide layer 108 .

[0271] As the second heat treatment, for example, typically, it is less than 400 °C, preferably less than 375 °C, more preferably, 150 °C or more and 350 °C or less.

[0272] The second heat treatment is nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas and water atmosphere may be used. It is preferable that the mixture does not contain hydrogen, water, etc. The heat treatment may be performed using an electric furnace, RTA, etc. can be done.

[0273] Through the above steps, the transistor 100C can be manufactured.

[0274] <Transistor manufacturing method 2> The following describes a method for manufacturing a transistor 100, which is different from the method for manufacturing a transistor 100 shown in the first embodiment. A method for manufacturing C will be described below. The manufacturing method is the same as the above-described manufacturing method 1 of the transistor (see FIG. 12B).

[0275] [Formation of insulating layer 114] Next, an insulating film is formed to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, and the like. The insulating layer 114 is formed (FIG. 13(A)). Since the description of the manufacturing method 1 of the photoresist can be referred to, a detailed description is omitted. Alternatively, the insulating layer 114 may have a two-layer structure of the insulating layer 114a and the insulating layer 114b. For example, the insulating layer 114a or the insulating layer 114b may have a single layer structure. The insulating layer 114 may preferably have a single-layer structure, which can increase productivity. The insulating layer 114 may have a stacked structure of three or more layers.

[0276] [Heat Treatment] After the insulating layer 114 is formed, heat treatment is performed. After the insulating layer 114 is formed, heat treatment is performed. This can reduce the amount of nitrogen oxide contained in the insulating layer 114. According to this process, a part of the oxygen contained in the insulating layer 114 is transferred to the metal oxide layer 108, and the metal oxide It is possible to reduce oxygen deficiency and VoH contained in the oxide layer 108.

[0277] As the heat treatment, for example, typically, it is less than 400 °C, preferably less than 375 °C, and more preferably, it is 150 °C or higher and 350 °C or lower.

[0278] The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 p pm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.). It should be noted that it is preferable that hydrogen, water, etc. are not contained in the aforementioned nitrogen, oxygen, ultra-dry air, or noble gas. For this heat treatment, an electric furnace, RTA, etc. can be used.

[0279] 〔Formation of Insulating Layer 116〕 Next, an insulating layer 116 is formed so as to cover the insulating layer 114. Regarding the method for forming the insulating layer 116, since reference can be made to the description in the manufacturing method 1 of the transistor, detailed description is omitted.

[0280] Since reference can be made to the description in the manufacturing method 1 of the transistor for the heat treatment after the formation of the insulating layer 116, detailed description is omitted.

[0281] Through the above steps, the transistor 100C can be manufactured.

[0282] <Manufacturing Method 3 of Transistor> Hereinafter, a manufacturing method of the transistor 100C, which is different from the manufacturing method shown in the manufacturing method 1 of the transistor, will be described. Note that up to the formation of the conductive layer 112a and the conductive layer 112b, it is the same as the aforementioned manufacturing method 1 of the transistor (see Fig. 12(B)).

[0283] ​​〔Formation of Insulating Layer 114〕 Next, insulating layers 114a and 114b are formed so as to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, etc. (Fig. 13(A)). Regarding the method for forming the insulating layers 114a and 114b, reference can be made to the description of Manufacturing Method 1 of the transistor, and thus detailed description is omitted. After forming the insulating layer 114a, it is preferable to continuously form the insulating layer 114b in a vacuum without exposing the surface of the insulating layer 114a to the atmosphere. By forming continuously, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114a.

[0284]

[0285] 〔Formation of Insulating Layer 116〕 Next, an insulating layer 116 is formed so as to cover the insulating layer 114.

[0286] As the insulating layer 116, the materials described above can be used. For example, aluminum oxide can be used as the insulating layer 116. Also, for example, In-Ga-Zn oxide can be used as the insulating layer 116. In the case of In-Ga-Zn oxide, it is preferable that the ratio of gallium in its composition is larger than the ratio of indium (for example, the atomic ratio is In:Ga:Zn = 1:3:2), so that the band gap of the insulating layer 116 becomes larger. A sputtering apparatus can be used for the formation of the insulating layer 116. A cross-sectional schematic view of the inside of the film-forming apparatus when forming the insulating layer 116 on the insulating layer 114b is shown in Fig. 13(B). Fig. 13(B) schematically shows a target 191 installed inside the sputtering apparatus and a plasma 192 formed below the target 191.

[0287] ​​​​​​​​​​​​​First, when forming the insulating layer 116, plasma is discharged in an atmosphere containing oxygen gas. At this time, oxygen 130b is added to the insulating layer 114b which is the surface to be formed of the insulating layer 116. In addition, when forming the insulating layer 116, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed with the oxygen gas. Oxygen 130b may be supplied to the insulating layer 114a and the insulating layer 114b.

[0288] The ratio of oxygen gas in the entire film-forming gas when forming the insulating layer 116 is greater than 0% and 100% or less, preferably 10% or more and 100% or less, more preferably 30% or more and 100% or less.

[0289] After forming the insulating layer 114a, it is preferable to continuously form the insulating layer 114b in a vacuum without exposing the surface of the insulating layer 114a to the atmosphere. By continuously forming, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114a. After forming the insulating layer 114b, it is preferable to continuously form the insulating layer 116 in a vacuum without exposing the surface of the insulating layer 114b to the atmosphere. By continuously forming, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 114b. It is more preferable to continuously form the insulating layer 114a, the insulating layer 114b, and the insulating layer 116. By continuously forming, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surfaces of the insulating layer 114a and the insulating layer 114b.

[0290] After forming the insulating layer 114a, the insulating layer 114b, and the insulating layer 116, it is preferable to perform a heat treatment. By this heat treatment, the insulating layer 114a, the insulating layer 114b, and the insulating layer 116 contain The rare nitrogen oxides can be reduced. Alternatively, by the heat treatment, a part of the oxygen contained in the insulating layer 114a and the insulating layer 114b can be moved to the metal oxide layer 108, and the oxygen deficiency and VoH contained in the metal oxide layer 108 can be reduced.

[0291] Since the heat treatment after the formation of the insulating layer 116 can be referred to the description of the manufacturing method 1 of the transistor , the detailed description is omitted.

[0292] Through the above steps, the transistor 100C can be manufactured.

[0293] <Manufacturing Method 4 of Transistor> Hereinafter, a manufacturing method of the transistor 100C different from the manufacturing methods shown in the manufacturing method 1 of the transistor and the manufacturing method 3 of the transistor will be described. Note that until the formation of the conductive layer 112a and the conductive layer 112b, it is the same as the manufacturing method 1 of the transistor described above (refer to FIG. 12 (B)).

[0294] 〔Formation of Insulating Layer 114〕 Next, the insulating layer 114a and the insulating layer 114b are formed so as to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, etc. (FIG. 13(A)). Regarding the formation method of the insulating layer 114a and the insulating layer 114b, since the description of the manufacturing method 1 of the transistor can be referred to, the detailed description is omitted.

[0295] After forming the insulating layer 114a, it is preferable to continuously form the insulating layer 114b in a vacuum without exposing the surface of the insulating layer 114a to the atmosphere. By forming continuously, it is possible to suppress the adhesion of impurities derived from atmospheric components to the surface of the insulating layer 1 14a.

[0296] ​​After forming the insulating layer 114b, a heat treatment may be performed. By this heat treatment, the nitrogen oxides contained in the insulating layer 114a and the insulating layer 114b can be reduced. Also, by this heat treatment, a part of the oxygen contained in the insulating layer 114a and the insulating layer 114b can be moved to the metal oxide layer 1 08, and the oxygen deficiency, VoH, contained in the metal oxide layer 108 can be reduced.

[0297] The temperature of this heat treatment is typically 150°C or higher and 400°C or lower, preferably 300°C or higher and 400°C or lower, preferably 320°C or higher and 370°C or lower. This heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 1 0 ppb or less), or a noble gas (argon, helium, etc.). It should be noted that it is preferable that the aforementioned nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, etc. For this heat treatment, an electric furnace, an RTA apparatus, etc. can be used.

[0298] 〔Oxygen supply treatment〕 Next, a conductive film 134 is formed covering the insulating layer 114b (Fig. 14(A)).

[0299] As the conductive film 134, a metal oxide film, or a metal film or an alloy film can be used. The thickness of the conductive film 134 is preferably extremely thin, for example, 1 nm or more and 20 nm or less, preferably 2 nm or more and 15 nm or less, more preferably 3 nm or more and 10 nm or less, and typically can be about 5 nm.

[0300] Examples of the metal oxide that can be used for the conductive film 134 include In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, Examples include In-Zn oxides, In-Sn-Si oxides, In-Ga-Zn oxides, etc.

[0301] In addition, as the conductive film 134, aluminum, titanium, chromium, iron, cobalt, nickel , copper, zinc, gallium, molybdenum, silver, indium, tin, tantalum, tungsten, etc. A metal film or alloy film containing these can be used.

[0302] Note that as the conductive film 134, in addition to single substances such as silicon and germanium, semiconductor films containing these compound semiconductors, oxide semiconductors, etc. may also be used.

[0303] Here, when a metal oxide is used as the conductive film 134 and a film is formed by sputtering or the like in an atmosphere containing oxygen, it is preferable because oxygen can be supplied into the insulating layer 114a and the insulating layer 114b even during film formation.

[0304] The maximum temperature in the process of forming the conductive film 134 is 350 °C or lower, preferably 340 °C or lower , more preferably 330 °C or lower, and even more preferably 300 °C or lower.

[0305] Subsequently, a process of supplying oxygen 130c to the insulating layer 114a and the insulating layer 114b through the conductive film 134 (hereinafter also referred to as an oxygen supply process) is performed (Fig. 14(B)).

[0306] As the oxygen supply process, it is preferable to use a plasma process in an oxygen atmosphere (also referred to as an oxygen plasma process). When oxygen is made into plasma, oxygen radicals, oxygen atoms, or oxygen ions can be added to the insulating layer 114a and the insulating layer 114b through the conductive film 134. The higher the oxygen flow ratio in the gas introduced into the apparatus, the more preferable, and 50% ​​​​​​​100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 1 0% or less, and even more preferably 100%.

[0307] In particular, it is preferable to use a processing apparatus having a pair of parallel plate electrodes as the processing apparatus At this time, plasma processing is performed with a bias voltage applied between the pair of electrodes, and more oxygen can be supplied to the insulating layer 114a and the insulating layer 114b. The bi as voltage is applied, for example, so that oxygen ions in the oxygen plasma can easily move toward the substrate side Oxygen ions in the oxygen plasma, for example, O + or O 2+ etc. tend to carry a positive charge Therefore, when a bias voltage is applied so that the electrode located on the substrate side has a negative potential, oxygen ions tend to move toward the substrate side

[0308] Here, when oxygen supply treatment is directly performed on the insulating layer 114a and the insulating layer 114b without providing the conductive film 134, a part of the oxygen supplied to the insulating layer 114a and the insulating layer 114b may desorb to the outside again. However, in this manufacturing method example, since the conductive film 134 is provided on the insulating layer 114a and the insulating layer 114b, it is possible to prevent the oxygen supplied to the insulating layer 114a and the insulating layer 114b from desorbing to the outside again. In addition, the conductive film 134 can mitigate damage to the insulating layer 114a and the insulating layer 114b

[0309] Also, the conductive film 134 on the insulating layer 114a and the insulating layer 114b becomes more likely to attract ionized oxygen when a bias voltage is applied between the pair of electrodes in the oxygen supply treatment ​​​​The effect is achieved. Therefore, by providing the conductive film 134, a bias voltage can be applied. The effects due to this can be synergistically enhanced.

[0310] In addition, as a processing apparatus, a dry etching apparatus, an ashing apparatus, a PECVD apparatus, etc. is preferably used because other processes and apparatuses can be shared. In particular, it is preferable to use an ashing apparatus.

[0311] The oxygen supply process is, for example, at a temperature of room temperature or higher and 350°C or lower, preferably 150°C or higher and lower than 350°C , more preferably 200°C or higher and 340°C or lower.

[0312] In addition, when a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage may be, for example, 10 V or higher and 1 kV or lower. Alternatively, the power density of the bias may be, for example, 1 W / cm 2 or higher and 5 W / cm 2 or lower.

[0313] Note that the oxygen supply process is not limited to the above, and a method capable of supplying oxygen to the insulating layer 114a and the insulating layer 114b through the conductive film 134 can be used. For example, an ion implantation method, an ion doping method, or a plasma immersion ion implantation method, etc. can be used to supply oxygen to the insulating film through the conductive film. Alternatively, a heat treatment may be performed in an oxygen atmosphere . Even when such a process is used, the conductive film 134 functions as a cap film that prevents the oxygen supplied to the insulating layer 114a and the insulating layer 114b from desorbing, and functions as a relaxation layer that relaxes the damage to the insulating layer 114a and the insulating layer 114b. This can be achieved.

[0314] When the conductive film 134 is subjected to an oxygen supply process, it may become brittle. In particular, when a metal or an alloy is used for the conductive film 134, it may be oxidized by the oxygen supply process, resulting in a high resistance value or a part of it may be etched and thinned. In such a case, it is preferable to remove the conductive film 134 by etching.

[0315] FIG. 14(C) shows a cross-sectional view after the conductive film 134 has been etched.

[0316] The maximum temperature in the etching process of the conductive film 134 is 350°C or lower, preferably 340 °C or lower, more preferably 330°C or lower, and even more preferably 300°C or lower.

[0317] Note that, as the oxygen supply process, plasma treatment may be performed in an atmosphere containing oxygen without providing the conductive film 134. By not providing the conductive film 134, productivity can be increased.

[0318] [Formation of Insulating Layer 116] Next, an insulating layer 116 is formed so as to cover the insulating layer 114. Regarding the method of forming the insulating layer 116, reference can be made to the description of Manufacturing Method 1 of the transistor, and thus detailed description is omitted.

[0319] Through the above steps, the transistor 100C can be manufactured.

[0320] The above is the description of an example of the manufacturing method of the transistor.

[0321] The configuration examples, manufacturing method examples, and the corresponding drawings etc. exemplified in this embodiment can be implemented by appropriately combining at least a part of them with other configuration examples, manufacturing method examples, or drawings etc. ​​​

[0322] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. and implemented in combination.

[0323] (Embodiment 2) In this embodiment, an example of a display device having the transistors exemplified in the previous embodiment will be described. An example will be described.

[0324] <Configuration Example> FIG. 15(A) is a top view showing an example of a display device. The display device 700 shown in FIG. 15(A) includes a pixel portion 702 provided on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701, a sealant 712 disposed so as to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 provided to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 15(A), a display element is provided between the first substrate 701 and the second substrate 705. are sealed by In addition, the display device 700 has FPC terminal portions 708 (FPC: Flexible printed circuit) that are electrically connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. are sealed by Although not shown in FIG. 15(A), a display element is provided between the first substrate 701 and the second substrate 705. between them.

[0325] Further, the display device 700 has FPC terminal portions 708 (FPC: Flexible printed circuit) that are electrically connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. In addition, the display device 700 has FPC terminal portions 708 (FPC: Flexible printed circuit) that are electrically connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. circuit portion 706, and the gate driver circuit portion 706, respectively, in a region different from the region surrounded by the sealant 712 on the first substrate 701. provided. It is also the case that an FPC 716 is connected to the FPC terminal portion 708, and various signals etc. are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. Also, signal lines 710 are respectively connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals etc. supplied by the FPC 716 are given to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 via the signal lines 710.

[0326] Also, a plurality of gate driver circuit portions 706 may be provided in the display device 700. Also, as the display device 700, an example is shown in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702, but the configuration is not limited to this. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a source driver circuit or a gate driver circuit etc. is formed may be configured to be formed on the first substrate 701. Note that the connection method of the separately formed driving circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, etc. can be used.

[0327] Also, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 have a plurality of transistors, and are semiconductor devices according to one aspect of the present invention. ​​​​​​​​​​​​​​​​A transistor which is a device can be applied.

[0328] In addition, the display device 700 can have various elements. As an example of the element, for example, an electroluminescence (EL) element (including an EL element containing an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, etc.), a light-emitting transistor element (a transistor that emits light according to an electric current), an electron-emitting element, a liquid crystal element, an electronic ink element, an electrophoretic element, an electro-wetting element, a plasma display panel (PDP), a MEMS (Micro-Electro-Mechanical System) display (for example, a grating light valve (GLV), a digital micromirror device (DMD), a digital micro-shutter (DMS) element, an interferometric modulation (IMOD) element, etc.), a piezoelectric ceramic display, etc. can be mentioned.

[0329] In addition, as an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there is a field emission display (FED) or a SED method flat panel display (SED: Surface-conduction Electron-emitter Display), etc. As an example of a display device using a liquid crystal element, there are a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, a projection liquid crystal display), etc. As an example of a display device using an electronic ink element or an electrophoretic element, there is electronic paper, etc. Note that a transflective liquid crystal display or a reflective liquid crystal display ​​​​​​​​​​​When realizing, part or all of the pixel electrodes may have the function as a reflective electrode. For example, part or all of the pixel electrodes may contain aluminum, silver, etc. Furthermore, in that case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

[0330] Note that the display method in the display device 700 can use a progressive method, an interlace method, etc. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Or, like a pentile arrangement, one color element is composed of two of RGB, and different two colors are selected and configured by the color elements. Or, one or more colors such as yellow, cyan, and magenta may be added to RGB. Note that the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device.

[0331] Also, in order to perform full-color display of the display device using white light emission (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.), a coloring layer (also called a color filter) may be used. The coloring layer can be appropriately combined and used, for example, with red (R), green (G), blue (B ), yellow (Y), etc. By using the coloring layer , the color reproducibility can be improved compared to the case where the coloring layer is not used. At this time, the coloring layer By arranging a region having [it] and a region not having a coloring layer, the white light in the region not having a coloring layer may be directly used for display. By arranging a region partly not having a coloring layer, when displaying brightly, the decrease in luminance due to the coloring layer can be reduced, and the power consumption may be reduced by about 20% to 30%. However, when performing full-color display using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be caused to emit light from elements each having the respective emission color. By using a self-luminous element, the power consumption may be further reduced in some cases as compared with the case of using a coloring layer.

[0332] Also, as a colorization method, in addition to the method (color filter method) of converting a part of the light emitted from the aforementioned white light through a color filter into red, green, and blue, a method (three-color method) of using red, green, and blue light emissions respectively, or a method (color conversion method, quantum dot method) of converting a part of the light emitted from blue light emission into red or green may be applied. The display device 700A shown in FIG. 15(B) is a display device that can be suitably used for an electronic device having a large screen.

[0333] For example, it can be suitably used for a television device, a monitor device, a digital signage, etc. The display device 700A has a plurality of source driver ICs 721 and a pair of gate driver circuits 722.

[0334] The plurality of source driver ICs 721 are each attached to an FPC 723. Also, one terminal of the plurality of FPCs 723 is connected to the substrate 701, and the other terminal is connected to the printed circuit board 72

[0335] ​​They are each connected to 4. By bending the FPC 723, the printed circuit board 724 can be placed on the back side of the pixel portion 702 and mounted on the electrical device.

[0336] On the other hand, the gate driver circuit 722 is formed on the substrate 701. As a result, a narrow bezel electronic device can be realized.

[0337] With such a configuration, a large and high-resolution display device can be realized. For example, it can be applied to display devices with a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. Also, a display device with an extremely high resolution such as full high vision, 4K2K, or 8K4K can be realized.

[0338] <Cross-sectional configuration example> Hereinafter, a configuration using a liquid crystal element and an EL element as display elements will be described with reference to FIGS. 16 to 18. FIGS. 16 and 17 are cross-sectional views taken along the dashed-dotted line Q-R shown in FIG. 15(A), and show a configuration using a liquid crystal element as a display element. FIG. 18 is a cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 15, and shows a configuration using an EL element as a display element. FIG. 15 shows a cross-sectional view taken along the dashed-dotted line Q-R shown in FIG. 15, and shows a configuration using an EL element as a display element. configuration.

[0339] First, the common parts shown in FIGS. 16 to 18 will be described first, and then the different parts will be described below.

[0340] 〔Explanation regarding the common parts of the display device〕 The display device 700 shown in FIGS. 16 to 18 includes a routing wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Also, the routing wiring The line portion 711 has a signal line 710. The pixel portion 702 has a transistor 750 and a capacitive element 790. The source driver circuit portion 704 has a transistor 752 .

[0341] The transistor 750 and the transistor 752 can be the transistors exemplified in Embodiment 1.

[0342] The transistor used in this embodiment has an oxide semiconductor film with high purity and suppression of the formation of oxygen vacancies. This transistor can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be lengthened, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, resulting in an effect of suppressing power consumption.

[0343] In addition, the transistor used in this embodiment can obtain a relatively high field-effect mobility, so that high-speed driving is possible. For example, by using such a transistor capable of high-speed driving in a display device, the switching transistor of the pixel portion and the driver transistor used in the driving circuit portion can be formed on the same substrate. That is, since there is no need to use a semiconductor device formed by a silicon wafer or the like as a separate driving circuit, the number of parts of the semiconductor device can be reduced. Also, in the pixel portion, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0344] The capacitive element 790 is formed through a process of processing the same conductive film as the conductive film that functions as the first gate electrode of the transistor 750, and the lower electrode formed through this process, and the transistor 750 has It is formed through a process of processing the same conductive film that functions as the second gate electrode. It has an upper electrode. Also, between the lower electrode and the upper electrode, there is a transistor 750. It is formed through a process of forming the same insulating film that functions as the first gate insulating film of the transistor 750. The insulating film formed through this process, and an insulating film formed through a process of forming the same insulating film that functions as the protective insulating film on the transistor 750 are provided. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes.

[0345] Also, in FIGS. 16 to 18, a planarization insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitor element 790.

[0346] Also, in FIGS. 16 to 18, the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are illustrated as having the same structure, but it is not limited to this. For example, different transistors may be used for the pixel portion 702 and the source driver circuit portion 704. Specifically, a configuration in which a top-gate type transistor is used for the pixel portion 702 and a bottom-gate type transistor is used for the source driver circuit portion 704, or a configuration in which a bottom-gate type transistor is used for the pixel portion 702 and a top-gate type transistor is used for the source driver circuit portion 704 can be mentioned. Note that the aforementioned source driver circuit portion 704 may be read as a gate driver circuit portion.

[0347] Also, the signal line 710 is connected to the source electrodes and drain electrodes of the transistors 750 and 752. It is formed through the same process as the conductive film that functions. As the signal line 710, for example, when using a material containing copper element the signal delay and the like due to wiring resistance are small, and it becomes possible to display on a large screen.

[0348] Also, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 71 6. Note that the connection electrode 760 is formed through the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Also, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

[0349] Also, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Also, as the first substrate 701 and the second substrate 705, a flexible substrate may be used. Examples of the flexible substrate include a plastic substrate and the like.

[0350] Also, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer and is provided to control the distance ( cell gap) between the first substrate 701 and the second substrate 705. Note that as the structure 778, a spherical spacer may be used.

[0351] Also, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the colored film 736 are provided.

[0352] 〔Configuration example of a display device using a liquid crystal element〕 ​​​​​The display device 700 shown in FIG. 16 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 shown in FIG. 16 changes the alignment state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774, and controls the transmission and non-transmission of light to display an image.

[0353] In addition, the conductive film 772 is electrically connected to a conductive film that functions as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transparent to visible light,

[0354] for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that is reflective to visible light, for example, aluminum or a material containing silver may be used. When a conductive film that is reflective to visible light is used for the conductive film 772, the display device 700 becomes a reflective liquid crystal display device. Also, when a conductive film that is transparent to visible light is used for the conductive film 772 the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates sandwiching the liquid crystal element are provided.

[0355] When a conductive film that is reflective to visible light is used for the conductive film 772, the display device 700 becomes a reflective liquid crystal display device. Also, when a conductive film that is transparent to visible light is used for the conductive film 772 the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates sandwiching the liquid crystal element are provided.

[0356] ​Also, by changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. An example in this case is shown in FIG. 17. Also, the display device 700 shown in FIG. 17 is an example of a configuration using the horizontal electric field method (for example, FFS mode) as the driving method of the liquid crystal element. In the case of the configuration shown in FIG. 17, an insulating film 773 is provided on the conductive film 772, and a conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 has the function as a common electrode (also referred to as a common electrode), and the alignment state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773.

[0357] Although not shown in FIGS. 16 and 17, a configuration may be adopted in which an alignment film is provided on either one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Also, although not shown in FIGS. 16 and 17, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source.

[0358] When using a liquid crystal element as the display element, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

[0359] Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. ​​​​​​​​​​​​The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational angle and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the occurrence of defects or damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0360] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0361] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0362] 〔Display device using a light-emitting element〕 The display device 700 shown in FIG. 18 has a light-emitting element 782. The light-emitting element 782 has a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 18 forms an image by the light emission of the EL layer 786 included in the light-emitting element 782 provided for each pixel. Note that the EL layer 786 contains an organic compound or an inorganic compound such as a quantum dot.

[0363] Examples of materials that can be used for the organic compound include a fluorescent material or a phosphorescent material. Examples of materials that can be used for the quantum dot include a colloidal quantum dot material, an alloy-type quantum dot material, a core-shell-type quantum dot material, and a core-type quantum dot material. In addition, materials containing elemental groups of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, a quantum dot material having elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), aluminum (Al), etc. may be used.

[0364] In the display device 700 shown in FIG. 18, an insulating film 7 30 is provided on the planarization insulating film 770 and the conductive film 772. The insulating film 730 covers a part of the conductive film 772. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency, and the EL layer 7 It transmits the light emitted by 86. In the present embodiment, although an example of a top emission structure is given, it is not limited thereto. For example, it can also be applied to a bottom emission structure that emits light to the side of the conductive film 772, or a dual emission structure that emits light to both the conductive film 772 and the conductive film 788. Regarding this, an example is given, but it is not limited thereto. For example, a bottom emission structure that emits light to the side of the conductive film 772, or a dual emission structure that emits light to both the conductive film 772 and the conductive film 788 can also be applied.

[0365] Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted. Also, a colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Moreover, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 18, although an example of a configuration in which the colored film 736 is provided is given, it is not limited thereto. For example, in a case where the EL layer 786 is formed in an island shape for each pixel, that is, formed by painting, a configuration in which the colored film 736 is not provided may be adopted.

[0366] 〔Configuration example of providing an input / output device to the display device〕 Moreover, an input / output device may be provided to the display device 700 shown in FIGS. 16 to 18. Examples of the input / output device include a touch panel and the like. Moreover, an input / output device may be provided to the display device 700 shown in FIGS. 16 to 18. Examples of the input / output device include a touch panel and the like.

[0367] The configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 17 is shown in FIG. 19, and the configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 18 is shown in FIG. 20, respectively. The configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 17 is shown in FIG. 19, and the configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 18 is shown in FIG. 20, respectively.

[0368] FIG. 19 is a cross-sectional view of the configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 17, and FIG. 20 is a cross-sectional view of the configuration in which a touch panel 791 is provided to the display device 700 shown in FIG. 18. It is.

[0369] First, the touch panel 791 shown in FIGS. 19 and 20 will be described below.

[0370] The touch panel 791 shown in FIGS. 19 and 20 is a so-called in-cell type touch panel provided between the substrate 705 and the colored film 736. The touch panel 791 may be formed on the substrate 705 side before forming the light shielding film 738 and the colored film 736. Note that the touch panel 791 includes a light shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, it is possible to detect a change in capacitance between the electrode 793 and the electrode 794 that may occur when a detection object such as a finger or a stylus approaches.

[0371] Also, above the transistor 750 shown in FIGS. 19 and 20, the intersection of the electrode 793 and the electrode 794 is clearly shown. The electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. In FIGS. 19 and 20, a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702 is illustrated, but it is not limited thereto. For example, it may be formed in the source driver circuit portion 704.

[0372] The electrodes 793 and 794 are provided in a region overlapping the light shielding film 738. Also, as shown in FIG. 19, it is preferable that the electrode 793 is provided so as not to overlap the light emitting element 782. Further, as shown in FIG. 20, it is preferable that the electrode 793 is provided so as not to overlap the liquid crystal element 775. In other words, the electrode 793 does not overlap the light emitting element 782 and the liquid crystal element 775.

[0373] It has an opening in the region. That is, the electrode 793 has a mesh shape. With such a configuration, the electrode 793 can be configured not to block the light emitted by the light-emitting element 782. Or, the electrode 793 can be configured not to block the light transmitted through the liquid crystal element 775. Therefore, since the decrease in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and reduced power consumption can be realized. Note that the electrode 794 may have the same configuration. By adopting such a configuration, the electrode 793 can be made not to block the light emitted by the light-emitting element 782. Or, the electrode 793 can be made not to block the light transmitted through the liquid crystal element 775. Therefore, since the decrease in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and reduced power consumption can be realized. Note that the electrode 794 may have the same configuration.

[0374] Also, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, a metal material with a low transmittance of visible light can be used for the electrodes 793 and 794. Or, since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, a metal material with a low transmittance of visible light can be used for the electrodes 793 and 794. Therefore, compared with electrodes using an oxide material with a high transmittance of visible light, the resistance of the electrodes 793 and 794 can be lowered, and the sensor sensitivity of the touch panel can be improved. Also, since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, a metal material with a low transmittance of visible light can be used for the electrodes 793 and 794.

[0375] Therefore, compared with electrodes using an oxide material with a high transmittance of visible light, the resistance of the electrodes 793 and 794 can be lowered, and the sensor sensitivity of the touch panel can be improved.

[0376] For example, conductive nanowires may be used for the electrodes 793, 794, and 796. The average diameter of the nanowires may be 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, more preferably 5 nm or more and 25 nm or less. Also, as the aforementioned nanowires, metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires, or carbon nanotubes may be used. For example, when Ag nanowires are used for any one or all of the electrodes 664, 665, and 667, in visible light ​​​​​​​​​ The light transmittance can be 89% or more, and the sheet resistance value can be 40 Ω / sq or more and 100 Ω / sq or less. It can be achieved.

[0377] In FIGS. 19 and 20, the configuration of an in-cell type touch panel is illustrated, but it is not limited thereto. For example, a so-called on-cell type touch panel formed on the display device 700, or a so-called out-cell type touch panel attached to and used with the display device 700 may be used.

[0378] As described above, the display device according to one aspect of the present invention can be used in combination with various types of touch panels. It can be used in combination.

[0379] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. It can be implemented in combination.

[0380] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention will be described with reference to FIG. 21. It will be described using FIG. 21.

[0381] <Circuit Configuration of Display Device> The display device shown in FIG. 21(A) includes a region having pixels of display elements (hereinafter referred to as a pixel portion 502), a circuit portion disposed outside the pixel portion 502 and having a circuit for driving the pixels (hereinafter referred to as a driving circuit portion 504), a circuit having an element protection function (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may not be provided. It may not be provided.

[0382] Part or all of the driving circuit portion 504 is formed on the same substrate as the pixel portion 502. This is desirable. This can reduce the number of components and terminals. The drive circuit section 504 If part or all of the drive circuit section 504 is not formed on the same substrate as the pixel section 502, part or all of the drive circuit section 504 can be mounted by COG or TAB (Tape Automated Bonding). The pixel section 502 has a circuit (hereinafter referred to as the pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The drive circuit section 504 has drive circuits such as a circuit (hereinafter referred to as the gate driver 504a) that outputs a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as the source driver 504b) that supplies a signal (data signal) for driving the display elements of the pixel. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal.

[0383] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) and has a circuit (hereinafter referred to as the pixel circuit 501) for driving a plurality of display elements. The drive circuit section 504 has drive circuits such as a circuit (hereinafter referred to as the gate driver 504a) that outputs a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as the source driver 504b) that supplies a signal (data signal) for driving the display elements of the pixel. The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) and has a circuit (hereinafter referred to as the pixel circuit 501) for driving a plurality of display elements. The drive circuit section 504 has drive circuits such as a circuit (hereinafter referred to as the gate driver 504a) that outputs a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as the source driver 504b) that supplies a signal (data signal) for driving the display elements of the pixel. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal.

[0384] The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal. The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal section 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 504a can also supply another signal.

[0385] The source driver 504b has a shift register and the like. The source driver 504b receives, via the terminal portion 507, not only a signal for driving the shift register but also a signal (image signal) that serves as the source of the data signal. The source driver 504b has a function of generating a data signal to be written into the pixel circuit 501 based on the image signal. Further, the source driver 504b has a function of controlling the output of the data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, and the like. Also, the source driver 504b has a function of controlling the potential of a wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is supplied. Or, the source driver 504b has a function of being able to supply an initialization signal. However, it is not limited to this, and the source driver 504b can also supply other signals.

[0386] The source driver 504b is configured using, for example, a plurality of analog switches and the like. The source driver 504b can output, as a data signal, a signal obtained by time-division multiplexing the image signal by sequentially turning on a plurality of analog switches. Also, the source driver 504b may be configured using a shift register or the like.

[0387] Each of the plurality of pixel circuits 501 receives a pulse signal via one of a plurality of scanning lines GL to which a scanning signal is supplied, and receives a data signal via one of a plurality of data lines DL to which the data signal is supplied. Also, for each of the plurality of pixel circuits 501, the writing and holding of the data of the data signal are controlled by the gate driver 504a. For example, the pixel circuit 501 at the m-th row and n-th column receives the gate driver via the scanning line GL_m (m is a natural number less than or equal to X). ​​​​​​​​​​​ A pulse signal is input from 504a, and a data signal is input from the source driver 504b via the data line DL_n ( n is a natural number less than or equal to Y) according to the potential of the scanning line GL_m.

[0388] The protection circuit 506 shown in FIG. 21(A) is connected to, for example, the scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 5 01. Alternatively, the protection circuit 506 may be connected to the data line DL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 refers to a portion provided with terminals for inputting power supply, control signals, and image signals from an external circuit to the display device.

[0389]

[0390] The protection circuit 506 is a circuit that makes the wiring to which it is connected and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected.

[0390] As shown in FIG. 21(A), by providing the protection circuits 50 6 in the pixel portion 502 and the drive circuit portion 504 respectively, the resistance of the display device against overcurrent generated by ESD (Electro Static Discharge: electrostatic discharge) and the like can be enhanced. However, the configuration of the protection circuit 506 is not limited to this. For example, a configuration in which the protection circuit 506 is connected to the gate driver 504a, or a configuration in which the protection circuit 506 is connected to the source driver 504b can also be adopted. Alternatively, a configuration in which the protection circuit 506 is connected to the terminal portion 507 can also be adopted.

[0391] ​ Also, in FIG. 21(A), an example is shown in which a gate driver 504a and a source driver 504b form a driving circuit section 504, but the configuration is not limited to this. For example, only the gate driver 504a may be formed, and a separately prepared source driver circuit may be mounted on a substrate (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film). Here, FIG. 22 shows a configuration different from that of FIG. 21(A). In FIG. 22, a pair of source lines (for example, source line DLa1 and source line DLb1) are arranged so as to sandwich a plurality of pixels arranged in the source line direction. Also, two adjacent gate lines (for example, gate line GL_1 and gate line GL_2) are electrically connected.

[0392] Moreover, the pixels connected to the gate line GL_1 are connected to one of the source lines (source line DLa1, source line DLa2, etc.), and the pixels connected to the gate line GL_2 are connected to the other source line (source line DLb1, source line DLb2, etc.). With such a configuration, two gate lines can be selected simultaneously. As a result, the length of one horizontal period can be doubled compared to the configuration shown in FIG. 21(A).

[0393] This makes it easier to increase the resolution and the size of the display device. Also, the plurality of pixel circuits 501 shown in FIG. 21(A) can have, for example, the configuration shown in FIG. 21(B). (The pixel circuit 501 shown in FIG. 21(B) includes a liquid crystal element 570, a transistor 550, and a capacitor.)

[0394] By adopting such a configuration, two gate lines can be selected simultaneously. As a result, the length of one horizontal period can be doubled compared to the configuration shown in FIG. 21(A). This makes it easier to increase the resolution and the size of the display device. Moreover, the plurality of pixel circuits 501 shown in FIG. 21(A) can have, for example, the configuration shown in FIG. 21(B).

[0395] The pixel circuit 501 shown in FIG. 21(B) includes a liquid crystal element 570, a transistor 550, and a capacitor. and can be configured as shown in FIG. 21(B).

[0396] The pixel circuit 501 shown in FIG. 21(B) includes a liquid crystal element 570, a transistor 550, and a capacitor. It has a quantum element 560 and a transistor 550. The transistor shown in the previous embodiment can be applied to the transistor 550. It can be applied.

[0397] One of the potentials of a pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The liquid crystal element 570 has its alignment state set according to the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row.

[0398] For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode may be used. Also, as a driving method of the display device, in addition to the driving methods described above, an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest - host mode, ​ There are modes such as the storm mode. However, it is not limited to this, and various liquid crystal elements and their driving methods can be used.

[0399] In the pixel circuit 501 at the m-th row and n-th column, one of the source electrode or drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Also, the gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling the writing of data of the data signal by being turned on or off.

[0400] One of the pair of electrodes of the capacitive element 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitive element 560 has a function as a holding capacitance for holding the written data.

[0401] For example, in a display device having the pixel circuit 501 shown in FIG. 21(B), for example, each pixel circuit 501 in each row is sequentially selected by the gate driver 504a shown in FIG. 21(A), and the transistor 550 is turned on to write the data of the data signal.

[0402] The pixel circuit 501 in which data has been written enters a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

[0403] Also, the plurality of pixel circuits 501 shown in FIG. 21(A) can have a configuration as shown in FIG. 21(C), for example. ​

[0404] Further, the pixel circuit 501 shown in FIG. 21(C) includes transistors 552 and 554, a capacitor element 562, and a light-emitting element 572. Either one or both of the transistors 552 and 554 can be applied with the transistors shown in the previous embodiments. .

[0405] One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 55 2 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0406] The transistor 552 has a function of controlling the writing of data of the data signal by being turned on or off.

[0407] One of a pair of electrodes of the capacitor element 562 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL _a) to which a potential is supplied, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

[0408] The capacitor element 562 has a function as a holding capacitor for holding the written data.

[0409] One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

[0410] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b One is electrically connected to the other of the source electrode and the drain electrode of the transistor 554 and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554

[0411] As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this and an inorganic EL element made of an inorganic material may be used

[0412] Note that a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b and a low power supply potential VSS is applied to the other

[0413] In the display device having the pixel circuit 501 in FIG. 21(C), for example, each row of pixel circuits 501 is sequentially selected by the gate driver 504a shown in FIG. 21(A), and the transistor 552 is turned on to write the data of the data signal When the data is written, the pixel circuit 501 enters a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with a luminance corresponding to the amount of current flowing

[0414] By sequentially performing this for each row, an image can be displayed

[0415]

[0416] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification

[0417] (Embodiment 4) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to the drawings

[0417] The electronic device exemplified below includes the display device according to one aspect of the present invention in a display unit. Therefore, it is an electronic device with high resolution realized. Also, high resolution and a large screen can be made compatible.

[0418] In the display unit of the electronic device according to one aspect of the present invention, for example, video with a resolution of full high vision, 4K2K, 8K4 K, 16K8K, or higher can be displayed. Also , as the screen size of the display unit, it can be 20 inches or more in diagonal, or 30 inches or more in diagonal, or it can also be 50 inches or more in diagonal, 60 inches or more in diagonal, or 70 inches or more in diagonal.

[0419] Examples of the electronic device include relatively large screen electronic devices such as television sets, desktop or notebook personal computers, monitors for computers, digital signage, large game machines such as pachinko machines, and in addition, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, and the like.

[0420] The electronic device or lighting device according to one aspect of the present invention can be incorporated along the inner wall or outer wall of a house or building, or along the curved surface of the interior or exterior of an automobile.

[0421] The electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, video, information, etc. can be displayed on the display unit. Also, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission. ​​​​​

[0422] An electronic device according to one aspect of the present invention may include a sensor (which has a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power , radiation, flow rate, humidity, gradient, vibration, odor or infrared rays). It may have.

[0423] An electronic device according to one aspect of the present invention can have various functions. For example, various information (such as still images, moving images, text images, etc.) can be displayed on a display unit, a touch panel function, a calendar , a function of displaying a date or time, etc., a function of executing various software (programs), a wireless communication function, a function of reading a program or data recorded on a recording medium and the like. It can have functions such as.

[0424] Fig. 23(A) shows an example of a television device. The television device 7100 has a display unit 7 000 incorporated in a housing 7 101. Here, a configuration in which the housing 7

[0425] 101 is supported by a stand 7103 is shown.

[0426] The operation of the television device 7100 shown in Fig. 23(A) can be performed by operation switches provided in the housing 7101 or by a separate remote control operation unit 7111. Alternatively, the display unit 70 00 may be provided with a touch sensor, and the operation may be performed by touching the display unit 7000 with a finger or the like. The remote control operation unit 7111 may have a display unit for displaying information output from the remote control operation unit 7111. Operation keys or touchs provided in the remote control operation unit 7111 may be used. ​The channel panel can be used to operate the channel and volume, and can also be used to operate the video displayed on the display unit 7000.

[0427] Note that the television device 7100 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0428] Figure 23(B) shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. The display unit 7000 is incorporated in the housing 7211.

[0429] The display device according to one aspect of the present invention can be applied to the display unit 7000.

[0430] Figures 23(C) and (D) show an example of digital signage.

[0431] The digital signage 7300 shown in Figure 23(C) has a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it can have an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0432] Also, Figure 23(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. ​​​​​​​​​​​​It is 0. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401. It has 7000.

[0433] In FIGS. 23(C) and (D), the display device according to one aspect of the present invention can be applied to the display unit 7000. It can be done.

[0434] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the easier it is to catch people's eyes, for example, the advertising effect can be enhanced. The larger the display unit 7000, the easier it is to catch people's eyes, for example, the advertising effect can be enhanced. It can be done.

[0435] By applying a touch panel to the display unit 7000, not only can an image or video be displayed on the display unit 7000, but also the user can operate it intuitively, which is preferable. Also, when used for applications such as providing route information or traffic information, the usability can be enhanced by intuitive operation. By applying a touch panel to the display unit 7000, not only can an image or video be displayed on the display unit 7000, but also the user can operate it intuitively, which is preferable. Also, when used for applications such as providing route information or traffic information, the usability can be enhanced by intuitive operation. When used for applications such as providing route information or traffic information, the usability can be enhanced by intuitive operation. When used for applications such as providing route information or traffic information, the usability can be enhanced by intuitive operation.

[0436] Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Also, as shown in FIGS. 23(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of wireless communication with an information terminal 7311 such as a smartphone held by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Also, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched.

[0437] Also, a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller) can be implemented on the digital signage 7300 or the digital signage 7400. Also, a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller) can be implemented on the digital signage 7300 or the digital signage 7400. It can also be made to do so. As a result, an unspecified number of users can participate in the game simultaneously and enjoy themselves.

[0438] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0439] (Embodiment 5) In this embodiment, an example of a television device to which a display device according to an aspect of the present invention can be applied will be described with reference to the drawings.

[0440] FIG. 24(A) shows a block diagram of a television device 600.

[0441] Note that in the drawings attached to this specification, the components are classified by function and shown as independent blocks in a block diagram. However, in actuality, it is difficult to completely separate the components by function, and one component may be related to multiple functions.

[0442] The television device 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder circuit 605, a video signal receiving unit 606, a timing controller 607, a source driver 608, a gate driver 609, a display panel 620, and the like.

[0443] The display device exemplified in the foregoing embodiment can be applied to the display panel 620 in FIG. 24(A). As a result, a television device 600 that is large, has high resolution, and has excellent visibility can be realized.

[0444] The control unit 601 is, for example, a central processing unit (CPU: Central Processing ​​​​​​​It can function as a g Unit). For example, the control unit 601 is connected to the memory unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605 and other components such as the video signal receiving unit 606 via the system bus 63 and has the function of controlling these components.

[0445] Signals are transmitted between the control unit 601 and each component via the system bus 630. In addition, the control unit 601 has functions such as processing signals input from each component connected via the system bus 630 and generating signals to be output to each component. By doing so, it can comprehensively control each component connected to the system bus 630.

[0446] The memory unit 602 functions as registers, cache memories, main memories, secondary memories, etc. that can be accessed by the control unit 601 and the image processing circuit 604.

[0447] As a storage device that can be used as a secondary memory, for example, a storage device to which a rewritable non-volatile memory element is applied can be used. For example, flash memory, MRAM (Magnetoresistive Random Access Memo ry), PRAM (Phase change RAM), ReRAM (Resisti ve RAM), FeRAM (Ferroelectric RAM), etc. can be used.

[0448] In addition, as a storage device that can be used as a temporary memory such as registers, cache memories, and main memories, DRAM (Dynamic RAM), SRAM (Sta tic RAM), etc. can be used. It is also possible to use a volatile memory device such as a (tic Random Access Memory). This is acceptable.

[0449] For example, as the RAM provided in the main memory, for example, DRAM is used, and a memory space is virtually allocated and used as the working space of the control unit 601. The operating system, application programs, program modules, program data, etc. stored in the storage unit 602 are loaded into the RAM for execution. These data, programs, and program modules loaded into the RAM are directly accessed and operated on by the control unit 601.

[0450] On the other hand, the ROM can store a BIOS (Basic Input / Output System) and firmware that do not require rewriting. As the ROM, a mask ROM, an OTPROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), etc. can be used. As the EPROM, a UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory) that enables erasure of stored data by ultraviolet irradiation, an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory, etc. can be mentioned.

[0451] In addition to the storage unit 602, it may also be configured to be able to connect a removable storage device. For example, a hard disk drive (Hard Disk Drive: HDD) or a solid state drive (Solid State Dri ve: SSD), etc., a recording media drive, a flash memory, a Blu-ray disc, It is preferable to have a terminal for connecting to a recording medium such as a DVD. Thereby, video can be recorded .

[0452] The communication control unit 603 has a function of controlling communication performed via a computer network . For example, in response to an instruction from the control unit 601, it controls a control signal for connecting to a computer network and transmits the signal to the computer network. Thereby , it can connect to a computer network such as the Internet, which is the basis of the World Wide Web (WWW), an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), a GAN (Global Area N etwork), etc. and perform communication.

[0453] In addition, the communication control unit 603 may have a function of communicating with a computer network or other electronic devices using communication standards such as Wi-Fi (registered trademark), Bluetooth (registered trademark ).

[0454] The communication control unit 603 may have a function of communicating wirelessly. For example, an antenna and A high-frequency circuit (RF circuit) may be provided to transmit and receive RF signals. The high-frequency circuit mutually converts electromagnetic signals and electrical signals in a frequency band defined by national laws and is a circuit for performing wireless communication with other communication devices using the electromagnetic signals. As practical frequency bands, several tens of kHz to several tens of GHz are generally used. The high-frequency circuit connected to the antenna has high-frequency circuit parts corresponding to a plurality of frequency bands, and the high-frequency circuit parts may be configured to have an amplifier (amp), mixer, filter, DSP, RF transceiver, etc. (amp), mixer, filter, DSP, RF transceiver, etc. It can be done.

[0455] The video signal receiving unit 606 has, for example, an antenna, a demodulation circuit, and an A-D conversion circuit (analog -digital conversion circuit), etc. The demodulation circuit has a function of demodulating the signal input from the antenna. The A-D conversion circuit has a function of converting the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605. It is sent. It is sent.

[0456] The decoder circuit 605 has a function of decoding the video data included in the digital signal input from the video signal receiving unit 606 according to the specifications of the broadcast standard to be transmitted and generating a signal to be transmitted to the image processing circui...

Claims

1. A substrate; a first conductive layer having a region in contact with an upper surface of the substrate and a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a second insulating layer having a region in contact with an upper surface of the first insulating layer and a region functioning as a gate insulating film; a metal oxide layer having a region in contact with an upper surface of the second insulating layer and a region that functions as a channel formation region; a second conductive layer having a region in contact with an upper surface of the metal oxide layer and functioning as one of a source electrode and a drain electrode; a third conductive layer having a region in contact with an upper surface of the metal oxide layer and a region functioning as the other of the source electrode and the drain electrode; a third insulating layer having a region in contact with an upper surface of the metal oxide layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; a fourth insulating layer having a region located above the second insulating layer; the first conductive layer comprises copper and titanium; the first insulating layer comprises silicon and nitrogen; the second insulating layer has a region having a higher oxygen concentration than the first insulating layer; the metal oxide layer includes a first metal oxide layer and a second metal oxide layer having a region in contact with an upper surface of the first metal oxide layer; the second conductive layer includes a first titanium film and a first copper film having a region in contact with an upper surface of the first titanium film; the third conductive layer includes a second titanium film and a second copper film having a region in contact with an upper surface of the second titanium film; the third insulating layer comprises silicon and oxygen; the fourth insulating layer comprises silicon and nitrogen; a thickness of the first metal oxide layer is smaller than a thickness of the second metal oxide layer; an end of the first titanium film has a region that protrudes further than an end of the first copper film in a cross-sectional view in a channel length direction; A semiconductor device, wherein an end of the second titanium film has a region that protrudes further than an end of the second copper film when viewed in a cross section in a channel length direction.

2. A substrate; a first conductive layer having a region in contact with an upper surface of the substrate and a region functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a second insulating layer having a region in contact with an upper surface of the first insulating layer and a region functioning as a gate insulating film; a metal oxide layer having a region in contact with an upper surface of the second insulating layer and a region that functions as a channel formation region; a second conductive layer having a region in contact with an upper surface of the metal oxide layer and functioning as one of a source electrode and a drain electrode; a third conductive layer having a region in contact with an upper surface of the metal oxide layer and a region functioning as the other of the source electrode and the drain electrode; a third insulating layer having a region in contact with an upper surface of the metal oxide layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; a fourth insulating layer having a region located above the second insulating layer; the first conductive layer comprises copper and titanium; the first insulating layer comprises silicon and nitrogen; the second insulating layer has a region having a higher oxygen concentration than the first insulating layer; the metal oxide layer includes a first metal oxide layer and a second metal oxide layer having a region in contact with an upper surface of the first metal oxide layer; the composition of the first metal oxide layer is different from the composition of the second metal oxide layer; the second conductive layer includes a first titanium film and a first copper film having a region in contact with an upper surface of the first titanium film; the third conductive layer includes a second titanium film and a second copper film having a region in contact with an upper surface of the second titanium film; the third insulating layer comprises silicon and oxygen; the fourth insulating layer comprises silicon and nitrogen; a thickness of the first metal oxide layer is smaller than a thickness of the second metal oxide layer; an end of the first titanium film has a region that protrudes further than an end of the first copper film in a cross-sectional view in a channel length direction; A semiconductor device, wherein an end of the second titanium film has a region that protrudes further than an end of the second copper film when viewed in a cross section in a channel length direction.

3. In claim 1 or 2, the first metal oxide layer comprises In, Ga, and Zn; The second metal oxide layer comprises In, Ga, and Zn.

Images