Semiconductor device

Abstract

To provide a semiconductor device capable of inhibiting a defect from being generated by hydrogen without increasing a formed film.SOLUTION: A semiconductor device 100 includes: a semiconductor substrate 1; a field effect transistor 120 that is arranged on the semiconductor substrate 1, is used for an analog circuit, and has a p-type gate electrode 7; an interlayer insulation film 8 arranged on the field effect transistor 120; and a hydrogen block metal film 10 that is arranged on the interlayer insulation film 8 and in the vicinity above the p-type gate electrode 7 to block hydrogen.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device position .

Background Art

[0002] Among semiconductor devices in which fine elements are formed on a semiconductor substrate such as silicon, there is an analog semiconductor device that combines semiconductor elements such as MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors), resistance elements, and fuse elements.

[0003] Examples of analog semiconductor devices include voltage regulators, voltage detectors, and switching regulators. In these analog semiconductor devices, with the development of wearable devices and IoT (Internet of the Things), those that can be driven for a long time with a low voltage and low current consumption by a secondary battery or the like have been developed. In particular, when a reference voltage generation circuit is provided in a power management IC such as a voltage regulator, reduction of the variation in the reference voltage and long-term stability are important. However, in the MISFET used in such a reference voltage generation circuit, hydrogen generated from a passivation film or the like binds to the dangling bonds (unbonded hands) present at the interface between the gate oxide film and the silicon substrate, and the threshold voltage may vary during manufacturing or change over time.

[0004] Therefore, for example, a semiconductor device has been proposed in which a silicon nitride film for hydrogen shielding is formed on an N-channel MOS transistor or the like so that hydrogen does not diffuse into the N-channel MOS transistor or the like (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] One aspect of the present invention aims to provide a semiconductor device capable of suppressing the occurrence of problems caused by hydrogen without increasing the film to be formed.

MEANS FOR SOLVING THE PROBLEMS

[0007] A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; a field effect transistor disposed on the semiconductor substrate and used in an analog circuit, the field effect transistor including a P-type gate electrode; an interlayer insulating film disposed on the field effect transistor; a hydrogen-blocking metal film disposed on the interlayer insulating film in the vicinity above the P-type gate electrode for blocking hydrogen. It has.

EFFECTS OF THE INVENTION

[0008] According to one aspect of the present invention, it is possible to provide a semiconductor device capable of suppressing the occurrence of problems caused by hydrogen without increasing the film to be formed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]

Figure 1

Figure 2

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Figure 5A

Figure 5B

Figure 5C

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Figure 7

Figure 8

BEST MODE FOR CARRYING OUT THE INVENTION

[0010] A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a field effect transistor that is disposed on the semiconductor substrate and used for an analog circuit and includes a P-type gate electrode, an interlayer insulating film that is disposed on the field effect transistor, and a hydrogen-blocking metal film that is disposed on the interlayer insulating film and in the vicinity above the P-type gate electrode and blocks hydrogen.

[0011] A semiconductor device according to an embodiment of the present invention is based on the following findings. The characteristics required for an analog semiconductor device are significantly different from those of a logic semiconductor device that handles binary signals. For example, in a charge / discharge control circuit of a secondary battery such as a lithium ion battery, in order to minimize the discharge of the secondary battery used in mobile devices and the like, a standard in the order of μV has been required in recent years in many cases. Also, reliability in the order of μV is required in a reference voltage generation circuit used in this charge / discharge control circuit. Therefore, it is necessary to reduce variations in the threshold voltage of a field effect transistor (hereinafter referred to as a "MOS transistor") included in the reference voltage generation circuit and changes over time that can be shown in a long-term reliability test.

[0012] When forming this MOS transistor, impurities such as boron, phosphorus, and arsenic are often implanted into the polysilicon film to form the gate electrode. Boron implanted as an impurity diffuses more easily into the polysilicon film than phosphorus or arsenic, and diffuses even to the gate oxide film under the polysilicon film. Then, this gate oxide film is likely to have its film quality deteriorated and is likely to allow minute atoms such as hydrogen to pass through, compared with the case where phosphorus or arsenic is implanted. At this time, if even a small amount of hydrogen generated from a passivation film or the like binds to the dangling bonds (unbonded hands) present at the interface between the gate oxide film and the silicon substrate, in an analog semiconductor device that requires adjustment in the μV unit, the threshold voltage may vary during manufacturing or change over time.

[0013] In this regard, in the semiconductor device described in Patent Document 1, a silicon nitride film for hydrogen shielding is disposed on the P-type gate electrode. However, not only does the number of steps for forming the silicon nitride film increase, but the threshold voltage may change due to the stress of the silicon nitride film disposed in the vicinity of the P-type gate electrode.

[0014] Therefore, the semiconductor device according to an embodiment of the present invention expands the area of the metal wiring layer disposed on the MOS transistor and uses it as a hydrogen-blocking metal film. That is, this semiconductor device disposes a hydrogen-blocking metal film also serving as a metal wiring layer in the vicinity above the P-type gate electrode whose threshold voltage is likely to change, thereby blocking hydrogen generated from a passivation film or the like, and thus suppressing the occurrence of problems due to hydrogen without increasing the films to be formed.

[0015] Next, as an example of the semiconductor device according to an embodiment of the present invention, an embodiment in which an analog circuit is an ED-type reference voltage generation circuit will be described with reference to the drawings.

[0016] Note that the drawings are schematic, and the relationship between film thickness and planar dimensions, the ratio of each film thickness, etc. are not as shown in the drawings. Also, in a semiconductor substrate, the surface on the side where other films or layers are laminated using a semiconductor manufacturing process is referred to as the "upper surface", and the surface on the side opposite to the upper surface is referred to as the "lower surface". Furthermore, in the following, the quantity, position, shape, structure, size, etc. of a plurality of films and semiconductor elements obtained by structurally combining these are not limited to the embodiments shown below, and can be the preferred quantity, position, shape, structure, size, etc. for implementing the present invention.

[0017] [First Embodiment] (Semiconductor Device) FIG. 1 is a circuit diagram showing an analog circuit of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 in the present embodiment includes an ED-type reference voltage generation circuit which is an analog circuit, and has a depletion-type N-channel field-effect transistor 110 and an enhancement-type N-channel field-effect transistor 120. Note that hereinafter, the "depletion-type N-channel field-effect transistor" may be referred to as "D-type NMOS transistor", and the "enhancement-type N-channel field-effect transistor" may be referred to as "E-type NMOS transistor".

[0018] When a power supply voltage VDD is applied to the drain of the D-type NMOS transistor 110 connected to the power supply terminal 100a, the D-type NMOS transistor 110 functions as a constant current source that supplies a constant current independent of the power supply voltage VDD from the source to the E-type NMOS transistor 120. The E-type NMOS transistor 120 generates a reference voltage V ref at the reference voltage terminal 100c based on the constant current supplied from the D-type NMOS transistor 110. In this way, the ED-type reference voltage generation circuit is formed by combining the D-type NMOS transistor 110 and the E-type NMOS transistor 120.

[0019] The source of the D-type NMOS transistor 110 is connected to the gate of the D-type NMOS transistor 110, the back gate, the reference voltage terminal 100c, and the gate and drain of the E-type NMOS transistor 120, and these are at the same potential. Also, the source of the E-type NMOS transistor 120 is connected to the back gate and the ground terminal 100b, and these are at the same potential.

[0020] Here, when obtaining the drain current I d1 of the D-type NMOS transistor 110, if the mutual conductance in the non-saturation operation or saturation operation is gmD, it can be expressed as in the following formula (1). As described above, since the gate and source of the D-type NMOS transistor 110 are connected, the gate-source voltage V g1 in the following formula (1) becomes 0V. Therefore, the drain current I d1 , which is the output current of the D-type NMOS transistor 110, depends on the threshold voltage V td . I d1 = 1 / 2·gmD·(V g1 - V td ) 2 = 1 / 2·gmD·(|V td |) 2 ···(1)

[0021] Next, when obtaining the drain current I d2 of the E-type NMOS transistor 120, if the mutual conductance in the saturation operation is gmE, it can be expressed as in the following formula (2). As described above, since the gate and drain of the E-type NMOS transistor 120 are connected, and further these are connected to the reference voltage terminal 100c, the gate-source voltage V g2 in the following formula (2) becomes the reference voltage V ref . Therefore, the drain current I d2 depends on the threshold voltage Vte and the reference voltage V ref . I d2 = 1 / 2·gmE·(V g2 - Vte ) 2 = 1 / 2·gmE·(V ref - V te ) 2 ···(2)

[0022] From the above, the reference voltage V ref is such that the I in the above formula (1) d1 is equal to the I in the above formula (2), d2 so it becomes as in the following formula (3). V ref ≈ V te + (gmD / gmE)1 / 2·|V td | ···(3)

[0023] Figure 2 is a schematic plan view showing a semiconductor device according to the first embodiment of the present invention, and is a plan view of an ED-type reference voltage generation circuit formed on a semiconductor substrate. In Figure 2, among the structures of the semiconductor device 100, an N-type gate electrode 6, a P-type gate electrode 7, a hydrogen-blocking metal film 10 that also serves as a function of a metal wiring layer, and metal wirings 9a to 9f connected to the hydrogen-blocking metal film 10 are shown. Also, the broken lines in Figure 2 respectively indicate the active regions of the D-type NMOS transistor 110 and the E-type NMOS transistor 120. Note that the plan view means a view (top view) when the semiconductor substrate is viewed from above in the direction of its normal.

[0024] When viewed in plan from above the semiconductor substrate (in the direction of the normal of the substrate), the hydrogen-blocking metal film 10 on the active region indicated by the broken line on the side of the E-type NMOS transistor 120 is wider than the area of the P-type gate electrode 7 and is arranged to cover the P-type gate electrode 7.

[0025] Here, the cross-sections of the D-type NMOS transistor 110 and the E-type NMOS transistor 120 will be described with reference to Figures 3 and 4.

[0026] Figure 3 is an explanatory diagram showing the cross-section along line A-A in Figure 2. Figure 4 is an explanatory diagram showing the cross-section along line B-B in Figure 2. As shown in FIGS. 3 and 4, it has a semiconductor substrate 1, an isolation oxide film 2, a gate oxide film 3, a P-type well region 4, source / drain regions 5, an N-type gate electrode 6, a P-type gate electrode 7, a silicon oxide film doped with phosphorus and boron (hereinafter referred to as "BPSG (Boro-Phospho Silicate Glass) film") 8, a metal wiring 9, a hydrogen-blocking metal film 10, and a passivation film 11. The D-type NMOS transistor 110 and the E-type NMOS transistor 120 are formed by structurally combining an isolation oxide film 2, a gate oxide film 3, a P-type well region 4, source / drain regions 5, an N-type gate electrode 6, and a P-type gate electrode 7 on the semiconductor substrate 1.

[0027] The semiconductor substrate 1 is a wafer-shaped P-type silicon semiconductor substrate. In this embodiment, a wafer-shaped P-type silicon semiconductor substrate is used as the semiconductor substrate 1. However, the shape, structure, size, material, and polarity of the semiconductor substrate 1 can be appropriately selected according to the purpose, and are not limited to this.

[0028] The isolation oxide film 2 is a LOCOS (LOCal Oxidation of Silicon) formed on the semiconductor substrate 1. The isolation oxide film 2 is provided at the outer edge of each active region to isolate the D-type NMOS transistor 110 and the E-type NMOS transistor 120. In this embodiment, LOCOS is formed to isolate the D-type NMOS transistor 110 and the E-type NMOS transistor 120. However, the present invention is not limited to this, and for example, STI (Shallow Trench Isolation) or the like may be formed for isolation.

[0029] The D-type NMOS transistor 110 has a gate oxide film 3, a P-type well region 4, source / drain regions 5, and an N-type gate electrode 6 formed by implanting phosphorus into a polysilicon film.

[0030] Since the impurity concentration of the D-type NMOS transistor 110 is adjusted so that the work function difference between the P-type well region 4 and the N-type gate electrode 6 becomes large, an electric field in the reverse direction is applied to the surface of the P-type semiconductor substrate 1, resulting in a low threshold voltage. Furthermore, since the threshold voltage can be lowered by the N-type channel doping region, the impurity implantation into the N-type gate electrode 6 and the channel doping region is appropriately controlled so that the D-type NMOS transistor 110 becomes a depletion type, and the threshold voltage V td can be made 0 V or less. As a result, even when the gate potential is 0 V, a drain current can flow through the channel by applying a drain voltage. Also, the back gate is connected to the P-type well region 4 via a region (not shown) containing a high concentration of P-type impurities and is connected to the source.

[0031] The E-type NMOS transistor 120 has a P-type gate electrode 7 formed by implanting BF2, and the impurity concentrations of the P-type gate electrode 7 and the channel doping region are adjusted so that the threshold voltage Vte becomes 0 V or more. Also, a hydrogen barrier metal film 10 is disposed above the P-type gate electrode 7. The E-type NMOS transistor 120 is otherwise the same as the D-type NMOS transistor 110. Note that the shape, structure, size, material of the P-type gate electrode 7, and the type and concentration of impurities are not particularly limited and can be appropriately selected according to the purpose.

[0032] On the upper surfaces of the D-type NMOS transistor 110 and the E-type NMOS transistor 120, a BPSG film 8 as an interlayer insulating film is formed with its surface planarized. Metal wirings 9a to 9d are respectively embedded in contact holes formed so as to penetrate to the source / drain regions 5 in the BPSG film 8, and conduction paths from the source / drain regions 5 are formed. In this embodiment, the interlayer insulating film is the BPSG film 8. However, the present invention is not limited to this, and for example, a laminated structure of an NSG (None-doped Silicate Glass) film and a BPSG film, a laminated structure of a TEOS (Tetra-Ethyl-Ortho-Silicate) film and a BPSG film, etc. may be used.

[0033] The hydrogen-blocking metal film 10 electrically connected to the upper portions of the metal wirings 9a to 9d is formed of AlSiCu. Since this hydrogen-blocking metal film 10 exists above the P-type gate electrode 7, it can block the upward movement of hydrogen generated from a passivation film 11 or the like and prevent it from entering the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7. That is, in the semiconductor device 100 of the present embodiment, since the hydrogen-blocking metal film 10 having the function of a metal wiring layer exists above the P-type gate electrode 7, it is possible to suppress the occurrence of problems due to hydrogen without increasing the number of films to be formed.

[0034] The material of the hydrogen-blocking metal film 10 is not particularly limited and can be appropriately selected according to the purpose. However, in terms of the hydrogen-blocking metal film 10 also serving as a metal wiring layer, an aluminum alloy is preferable. Examples of the aluminum alloy include AlNd, AlCu, AlSi, etc. in addition to AlSiCu. Also, a mode in which tungsten is formed in a film shape on the underlying titanium may be adopted. In the mode in which tungsten is formed in a film shape on the underlying titanium, it is advantageous in that tungsten blocks the intrusion of hydrogen and the underlying titanium can absorb hydrogen. In this embodiment, the hydrogen-blocking metal film 10 is made wider than the area of the active region of the P-type gate electrode 7. However, as long as it can block the hydrogen diffusing with respect to the active region of the P-type gate electrode 7, the present invention is not limited to this, and the area of the hydrogen-blocking metal film 10 may be equal to or smaller than the active region of the P-type gate electrode 7.

[0035] The thickness of the hydrogen-blocking metal film 10 is not particularly limited and can be appropriately selected according to the purpose. However, from the viewpoint of ensuring a thickness capable of blocking hydrogen, a thickness of 300 nm or more and 500 nm or less is preferable.

[0036] The size of the hydrogen-blocking metal film 10 is not particularly limited and can be appropriately selected according to the purpose. However, when viewed in plan, it is preferably larger than the P-type gate electrode 7 in the active region.

[0037] A passivation film 11 is provided on the uppermost surface of the semiconductor device 100. As the passivation film 11, a silicon nitride film is preferable. As a method for forming the silicon nitride film, since the metal wirings 9a to 9d may melt when using low-pressure CVD (Chemical Vaper Deposition), it is preferable to use plasma CVD. In this embodiment, the passivation film 11 has a single-layer structure of a silicon nitride film. However, the present invention is not limited to this, and for example, a two-layer structure of a silicon oxide film and a silicon nitride film may be used. Further, the shape, structure, and size of the passivation film 11 are not particularly limited and can be appropriately selected according to the purpose.

[0038] As described above, the semiconductor device 100 of this embodiment includes, on the semiconductor substrate 1, an E-type NMOS transistor 120 used in an ED-type reference voltage generation circuit and having a P-type gate electrode 7, a BPSG film 8 disposed on the E-type NMOS transistor 120, and a hydrogen-blocking metal film 10 disposed above and in the vicinity of the P-type gate electrode 7 on the BPSG film 8 and blocking hydrogen. Thereby, the semiconductor device 100 can suppress the occurrence of problems caused by hydrogen without increasing the number of films to be formed.

[0039] Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to FIGS. 5A to 5C.

[0040] First, prepare a semiconductor substrate 1 and perform a LOCOS formation process to form an isolation oxide film 2 on the semiconductor substrate 1. Next, as shown in Fig. 5A, by using conventional MOSFET manufacturing techniques such as a gate oxide film formation process, a source / drain region formation process, and a gate electrode formation process using polysilicon, a gate oxide film 3, a P-type well region 4, source / drain regions 5, an N-type gate electrode 6, and a P-type gate electrode 7 are formed on the semiconductor substrate 1. Thereby, a D-type NMOS transistor 110 and an E-type NMOS transistor 120 are formed.

[0041] Specifically, to form the D-type NMOS transistor 110, first, boron is implanted into a part of each active region to form a P-type well region 4, and an N-type channel doping region is formed on a part of the surface of the P-type well region 4. Next, after forming a gate oxide film 3 on this channel doping region, a polysilicon film formed on the gate oxide film 3 is implanted with phosphorus at a low concentration of 5×10 16 or more and 1×10 18 / cm 3 or less to form an N-type gate electrode 6. Then, at a position sandwiching the channel doping region under the gate oxide film 3, a high-concentration N-type source / drain region of 1×10 19 / cm 3 or more is formed on the surface of the P-type well region 4. Note that these are formed by performing a photomask process on necessary parts. Also, the thickness of the polysilicon film is not particularly limited and can be appropriately selected according to the purpose, but it is preferably 100 nm or more and 500 nm or less.

[0042] Next, as shown in Fig. 5B, a BPSG film 8 is formed over the entire surface and flattened. The method for forming the BPSG film 8 is not particularly limited and can be appropriately selected according to the purpose. The method for planarizing the BPSG film 8 is not particularly limited and can be appropriately selected according to the purpose. For example, a reflow method, an etch-back method, a CMP (Chemical Mechanical Polishing) method, etc. can be mentioned. Specifically, in the reflow method, after forming an oxide film containing phosphorus or boron, it may be planarized by heat treatment at 850°C or higher.

[0043] Next, contact holes are opened in the BPSG film 8 by photolithography and dry etching, and tungsten is embedded with titanium as a base to form metal wirings 9a to 9d. Then, a hydrogen-blocking metal film 10 is formed by photolithography and etching. Since this hydrogen-blocking metal film 10 also serves as a metal wiring layer, there are portions where it is electrically connected to the upper part of the metal wirings 9a to 9d.

[0044] Next, after forming and planarizing the BPSG film 8, a passivation film 11 which is a silicon nitride film is formed on the BPSG film 8 and the hydrogen-blocking metal film 10 by plasma CVD.

[0045] Thus, the semiconductor device 100 of the present embodiment is disposed on the semiconductor substrate 1 and used for an ED-type reference voltage generation circuit, and includes a step of forming an E-type NMOS transistor 120 having a P-type gate electrode 7, a step of forming a BPSG film 8 on the E-type NMOS transistor 120, and a step of forming a hydrogen-blocking metal film 10 for blocking hydrogen above the BPSG film 8 and in the vicinity above the P-type gate electrode 7. Thereby, the manufactured semiconductor device 100 can suppress the occurrence of problems caused by hydrogen without increasing the films to be formed.

[0046] In the present embodiment, as shown in FIG. 6, the source terminal of the E-type NMOS transistor 120 and the hydrogen-blocking metal film 10 may be integrated. Thereby, the area of the hydrogen-blocking metal film 10 can be widened, and there is no gap between the source terminal and the hydrogen-blocking metal film 10, which is preferable in that hydrogen is less likely to diffuse into the E-type NMOS transistor 120 having the P-type gate electrode 7.

[0047] [Second Embodiment] FIG. 7 is an explanatory diagram showing a cross section of a semiconductor device according to a second embodiment of the present invention. As shown in FIG. 7, in addition to the first embodiment shown in FIG. 3, in the second embodiment, a wide-area hydrogen barrier metal film 13 is disposed on the hydrogen barrier metal film 10 via a BPSG film 12. The wide-area hydrogen barrier metal film 13 is formed of AlSiCu, similarly to the hydrogen barrier metal film 10. Since this wide-area hydrogen barrier metal film 13 exists above the P-type gate electrode 7 and the hydrogen barrier metal film 10, in addition to the hydrogen barrier metal film 10, the wide-area hydrogen barrier metal film 13 can block the intrusion of hydrogen into the E-type NMOS transistor 120 having the P-type gate electrode 7, so that the occurrence of problems due to hydrogen can be further suppressed.

[0048] Also, when the semiconductor device 100 of the present embodiment has a plurality of field effect transistors, the wide-area hydrogen barrier metal film 13 is preferably disposed above the hydrogen barrier metal film 10 so as to cover the entire plurality of field effect transistors.

[0049] [Third Embodiment] FIG. 8 is an explanatory diagram showing a cross section of a semiconductor device according to a third embodiment of the present invention. As shown in FIG. 8, in addition to the first embodiment shown in FIG. 3, in the third embodiment, metal silicide films 14 and 15 of CoSi are formed on the upper part of the P-type gate electrode 7 and the upper part of the source / drain region 5. Thereby, the semiconductor device 100 of the present embodiment can block the intrusion of hydrogen in the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7 by the metal silicide films 14 and 15 in addition to the hydrogen barrier metal film 10, so that the occurrence of problems due to hydrogen can be further suppressed. In this embodiment, the metal silicide films 14 and 15 are CoSi, but the present invention is not limited thereto, and for example, they can be WSi, TiSi, NiSi, etc.

[0050] As described above, the semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a field-effect transistor that is disposed on the semiconductor substrate, used in an analog circuit, and includes a P-type gate electrode, and an interlayer insulating film that is disposed on the field-effect transistor, and a hydrogen-blocking metal film that is disposed on the interlayer insulating film in the vicinity above the P-type gate electrode and blocks hydrogen. Accordingly, the semiconductor device according to an embodiment of the present invention can suppress the occurrence of problems caused by hydrogen without increasing the number of films to be formed.

[0051] In each of the above embodiments, the D-type NMOS transistor 110 is provided with the N-type gate electrode 6, and the E-type NMOS transistor 120 is provided with the P-type gate electrode. However, the present invention is not limited to this, and the D-type NMOS transistor 110 may be provided with the P-type gate electrode. In the present embodiment, both the D-type NMOS transistor 110 and the E-type NMOS transistor 120 are NMOS transistors. However, the present invention is not limited to this, and both may be PMOS transistors.

[0052] In each of the above embodiments, the analog circuit is an ED-type reference voltage generation circuit. However, the present invention is not limited to this, and examples thereof include a reference voltage generation circuit that is not of the ED type, a circuit in which the output of a reference voltage generation circuit that is of the ED type or not of the ED type is connected to at least one of the non-inverting input terminal and the inverting input terminal of a comparator, and a current mirror circuit.

Explanation of Reference Numerals

[0053] 1 Semiconductor substrate 2 Isolation oxide film 3 Gate oxide film 4 P-type well region 5 Source / drain region 6 N-type gate electrode 7 P-type gate electrode 8 BPSG film (interlayer insulating film) 9 Metal wiring 10 Hydrogen-blocking metal film 11 Passivation film 12 BPSG film (interlayer insulating film) 13 Wide-area hydrogen-blocking metal film 14, 15 Metal silicide film 100 Semiconductor device 110 Depletion-type NMOS transistor 120 Enhancement-type NMOS transistor

Claims

1. A semiconductor device having a reference voltage generating circuit, The reference voltage generating circuit includes: a depletion-type field effect transistor that generates a constant current and has a gate electrode and a source region connected thereto; an enhancement type field effect transistor, the drain region and a gate electrode of which are connected to a source region of the depression type field effect transistor, the gate electrode being a P-type gate electrode, and which generates a voltage based on the constant current; on a semiconductor substrate, an interlayer insulating film disposed above the depression type field effect transistor and the enhancement type field effect transistor; a hydrogen barrier metal film that blocks hydrogen, which also serves as a metal wiring layer disposed on the interlayer insulating film and in the vicinity of the upper side of the P-type gate electrode, and which also serves as a metal wiring layer that connects the gate electrode and the source region of the depression type field effect transistor and the P-type gate electrode and the drain region of the enhancement type field effect transistor in the same layer as the metal wiring layer; having A semiconductor device characterized in that the area of ​​the hydrogen barrier metal film arranged in the vicinity of the upper part of the P-type gate electrode is equal to or greater than the area of ​​the P-type gate electrode, at least in an active region of the field effect transistor, when the semiconductor substrate is viewed in a plan view.

2. A semiconductor device as described in claim 1, wherein the hydrogen-blocking metal film is an aluminum alloy.

3. A semiconductor device as described in claim 1 or 2, further comprising a wide-area hydrogen-blocking metal film arranged above the hydrogen-blocking metal film so as to cover all or part of the field effect transistor when the semiconductor substrate is viewed in a planar view.

4. A semiconductor device according to claim 1, wherein a metal silicide film is formed on the upper part of the P-type gate electrode.

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