Method and apparatus for producing a three-dimensional nanostructure

Abstract

Provided herein are methods and apparatus for forming a plurality of non-volatile memory cells. In some embodiments, the methods include, for example, forming a plurality of non-volatile memory cells, including forming a stack of alternating layers of metal on a substrate, the stack including a first metal layer and a second metal layer different from the first metal layer, removing the first metal layer to form spaces between the alternating layers of the second metal layer, and one of depositing a first material layer to partially fill the spaces and leave voids therein or depositing a second material layer to fill the spaces.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to substrate processing apparatuses and techniques, and more particularly, to methods and apparatuses for fabricating three-dimensional (3D) NAND structures.

Background Art

[0002] To address the challenges encountered in scaling planar (2D) NAND memory devices to achieve higher density at lower cost per bit, ultra-high density, three-dimensional (3D) stacked memory structures have been introduced. Such 3D memory structures are sometimes said to have a Bit Cost Scalable (BiCS) architecture and include strings of memory cells aligned in the vertical direction. Typically, these vertically aligned memory cells are formed from an array of alternating conductor and insulating layers, where the conductive layer corresponds to the word line of the memory structure.

[0003] As the number of vertically stacked memory cells in a 3D NAND device increases (e.g., as chip density increases), the aspect ratio of the memory cell strings also increases, leading to numerous manufacturing problems. The inventors have observed, for example, that as the stacking increases, the difficulty in etching / filling and stress control also increases. The inventors have further observed that thinning the layers in the stack to maintain the aspect ratio of the memory cell strings within manageable limits results in a more difficult downstream etching process.

[0004] In response, the inventors have provided methods and apparatuses for fabricating 3D NAND structures.

Summary of the Invention

[0005] Provided herein are methods and apparatuses for forming a plurality of non-volatile memory cells. In some embodiments, the method comprises Forming a stack of alternating layers of metal on a substrate, the stack including a first metal layer and a second metal layer different from the first metal layer; Removing the first metal layer to form a space between the alternating layers of the second metal layer; Performing one of depositing a first material layer to partially fill the space and leave voids therein, or depositing a second material layer to fill the space; Including.

[0006] According to some embodiments of the present disclosure, a semiconductor memory device includes: A first material layer that is at least one of a metal, a metal nitride, or a conductive metal compound; A second material layer that is at least one of a metal, a metal alloy, or a metal having a dopant including one or more metal elements; A substrate including a stack of alternating layers of materials including the first material layer and the second material layer, wherein the first material layer is different from the second material layer. A semiconductor memory device is provided.

[0007] According to one aspect of the present disclosure, a system for forming a plurality of non-volatile memory cells is provided. The system includes: A silicon nitride (SiN) layer and a polysilicon (poly-Si) layer; A stack of alternating layers of metal including a first metal layer and a second metal layer different from the first metal layer; An apparatus configured to deposit the silicon nitride (SiN) layer, the polysilicon (poly-Si) layer, and the stack of alternating layers of metal on a substrate; An apparatus configured to remove the first metal layer to form a space between the alternating layers of the second metal layer; An apparatus configured to perform one of depositing a first material layer to partially fill the space and leave voids therein, or depositing a second material layer to fill the space; Comprising.

[0008] Other embodiments and further embodiments of the present disclosure will be described below.

[0009] The embodiments of the present disclosure, briefly summarized above and described in more detail below, can be understood by reference to the exemplary embodiments of the present disclosure shown in the accompanying drawings. However, since the present disclosure may admit other equally effective embodiments, the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not therefore be regarded as limiting the scope.

Brief Description of the Drawings

[0010]

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Best Mode for Carrying Out the Invention

[0011] For ease of understanding, the same reference numerals are used to denote the same elements common to a plurality of figures, where possible. The figures are not drawn to scale and may be simplified for clarity. The elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0012] Embodiments described herein generally relate to 3D NAND memory devices with improved word line insulation and methods of forming the same. Specifically, alternating layers of materials, such as a first metal layer and a second metal layer which are (metal) multilayers of different types, are used for a 3D NAND cell film stack and memory holes are formed. One of the metal layers (e.g., the first metal) can then be removed (e.g., etched) to form a space or void that will later be filled with one or more materials, such as a low dielectric constant oxide (e.g., SiO, SiO2, etc.). Both metal layers can be removed by etching using the same etching chemistry. Thus, HAR (high aspect ratio) etching can be performed with higher throughput. For example, both metals can be removed by etching using chemical dry etching with hydrofluoric acid (HF) having a high selectivity (e.g., >100:1). Further, in the embodiments described herein, there is no word line (WL) metal filling step, which is an important step for replacement metal gate (RMG) that is sometimes used in conventional methods for forming 3D NAND memory devices, for example, used with an oxygen nitrogen (ON) mold. Herein, the WL metal can be deposited as a mold stack and after removing TiN, silicon oxide can be filled, i.e., the filling of SiO2 is a much easier and cost - effective process than the conventional process used for WL metal filling. Also, in contrast to voids that can sometimes be formed during the conventional RMG process and can cause severe SiO2 degradation due to residual fluorine (F) gas present in the voids, voids that can sometimes be formed due to incomplete filling of SiO2 can function as voids (which can be formed without incorporating any extra steps) and are not harmful to the fabricated 3D NAND memory devices described herein.Furthermore, the mechanical stress of the mold stack used in forming a 3D NAND memory device can be varied by the deposition conditions of the metal using physical vapor deposition (PVD) or chemical vapor deposition (CVD). As a result, for example, it is not necessary to use RMG, and the overall height of the stack can be made lower when compared to the current SiO2 / silicon nitride (Si3N4) multilayer.

[0013] FIG. 1 is a schematic diagram of a system 100 for forming a plurality of non-volatile memory cells in a 3D NAND memory device (e.g., the memory device 300 of FIGS. 3A-3P). FIG. 2 is a flowchart of a method 200 for forming a plurality of non-volatile memory cells in a memory device according to an embodiment of the present disclosure. FIGS. 3A-3P are schematic cross-sectional views of a portion of a 3D NAND memory device during fabrication steps according to at least one embodiment of the present disclosure, for example using method 200.

[0014] FIG. 3A shows a memory device 300 that can be a bit cost scalable (BiCS) device, the memory device 300 including a string of (a plurality of) vertically stacked memory cell layers 302 (e.g., conductive layers (e.g., a second material layer) used as word lines alternately disposed between a plurality of layers (e.g., a first material layer) 304) formed on a substrate 301 that can be a semiconductor in some embodiments.

[0015] The substrate 301 can be any starting material suitable for forming integrated circuits, such as a silicon (Si) wafer or a germanium (Ge) wafer. The semiconductor substrate 301 can be a silicon semiconductor substrate on which one or more layers, such as a film stack, are formed thereon, and a structure such as the memory device 300 is used to be formed on the substrate 301. The substrate 301 can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), Si3N4, strained silicon, silicon germanium, doped or undoped polysilicon (poly-Si), doped or undoped silicon, patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride (SiN, Si3N4, etc.), doped silicon, germanium, gallium arsenide, glass, sapphire, a metal layer disposed on silicon, and the like. The substrate 301 can be a circular wafer, such as a wafer having a diameter of 200 mm, 300 mm, or 450 mm, or can also be a rectangular or square panel.

[0016] In some embodiments, the memory cell layer 302 and the layer 304 can be formed on a common source line (CSL) layer, and this common source line (CSL) layer can be formed on an etch stop layer (ESL). In such embodiments, the CSL layer and the ESL can be made of materials such as tungsten (W), silicon nitride (SiN), poly-Si, or combinations thereof. In some embodiments, a mask layer (ML) (e.g., a silicon oxide layer) can be deposited on the memory cell layer 302 or the layer 304 to form the topmost or final layer of the material. The ML is patterned to cover regions that are not removed during the stack etching process before the stack is etched.

[0017] Layer 304 is disposed between the memory cell layers 302. Layer 304 can be formed using any suitable material (e.g., metal, metal nitride, or conductive metal compound), such as W, molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), titanium nitride (TiN), TaN, WN, MoN, ZrN, WO x , RuO x , IrO x , etc. Layer 304 is provided to facilitate the formation (or construction) of the memory cell layers 302 on the semiconductor substrate 301. After the memory cell layers 302 are formed, layer 304 is removed using one or more suitable processes and filled with one or more suitable materials, as described in more detail below.

[0018] Each of the memory cell layers 302 corresponds to a word line of the memory device 300, and each word line extends toward the back of this page and forms additional memory cells of the memory device 300 that are not visible. Accordingly, each of the memory cell cells 302 is configured to store one or more bits of data. Thus, each of the memory cell layers 302 can be formed using any suitable material (e.g., metal, metal alloy, metal having a dopant containing one or more metal elements), for example, among others, W, tungsten silicide (WSi), tungsten poly-Si (W / poly-Si), tungsten alloy, Ta, Ti, Nb, Os, Zr, Ir, Re, copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), aluminum (Al), hafnium (Hf), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum (Pt), alloys thereof, nitride compounds such as titanium nitride (TiN) and tantalum nitride (TaN), and combinations thereof. For each substrate 301, the memory cell layer 302 and the layer 304 are formed from different materials. For example, in at least some embodiments, the memory cell layer 302 can be formed from W while the layer 304 can be formed from TiN, and other combinations of materials can also be used.

[0019] Continuing to refer to FIG. 3A, at 202, the memory cell layer 302 and layer 304 can be deposited on the semiconductor substrate 301 using any suitable deposition process and / or apparatus 130 (FIG. 1). Examples of such deposition processes and / or apparatus 130 can include a chemical vapor deposition (CVD) apparatus 130a, a physical vapor deposition (PVD) apparatus 130b, or an atomic layer deposition (ALD) apparatus 130c. For example, in one particular embodiment, layer 304 (e.g., TiN) can be deposited using, for example, a PVD apparatus 130b which can be part of a stand-alone apparatus or a cluster tool configured to perform a PVD process. Exemplary apparatuses configurable to perform the above processes can include, for example, stand-alone PVD apparatuses of the ENDURA® VERSA® line available from Applied Materials, Inc. Similarly, the memory cell layer 302 (e.g., W) can be deposited using, for example, a CVD apparatus 130a which can be a stand-alone apparatus or a cluster tool configured to perform a CVD process. Exemplary apparatuses configurable to perform the above processes can include, for example, stand-alone CVD apparatuses of the PRODUCER® APF line available from Applied Materials, Inc. Alternatively or additionally, layer 304 can be deposited using, for example, a CVD apparatus 130a, and the memory cell layer 302 can be deposited using, for example, a PVD apparatus 130b.

[0020] Next, the WL staircase can be formed by etching the memory cell layer 302, layer 304, and the ML (FIG. 3B). For example, any suitable etching apparatus 110 (FIG. 1) and / or method, such as a deep reactive-ion etching (DRIE) process, a highly anisotropic etching process used to create high aspect ratio holes and trenches in a wafer or other substrate, can be used to form the WL staircase. Etching gases suitable for such an etching process are fluorides (SF6, CF4, CHF3) It may contain fluorides (such as CH3F, C2F6, C4F8, and NF3), chlorides (HCl, Cl2, BCl3), bromides (Br2, HBr), or oxygen-containing gases (such as O3, O2, CO2, CO, H2O, NO, NO2, N2O, CO, etc.), and optionally, it may contain inert gases such as argon (Ar) or helium (He).

[0021] After the WL step portion is formed, an interlayer dielectric deposition (ILD) process can be carried out to deposit the material layer 305 on the memory cell layer 302 and the layer 304. The ILD process can use a dielectric material, and this dielectric material is filled in the region where the step portion is formed. In at least some embodiments, thick silicon oxide (about 1.2 times thicker than the stack height of the memory cell layer 302 and the layer 304) is deposited and planarized by chemical mechanical polishing (CMP).

[0022] Next, referring to FIG. 3C, using the etching apparatus 110, at least one memory hole 306 (or a plurality of memory holes 306, for example, three memory holes 306) is formed in the stack CSL where the ML, the memory cell layer 302 and the layer 304 are alternately arranged, and is partially formed in the ESL. Alternatively or additionally, the memory hole 306 can be formed to extend into the substrate 301. A string of vertically stacked memory cell layers 302 and layer 304 is shown arranged by four vertical columns. The etching apparatus 110 can be configured to use a sulfur hexafluoride (SF6) chemical substance with an ion acceleration voltage in the range of 0.5 - 10 kV. Before performing the etching, a hard mask deposition process can be first carried out, and after the etching is completed and the memory hole 306 is formed, the hard mask layer deposited before the etching can be removed. Other etching apparatuses and / or processes can be used to form the memory hole 306.

[0023] Referring to FIGS. 3D and 3E, after the memory hole 306 is formed, one or more additional material layers can be deposited within the memory hole 306. For example, as shown in the detailed region shown in FIG. 3E, a layer of aluminum oxide (AlO) (e.g., a continuous layer) (layer 307) is first deposited on the side surfaces defining the memory hole 306 and along the ESL at the bottom of the memory hole 306. Next, a layer of silicon oxide (layer 309) is deposited on top of the layer AlO and along the bottom of the memory hole 306. Next, a layer of trap silicon nitride (SiN) (layer 311) is deposited on top of the layer 309 and along the bottom of the memory hole 306. Next, another silicon oxide 313 layer is deposited on top of the layer 311 and along the bottom of the memory hole 306. Next, a layer of poly-Si (layer 315) is deposited on top of the silicon oxide layer 313 and along the bottom of the memory hole 306 to form a poly-Si channel at the bottom of the memory hole 306. Next, a core silicon oxide (layer 317), e.g., SiO, SiOC, etc., is deposited to fill the poly-Si channel (see, e.g., FIG. 3E). Layers 307-317 can be deposited using any suitable deposition process and / or apparatus. For example, it is possible to perform CVD and PVD respectively using the CVD apparatus 130a and PVD apparatus 130b of FIG. 1 to deposit layers 307-317. Alternatively or additionally, it is possible to perform an ALD process using an ALD apparatus 130c, which can be a stand-alone apparatus or a cluster tool, to deposit layers 307-317. Exemplary apparatuses configurable to perform the above processes include, for example, ALD apparatuses of the OLYMPIA® line available from Applied Materials, Inc.

[0024] After layer 317 is deposited to fill the poly-Si channel, as shown in FIGS. 3F and 3G, an additional layer 321 (e.g., a layer of poly-Si) can be deposited on top of layer 317 to cover layer 317, and an additional ML layer can be deposited on top of layer 321 to cover layer 321.

[0025] Next, with respect to FIG. 3H, two additional slits or holes 308 are formed in the stack where ML, the memory cell layer 302 and layer 304 alternate, CSL, ESL (e.g., using the etching process described above), and can be formed partially into the substrate 301. However, unlike the memory holes 306, the holes 308 are used to remove the CSL and layer 304. For example, after the holes 308 are formed, the CSL is removed using the etching process described above (e.g., wet etching and / or chemical dry etching), and layers 309 - 313 deposited within the memory holes 306 in the range of the CSL are also removed (see FIGS. 3I and 3J for example).

[0026] Next, the region containing the CSL and layers 307 - 313 is filled with a layer of phosphorus-doped poly-Si (n+-type silicon) (e.g., layer 323), the holes 308 are left as they are, and are not filled or minimally filled with, for example, layer 323 (FIG. 3K).

[0027] Next, in 204, layer 304 is removed using the etching process described above (e.g., wet etching or chemical dry etching using the etching apparatus 110). More specifically, layer 304 (e.g., a layer of TiN) is removed by selectively oxidizing the layer 304 as shown in FIG. 3L, and a space 325 is formed between the alternating layers (e.g., layers of W) of the memory cell layer 302.

[0028] The removal of layer 304 can be achieved without imparting undesirable damage to the memory cell layer 302 using any suitable etching or patterning process for selectively removing layer 304 from the memory device 300.

[0029] For example, any isotropic etching process that is selective to at least the memory cell layer 302 can be used to remove the highly selective layer 304. For example, in some embodiments, layer 304 can be removed using reactive species formed via remote plasma from a process gas containing oxygen (O2) and nitrogen trifluoride (NF3), e.g., using the etching apparatus 120 of FIG. 1. The isotropic etching process can be performed in any suitable isotropic etching apparatus. A highly selective isotropic dry etching process that can be used to remove layer 304 is described in U.S. Patent No. 9,165,786, entitled "Integrated oxide and nitride recess for better channel contact in 3D architectures," filed on August 5, 2014. The dry etching process can be performed using a suitable dry etching apparatus. Exemplary apparatuses configurable to perform the above processes include, for example, etching apparatuses of the PRODUCER (registered trademark) SELECTRA (registered trademark) line available from Applied Materials, Inc. of Santa Clara, California (FIG. 1).

[0030] Alternatively or additionally, to remove layer 304, a selective oxidation apparatus 140 can be used to deposit a silicon oxide layer (not shown) on layer 304 using rapid thermal oxidation (RTO), radical oxidation, or remote plasma oxidation (RPO), e.g., decoupled plasma oxidation (DPO). In some embodiments where low heat budget and / or reduced oxygen diffusion are desired, plasma oxidation or radical oxidation can be utilized. As used herein, low heat budget means a heat budget smaller than that of a furnace process of several tens of minutes at a peak temperature of 850°C. For example, when RPO is used at 204, one or more suitable plasma reactors, such as an RPO reactor available from Applied Materials, can be used to provide a silicon oxide layer on layer 304.

[0031] Alternatively, a high heat budget process (i.e., high oxygen diffusion) can also be used. For example, a high heat budget process (e.g., wet, dry, or RTO) can result in conformal oxidation, a faster oxidation rate, and a thicker oxide.

[0032] The type of selective oxidation apparatus 140 and / or etching apparatus 120 used to remove the carbon layer 304 can depend on one or more factors including, but not limited to, time constraints, desired oxidation rate, etc.

[0033] Regardless of the selective oxidation apparatus 140 and / or etching apparatus 120 used (or the etching process using etching apparatus 110), after the layer 304 is removed from the memory device 300, an intermediate film stack containing only the memory cell layer 302 remains on the substrate 301 for further processing (see FIG. 3L).

[0034] In some embodiments, referring to FIG. 3M at 206, a layer 327 of material (e.g., a low (dielectric constant) oxide material, silicon oxide, silicon dioxide, etc.) can be deposited to fill the space 325 (e.g., without voids). The material layer 327 can be deposited using, for example, the CVD apparatus 130a or ALD apparatus 130c of FIG. 1. The low dielectric constant oxide material can include, but is not limited to, silicon oxide, silicon dioxide, etc. The material layer 327 can have a dielectric constant of 3.9 or less.

[0035] Conversely, referring to FIG. 3N, in some embodiments at 204, the material layer 327 can be deposited to partially fill the space 325 and leave voids 329 therein. The material layer 327 can be deposited using, for example, the CVD apparatus 130a or ALD apparatus 130c of FIG. 1. The space 325 can be partially filled such that the voids 329 can occupy any particular deposition of the space 325.

[0036] After one of the processes of 206 is completed, the memory device 300 will have a stack of alternating memory cell layers 302 and a material layer 327 (e.g., a low dielectric constant oxide material) that contains voids (FIG. 3N) or does not contain voids 329 (FIG. 3M). Once formed, the 3D NAND memory device 300 can be further processed, for example, to deposit gate silicon oxide for gate formation.

[0037] For example, after the process of 206 is completed, the hole 308 can be filled with one or more suitable materials including, but not limited to, TiN, W, SiN, oxides, or combinations thereof (e.g., planarization) (FIG. 3O). Similarly, after planarization is performed, one or more wiring (BEOL: back end of the line) processes (e.g., WL staircase contact formation) can be carried out to complete the manufacture of the 3D NAND memory device 300 (FIG. 3P).

[0038] FIGS. 4A - 4C are schematic cross-sectional views of a portion of 3D NAND memory devices 400a - 400c according to at least one embodiment of the present disclosure. The 3D NAND memory devices 400a - 400c are substantially similar to the 3D NAND memory device 300. Therefore, only the features specific to the 3D NAND memory devices 400a - 400c will be described here.

[0039] As shown in FIG. 4A, before 206 (e.g., before depositing material layers 427b and 427c for filling the space 425a (e.g., with or without voids 429c as described above)), one or more of the layers (e.g., layers 407b - 415b or layers 407c - 415c) that fill the memory holes can be removed from the memory cell layer 402.

[0040] For example, as shown by the detailed region shown in FIG. 4B, instead of applying a continuous AlO layer 407b, a discontinuous layer 407b can be formed to cover only the memory cell layer 402b on the side surface defining the memory hole and along the ESL at the bottom of the memory hole (not covering the layer 404b). The memory cell layer 402b having the discontinuous layer 407b can be fabricated by removing the layer 407b from the region within the memory hole adjacent to the location where the material layer 427b is to be deposited, prior to 206. By using the discontinuous layer 407b, it is possible to reduce the cell - to - cell interference between adjacent memory cell layers 402. For illustrative purposes, the 3D NAND memory device 400b is shown without voids.

[0041] Similarly, discontinuous layers 407c, and discontinuous silicon oxide and SiN layers (e.g., layers 409c and 411c) can be used to form the 3D NAND memory device 400c (FIG. 4C). The memory cell layer 402c having the discontinuous layers 407c - 411c can be fabricated by removing the layers 407c - 411c from the region within the memory hole adjacent to the location where the material layer 427c is to be deposited, prior to 206. The memory cell layer 402c having the discontinuous layers 407c - 411c can prevent data loss through the layer 411c (e.g., trap SiN) between adjacent memory cell layers 402c. For illustrative purposes, the 3D NAND memory device 400 is shown having a void 429c.

[0042] FIG. 5 is a schematic cross - sectional view of a portion of a 3D NAND memory device 500 according to at least one embodiment of the present disclosure. The inventors have found that the present disclosure is not limited to charge - trap - based NAND flash memory devices. For example, memory cells having resistive RAM (ReRAM: resistive RAM) or phase change memory (PCM: phase change memory) can be formed using the methods described herein. More specifically, as shown in FIG. 5, a resistive memory material (e.g., Ta2O5, TiO2, etc. for ReRAM, or Ge x Sb yTe z A resistive layer 550 (such as (GST)) can be deposited between the memory cell layer 502 and the layer 515, and the memory cell layer 502 can be made of the same material as the layer 515 (for example, for forming a poly-Si channel).

[0043] The method described herein can be used to form a 3D NAND memory device, and by forming a plurality of memory cell layers 302 together with a layer 304, crosstalk between adjacent memory cells of the memory cell layer 302 of the memory device 300, for example, leakage of trapped charges, is reduced even if not eliminated. The layer 304 can be removed and replaced with a material 327 (such as a low dielectric constant oxide material, silicon oxide, etc.) that may or may not contain voids 329. Further, since both the memory cell layer 302 and the layer 304 can be etched and removed using an oxygen-based etching process, high aspect ratio memory hole etching and void filling are not as difficult as in conventional processes. Additionally, when the memory cell layer 302 and the layer 304 are formed from one or more of the aforementioned materials, the mechanical stress of the mold stack can be changed by the deposition conditions of the aforementioned materials, which can reduce the possibility of pattern collapse even if it cannot be eliminated, and can make the overall stack height of the memory device 300 / 400 relatively low compared to conventional memory devices. In addition, since the memory cell layer 302 is made of one or more of the aforementioned metals (such as W), the use of a conventional replacement metal gate process sometimes used to construct the staircase portion of the word line is eliminated.

[0044] The above description is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure.

Claims

1. A method of forming a plurality of non-volatile memory cells, comprising: Forming an etching stop layer (ESL) made of tungsten (W), poly-Si, or a combination thereof directly on a substrate; Forming a stack of alternating layers of metals including a first metal layer and a second metal layer different from the first metal layer on the etching stop layer (ESL); Removing the first metal layer to form a space between the alternating layers of the second metal layer; Performing one of depositing a first material layer to partially fill the space and leave a void therein, or depositing a second material layer to fill the space; Forming at least one memory hole in the stack of the alternating layers of the first metal layer and the second metal layer and the etching stop layer (ESL) deposited between the first metal layer and the substrate; In the at least one memory hole, Depositing an aluminum oxide (AlO) layer; Depositing a first silicon oxide layer on the AlO layer; Depositing a SiN layer on the first silicon oxide layer; Depositing a second silicon oxide layer on the SiN layer; Depositing a poly-Si layer for forming a poly-Si channel on the second silicon oxide layer; And core silicon oxide for filling the poly-Si channel And depositing. A method comprising.

2. The method according to claim 1, wherein one of depositing the first material layer to partially fill the space and leave a void therein, or depositing the second material layer to fill the space, is performed using one of chemical vapor deposition or atomic layer deposition.

3. The method according to claim 1, wherein the first metal layer and the second metal layer are deposited using at least one of chemical vapor deposition and physical vapor deposition.

4. Removing the first metal layer is performed using an F-based chemical substance containing a fluorine compound including at least one of SF ６ , CF ４ , CHF ３ , CH ３ F, C ２ F ６ , C ４ F ８ , or NF ３ in a chemical dry etching process or one of wet etching processes. The method according to claim 1.

5. Forming the at least one memory hole is performed using a chemical dry etching process using an F-based chemical substance containing a fluorine compound including at least one of SF ６ , CF ４ , CHF ３、 CH ３ F, C ２ F ６ , C ４ F ８ , or NF ３ in the method according to any one of claims 1 to 4.

6. Before removing the first metal layer to form a space between the alternating layers of the second metal layer, forming at least two slits penetrating the first metal layer, the second metal layer, the SiN layer, and the poly-Si layer using an F-based chemical substance containing a fluorine compound including at least one of SF ６ , CF ４ , CHF ３ , CH ３ F, C ２ F ６ , C ４ F ８ , or NF ３ and, Using one of a wet etching process or a chemical dry etching process, removing the SiN layer and the poly-Si layer from the substrate, Using a chemical dry etching process from at least one memory hole within the region occupied by the SiN layer and the poly-Si layer before being removed, removing the AlO layer, the first silicon oxide layer on the AlO layer, the SiN layer on the first silicon oxide layer, and the second silicon oxide layer on the SiN layer, Depositing a layer of phosphorus-doped poly-Si on the substrate to cover a portion of the poly-Si channel in place of the removed AlO layer, the removed first silicon oxide layer, the removed SiN layer, and the removed second silicon oxide layer, The method according to claim 1, further comprising.

7. After removing the first metal layer to form a space between the alternating layers of the second metal layer, and depositing the first material layer to partially fill the space and leave a void therein, or depositing a second material layer to fill the space, before performing one of the above, Using the chemical dry etching process to remove the AlO layer, the first silicon oxide layer on the AlO layer, and the SiN layer on the first silicon oxide layer from at least one memory hole within the region occupied by the first metal layer before being removed, The method according to any one of claims 4 or 6, further comprising.

8. The first metal layer is at least one of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), titanium nitride (TiN), TaN, WN, MoN, ZrN, WO ｘ , RuO ｘ , and IrO ｘ , and is at least one of, the second metal layer is one of W, Mo, Ta, Ru, Nb, Os, Zr, Ir, Re, and Ti, The method according to claim 1, wherein the first material layer is silicon oxide and the second material layer is a low dielectric constant oxide.

9. The method according to claim 8, wherein the low dielectric constant oxide is one of silicon oxide or silicon dioxide having a dielectric constant of 3.9 or less.

10. A semiconductor memory device, a first material layer that is at least one of a low dielectric constant (low-k) oxide material, silicon oxide, and silicon dioxide, and has a dielectric constant of 3.9 or less; a second material layer that is at least one of a metal, a metal alloy, or a metal having a dopant containing one or more metal elements; a substrate including a stack of alternating layers of materials including; an etching stop layer (ESL) made of tungsten (W), poly-Si, or a combination thereof, deposited directly on the substrate; a layer of phosphorus-doped poly-Si deposited on the etching stop layer; at least one memory hole reaching into the etching stop layer (ESL) through the stack of the alternating layers of the first material layer and the second material layer deposited on the layer of phosphorus-doped poly-Si; within the at least one memory hole, an aluminum oxide (AlO) layer; a first silicon oxide layer on the AlO layer; a SiN layer on the first silicon oxide layer; a second silicon oxide layer on the SiN layer; a poly-Si layer for forming a poly-Si channel on the second silicon oxide layer; and core silicon oxide for filling the poly-Si channel; are deposited, The first material layer is different from the second material layer. Semiconductor memory device.

11. The semiconductor memory device according to claim 10, wherein the second material layer is one of W, Mo, Ta, Ru, Nb, Os, Zr, Ir, Re, and Ti.

12. A system for forming a plurality of non-volatile memory cells, An etching stop layer (ESL) made of tungsten (W), poly-Si, or a combination thereof deposited directly on a substrate, A stack of alternating layers of metals including a first metal layer deposited on the etching stop layer (ESL) and a second metal layer different from the first metal layer, An apparatus configured to deposit on a substrate, An apparatus configured to form at least one memory hole in the stack of the alternating layers of the first metal layer and the second metal layer and the etching stop layer (ESL), wherein in the at least one memory hole, An aluminum oxide (AlO) layer, A first silicon oxide layer on the AlO layer, A SiN layer on the first silicon oxide layer, A second silicon oxide layer on the SiN layer, A poly-Si layer for forming a poly-Si channel on the second silicon oxide layer, Core silicon oxide for filling the poly-Si channel, An apparatus for depositing, An apparatus configured to remove the first metal layer to form a space between the alternating layers of the second metal layer, An apparatus configured to perform one of depositing a first material layer to partially fill the space and leave a void therein, or depositing a second material layer to fill the space, A system comprising.

13. depositing the first material layer to partially fill the space and leave voids therein, or depositing the second material layer in the space, wherein one of the depositing operations is performed using one of chemical vapor deposition or atomic layer deposition, the system of claim 12.

14. The semiconductor memory device of claim 10, wherein the first material layer has voids therein.

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