Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

To control trade-off characteristics while realizing the operation of a high-speed side region of the trade-off characteristics without relying on a carrier lifetime control method in a power semiconductor device.SOLUTION: A semiconductor substrate 20 of a pin diode 1001 comprises: an n-drift layer 7; an n buffer layer 8 which is provided between the n-drift layer 7 and a second metal layer 14 in an active cell region R1; and an n+cathode layer 90 which is provided between the n buffer layer 8 and the second metal layer 14 in the active cell region R1 so as to be in contact with them. The n+cathode layer 90 comprises: a first n+cathode layer 91 which is in contact with the second metal layer 14; and a second n+cathode layer 92 which is provided between the first n+cathode layer 91 and the n buffer layer 8 so as to be in contact with them. The crystal defect density of the first n+cathode layer 91 is higher than the crystal defect density of the second n+cathode layer 92. The n+cathode layer 90 is not provided in an intermediate region R2 and a termination region R3.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device.

Background Art

[0002] Patent Document 1 discloses a power diode in which grooves are formed on the surface of a substrate, and a p-type anode layer and an n-type carrier injection suppression layer are provided between the grooves. According to this configuration, the amount of carrier injection from the anode side is suppressed, and it is possible to improve the breakdown voltage without providing an n+ cathode structure in the termination region while reducing the rise voltage of the output characteristics without lifetime control.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the power diode of Patent Document 1, compared with a diode into which a lifetime killer is introduced, the rise voltage of the output characteristics of the diode decreases, and the on-voltage is the same at the rated current density.

[0005] However, in order to control the trade-off characteristics while realizing the high-speed side operation of the trade-off characteristics between the on-voltage and the switching loss, it is necessary to rely on a carrier lifetime control method. Here, the carrier lifetime control method is, for example, control using a charged particle system such as an electron beam, a proton, or helium, or a heavy metal system such as platinum.

[0006] The present disclosure has been made to solve the above problems, and in a power semiconductor device, it aims to control the trade-off characteristics while realizing the operation in the high-speed side region of the trade-off characteristics between the on-voltage and the switching loss without depending on the carrier lifetime control method.

Means for Solving the Problems

[0007] The power semiconductor device of the present disclosure is divided, in a plan view, into an active cell region, an intermediate region surrounding the active cell region, and a termination region, and includes a semiconductor substrate having a first main surface and a second main surface facing each other, a first metal layer provided on the first main surface of the semiconductor substrate, and a second metal layer provided on the second main surface of the semiconductor substrate. The semiconductor substrate includes a drift layer of a first conductivity type, a buffer layer of the first conductivity type provided between the drift layer and the second metal layer in the active cell region, and at least one cathode layer of the first conductivity type provided in contact with both between the buffer layer and the second metal layer in the active cell region. The cathode layer of the first conductivity type includes a first cathode layer having one impurity concentration peak point and in contact with the second metal layer, and a second cathode layer having one impurity concentration peak point and provided in contact with both between the first cathode layer and the buffer layer. The crystal defect density of the first cathode layer is higher than that of the second cathode layer, and the cathode layer of the first conductivity type is not provided in the intermediate region and the termination region Region excluding the outer peripheral end is not provided.

Advantages of the Invention

[0008] According to the power semiconductor device of the present disclosure, it is possible to control the trade-off characteristics while realizing the operation in the high-speed side region of the trade-off characteristics between the on-voltage and the switching loss without depending on the carrier lifetime control method.

Brief Description of the Drawings

[0009]

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Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the attached drawings. Note that the drawings are schematically shown, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately described and can be appropriately changed. Also, in the following description, the same reference numerals are given to similar components for illustration, and their names and functions are also assumed to be the same. Therefore, detailed descriptions thereof may be omitted in some cases.

[0011] In addition, in the following description, terms meaning specific positions and directions such as "upper", "lower", "side", "bottom", "front" or "back" may be used, but these terms are used for convenience to facilitate understanding of the content of the embodiments and do not limit the direction during actual implementation.

[0012] Also, in the following description, regarding the conductivity type of the semiconductor, the first conductivity type is an n-type and the second conductivity type is a p-type, but the reverse may also be true.

[0013] Regarding the conductivity type of the semiconductor, n- indicates that the n-type impurity concentration is smaller than that of n, and n+ indicates that the n-type impurity concentration is larger than that of n. Similarly, p- indicates that the p-type impurity concentration is smaller than that of p, and p+ indicates that the p-type impurity concentration is larger than that of p.

[0014] <A. Embodiment 1> <A-1. Configuration> In this embodiment, a power semiconductor device that realizes the high-speed side in the trade-off characteristic between the on-voltage and the switching loss without using the conventional lifetime control method by charged particles and improves the breakdown tolerance during the recovery operation at high temperatures will be described. The power semiconductor device of this embodiment is a power diode or a freewheeling diode (FWD). Also, the on-voltage V F and the switching loss E RECThe high-speed side in the trade-off characteristics refers to the direction of low switching loss in a trade-off curve that represents the trade-off characteristics between the on-voltage and switching loss controlled by the conventional lifetime control using charged particles (for example, the curve represented as the characteristics of the Con. pin diode in FIG. 7).

[0015] FIG. 1 schematically shows the planar structure of a vertical power semiconductor device. As shown in the figure, a plurality of active cell regions R1 are formed in the central part, a surface gate wiring part R12 is provided between two active cell regions R1, and further, a gate pad part R11 is provided in a part of the region.

[0016] An intermediate region R2 is formed surrounding the peripheries of the active cell region R1, the gate pad part R11, and the surface gate wiring part R12, and a termination region R3 is provided surrounding the periphery of the intermediate region R2.

[0017] The above-mentioned active cell region R1 is an element formation region that guarantees the basic performance of the power semiconductor device. And the peripheral region composed of the intermediate region R2 and the termination region R3 is provided for maintaining the breakdown voltage including the reliability aspect. Among them, the intermediate region R2 is a region where the active cell region R1 and the termination region R3 join, which guarantees the breakdown withstand capacity during the dynamic operation of the power semiconductor and supports the original performance of the semiconductor element in the active cell region R1. Also, the termination region R3 supports the original performance of the active cell region R1 by maintaining the breakdown voltage in a static state, ensuring the stability of the breakdown voltage characteristics and the reliability aspect, and suppressing the defect of the breakdown withstand capacity during the dynamic operation.

[0018] However, when the power semiconductor device is a diode, the surface gate wiring part R12 and the gate pad part R11 may not be provided.

[0019] Figures 2 and 3 show the cross-sectional structure of a pin diode, which is an example of a power semiconductor device, along the line A-A' in Figure 1. Figure 2 is a cross-sectional view of a conventional pin diode 1000, and Figure 3 is a cross-sectional view of a pin diode 1001 according to Embodiment 1. In the figures, the conventional pin diode 1000 may be denoted as Con. pin diode, and the pin diode 1001 according to Embodiment 1 may be denoted as New pin diode 1.

[0020] First, the conventional pin diode 1000 will be described. The pin diode 1000 includes a semiconductor substrate 20, a first metal layer 5, a second metal layer 14, an oxide film 15, a TEOS layer 16, and passivation films 12 and 13.

[0021] The semiconductor substrate 20 includes a first main surface 21, which is the upper main surface in Figures 2 and 3, and a second main surface 22 facing the first main surface 21. The first metal layer 5 is provided on the first main surface 21 of the semiconductor substrate 20, and the second metal layer 14 is provided on the second main surface 22 of the semiconductor substrate 20.

[0022] The semiconductor substrate 20 includes a p anode layer 6, an n-drift layer 7, an n-buffer layer 8, an n+ cathode layer 9, a p layer 10, and an n+ layer 11. The p anode layer 6 is provided between the n-drift layer 7 and the first main surface 21 in the active cell region R1. The sidewall of the contact hole for connecting the p anode layer 6 and the first metal layer 5 is located at the boundary between the active cell region R1 and the intermediate region R2.

[0023] The p layer 10 is provided between the n-drift layer 7 and the first main surface 21 in the intermediate region R2 and a part of the terminal region R3. The surfaces of the p anode layer 6 and the p layer 10 constitute the first main surface 21 of the semiconductor substrate 20. In Figures 2 and 3, the depths of the p layer 10 and the p anode layer 6 are different, but as described in the manufacturing methods of Figures 23 and 24 to be described later, they may have the same depth by being formed in the same ion implantation and annealing process. In the active cell region R1, the intermediate region R2, and the termination region R3, an n-buffer layer 8 is provided between the n-drift layer 7 and the second main surface 22. An n+ cathode layer 9 is provided between the n-buffer layer 8 and the second main surface 22. The lower surface of the n+ cathode layer 9 constitutes the second main surface 22 of the semiconductor substrate 20 and is in contact with the second metal layer 14.

[0024] The n+ layer 11 is provided at the end of the termination region R3 on the first main surface 21 side of the semiconductor substrate 20. The n+ layer 11 is also referred to as the first impurity region.

[0025] In the active cell region R1, the intermediate region R2, and the termination region R3, a vertical region including the n+ cathode layer 9, that is, the n+ cathode layer 9 and the n-buffer layer 8, the n-drift layer 7, and the p-anode layer 6 above it constitute a vertical structure 29. The vertical structure 29 guarantees the total loss performance, the breakdown voltage holding in the static state, the stability of the breakdown voltage characteristics, the leakage characteristics during voltage holding at high temperatures, the guarantee in terms of reliability, and the controllability and breakdown tolerance during dynamic operation, and supports the basic performance of the power semiconductor. The total loss in the power diode is the sum of the on-state loss, the off-state loss, and the turn-off state loss.

[0026] Also, the structure between the n-drift layer 7 and the second metal layer 14 is also referred to as the back surface side structure. That is, in the pin diode 1000, the n-buffer layer 8 and the n+ cathode layer 9 are the back surface side structures.

[0027] The n-drift layer 7 has an impurity concentration C n- of 1.0×10 12 atoms / cm 3 or more and 1.0×10 15 atoms / cm 3 or less, and is formed using an Si wafer. That is, the semiconductor substrate 20 is an Si substrate. The device thickness t device which is the thickness of the semiconductor substrate 20 is 40 μm or more and 700 μm or less.

[0028] The p-anode layer 6 has an impurity concentration of 1.0×10 on the surface in contact with the first metal layer 5, that is, on the first main surface 2116 atoms / cm 3 is above, and the peak impurity concentration is 2.0×10 16 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less, and the depth is 2.0 μm or more and 10.0 μm or less.

[0029] The n-buffer layer 8 has a peak impurity concentration C nb,p of 1.0×10 15 atoms / cm 3 or more and 5.0×10 16 atoms / cm 3 or less, and the depth X j,nb is 1.2 μm or more and 50 μm or less.

[0030] Next, the pin diode 1001 according to Embodiment 1 will be described. The back-side structure of the pin diode 1001 is different from that of the pin diode 1000. The pin diode 1001 includes an n+ cathode layer 90 instead of the conventional n+ cathode layer 9.

[0031] The n+ cathode layer 90 is provided between the n-buffer layer 8 and the second metal layer 14 inside the active cell region R1. The n+ cathode layer 90 is a two-layer cathode layer composed of a first n+ cathode layer 91 and a second n+ cathode layer 92. The first n+ cathode layer 91 is in contact with the second metal layer 14, and the second n+ cathode layer 92 is in contact with the n-buffer layer 8. The lower surface of the first n+ cathode layer 91 in FIG. 3 constitutes the second main surface 22 of the semiconductor substrate 20. That is, in the pin diode 1001, the n-buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92 constitute the back-side structure.

[0032] The n+ cathode layer 90 is not provided in the intermediate region R2 and the terminal region R3. In the intermediate region R2 and the terminal region R3, the n-buffer layer 8 is directly in contact with the second metal layer 14. In other respects, the pin diode 1001 has the same configuration as the pin diode 1000.

[0033] Hereinafter, the first n+ cathode layer 91 is referred to as the first cathode layer, and its conductivity type may be denoted as n+1 in the figure. Also, the second n+ cathode layer 92 is referred to as the second cathode layer, and its conductivity type may be denoted as n+2 in the figure.

[0034] The first n+ cathode layer 91 has an impurity concentration of 1.0×10 19 atoms / cm 3 or more and 1.0×10 20 atoms / cm 3 or less on the surface in contact with the second metal layer 14, i.e., the second main surface 22, and the depth is 0.1 μm or more and 0.2 μm or less.

[0035] The second n+ cathode layer 92 has a peak impurity concentration of 1.0×10 17 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less, and the depth is 0.3 μm or more and 0.5 μm or less.

[0036] The n+ cathode layer 90 exists only inside the active cell region R1. That is, the n+ cathode layer 90 is provided away from the boundary between the active cell region R1 and the intermediate region R2. The n+ cathode layer 90 is not formed at the boundary portion of the active cell region R1 with the intermediate region R2, and in this portion, the n buffer layer 8 is in direct contact with the second metal layer 14. That is, the n buffer layer 8 is in direct contact with the second metal layer 14 from the boundary portion of the active cell region R1 with the intermediate region R2 over the intermediate region R2 and the terminal region R3.

[0037] As described above, the pin diode 1001 includes two n+ cathode layers in the active cell region R1, i.e., the first n+ cathode layer 91 and the second n+ cathode layer 92. The purpose of each layer is as follows.

[0038] The first n+ cathode layer 91 is a diffusion layer for improving the contact property with the second metal layer 14. The crystal defect density of the first n+ cathode layer 91 is higher than that of the second n+ cathode layer 92 and the n buffer layer 8. The second n+ cathode layer 92 is a diffusion layer for controlling the performance of the pin diode 1001 and ensuring normal on-operation.

[0039] The impurity profile and depth of the diffusion layer can be determined by the range (RP) during ion implantation, based on the characteristics of the annealing technique during the formation of the diffusion layer. Here, the range is defined as the depth from the second major surface 22 to the position of the peak concentration of each diffusion layer. Therefore, the ranges during ion implantation when forming the first n+ cathode layer 91 and the second n+ cathode layer 92 are defined by the following formula (1) so that the layers do not interfere with each other.

[0040] R n+2 / R n+1 =5.0 …(1) Here, R n+1 ,R n+2 represents the ranges (m) of the first n+ cathode layer 91 and the second n+ cathode layer 92, respectively.

[0041] Figure 4 shows the impurity concentration in the diffusion layer of the pin diode 1001 along the C-C' line in Figure 3. The horizontal axis in Figure 4 indicates the depth (μm) from the second major surface 22 of the semiconductor substrate 20, and the vertical axis indicates the impurity concentration (atoms / cm 3 ).

[0042] <A-2. Performance> The performance of the pin diode 1001 according to Embodiment 1 is shown below. FIG. 5 shows the PL spectra when the n+ cathode layer 9 in the conventional pin diode 1000 and the first n+ cathode layer 91 in the pin diode 1001 according to Embodiment 1 are analyzed by the Photoluminescence (PL) method. The PL method is an analytical technique in which light is irradiated onto a semiconductor, and the light emitted when electrons and holes recombine via defect energy levels is observed. The horizontal axis in FIG. 5 indicates the photon energy (eV), and the vertical axis in FIG. 5 indicates a physical quantity normalized by the PL intensity at the band edge detected by the PL method.

[0043] The analysis conditions for the PL method are as follows. A He-Ne laser with a wavelength of 633 nm is used. The temperature is 30 K. The output of the laser light irradiated onto the sample surface is 4.5 mW. The diameter of the laser light is 1.3 μm. The intensity of the laser light on the sample surface is 0.339 MW / cm 2 is.

[0044] In FIG. 5, the dashed line indicates the PL spectrum of the conventional n+ cathode layer 9, and the solid line indicates the PL spectrum of the first n+ cathode layer 91 in Embodiment 1. It can be seen from FIG. 5 that there are two peaks in the PL intensity in the first n+ cathode layer 91. The first peak is due to trap A with a photon energy of 0.969 eV, and the second peak is due to trap B with a photon energy of 1.018 eV. Trap A and trap B are energy levels derived from C i C s (G-center) and W-center, respectively. Trap A is also referred to as the first lattice defect, and trap B is also referred to as the second lattice defect.

[0045] FIG. 6 is a diagram comparing the PL intensities of three diffusion layers constituting the second main surface 22 of the pin diode 1001. The PL intensity in the figure is a value normalized by the intensity of the band edge detected in the PL spectrum. When the PL intensity in the figure is high, it means that the density of crystal defects to be detected is high. For the n-buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92 that constitute the second main surface 22 of the pin diode 1001, there is a relationship of (n-buffer layer 8) < (second n+ cathode layer 92) < (first n+ cathode layer 91) regarding the crystal defect density of traps A and B. This relationship is obtained from the fact that the impurity concentration of the first n+ cathode layer 91 is one digit or more higher than that of the second n+ cathode layer 92 and the manufacturing method described later.

[0046] The n-buffer layer 8 has a role of stopping the depletion layer extending from the main junction and preventing it from reaching the n+ cathode layer when holding the voltage during reverse bias application to the p-anode layer 6 and the n-drift layer 7 which are the main junctions in the diode. As a result, in the pin diode 1001 of the present embodiment, there is the above-described relationship of crystal defects between the diffusion layers constituting the second main surface 22, and there are no crystal defects in the n-buffer layer 8. Therefore, the increase in leakage current due to crystal defects is eliminated, and it becomes possible to reduce the off-state loss by reducing the leakage current during breakdown voltage holding at high temperatures. For example, when a reverse bias of 1200 V is applied to the main junction of a diode of the 1200 V breakdown voltage class, the loss is reduced from 2.0 W / cm 2 when there are crystal defects in the n-buffer layer 8 to 0.8 W / cm 2 when there are no crystal defects in the n-buffer layer 8. The reduction of the off-state loss is effective from the viewpoint of the thermal design of the power module mounting the power semiconductor.

[0047] As described above, there are two traps in the first n+ cathode layer 91. The first n+ cathode layer 91 in which two traps exist is formed by the process described in Embodiment 6 to be described later. Traps A and B, which are crystal defects in the first n+ cathode layer 91, are formed by reacting with impurities in Si such as oxygen, carbon, or hydrogen through the following steps.

[0048] Step A: By performing ion implantation on the second main surface 22 of the semiconductor substrate 20, lattice defects such as vacancies (V) and interstitial Si pairs (I si ) are formed.

[0049] Step B: The lattice defects formed in Step A diffuse and self-aggregation occurs, forming V2 and interstitial Si pairs (I si :W-center).

[0050] Step C: Simultaneously with Step B, a substitution reaction occurs between carbon atoms (C s ) existing at lattice positions and interstitial Si pairs (I si ), forming interstitial carbon (C i ).

[0051] Step D: Interstitial carbon (C i ) and lattice defects (vacancies (V)) diffuse, and reactions occur between lattice position-substituted carbon (C s ) and interstitial Si pairs (I si ) and impurities (oxygen, carbon, hydrogen) in Si at room temperature, generating impurity defects (complex defects: C i C s ).

[0052] Step E: Crystallinity is restored by annealing treatment, but some interstitial Si pairs (I si :W-center) and impurity defects (complex defects: C i C s ) remain.

[0053] Here, the subscript i represents interstitial, and the subscript s represents substitutional.

[0054] As described above, crystal defects exist in the first n+ cathode layer 91. Due to these crystal defects, the diode performance of the pin diode 1001 is improved, and thermal stability performance is obtained, which is shown by the diode performance of the 1200V class below.

[0055] FIG. 7 shows the trade-off characteristics between the on-voltage V F and the switching loss E REC for each of the conventional pin diode 1000 and the pin diode 1001 according to Embodiment 1. In FIG. 7, the trade-off characteristics of the pin diode 1001 are shown as New pin diode 1. The trade-off characteristics of the pin diode 1000 are the result of control by lifetime control using an electron beam which is a charged particle. Con. pin diode 1 in the figure is the pin diode 1000 without lifetime control by electron beam irradiation.

[0056] In the pin diode 1001, by forming the first n+ cathode layer 91 and the second n+ cathode layer 92 by the process described later in Embodiment 6, the contact property of the second metal layer 14 is improved. As a result, stable electron injection from the n+ cathode layer area when the pin diode 1001 is in the on state becomes possible. As shown in FIG. 7, in the pin diode 1001, due to the first n+ cathode layer 91 having a high defect density of two traps, electron injection from the n+ cathode layer area is suppressed. As a result, the high-speed side in the trade-off characteristic curve realized by the conventional diode by lifetime control using an electron beam can be realized without using lifetime control.

[0057] FIG. 8 shows the recovery waveforms by simulation of the conventional pin diode 1000 and the pin diode 1001 according to Embodiment 1. The device structure used for the simulation is assumed to have a termination region capable of maintaining a breakdown voltage of 2000 V at 298K. The maximum temperature during the recovery operation is also plotted in the figure. Also, in the figure, the on-state point is represented as Point A, and the point where the maximum temperature is reached during the recovery operation is represented as Point B.

[0058] FIG. 9 shows the current density distribution at Point B of the conventional pin diode 1000. FIG. 10 shows the current density distribution at Point B of the pin diode 1001 according to Embodiment 1. FIG. 11 shows the temperature distribution at Point B of the conventional pin diode 1000. FIG. 12 shows the temperature distribution at Point B of the pin diode 1001 according to Embodiment 1.

[0059] From FIGS. 9 and 11, it can be seen that in the conventional pin diode 1000, there is a point where the current density locally increases at the boundary between the active cell region R1 and the intermediate region R2, and a local temperature rise occurs at this point. Since the temperature at this point exceeds 800K, which is the critical temperature at which the pn junction of the Si-based device disappears, it is suggested that the breakdown tolerance during the recovery operation is reduced in the conventional pin diode 1000.

[0060] On the other hand, from FIGS. 10 and 12, it can be seen that in the pin diode 1001 according to Embodiment 1, there is no point where the current density locally increases at the boundary between the active cell region R1 and the intermediate region R2, and it can be seen that the breakdown tolerance during the recovery operation is improved.

[0061] FIG. 13 is a diagram showing the carrier concentration distribution at Point A of the conventional pin diode 1000. FIG. 14 shows the carrier concentration distribution at Point A of the pin diode 1001 according to Embodiment 1. FIG. 15 shows the carrier concentration distribution at Point B of the conventional pin diode 1000. FIG. 16 shows the carrier concentration distribution at Point B of the pin diode 1001 according to Embodiment 1. FIGS. 13 to 16 show the carrier concentration distributions in the device depth direction along the B-B' line (Position B) and the C-C' line (Position C) of FIGS. 2 and 3 for electrons and holes.

[0062] As shown in FIGS. 13 to 16, compared with the conventional pin diode 1000, the pin diode 1001 according to Embodiment 1 has a lower carrier concentration on the first main surface 21 side at the boundary between the active cell region R1 and the intermediate region R2 in the on state. Therefore, it can be seen that the carrier concentration on the first main surface 21 side during the recovery operation decreases rapidly.

[0063] FIG. 17 shows the electric field strength distributions at Point B of the pin diodes 1000 and 1001 according to the conventional and Embodiment 1. FIG. 17 shows the electric field strength distributions in the device depth direction along the B-B' line (Position B) and C-C' line (Position C) of FIGS. 2 and 3.

[0064] From FIGS. 13 to 17, it can be seen that the pin diode 1001 according to Embodiment 1 exhibits the following two characteristic carrier concentration distributions.

[0065] (1) The active cell region R1 in the on state exhibits the same carrier concentration distribution as the conventional pin diode 1000.

[0066] (2) As compared with the conventional pin diode 1000, in the on state, carrier injection on the second main surface 22 side from the boundary between the active cell region R1 and the intermediate region R2 to the termination region R3 is suppressed. As a result, the carrier concentration on the first main surface 21 side at the boundary between the active cell region R1 and the intermediate region R2 is lower than that in the active cell region R1 in the on state.

[0067] As a result, the carrier concentration on the first main surface 21 side during the recovery operation is reduced, and the depletion of the corresponding portion is promoted, resulting in the effect that the electric field strength decreases. As shown in FIGS. 9 to 12, this behavior is the reason why the pin diode 1001 according to Embodiment 1 does not cause a temperature rise due to local current concentration at the boundary between the active cell region R1 and the intermediate region R2 compared with the conventional pin diode 1000.

[0068] FIG. 18 shows the relationship between the maximum power density and the forward current density (JF) during the recovery operation of the pin diodes 1000 and 1001 according to the conventional and Embodiment 1. In the comparison of FIG. 18, the device thickness t of the pin diodes 1000 and 1001 according to the conventional and Embodiment 1 device is constant.

[0069] The conventional pin diode 1000 breaks down when the power density reaches 2.5 MW / cm 2 . The power density at which the conventional pin diode 1000 breaks down is a physical quantity that depends on the device thickness t device . The conventional pin diode 1000 is considered to have broken down because it reached the power density determined by t device .

[0070] The pin diode 1001 according to Embodiment 1 has the first n+ cathode layer 91 with a high crystal defect density, but there are no crystal defects in the n buffer layer 8. Therefore, there is no problem in operating at a high temperature of 423K, and it can block a higher current density than the conventional pin diode 1000, improving the breakdown tolerance during the recovery operation. Also, in the pin diode 1001 according to Embodiment 1, since the electron injection efficiency from the first n+ cathode layer 91 and the second n+ cathode layer 92 is suppressed, the power density at the same current density J F is lower than that of the conventional pin diode 1000. As a result, the J F value at which the device breaks down reaches the critical power density, enabling the blocking of a higher current density.

[0071] From the above, the pin diode 1001 according to Embodiment 1 can achieve the on-voltage V F and the switching loss E RECWhile controlling the trade-off characteristics to the high-speed side, it is thermally stable because the breakdown tolerance at high temperatures is improved. The performance of this pin diode 1001 can be realized not only with an Si wafer manufactured by the Floating Zone (FZ) method on the semiconductor substrate 20, but also when using an Si wafer manufactured by the Magnetic applied Czochralski (MCZ) method with a higher residual oxygen and carbon concentration in the Si material. The Si wafer manufactured by the MCZ method has an oxygen concentration of 1.0×10 17 atoms / cm 3 or more and 7.0×10 17 atoms / cm 3 or less, and a carbon concentration of 1.0×10 14 atoms / cm 3 or more and 5.0×10 15 atoms / cm 3 or less. This is because the main crystal defects that control the diode performance in the pin diode 1001 are not impurity defects, but are the interstitial Si pairs formed by ion implantation and annealing in the manufacturing method, and are not formed by the reaction with residual oxygen and residual carbon in the Si.

[0072] <A-3. Effect> The pin diode 1001 according to Embodiment 1 is divided, in a plan view, into an active cell region R1, an intermediate region R2 surrounding the active cell region R1, and a termination region R3 surrounding the intermediate region R2. The pin diode 1001 includes a semiconductor substrate 20 having first and second main surfaces 21 and 22 facing each other, first metal layers 51, 52, 53 provided on the first main surface 21 of the semiconductor substrate 20, and a second metal layer 14 provided on the second main surface 22 of the semiconductor substrate 20. The semiconductor substrate 20 includes an n-drift layer 7 of a first conductivity type, an n-buffer layer 8 of the first conductivity type provided between the n-drift layer 7 and the second metal layer 14 in the active cell region R1, and at least one n+-cathode layer 90 of the first conductivity type provided in contact with both the n-buffer layer 8 and the second metal layer 14 in the active cell region R1. The n+-cathode layer 90 includes a first n+-cathode layer 91 having one impurity concentration peak point and in contact with the second metal layer 14, and a second n+-cathode layer 92 having one impurity concentration peak point and provided in contact with both the first n+-cathode layer 91 and the n-buffer layer 8 therebetween. The crystal defect density of the first n+-cathode layer 91 is higher than that of the second n+-cathode layer 92, and the n+-cathode layer 91 of the first conductivity type is not provided in the intermediate region R2 and the termination region R3. Therefore, even without using the conventional lifetime control method, the on-voltage V F and the switching loss E REC of the trade-off characteristics are controlled to the high-speed side, and the breakdown tolerance at high temperatures is improved, so that it is thermally stable.

[0073] <B. Embodiment 2> <B-1. Configuration> FIG. 19 shows a cross-sectional configuration of the pin diode 1002 according to Embodiment 2 along the line A-A' of FIG. 1. In the following figures, the pin diode 1002 according to Embodiment 2 may be denoted as New pin diode 2. The pin diode 1002 has a structure in which a p-cathode layer 31 is added to the configuration of the pin diode 1001 according to Embodiment 1.

[0074] The p cathode layer 31 is provided between the n buffer layer 8 and the second metal layer 14 in the intermediate region R2 and the terminal region R3. The lower surface of the p cathode layer 31 contacts the second metal layer 14. That is, the pin diode 1002 has a back surface structure composed of the n buffer layer 8, the first n+ cathode layer 91, the second n+ cathode layer 92, and the p cathode layer 31.

[0075] Similar to the pin diode 1001, in the pin diode 1002, the n+ cathode layer 90 exists only inside the active cell region R1. At the boundary between the active cell region R1 and the intermediate region R2, the n+ cathode layer 90 is not provided. In this part, the p cathode layer 31 contacts the second metal layer 14, and the lower surface of the p cathode layer 31 constitutes the second main surface 22. That is, the p cathode layer 31 contacts the end of the n+ cathode layer 90 on the intermediate region R2 side, and directly contacts the second metal layer 14 from the boundary between the active cell region R1 and the intermediate region R2 to the intermediate region R2 and the terminal region R3.

[0076] The various parameters of the n - drift layer 7, the p anode layer 6, the n buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92 are the same as those in the first embodiment. The impurity concentration on the surface of the p cathode layer 31 that contacts the second metal layer 14, that is, the second main surface 22, is 1.0×10 17 atoms / cm 3 or more and 1.0×10 19 atoms / cm 3 or less, and the depth is 0.3 μm or more and 0.5 μm or less.

[0077] <B - 2. Effect> In the pin diode 1002 according to Embodiment 2, the n-buffer layer 8 is provided between the n-drift layer 7 and the second metal layer 14 in the intermediate region R2 and the termination region R3. Further, the pin diode 1002 includes a second conductivity type cathode layer 31 provided in contact with the second metal layer 14 between the n-buffer layer 8 and the second metal layer 14 in the intermediate region R2 and the termination region R3. By the p-cathode layer 31, in the pin diode 1002, the carrier injection efficiency on the second main surface 22 side in the on state of the diode is suppressed. Therefore, the same effects as those of the pin diode 1001 according to Embodiment 1 shown in FIGS. 9 to 16 can be obtained. That is, according to the pin diode 1002, even without using a conventional lifetime control method, the on voltage V F and the switching loss E REC of the trade-off characteristics can be controlled to the high-speed side while improving the breakdown tolerance at high temperatures, so that it is thermally stable.

[0078] <C. Embodiment 3> <C-1. Configuration> FIG. 20 shows a cross-sectional configuration of the pin diode 1003 according to Embodiment 3 along the line A-A' in FIG. 1. In the following figures, the pin diode 1003 according to Embodiment 3 may be denoted as New pin diode 3. The pin diode 1003 is different from the pin diode 1001 according to Embodiment 1 in that the n-buffer layer 8 is not present in the intermediate region R2 and the termination region R3 and is provided only directly above the n+ cathode layer 90. That is, the pin diode 1003 has a back surface side structure including an n-buffer layer 8, a first n+ cathode layer 91, and a second n+ cathode layer 92.

[0079] Similar to the pin diode 1001, in the pin diode 1003, the n+ cathode layer 90 is also provided inside the active cell region R1, that is, avoiding the boundary with the intermediate region R2. In the boundary portion of the active cell region R1 with the intermediate region R2, the n+ cathode layer 90 is not provided. In this portion, the n-drift layer 7 is in contact with the second metal layer 14, and the lower surface of the n-drift layer 7 constitutes the second main surface 22. Also in the intermediate region R2 and the termination region R3, the n-drift layer 7 is in contact with the second metal layer 14. That is, the n-drift layer 7 is in contact with the end portion on the intermediate region R2 side of the n+ cathode layer 90, and directly contacts the second metal layer 14 from the boundary portion of the active cell region R1 with the intermediate region R2 to the intermediate region R2 and the termination region R3.

[0080] The various parameters of the n-drift layer 7, the p-anode layer 6, the n-buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92 are the same as those in the first embodiment.

[0081] <C - 2. Effect> In the pin diode 1003 according to the third embodiment, the n-buffer layer 8 is provided only in the active cell region R1, and the n-drift layer 7 is in contact with the second metal layer 14 in the intermediate region R2 and the termination region R3. According to the pin diode 1003, since the n-drift layer 7 directly contacts the second metal layer 14 from the intermediate region R2 to the termination region R3, the carrier injection efficiency on the second main surface 22 side in the on state of the diode is suppressed. Therefore, the same effect as that of the pin diode 1001 according to the first embodiment shown in FIGS. 9 to 16 is obtained. That is, according to the pin diode 1003, even without using the conventional lifetime control method, while controlling the trade-off characteristics of the on voltage V F and the switching loss E REC toward the high-speed side, the breakdown tolerance at high temperatures is improved, so it is thermally stable.

[0082] <D. Fourth Embodiment> <D - 1. Configuration> FIG. 21 shows a cross-sectional configuration of the pin diode 1004 according to Embodiment 4 along the line A-A' in FIG. 1. In the following figures, the pin diode 1004 according to Embodiment 4 may be denoted as New pin diode 4. The pin diode 1004 is different from the pin diode 1001 according to Embodiment 1 only in that the two-layer n+ cathode layer 90 is also provided on the second main surface 22 side of the n+ layer 11 in the termination region R3. That is, in the region of the termination region R3 that overlaps the n+ layer 11 in a plan view, the n+ cathode layer 90 is provided between the n buffer layer 8 and the second metal layer 14. In the n+ cathode layer 90 in the termination region R3, similar to the n+ cathode layer 90 in the active cell region R1, the first n+ cathode layer 91 is in contact with the second metal layer 14, and the second n+ cathode layer 92 is in contact with the n buffer layer 8. The pin diode 1004 has a back-side structure composed of the n buffer layer 8, the first n+ cathode layer 91, and the second n+ cathode layer 92.

[0083] The parameters of the n+ cathode layer 90 in the termination region R3 are the same as those of the n+ cathode layer 90 in the active cell region R1. Also, the various parameters of the n-drift layer 7, the p-anode layer 6, and the n buffer layer 8 are the same as those in Embodiment 1.

[0084] <D-2. Effect> In the pin diode 1004 according to Embodiment 4, in the intermediate region R2 and the terminal region R3, the n-buffer layer 8 is provided in contact with the second metal layer 14 between the n-drift layer 7 and the second metal layer 14. Further, the semiconductor substrate 20 includes an n+-layer 11 which is a first impurity region of the first conductivity type having a higher impurity concentration than the n-drift layer 7, provided in the surface layer including the first main surface 21 at the outer peripheral end of the terminal region R3. The n+ cathode layer 90 is also provided in contact with both the n-buffer layer 8 and the second metal layer 14 between them directly below the n+-layer 11. The n-buffer layer 8 is in contact with the second metal layer 14 in the region of the terminal region R3 where the n+ cathode layer 90 is not provided and in the intermediate region R2. Even with such a structure, in the regions of the intermediate region R2 and the terminal region R3 other than directly below the n+-layer 11, since the n-buffer layer 8 contacts the second metal layer 14, the carrier injection efficiency on the second main surface 22 side in the on state of the diode is suppressed. Therefore, the same effect as that of the pin diode 1001 according to Embodiment 1 shown in FIGS. 9 to 16 is obtained. That is, according to the pin diode 1004, even without using the conventional lifetime control method, while controlling the trade-off characteristics between the on voltage V F and the switching loss E REC to the high-speed side, the breakdown tolerance at high temperature is improved, so it is thermally stable.

[0085] <E. Embodiment 5> <E-1. Configuration> FIG. 22 shows a cross-sectional configuration of the pin diode 1005 according to Embodiment 5 along the line A-A' in FIG. 1. In the following figures, the pin diode 1005 according to Embodiment 5 may be denoted as New pin diode 5. The pin diode 1005 is different from the pin diode 1001 according to Embodiment 1 in that a plurality of n+ cathode layers 90 are provided spaced apart inside the active cell region R1. That is, the pin diode 1005 has a back-side structure including an n-buffer layer 8, a first n+ cathode layer 91, and a second n+ cathode layer 92.

[0086] Each n+ cathode layer 90 is provided between the n buffer layer 8 and the second metal layer 14. Between two adjacent n+ cathode layers 90, the n buffer layer 8 contacts the second metal layer 14. Among the plurality of n+ cathode layers 90, even the n+ cathode layer 90 disposed closest to the middle region R2 does not contact the boundary with the middle region R2. In a region where the n+ cathode layer 90 is not formed on the second metal layer 14 in the active cell region R1, the n buffer layer 8 contacts the second metal layer 14.

[0087] FIG. 22 shows two n+ cathode layers 90 in the active cell region R1, but three or more n+ cathode layers 90 may be provided spaced apart in the active cell region R1.

[0088] Let the width of the n+ cathode layer 90 be Wn+. And let the width of a unit unit composed of the n buffer layer 8 between adjacent n+ cathode layers 90 and one n+ cathode layer 90 be Wcell. At this time, by setting Wn+ / Wcell to an arbitrary value in the range of 0.1 or more and less than 1.0, as shown as the New pin diode 5 in FIG. 7, the on voltage V F and the switching loss E REC It is possible to achieve compatibility with the high-speed side region of the trade-off characteristics and control. The other various parameters of the n-drift layer 7, p-anode layer 6, n-buffer layer 8, first n+ cathode layer 91, and second n+ cathode layer 92 are the same as those in the first embodiment.

[0089] <E-2. Effect> The pin diode 1005 according to the fifth embodiment has the same back side structure as the pin diode 1001 according to the first embodiment in the middle region R2 and the terminal region R3. Therefore, the breakdown withstand during the recovery operation is improved. Also, at least one n+ cathode layer 90 of the first conductivity type in the active cell region R1 is a plurality of n+ cathode layers 90 provided spaced apart. Therefore, by setting Wn+ / Wcell to an arbitrary value in the range of 0.1 or more and less than 1.0, as shown as the New pin diode 5 in FIG. 7, without relying on the conventional lifetime control method, the on voltage V Fand switching loss E REC is thermally stable while controlling the trade-off characteristics to the high-speed side.

[0090] <F. Embodiment 6> <F-1. Manufacturing method> In this embodiment, a method for manufacturing the pin diode 1001 according to Embodiment 1 will be described. FIGS. 23 to 31 are cross-sectional views showing the method for manufacturing the pin diode 1001.

[0091] The features of the method for manufacturing the pin diode 1001 are as follows. There are ion implantation and annealing for forming the first n+ cathode layer 91 and the second n+ cathode layer 92. In the method for manufacturing the pin diode 1002 described later, before the ion implantation for forming the first n+ cathode layer 91 and the second n+ cathode layer 92, there is ion implantation for forming the p cathode layer 31. There is no lifetime control process. Also, the second metal layer 14 is for a two-layer diffusion layer structure.

[0092] Hereinafter, the method for manufacturing the pin diode 1001 will be described with reference to FIGS. 23 to 31. FIG. 23 shows an active cell region R1, an intermediate region R2, and a termination region R3 formed so as to surround the active cell region R1. First, a semiconductor substrate 20 having only the n-drift layer 7 formed thereon is prepared. Then, a plurality of p-layers 10 are selectively formed on the surface of the n-drift layer 7 in the intermediate region R2 and the termination region R3. The plurality of p-layers 10 are formed by ion implantation using a previously formed oxide film 15 as a mask and then subjecting the semiconductor substrate 20 to an annealing process. Note that an oxide film 68 formed during the formation of the oxide film 15 is also formed on the second main surface 22 of the semiconductor substrate 20.

[0093] Next, as shown in FIG. 24, ion implantation and annealing are performed on the surface of the n-drift layer 7 in the active cell region R1 to form the p anode layer 6. Note that the p-layer 10 and the p anode layer 6 may be formed by the same ion implantation and annealing process.

[0094] Subsequently, as shown in FIG. 25, an n+ layer 11 is formed at the end of the termination region R3 on the first main surface 21 side of the semiconductor substrate 20. The impurity concentration on the surface of the n+ layer 11 is 1.0×10 20 cm -3 or more and 1.0×10 22 cm -3 or less, and the depth is 1.0 μm or more and 10 μm or less. Next, a TEOS layer 16 is formed on the upper surface of the semiconductor substrate. Then, a process is performed to remove the oxide film 68 and expose the second main surface 22 of the semiconductor substrate 20. And a doped polysilicon layer 65 doped with impurities is formed in contact with the n- drift layer 7 exposed on the second main surface 22 of the semiconductor substrate 20. The impurities in the doped polysilicon layer 65 are atoms that can diffuse into Si such as phosphorus, arsenic, or antimony to form an n+ layer. The doped polysilicon layer 65 is a film doped with high-concentration impurities of 1×10 19 atoms / cm 3 or more, and the film thickness is 500 nm or more. At this time, a doped polysilicon layer 64 is also formed on the first main surface 21 of the semiconductor substrate 20.

[0095] Next, the semiconductor substrate 20 is thermally annealed at 900° C. or more and 1000° C. or less in a nitrogen atmosphere. Further, while maintaining the nitrogen atmosphere, the heating temperature is set to 600° C. or more and 700° C. or less at an arbitrary cooling speed, and low-temperature thermal annealing is performed. As shown in FIG. 26, the impurities in the doped polysilicon layer 65 are diffused to the second main surface 22 side of the n- drift layer 7, and a gettering layer 55 having crystal defects and impurities is formed on the second main surface 22 side of the n- drift layer 7. Then, an annealing process is performed to capture the metal impurities, contaminant atoms, and damage in the n- drift layer 7 by the gettering layer 55. As a result, the carrier lifetime of the n- drift layer 7 that has decreased during the previous wafer process is recovered, and τ t or more of the value defined by Equation (2) is realized. This process can be adopted not only for power diodes but also for IGBTs or RC-IGBTs.

[0096] τ t =1.5×10 -5 exp(5.4×10 3 tN- ) ··· (2) Here, t N- represents the thickness (m) of the n-drift layer 7. τ t represents the carrier lifetime (sec) in the n-drift layer 7 where the influence of the carrier lifetime on the on-voltage disappears.

[0097] The on-voltage of the pin diode 1001 depends on the carrier lifetime of the n-drift layer 7. Equation (2) represents the carrier lifetime τ t (s) that minimizes the dependence of the on-voltage of the pin diode 1001 on the carrier lifetime of the n-drift layer 7. The carrier lifetime τ represented by Equation (2) t If realized, the influence of the carrier lifetime on the switching loss can be minimized, which is effective for reducing the off-loss or suppressing thermal runaway.

[0098] Thereafter, as shown in FIG. 27, the doped polysilicon layer 64 formed on the first main surface 21 side of the semiconductor substrate 20 is selectively removed using a liquid of hydrofluoric acid or a mixed acid (for example, a mixed solution of hydrofluoric acid / nitric acid / acetic acid).

[0099] Next, as shown in FIG. 28, contact holes are formed to expose the p-layer 10, p-anode layer 6, and n+-layer 11 on the first main surface 21 of the semiconductor substrate 20. That is, the TEOS layer 16 is processed as shown in FIG. 28. Thereafter, an aluminum wiring 5A doped with Si at about 1% or more and 3% or less is formed by a sputtering method. The aluminum wiring 5A corresponds to the first metal layers 51, 52, 53 in FIG. 3.

[0100] Subsequently, as shown in FIG. 29, passivation films 12, 13 are formed on the first main surface 21 side of the semiconductor substrate 20.

[0101] Thereafter, as shown in FIG. 30, a surface protection film 23 is formed on the first main surface 21 side of the semiconductor substrate 20. Then, the gettering layer 55 and the doped polysilicon layer 65 formed on the second main surface 22 of the semiconductor substrate 20 are removed by polishing or etching. By this removal process, the thickness tD of the semiconductor substrate 20 becomes corresponding to the breakdown voltage class of the semiconductor device.

[0102] Then, as shown in FIG. 31, an n buffer layer 8 is formed on the lower surface side of the n-drift layer 7. Thereafter, a first n+ cathode layer 91 and a second n+ cathode layer 91 are formed on the lower surface of the n buffer layer 8 in the active cell region R1. The first n+ cathode layer 91 and the second n+ cathode layer 92 are diffusion layers formed by ion implantation and annealing processes.

[0103] Note that although FIG. 31 shows the pin diode 1001, when manufacturing the pin diode 1004 according to Embodiment 4, in the process shown in FIG. 31, not only in the active cell region R1 but also directly below the n+ layer 11 in the termination region R3, the first n+ cathode layer 91 and the second n+ cathode layer 91 are formed. Further, when manufacturing the pin diode 1005 according to Embodiment 5, in the process shown in FIG. 31, a plurality of sets of the first n+ cathode layer 91 and the second n+ cathode layer 91 spaced apart from each other are formed in the active cell region R1.

[0104] Note that when forming the diffusion layer, on the first main surface 21 side of the semiconductor substrate 20, there are the aluminum wiring 5A and the passivation films 12 and 13. Therefore, the annealing for forming the diffusion layer is performed using an annealing technique such that the temperature on the first main surface 21 side of the semiconductor substrate 20 is lower than the melting point 660° C. of the aluminum used for the aluminum wiring 5A, or a laser having a wavelength that has a temperature gradient in the device depth direction and does not transmit heat of 660° C. or higher of the aluminum to the first main surface 21 side.

[0105] FIG. 32 is a flowchart showing the processes after the formation of the surface protection film 23 for the manufacturing processes of the pin diodes 1001, 1004, and 1005 according to Embodiments 1, 4, and 5.

[0106] First, in step S101, a surface protection film 23 is formed on the first main surface 21 side of the semiconductor substrate 20. Next, in steps S102 and S103, the gettering layer 55 and the doped polysilicon layer 65 formed on the second main surface 22 of the semiconductor substrate 20 are removed by polishing and etching. By this removal process, the thickness t of the semiconductor substrate 20 D becomes corresponding to the breakdown voltage class of the semiconductor device. Also, the carrier lifetime of the n-drift layer 7 satisfies Equation (2).

[0107] Next, in step S104, ion implantation for forming the n-buffer layer 8 is performed. This ion implantation is also referred to as the first ion implantation. Next, in step S105, annealing for activating the ions implanted in step S104 is performed. The annealing in step S105 is also referred to as the first annealing.

[0108] Thereafter, a backside structure is formed. First, in step S106, photolithography for forming an n+ cathode layer 90 partially in the active cell region R1 is performed. The resist formed in this step is also referred to as the first resist.

[0109] Next, in step S107, ion implantation for forming the second n+ cathode layer 92 is performed. This ion implantation is also referred to as the second ion implantation.

[0110] Next, in step S108, ion implantation for forming the first n+ cathode layer 91 is performed. This ion implantation is also referred to as the third ion implantation. The acceleration energy in the second ion implantation and the third ion implantation is determined such that the range satisfies Equation (1). Thereby, the first n+ cathode layer 91 and the second n+ cathode layer 92 can be formed so as not to interfere with each other.

[0111] Next, in step S109, the first resist for photolithography is removed.

[0112] Thereafter, in step S110, annealing is performed to activate the ions implanted in steps S107 and S108. This annealing is also referred to as the second annealing. By the second annealing, the first n+ cathode layer 91 and the second n+ cathode layer 92 are formed. The first annealing and the second annealing are performed by laser annealing or in a diffusion furnace at a low temperature equal to or lower than the melting point of the metal of the first metal layer 5. The feature of the annealing adopted here is to reproduce the impurity profile at the time of ion implantation even after activation after annealing.

[0113] Thereafter, in step S111, the surface protective film 23 is removed. Next, in step S112, the second main surface 22 is light-etched.

[0114] Thereafter, in step S113, the second metal layer 14 is formed on the second main surface 22 by a sputtering method. The second metal layer 14 is a laminated film composed of a plurality of metal films, for example, a laminated film of a metal in contact with Si, Ti, Ni, and Au. By using AlSi or NiSi in which 1% or more and 3% or less of Si is added to the metal in contact with Si, the effects of the first n+ cathode layer 91 and the second n+ cathode layer 92 are ensured.

[0115] Next, in step S114, annealing is performed at 350°C to form an alloy layer or a silicide layer at the interface between the first n+ cathode layer 91 and the second metal layer 14. The annealing in step S114 is also referred to as the third annealing.

[0116] <G. Embodiment 7> <G-1. Manufacturing Method> In Embodiment 7, a method for manufacturing the pin diode 1002 according to Embodiment 2 will be described. FIG. 33 is a flowchart showing the steps after the formation of the surface protective film 23 for the method of manufacturing the pin diode 1002. The flow in FIG. 33 is obtained by adding step S105A between step S105 and step S106 in the manufacturing steps of the pin diodes 1001, 1004, and 1005 according to Embodiments 1, 4, and 5 shown in FIG. 32.

[0117] After performing the first annealing in step S105 to form the n-buffer layer 8, ion implantation for forming the p-cathode layer 31 is performed in step S105A. This ion implantation is also referred to as the fourth ion implantation. Then, in step S106, photolithography for partially forming the n+ cathode layer 90 in the active cell region R1 is performed. In the second annealing of step S110, the ions implanted in step S105A, step S107, and step S108 are activated. The second annealing forms the p-cathode layer 31, the first n+ cathode layer 91, and the second n+ cathode layer 92.

[0118] The manufacturing method of the other pin diode 1002 is the same as the manufacturing method of the pin diode 1001 described in Embodiment 6.

[0119] <H. Embodiment 8> <H-1. Manufacturing Method> In Embodiment 8, the manufacturing method of the pin diode 1003 according to Embodiment 3 will be described. FIG. 34 is a flowchart showing the process after the formation step of the surface protective film 23 for the manufacturing method of the pin diode 1003. The flow in FIG. 34 adds step S103A between step S103 and step S104, and adds step S104A between step S104 and step S105 in the manufacturing processes of the pin diodes 1001, 1004, and 1005 according to Embodiments 1, 4, and 5 shown in FIG. 32.

[0120] Step S103A is a photolithography process for forming the n-buffer layer 8 only inside the active cell region R1. The resist formed in this step is also referred to as the second resist. Then, in step S104, ion implantation is performed to form the n-buffer layer 8 only inside the active cell region R1. Then, in step S104A, the second resist for photolithography is removed.

[0121] Note that in FIGS. 32 to 34, a manufacturing method is shown in which the n-buffer layer 8, the p-cathode layer 31, the second n+-cathode layer 92, and the first n+-cathode layer 91 are activated in separate annealing processes. However, all the diffusion layers may be activated in a batch by the second annealing.

[0122] <I. Embodiment 9> In Embodiment 9, an example in which the back-side structure of the pin diodes 1001-1005 according to Embodiments 1-5 is applied to an RC (Reverse Conductivity)-IGBT will be described.

[0123] <I-1. Configuration> FIG. 35 shows a cross-sectional configuration of the RC-IGBT 1011 along line A-A' of FIG. 1. The RC-IGBT 1011 is an RC-IGBT to which the back-side structure of the pin diode 1001 according to Embodiment 1 is applied. The RC-IGBT 1011 has the same back-side structure as the pin diode 1001 in the diode region 45, the intermediate region R2, and the termination region R3 of the active cell region R1.

[0124] The configurations of the intermediate region R2 and the termination region R3 of the RC-IGBT 1001 are the same as those of the intermediate region R2 and the termination region R3 of the pin diode 1001.

[0125] Hereinafter, the configuration of the active cell region R1 of the RC-IGBT 1011 will be described. An n-layer 26 is formed on the first main surface 21 side of the drift layer 7. A p-base layer 6A is formed on the first main surface 21 side of the n-layer 26. The p-base layer 6A is the same as the p-anode layer 6 in the pin diode 1001 according to Embodiment 1.

[0126] The active cell region R1 of the RC-IGBT 1011 is divided, in a plan view, into an IGBT region 44 that operates as an IGBT and a diode region 45 that operates as a diode. In the IGBT region 44, an n+ emitter layer 24 is formed on the surface layer of the p base layer 6A. A trench 41 is formed from the first main surface 21, which is the upper surface of the n+ emitter layer 24, through the n+ emitter layer 24, the p base layer 6A, and the n layer 26. Also in the diode region 45, a trench 41 is formed from the first main surface 21, which is the upper surface of the p base layer 6A, through the p base layer 6A and the n layer 26.

[0127] A gate electrode 43 is embedded in the trench 41 via a gate insulating film 42. A p+ layer 25 is formed on the surface layer of the p base layer 6A between adjacent trenches 41 in the IGBT region 44. An interlayer insulating film 27 is formed on the first main surface 21 in the IGBT region 44. A first metal layer 51 is formed on the interlayer insulating film 27. Contact holes are formed in the interlayer insulating film 27 to bring the first metal layer 51 into contact with the gate electrode 32 and the p+ layer 25.

[0128] In the IGBT region 44, a p collector layer 31A is formed on the second main surface 22 side of the n buffer layer 8. The p collector layer 31A has the same parameters as the p cathode layer 31 in Embodiment 2. In the diode region 45, an n+ cathode layer 90 is formed on the second main surface 22 side of the n buffer layer 8. The n+ cathode layer 90 has a two-layer structure composed of a first n+ cathode layer 91 and a second n+ cathode layer 92. The second n+ cathode layer 92 is in contact with the n buffer layer 8, and the first n+ cathode layer 91 is in contact with the second metal layer 14.

[0129] <I-2. Modification Example> FIG. 36 shows a cross-sectional configuration of the RC-IGBT 1012 according to the first modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1012 is an example in which the back-side structure of the pin diode 1004 according to the first embodiment is applied to the RC-IGBT. The RC-IGBT 1012 includes a plurality of n+ cathode layers 90 spaced apart between the n buffer layer 8 and the second metal layer 14 in the diode region 45 of the active cell region R1. A p cathode layer 31 is formed between adjacent n+ cathode layers 90. The configuration of the other parts of the RC-IGBT 1012 is the same as that of the RC-IGBT 1011.

[0130] FIG. 37 shows a cross-sectional configuration of the RC-IGBT 1013 according to the second modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1013 is an example in which the back-side structure of the pin diode 1004 according to the fourth embodiment is applied to the RC-IGBT. The RC-IGBT 1013 includes an n+ cathode layer 90 between the n buffer layer 18 and the second metal layer 14 directly below the n+ layer 11 in the termination region R3. The configuration of the other parts of the RC-IGBT 1013 is the same as that of the RC-IGBT 1011.

[0131] FIG. 38 shows a cross-sectional configuration of the RC-IGBT 1014 according to the third modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1014 is an example in which the back-side structure of the pin diode 1005 according to the fifth embodiment is applied to the RC-IGBT. In the diode region of the RC-IGBT 1014, a plurality of n+ cathode layers 90 are provided spaced apart between the n buffer layer 8 and the second metal layer 14. The n buffer layer 8 is in contact with the second metal layer 14 between adjacent n+ cathode layers 90. The configuration of the other parts of the RC-IGBT 1013 is the same as that of the RC-IGBT 1011.

[0132] FIG. 39 shows a cross-sectional configuration of the RC-IGBT 1015 according to the fourth modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1015 is an example in which the back-side structure of the pin diode 1003 according to the third embodiment is applied to the RC-IGBT. In the RC-IGBT 1015, the n-buffer layer 8 is provided only on the p-collector layer 31A and the n+-cathode layer 90 of the active cell region R1. The n-buffer layer 8 is not formed from the boundary with the intermediate region R2 of the active cell region R1 to the intermediate region R2 and the termination region R3, and in these regions, the n-drift layer 7 is in contact with the second metal layer 14. The configuration of the other RC-IGBT 1013 is the same as that of the RC-IGBT 1011.

[0133] FIG. 40 shows a cross-sectional configuration of the RC-IGBT 1016 according to the fifth modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1016 has a configuration in which a p+ layer 28 is added to the RC-IGBT 1011. The p+ layer 28 is provided between the p-base layer 6A of the diode region 45 in the active cell region R1 and the first main surface 21, and forms a contact with the first metal layer 51. The p+ layer 28 is also referred to as the second impurity region.

[0134] FIG. 41 shows a cross-sectional configuration of the RC-IGBT 1017 according to the sixth modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1017 has a configuration in which a p+ layer 28 is added to the RC-IGBT 1012. The p+ layer 28 is provided between the p-base layer 6A of the diode region 45 in the active cell region R1 and the first main surface 21, and forms a contact with the first metal layer 51.

[0135] FIG. 42 shows a cross-sectional configuration of the RC-IGBT 1018 according to the seventh modification of the ninth embodiment along the line A-A' in FIG. 1. The RC-IGBT 1018 has a configuration in which a p+ layer 28 is added to the RC-IGBT 1013. The p+ layer 28 is provided between the p-base layer 6A of the diode region 45 in the active cell region R1 and the first main surface 21, and forms a contact with the first metal layer 51.

[0136] Figure 43 shows a cross-sectional configuration of the RC-IGBT 1019 according to the eighth modification of the ninth embodiment, taken along line A-A' of FIG. 1. The RC-IGBT 1019 has a configuration in which a p+ layer 28 is added to the RC-IGBT 1014. The p+ layer 28 is provided between the p-base layer 6A of the diode region 45 in the active cell region R1 and the first main surface 21, and forms a contact with the first metal layer 51.

[0137] Figure 44 shows a cross-sectional configuration of the RC-IGBT 1020 according to the ninth modification of the ninth embodiment, taken along line A-A' of FIG. 1. The RC-IGBT 1020 has a configuration in which a p+ layer 28 is added to the RC-IGBT 1015. The p+ layer 28 is provided between the p-base layer 6A of the diode region 45 in the active cell region R1 and the first main surface 21, and forms a contact with the first metal layer 51.

[0138] The parameters of the n-drift layer 7, n-buffer layer 8, and n+ cathode layer 90 in the RC-IGBTs 1011 - 1020 are the same as those in the first embodiment. Also, the parameters of the p-cathode layer 31 in the RC-IGBTs 1012, 1017 are the same as those in the second embodiment. Also, the thickness t of the semiconductor substrate 20 in the RC-IGBTs 1011 - 1020 device is also the same as that in the first embodiment.

[0139] The parameters specific to the RC-IGBTs 1011 - 1020 are as follows. The p-base layer 6A has a peak impurity concentration of 1.0×10 16 atoms / cm 3 or more and 1.0×10 18 atoms / cm 3 or less, and the junction depth is made deeper than the n+ emitter layer 24 and shallower than the n layer 26.

[0140] The n layer 26 has a peak impurity concentration of 1.0×10 15 atoms / cm 3 or more and 1.0×10 17 atoms / cm 3 or less, and the junction depth is made 0.5 μm or more and 1.0 μm or less deeper than the p-base layer 6A.

[0141] The n+ emitter layer 24 and the n+ layer 11 have a peak impurity concentration of 1.0×10 18 atoms / cm 3 or more and 1.0×10 21 atoms / cm 3 or less, and the depth is 0.2 μm or more and 1.0 μm or less.

[0142] The trench depth Dtrench is 2.0 μm or more and deeper than the n layer 26.

[0143] The p+ layer 28 has a surface impurity concentration of 1.0×10 18 atoms / cm 3 or more and 1.0×10 21 atoms / cm 3 or less, and the junction depth is equal to or greater than the n+ emitter layer 24.

[0144] <I-3. Effect> The backside structure in the diode region 45, the intermediate region R2, and the termination region R3 of the RC-IGBTs 1011 - 1020 according to Embodiment 9 and its various modifications is formed by the process flow shown in Embodiments 6 - 8. Also in the RC-IGBTs 1011 - 1020, similar to the pin diodes 1001 - 1005 of Embodiments 1 - 5, without using the conventional lifetime control method, while controlling the trade-off characteristics of the on-voltage V F and the switching loss E REC toward the high-speed side, the breakdown withstand at high temperatures is improved, so it is thermally stable. However, this performance relates to the diode region 45 that constitutes the RC-IGBTs 1011 - 1020.

[0145] As described in detail above for the preferred embodiments and the like, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments and the like without departing from the scope described in the claims.

[0146] Hereinafter, aspects of the present disclosure will be summarized and described as appendices.

[0147] (Appendix 1) In a plan view, it is divided into an active cell region, an intermediate region surrounding the active cell region, and a terminal region surrounding the intermediate region, a semiconductor substrate having a first main surface and a second main surface facing each other, a first metal layer provided on the first main surface of the semiconductor substrate, a second metal layer provided on the second main surface of the semiconductor substrate, and includes, the semiconductor substrate, a drift layer of a first conductivity type, a first conductivity type buffer layer provided between the drift layer and the second metal layer in the active cell region, at least one first conductivity type cathode layer provided in contact with both between the buffer layer and the second metal layer in the active cell region, and includes, the first conductivity type cathode layer, a first cathode layer having one impurity concentration peak point and in contact with the second metal layer, a second cathode layer having one impurity concentration peak point and provided in contact with both between the first cathode layer and the buffer layer, and includes, the crystal defect density of the first cathode layer is higher than that of the second cathode layer, the first conductivity type cathode layer is not provided in the intermediate region and the terminal region, A power semiconductor device. (Appendix 2) The crystal defect density of the second cathode layer is higher than that of the buffer layer, The power semiconductor device according to Appendix 1. (Appendix 3) The crystal defects in the first cathode layer are two types of lattice defects detected by a photoluminescence method, The power semiconductor device according to Appendix 1 or Appendix 2. (Appendix 4) The photon energy of one type of lattice defect among the two types of lattice defects in the first cathode layer is 1.018 eV, The power semiconductor device according to Appendix 3. (Supplementary Note 5) The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer in the intermediate region and the terminal region. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 6) The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer at the boundary portion with the intermediate region in the active cell region. The power semiconductor device according to Supplementary Note 5. (Supplementary Note 7) The buffer layer is provided between the drift layer and the second metal layer in the intermediate region and the terminal region. The power semiconductor device further includes a cathode layer of the second conductivity type provided in contact with the second metal layer between the buffer layer and the second metal layer in the intermediate region and the terminal region. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 8) The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The cathode layer of the second conductivity type is provided in contact with the second metal layer between the buffer layer and the second metal layer at the boundary portion with the intermediate region in the active cell region. The power semiconductor device according to Supplementary Note 7. (Supplementary Note 9) The buffer layer is provided only in the active cell region. The drift layer is in contact with the second metal layer in the intermediate region and the terminal region. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 10) The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The drift layer is in contact with the second metal layer at the boundary portion with the intermediate region in the active cell region. The power semiconductor device according to Supplementary Note 9. (Supplementary Note 11) The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer in the intermediate region and the terminal region. The semiconductor substrate includes a first impurity region of a first conductivity type having a higher impurity concentration than the drift layer, provided in a surface layer including the first main surface at an outer peripheral end of the terminal region. The cathode layer of the first conductivity type is provided in contact with both the buffer layer and the second metal layer between the buffer layer and the second metal layer even directly below the first impurity region. The buffer layer is in contact with the second metal layer in a region of the terminal region where the cathode layer of the first conductivity type is not provided and in the intermediate region. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 12) The cathode layer of the first conductivity type is provided avoiding a boundary portion with the intermediate region in the active cell region. The buffer layer is in contact with the second metal layer at a boundary portion with the intermediate region in the active cell region. The power semiconductor device according to Supplementary Note 11. (Supplementary Note 13) The at least one cathode layer of the first conductivity type in the active cell region is a plurality of cathode layers of the first conductivity type provided separately. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 14) The plurality of cathode layers of the first conductivity type are provided avoiding a boundary portion with the intermediate region in the active cell region. The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer at a boundary portion with the intermediate region in the active cell region, in the intermediate region, and in the terminal region. The power semiconductor device according to Supplementary Note 13. (Supplementary Note 15) The semiconductor substrate further includes an anode layer of a second conductivity type provided between the drift layer and the first metal layer in the active cell region and in electrical contact with the first metal layer. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 16) The active cell region includes an IGBT region operating as an IGBT and a diode region operating as a diode. The semiconductor substrate a base layer of a second conductivity type provided between the drift layer and the first main surface; an emitter layer of a first conductivity type provided between the base layer and the first main surface in the IGBT region; a trench penetrating the emitter layer and the base layer; and a gate electrode provided inside the trench. The power semiconductor device according to Supplementary Note 1. (Supplementary Note 17) In the diode region, the base layer is in contact with the first main surface. The power semiconductor device according to Supplementary Note 16. (Supplementary Note 18) The semiconductor substrate further includes a second impurity region of a second conductivity type having a higher impurity concentration than the base layer, which is provided in contact with the first main surface between the base layer and the first main surface in the diode region. The power semiconductor device according to Supplementary Note 16. (Supplementary Note 19) A step of forming a first metal layer and a surface protective film on a first main surface of a semiconductor substrate having a drift layer of a first conductivity type, which is divided into an active cell region, an intermediate region surrounding the active cell region, and a termination region surrounding the intermediate region in a plan view; After forming the surface protective film, a first ion implantation and a first annealing for forming a buffer layer of a first conductivity type are performed on at least the active cell region of a second main surface of the semiconductor substrate facing the first main surface; After the first annealing, a first resist for forming a first cathode layer and a second cathode layer of a first conductivity type is formed on a partial region of the active cell region on the second main surface of the semiconductor substrate; After forming the first resist, a step of performing a second ion implantation for forming the second cathode layer using the first resist; After the second ion implantation, a step of performing a third ion implantation for forming the first cathode layer using the first resist at an acceleration energy smaller than that of the second ion implantation; After the third ion implantation, a step of removing the first resist; After removing the first resist, by performing a second annealing for activating the ions implanted by the second ion implantation and the third ion implantation, the second cathode layer is formed between the buffer layer and the second main surface, and the first cathode layer is formed between the second cathode layer and the second main surface; After forming the second cathode layer and the first cathode layer, a step of forming a second metal layer on the second main surface of the semiconductor substrate; After forming the second metal layer, a step of performing a third annealing at 350°C in a nitrogen atmosphere; A method for manufacturing a power semiconductor device. (Appendix 20) Between the first annealing and the formation of the first resist, a fourth ion implantation for forming a cathode layer of a second conductivity type on the second main surface in the intermediate region and the terminal region of the semiconductor substrate is performed. The method for manufacturing a power semiconductor device according to Appendix 19. (Appendix 21) Between the formation of the surface protection film and the first ion implantation, a second resist for forming the buffer layer only on the second main surface in the active cell region is formed. Between the first annealing and the formation of the first resist, the second resist is removed. The method for manufacturing a power semiconductor device according to Appendix 20.

Description of Reference Numerals

[0148] 5A Aluminum wiring, 6 p anode layer, 6A p base layer, 7 n-drift layer, 8 n buffer layer, 9,90 n+ cathode layer, 10 p layer, 11 n+ layer, 12,13 Passivation film, 14 Second metal layer, 15 Oxide film, 16 TEOS layer, 18 n buffer layer, 20 Semiconductor substrate, 21 First main surface, 22 Second main surface, 23 Surface protection film, 24 Emitter layer, 25 p+ layer, 26 n layer, 27 Interlayer insulating film, 28 p+ layer, 29 Vertical structure, 31 p cathode layer, 31A p collector layer, 32 Gate electrode, 41 Trench, 42 Gate insulating film, 43 Gate electrode, 44 IGBT region, 45 Diode region, 51,52,53 First metal layer, 55 Gettering layer, 64,65 Doped polysilicon layer, 68 Oxide film, 91 First n+ cathode layer, 92 Second n+ cathode layer, 1000 - 1005 pin diode, R1 Active cell region, R11 Gate pad portion, R12 Surface gate wiring portion, R2 Intermediate region, R3 Terminal region.

Claims

1. In a plan view, it is divided into an active cell region, an intermediate region surrounding the active cell region, and a terminal region surrounding the intermediate region, a semiconductor substrate having first and second main surfaces facing each other, a first metal layer provided on the first main surface of the semiconductor substrate, a second metal layer provided on the second main surface of the semiconductor substrate, and includes: The semiconductor substrate, a drift layer of a first conductivity type, a first conductivity type buffer layer provided between the drift layer and the second metal layer in the active cell region, at least one first conductivity type cathode layer provided in contact with both the buffer layer and the second metal layer between the buffer layer and the second metal layer in the active cell region, and includes: The first conductivity type cathode layer, a first cathode layer having one impurity concentration peak point and in contact with the second metal layer, a second cathode layer having one impurity concentration peak point and provided in contact with both the first cathode layer and the buffer layer between the first cathode layer and the buffer layer, and includes: The crystal defect density of the first cathode layer is higher than that of the second cathode layer, The first conductivity type cathode layer is not provided in a region excluding the outer peripheral end portions of the intermediate region and the terminal region. A power semiconductor device.

2. The crystal defect density of the second cathode layer is higher than that of the buffer layer. The power semiconductor device according to claim 1.

3. The crystal defects in the first cathode layer are two types of lattice defects detected by a photoluminescence method. The power semiconductor device according to claim 1 or claim 2.

4. The photon energy of one type of the two types of lattice defects in the first cathode layer is 1.018 eV. The power semiconductor device according to claim 3.

5. The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer in the intermediate region and the terminal region. The power semiconductor device according to claim 1.

6. The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer at the boundary portion with the intermediate region in the active cell region. The power semiconductor device according to claim 5.

7. The buffer layer is provided between the drift layer and the second metal layer in the intermediate region and the terminal region. The intermediate region and the terminal region further include a cathode layer of the second conductivity type provided in contact with the second metal layer between the buffer layer and the second metal layer. The power semiconductor device according to claim 1.

8. The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The cathode layer of the second conductivity type is provided in contact with the second metal layer between the buffer layer and the second metal layer at the boundary portion with the intermediate region in the active cell region. The power semiconductor device according to claim 7.

9. The buffer layer is provided only in the active cell region. The drift layer is in contact with the second metal layer in the intermediate region and the terminal region. The power semiconductor device according to claim 1.

10. The cathode layer of the first conductivity type is provided avoiding the boundary portion with the intermediate region in the active cell region. The drift layer is in contact with the second metal layer at the boundary with the intermediate region in the active cell region. The power semiconductor device according to claim 9. **Claim 11** The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer in the intermediate region and the terminal region. The semiconductor substrate includes a first impurity region of a first conductivity type having a higher impurity concentration than the drift layer, provided in a surface layer including the first main surface at an outer peripheral end of the terminal region. The first conductivity type cathode layer is provided in contact with both the buffer layer and the second metal layer between the buffer layer and the second metal layer even directly below the first impurity region. The buffer layer is in contact with the second metal layer in the region of the terminal region where the first conductivity type cathode layer is not provided and in the intermediate region. The power semiconductor device according to claim 1. **Claim 12** The first conductivity type cathode layer is provided avoiding the boundary with the intermediate region in the active cell region. The buffer layer is in contact with the second metal layer at the boundary with the intermediate region in the active cell region. The power semiconductor device according to claim 11. **Claim 13** The at least one first conductivity type cathode layer in the active cell region is a plurality of first conductivity type cathode layers provided separately. The power semiconductor device according to claim 1. **Claim 14** The plurality of first conductivity type cathode layers are provided avoiding the boundary with the intermediate region in the active cell region. The buffer layer is provided in contact with the second metal layer between the drift layer and the second metal layer at the boundary with the intermediate region in the active cell region, in the intermediate region, and in the terminal region. The power semiconductor device according to claim 13. **Claim 15** The semiconductor substrate further includes a second conductivity type anode layer provided between the drift layer and the first metal layer in the active cell region and in electrical contact with the first metal layer. The power semiconductor device according to claim 1.

16. The active cell region includes an IGBT region operating as an IGBT and a diode region operating as a diode. The semiconductor substrate includes a second conductivity type base layer provided between the drift layer and the first main surface, a first conductivity type emitter layer provided between the base layer and the first main surface in the IGBT region, a trench penetrating the emitter layer and the base layer, and a gate electrode provided inside the trench. The power semiconductor device according to claim 1.

17. In the diode region, the base layer is in contact with the first main surface. The power semiconductor device according to claim 16.

18. The semiconductor substrate further includes a second conductivity type second impurity region having a higher impurity concentration than the base layer, which is provided in contact with the first main surface between the base layer and the first main surface in the diode region. The power semiconductor device according to claim 16.

19. A step of forming a first metal layer and a surface protection film on a first main surface of a semiconductor substrate having a first conductivity type drift layer, which is divided into an active cell region, an intermediate region surrounding the active cell region, and a terminal region surrounding the intermediate region in a plan view; After forming the surface protection film, a first ion implantation and a first annealing for forming a first conductivity type buffer layer are performed on at least the active cell region of a second main surface of the semiconductor substrate facing the first main surface. After the first annealing, a first resist for forming a first cathode layer and a second cathode layer of a first conductivity type is formed on a partial region of the active cell region on the second main surface of the semiconductor substrate; After the formation of the first resist, a second ion implantation for forming the second cathode layer is performed using the first resist; After the second ion implantation, a third ion implantation for forming the first cathode layer is performed using the first resist at an acceleration energy smaller than that of the second ion implantation; After the third ion implantation, the first resist is removed; After the removal of the first resist, a second annealing is performed to activate the ions implanted by the second ion implantation and the third ion implantation, thereby forming the second cathode layer between the buffer layer and the second main surface, and forming the first cathode layer between the second cathode layer and the second main surface; After the formation of the second cathode layer and the first cathode layer, a second metal layer is formed on the second main surface of the semiconductor substrate; After the formation of the second metal layer, a third annealing is performed at 350 °C in a nitrogen atmosphere. The crystal defect density of the first cathode layer is higher than that of the second cathode layer. A method for manufacturing a power semiconductor device.

20. Between the first annealing and the formation of the first resist, a fourth ion implantation for forming a cathode layer of a second conductivity type is performed on the second main surface in the intermediate region and the terminal region of the semiconductor substrate. The method for manufacturing a power semiconductor device according to claim 19.

21. Between the formation of the surface protection film and the first ion implantation, a second resist for forming the buffer layer is formed only on the second main surface in the active cell region, Between the first ion implantation and the first annealing, the second resist is removed. The manufacturing method of the power semiconductor device according to claim 20.

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