Semiconductor device

Abstract

To reduce power consumption of a shift register or a display device including the shift register.SOLUTION: A clock signal is not supplied to a shift register through one wiring but is supplied through a plurality of wiring. Further, any one of the plurality of wiring does not supplies the clock signal during the whole operation period of the shift register but supplies the clock signal in only part of the operation period. Therefore, a capacity load driven with supply of the clock signal can be reduced. As the result, power consumption of the shift register can be reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a shift register. Further, it relates to a display device having the shift register.

Background Art

[0002] As represented by a liquid crystal display device, thin film transistors (hereinafter, also referred to as TFT: Thin Film Transistor) formed on a flat plate such as a glass substrate are mainly manufactured using a semiconductor material such as amorphous silicon or polycrystalline silicon. The TFT using amorphous silicon has a low field effect mobility but can cope with the enlargement of the area of the glass substrate. On the other hand, the TFT using polycrystalline silicon has a high field effect mobility but requires a crystallization process such as laser annealing and is not necessarily suitable for the enlargement of the area of the glass substrate.

[0003] On the other hand, TFTs using an oxide semiconductor as a semiconductor material have attracted attention. For example, techniques of manufacturing a TFT using zinc oxide or an In-Ga-Zn-O-based oxide semiconductor as a semiconductor material and using it as a switching element of an image display device are disclosed in Patent Document 1 and Patent Document 2.

[0004] A TFT provided with a channel formation region in an oxide semiconductor has a higher field effect mobility than a TFT using amorphous silicon. Further, the oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, and is easier to manufacture than a TFT using polycrystalline silicon.

[0005] ​​​​​​​​​​​​​TFTs made from such oxide semiconductors are widely used in liquid crystal displays, electro- A device that configures the pixel section and driving circuit of a display device such as a luminescence display or electronic paper. For example, the above-mentioned oxide semiconductors are expected to be used in switching elements. The technology for constructing the pixel section and driving circuit of a display device using TFTs manufactured using this method is a non-patent document. This is disclosed in reference 1.

[0006] However, all of the TFTs manufactured using the above oxide semiconductors are n-channel transistors. Therefore, the driver circuit is constructed using TFTs made of oxide semiconductors. In this case, the driving circuit is composed of only n-channel TFTs (hereinafter also referred to as unipolar). This will be accomplished. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Non-patent literature]

[0008] [Non-Patent Document 1] T.Osada, and 8 others, SID 09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] The driving circuit is composed of a shift register and a buffer. When the capacitor is composed of a single-polarity TFT, the signal is lowered by the threshold voltage of the TFT or Problems such as an increase occur. Therefore, at the location where such a problem occurs, a bootstrap trap is often used. Specifically, it is often used when driving an analog switch or the like that drives a signal line or a scanning line of a display device.

[0010] Furthermore, when the load of a drive circuit using a bootstrap becomes large, it is necessary to increase the gate width of the TFT that constitutes the drive circuit. Along with this, the parasitic capacitance generated in the TFT also increases. In particular, in a TFT (so-called, reverse staggered type TFT, etc.) that needs to superimpose a conductive layer that functions as a gate terminal and a conductive layer that functions as a source terminal or a drain terminal via a gate insulating layer, the parasitic capacitance increases. As a result

[0011] In view of the above-described problems, one aspect of the present invention aims to reduce the power consumption of a shift register or a display device having the shift register.

Means for Solving the Problems

[0012] The above problems can be solved by dividing the clock signal line included in the shift register into a plurality of pulse signal lines. That is, instead of a plurality of flip-flops included in the shift register being electrically connected to one clock signal line, a plurality of pulse signal lines are provided and a part of the plurality of flip-flops is electrically connected to any one of the plurality of pulse signal lines. Furthermore, the pulse signal line does not supply a clock signal throughout the operation period of the shift register, but supplies a clock signal in a part of the period included in the operation period. ​​​​​​​​​​ Supplies a signal. As a result, the capacitive load driven with the supply of the clock signal to the shift register can be reduced. Consequently, the power consumption of the shift register can be reduced.

[0013] That is, one aspect of the present invention is a shift register having an operation period including a first period, a second period, a third period including a period overlapping with the first period, and a fourth period including a period overlapping with the second period. During the first period, a first pulse signal line that functions as a wiring for supplying a clock signal that periodically repeats a low power supply potential and a high power supply potential, During the second period, a second pulse signal line that functions as a wiring for supplying a clock signal, During the third period, a third pulse signal line that functions as a wiring for supplying an inverted clock signal that is an inverted signal of the clock signal, During the fourth period, a fourth pulse signal line that functions as a wiring for supplying an inverted clock signal, A first flip-flop electrically connected to the first pulse signal line and outputting a high power supply potential during the first period, A second flip-flop electrically connected to the second pulse signal line and outputting a high power supply potential during the second period, A third flip-flop electrically connected to the first flip-flop and the third pulse signal line and outputting a high power supply potential during the third period, A fourth flip-flop electrically connected to the second flip-flop and the fourth pulse signal line and outputting a high power supply potential during the fourth period.

[0014] Also, in one aspect of the present invention, in the above configuration, the first pulse signal line is ​functions as a wiring for supplying a low power supply potential throughout the period, and the second pulse signal line functions as a wiring for supplying a low power supply potential throughout the period other than the second period, and the third pulse signal line functions as a wiring for supplying a low power supply potential throughout the period other than the third period, and the fourth pulse signal line functions as a wiring for supplying a low power supply potential throughout the period other than the fourth period, which is a shift register.

[0015] In addition, in the above configuration, a shift register in which the flip-flop has a transistor whose channel formation region is formed of an oxide semiconductor is also an aspect of the present invention.

[0016] Also, in the above configuration, a shift register in which the pulse signal line is electrically connected to the reference clock signal line or the reference inverted clock signal line via a transistor that is turned on during the period in which the pulse signal line supplies a clock signal or an inverted clock signal is also an aspect of the present invention.

[0017] Also, in the above configuration, a shift register in which the pulse signal line is electrically connected to a wiring for supplying a low power supply potential via a transistor that is turned on during the period in which the pulse signal line does not supply a clock signal or an inverted clock signal is also an aspect of the present invention.

[0018] Furthermore, a display device having the shift register configured as described above is also an aspect of the present invention.

Advantages of the Invention

[0019] In the shift register according to one aspect of the present invention, the clock signal is supplied not by one wiring but by a plurality of wirings. Further, any one of the plurality of wirings is a shift ​​​​​​Rather than supplying a clock signal throughout the operation period of the register, a clock signal is supplied during a partial period. Thus, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced.

Brief Description of the Drawings

[0020]

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Embodiments for Carrying Out the Invention

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0022] Note that since the source terminal and drain terminal of the transistor vary depending on the structure and operating conditions of the transistor etc., it is difficult to identify which is the source terminal or the drain terminal. Therefore, in this document, one of the source terminal and the drain terminal is designated as the first terminal and the other of the source terminal and the drain terminal is designated as the second terminal for distinction.

[0023] In addition, the size, layer thickness, or area of each component shown in the drawings and the like of each embodiment may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Also, the ordinal numbers such as "first", "second", and "third" used in this specification are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0024] (Embodiment 1) In this embodiment, an example of the configuration and operation of the shift register will be described with reference to FIGS. 1 to 7. Specifically, during a part of the operation period of the shift register, it functions as a wiring for supplying a clock signal, and during the period other than that, it functions as a wiring for supplying a low power supply level. A shift register having a pulse signal line and a flip-flop electrically connected to the pulse signal line will be described.

[0025] <Example of Shift Register Configuration> The shift register of this embodiment has first to sixth pulse signal lines and first to tenth flip-flops.

[0026] Note that the first pulse signal line (PS1) is connected to the first flip-flop (FF1) and the third is electrically connected to the flip-flop (FF3), and the second pulse signal line (PS2) is electrically connected to the fifth flip-flop (FF5) and the seventh flip-flop (FF7). Subsequently, the third pulse signal line (PS3) is electrically connected to the ninth flip-flop (FF9). The fourth pulse signal line (PS4) is electrically connected to the second flip-flop (FF2) and the fourth flip-flop (FF4), and the fifth pulse signal line (PS5) is electrically connected to the sixth flip-flop (FF6) and the eighth flip-flop (FF8). The sixth pulse signal line (PS6) is electrically connected to the tenth flip-flop (FF10). (See FIG. 1(A)).

[0027] Furthermore, the output terminal of each flip-flop is electrically connected to the input terminal of the next-stage flip-flop. Note that the input terminal of the first flip-flop (FF1) is electrically connected to the wiring that supplies the start pulse (SP). The first pulse signal line (PS1) functions as a wiring that supplies a clock signal that periodically repeats a high power supply potential and a low power supply potential in the first period (t1). The second pulse signal line (PS2) functions as a wiring that supplies a clock signal in the second period (t2). The third pulse signal line (PS3) functions as a wiring that supplies a clock signal in the third period (t3). The fourth pulse signal line (PS4) functions as a wiring that supplies an inverted clock signal, which is an inverted signal of the clock signal, in the fourth period (t4). The fifth pulse signal line (PS5) functions as a wiring that supplies an inverted clock signal in the fifth period (t5).

[0028] Also, the first pulse signal line (PS1) functions as a wiring that supplies a clock signal that periodically repeats a high power supply potential and a low power supply potential in the first period (t1). The second pulse signal line (PS2) functions as a wiring that supplies a clock signal in the second period (t2). The third pulse signal line (PS3) functions as a wiring that supplies a clock signal in the third period (t3). The fourth pulse signal line (PS4) functions as a wiring that supplies an inverted clock signal, which is an inverted signal of the clock signal, in the fourth period (t4). The fifth pulse signal line (PS5) functions as a wiring that supplies an inverted clock signal in the fifth period (t5). The second pulse signal line (PS2) functions as a wiring that supplies a clock signal in the second period (t2). The third pulse signal line (PS3) functions as a wiring that supplies a clock signal in the third period (t3). The fourth pulse signal line (PS4) functions as a wiring that supplies an inverted clock signal, which is an inverted signal of the clock signal, in the fourth period (t4). The fifth pulse signal line (PS5) functions as a wiring that supplies an inverted clock signal in the fifth period (t5). The fourth pulse signal line (PS4) functions as a wiring that supplies an inverted clock signal, which is an inverted signal of the clock signal, in the fourth period (t4). The fifth pulse signal line (PS5) functions as a wiring that supplies an inverted clock signal in the fifth period (t5). The fifth pulse signal line (PS5) functions as a wiring that supplies an inverted clock signal in the fifth period (t5). functions as, and the sixth pulse signal line (PS6) functions as a wiring for supplying an inverted clock signal in the sixth period (t6) (see FIG. 1(B)).

[0029] <Operation example of shift register> The operation of the shift register according to this embodiment will be described below.

[0030] First, a signal of a high power supply potential is input as a start pulse (SP) to the input terminal of the first flip-flop (FF1). The first flip-flop (FF1) operates using the input signal and outputs a signal of a high power supply potential as the output signal (FF1out) of the first flip-flop after a half clock cycle.

[0031] This output signal (FF1out) is input to the input terminal of the second flip-flop (FF2). The second flip-flop (FF2) operates in the same manner as the first flip-flop (FF1) using the input signal and outputs a signal of a high power supply potential as the output signal (FF2out) of the second flip-flop after a half clock cycle.

[0032] Similarly, a signal of a high power supply potential is input to the input terminal of the next-stage flip-flop, and a signal of a high power supply potential is output from the flip-flop after a half clock cycle.

[0033] <Specific example of flip-flop> A specific circuit configuration example of the flip-flop according to this embodiment is shown in FIG. 2(A). Note that in FIG. 2(A), only the configurations of the first flip-flop (FF1) and the second flip-flop (FF2) are shown for convenience.

[0034] ​​​​​​​​The first flip-flop (FF1) includes transistors 101 to 106. Here, transistors 101 to 106 are assumed to be n-channel transistors.

[0035] The gate terminal of transistor 101 is electrically connected to the output terminal of the second flip-flop (FF2), and the first terminal is electrically connected to a wiring that supplies a high power supply potential (VDD) (hereinafter also referred to as a high power supply potential line).

[0036] The gate terminal of transistor 102 is electrically connected to a wiring that supplies a start pulse (SP) (hereinafter also referred to as a start pulse line), the first terminal is electrically connected to the second terminal of transistor 101, and the second terminal is electrically connected to a wiring that supplies a low power supply potential (VSS) (hereinafter also referred to as a low power supply potential line).

[0037] The gate terminal of transistor 103 is electrically connected to the start pulse line, and the first terminal is electrically connected to the high power supply potential line.

[0038] The gate terminal of transistor 104 is electrically connected to the second terminal of transistor 101 and the first terminal of transistor 102, the first terminal is electrically connected to the second terminal of transistor 103, and the second terminal is electrically connected to the low power supply potential line.

[0039] The gate terminal of transistor 105 is electrically connected to the second terminal of transistor 103 and the first terminal of transistor 104, and the first terminal is electrically connected to the first pulse signal line (PS1).

[0040] ​​​​​​​​​​​Transistor 106 has its gate terminal electrically connected to the second terminal of transistor 101, the first terminal of transistor 1 02 and the gate terminal of transistor 104, its first terminal is electrically connected to the second terminal of transistor 105, and its second terminal is electrically connected to the low power supply potential line. It continues.

[0041] In the following, for convenience, the second terminal of transistor 101, the first terminal of transistor 102 , the gate terminal of transistor 104, and the gate terminal of transistor 106 are electrically connected at a point called node A, and the second terminal of transistor 103, the first terminal of transistor 104 , and the point where the gate terminal of transistor 105 is electrically connected is called node B. It shall be so.

[0042] In addition to the above configuration, a configuration in which a capacitive element is provided between the gate terminal and the source terminal of transistor 105 may be adopted. By providing the capacitive element, the bootstrap operation described below can be surely performed.

[0043] <Operation example of flip - flop> Hereinafter, taking the first flip - flop (FF1) as an example, the operation of the flip - flop described above will be described with reference to FIG. 2(B).

[0044] First, the potential of the start pulse line electrically connected to the first flip - flop (FF1) increases to a high level (hereinafter referred to as the H level). As a result, an H - level signal is input to the gate terminal of transistor 102 and the gate terminal of transistor 103. Therefore, transistors 102 and 103 turn on. As a result, node A The potential of decreases to a low level (hereinafter referred to as the L level), and the potential of node B increases to the H level. Accordingly, transistor 105 also turns on. As a result, during this period, the potential of the first pulse signal line (PS1), which is the L level potential, is output as the output signal (FF1out) of the first flip-flop.

[0045] In the subsequent period, the potential of the start pulse line decreases to the L level. Therefore, transistors 102 and 103 turn off. As a result, nodes A and B become floating states. At this time, there is a potential difference from the L level to the H level between the source terminal and the gate terminal of transistor 105. Since node B is in a floating state, this potential difference is retained. That is, transistor 105 continues to turn on regardless of the state of the potential of the source terminal. Also, the potential of the first pulse signal line (PS1) increases to the H level. Accordingly, the potential of node B, which is floating and electrically connected to the gate terminal of transistor 105, further increases due to the H level potential of the first pulse signal line (PS1) during this period. In this way, the operation in which the potential of node B increases due to the capacitive coupling between the gate terminal and the source terminal of transistor 105, which is electrically connected to node B in a floating state, is called bootstrapping. As described above, the H level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop.

[0046] Here, transistor 105 is an n-channel type transistor. That is, during the period when the potential of the first pulse signal line (PS1) becomes the H level, transistor 1 ​​​​​​​​​​​​​In step 05, the terminal electrically connected to the output terminal of the first flip-flop (FF1) becomes the source terminal, and the terminal electrically connected to the first pulse signal line (PS1) becomes the drain terminal. Also, the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the terminal electrically connected to the output terminal of the first flip-flop (FF1) becomes the source terminal, and the terminal electrically connected to the first pulse signal line (PS1) becomes the drain terminal. Also, the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1). And the on and off states of the transistor are determined by the potential difference between the source terminal and the gate terminal. Therefore, when the H-level potential of the first pulse signal line (PS1) is output as the output signal (FF1out) of the first flip-flop via an n-channel transistor without bootstrap, the output potential will decrease by the threshold voltage (Vth) of the n-channel transistor from the H-level potential. However, since the transistor 105 performs bootstrap, the output signal (FF1out) of the first flip-flop can be obtained without reducing the potential of the first pulse signal line (PS1).

[0047] Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2) has the same configuration as the first flip-flop (FF1), except that the first pulse signal line (PS1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to. During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period.

[0048] In the subsequent period, as the potential of the first pulse signal line (PS1) decreases to the L level, The potential of the fourth pulse signal line (PS4) increases to the H level. As a result, the output signal (FF1out) of the first flip-flop decreases to the L level. Also, the H-level potential, which is the potential of the fourth pulse signal line (PS4), is output as the output signal (FF2out) of the second flip-flop. Moreover, the output signal (FF2out) of the second flip-flop is input to a third flip-flop (not shown) and also input to the gate terminal of the transistor 101 included in the first flip-flop (FF1). Therefore, the transistor 101 included in the first flip-flop (FF1) is turned on. Thereby, the potential of node A becomes the H level. Along with this, the transistors 104 and 106 are also turned on. When the transistor 104 is turned on, the potential of node B decreases to the L level. That is, the potential of the gate terminal of the transistor 105 decreases to the L level. Therefore, the transistor 105 is turned off. In addition, when the transistor 106 is turned on, the output signal (FF1out) of the first flip-flop changes from the L level of the first pulse signal (PS1) via the transistor 105 to the L level of the low power supply potential (VSS) via the transistor 106 during that period. That is, there is no substantial change in the output signal (FF1out) of the first flip-flop, but the origin thereof changes. In the subsequent period, the potential of the fourth pulse signal line (PS4) decreases to the L level. That is, the output signal (FF2out) of the second flip-flop decreases to the L level.

[0049] Note that the output signal (FF2out) of the second flip-flop is input to a third flip-flop (not shown) and also input to the gate terminal of the transistor 101 included in the first flip-flop (FF1). Therefore, the transistor 101 included in the first flip-flop (FF1) is turned on. Thereby, the potential of node A becomes the H level. Along with this, the transistors 104 and 106 are also turned on. When the transistor 104 is turned on, the potential of node B decreases to the L level. That is, the potential of the gate terminal of the transistor 105 decreases to the L level. Therefore, the transistor 105 is turned off. In addition, when the transistor 106 is turned on, the output signal (FF1out) of the first flip-flop changes from the L level of the first pulse signal (PS1) via the transistor 105 to the L level of the low power supply potential (VSS) via the transistor 106 during that period. That is, there is no substantial change in the output signal (FF1out) of the first flip-flop, but the origin thereof changes.

[0050] Therefore, the transistor 101 of the first flip-flop (FF1) turns off. Then As a result, the nodes electrically connected to the gate terminals of the transistors 104 and the nodes electrically connected to the gate terminals of the transistor 106 float while holding an H-level signal. That is, the transistors 104 and 106 continue to be on, and the output signal (FF1out) of the first flip-flop maintains an L level. Note that this state is maintained until a potential of H level is input again to the input terminal of the first flip-flop (FF1).

[0051] The first flip-flop (FF1) shown in Fig. 2(A) can output the powered signal delayed by a half clock cycle by the above-described operation.

[0052] <An example of a pulse signal line> The first pulse signal line (PS1) to the sixth pulse signal line (PS6) of the shift register according to the present embodiment function as wiring for supplying a clock signal during a part of the operation period and function as wiring for supplying a low power supply potential during periods other than the period. An example of the wiring having this function will be described below with reference to Figs. 3 and 4.

[0053] Each of the first pulse signal line (PS1) to the sixth pulse signal line (PS6) shown in Fig. 3(A) is electrically connected to the reference clock signal line (CK) or the reference inverted clock signal line (CKB) via any one of the source terminals and drain terminals of the clock signal selection transistors 111, 112, 113 and the inverted clock signal selection transistors 114, 115, 116. Here, the clock signal selection transistors 111, 112, ​​​​​​​​​​​​ The transistors 113 and 114, 115, 116 for selecting the inversion clock signal are assumed to be n-channel type transistors.

[0054] Specifically, for the transistor 111 for selecting the clock signal, the gate terminal is electrically connected to the control terminal a, the first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal is electrically connected to the reference clock signal line (CK). For the transistor 112 for selecting the clock signal, the gate terminal is electrically connected to the control terminal b, the first terminal is electrically connected to the second pulse signal line (PS2), and the second terminal is electrically connected to the reference clock signal line (CK). For the transistor 113 for selecting the clock signal, the gate terminal is electrically connected to the control terminal c, the first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is electrically connected to the reference clock signal line (CK).

[0055] For the transistor 114 for selecting the inversion clock signal, the gate terminal is electrically connected to the control terminal d, the first terminal is electrically connected to the fourth pulse signal line (PS4), and the second terminal is electrically connected to the reference inversion clock signal line (CKB). For the transistor 115 for selecting the inversion clock signal, the gate terminal is electrically connected to the control terminal e, the first terminal is electrically connected to the fifth pulse signal line (PS5), and the second terminal is electrically connected to the reference inversion clock signal line (CKB). For the transistor 116 for selecting the inversion clock signal, the gate terminal is electrically connected to the control terminal f, the first terminal is electrically connected to the sixth pulse signal line (PS6), and the second terminal is electrically connected to the reference inversion clock signal line (CKB).

[0056] Also, as shown in FIG. 3(B), the reference clock signal line is a wiring that supplies a clock signal that periodically repeats a high power supply potential and a low power supply potential, and the inverted clock signal line is a wiring that supplies an inverted clock signal that is the inverted signal of the clock signal regardless of the period.

[0057] Furthermore, the potential of the control terminal a becomes H level in the first period (t1) and becomes L level in other periods. Thereby, the first pulse signal line (PS1) can be made to function as a wiring that supplies a clock signal in the first period . In other words, the first period is a period in which the potential of the control terminal a becomes H level. In other words, the first period is a period in which the potential of the control terminal a becomes H level.

[0058] Similarly, the potentials of the control terminals b to f become H level in any of the second period (t2) to the sixth period (t6) and become L level in other periods. Thereby, the second pulse signal line in the second period, the third pulse signal line in the third period function as wirings that supply a clock signal, the fourth pulse signal line in the fourth period, the fifth pulse signal line in the fifth period, and the sixth pulse signal line in the sixth period function as wirings that supply an inverted clock signal. In other words , the second period (t2) to the sixth period (t6) are periods in which the potentials of the control terminals b to f become H level . In other words, the second period (t2) to the sixth period (t6) are periods in which the potentials of the control terminals b to f become H level and the periods in which the potential of the control terminal b to f becomes H level. and the periods in which the potential of the control terminal b to f becomes H level.

[0059] Also, each of the first pulse signal line (PS1) to the sixth pulse signal line (PS 6) shown in FIG. 4(A) is electrically connected to a wiring that supplies a low power supply potential (VSS) via the source terminal and the drain terminal of any one of the low power supply potential selection transistors 121 to 126 This is the case where the transistors 121 to 126 for selecting the low power supply potential are n-channel type transistors.

[0060] The gate terminal of the transistor 121 for selecting the low power supply potential is electrically connected to the control terminal g, the first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS). The gate terminal of the transistor 122 for selecting the low power supply potential is electrically connected to the control terminal h, the first terminal is electrically connected to the second pulse signal line (PS 2), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS). The gate terminal of the transistor 123 for selecting the low power supply potential is electrically connected to the control terminal i, the first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS). The gate terminal of the transistor 124 for selecting the low power supply potential is electrically connected to the control terminal j, the first terminal is electrically connected to the fourth pulse signal line (PS4), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS). The gate terminal of the transistor 125 for selecting the low power supply potential is electrically connected to the control terminal k, the first terminal is electrically connected to the fifth pulse signal line (PS5), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS). The gate terminal of the transistor 126 for selecting the low power supply potential is electrically connected to the control terminal l, the first terminal is electrically connected to the sixth pulse signal line (PS6), and the second terminal is electrically connected to the wiring for supplying the low power supply potential (VSS).

[0061] Furthermore, the potential of the control terminal g becomes the L level in the first period (t1), and otherwise ​​During this period, it becomes the H level. As a result, the first pulse signal line (PS1) can function as a wiring for supplying a low power supply potential (VSS) during periods other than the first period (t1). Similarly, the potentials of the control terminals h to l become the L level during the second period (t2) to the sixth period (t6), respectively, and become the H level during other periods. As a result, the second pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the second period, the third pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the third period, the fourth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the fourth period, the fifth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the fifth period, and the sixth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the sixth period. This can be achieved.

[0062] Similarly, the potentials of the control terminals h to l become the L level during the second period (t2) to the sixth period (t6), respectively, and become the H level during other periods. As a result, the second pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the second period, the third pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the third period, the fourth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the fourth period, the fifth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the fifth period, and the sixth pulse signal line can function as a wiring for supplying a low power supply potential (VSS) during periods other than the sixth period. During this period, it becomes the H level. As a result, the first pulse signal line (PS1) can function as a wiring for supplying a low power supply potential (VSS) during periods other than the first period (t1). During periods other than the second period, the third pulse signal line during periods other than the third period, the fourth pulse signal line during periods other than the fourth period, the fifth pulse signal line during periods other than the fifth period, and the sixth pulse signal line during periods other than the sixth period, it can function as a wiring for supplying a low power supply potential (VSS). During periods other than the second period, the third pulse signal line during periods other than the third period, the fourth pulse signal line during periods other than the fourth period, the fifth pulse signal line during periods other than the fifth period, and the sixth pulse signal line during periods other than the sixth period, it can function as a wiring for supplying a low power supply potential (VSS). During periods other than the second period, the third pulse signal line during periods other than the third period, the fourth pulse signal line during periods other than the fourth period, the fifth pulse signal line during periods other than the fifth period, and the sixth pulse signal line during periods other than the sixth period, it can function as a wiring for supplying a low power supply potential (VSS). During periods other than the second period, the third pulse signal line during periods other than the third period, the fourth pulse signal line during periods other than the fourth period, the fifth pulse signal line during periods other than the fifth period, and the sixth pulse signal line during periods other than the sixth period, it can function as a wiring for supplying a low power supply potential (VSS).

[0063] In the shift register of this embodiment, since the clock signal is supplied by a plurality of wirings instead of being supplied by one wiring. Furthermore, any one of the plurality of wirings supplies the clock signal only during a part of the operation period of the shift register, not throughout the operation period. Therefore, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced. In the shift register of this embodiment, since the clock signal is supplied by a plurality of wirings instead of being supplied by one wiring. Furthermore, any one of the plurality of wirings supplies the clock signal only during a part of the operation period of the shift register, not throughout the operation period. Therefore, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced. In the shift register of this embodiment, since the clock signal is supplied by a plurality of wirings instead of being supplied by one wiring. Furthermore, any one of the plurality of wirings supplies the clock signal only during a part of the operation period of the shift register, not throughout the operation period. Therefore, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced. In the shift register of this embodiment, since the clock signal is supplied by a plurality of wirings instead of being supplied by one wiring. Furthermore, any one of the plurality of wirings supplies the clock signal only during a part of the operation period of the shift register, not throughout the operation period. Therefore, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced. In the shift register of this embodiment, since the clock signal is supplied by a plurality of wirings instead of being supplied by one wiring. Furthermore, any one of the plurality of wirings supplies the clock signal only during a part of the operation period of the shift register, not throughout the operation period. Therefore, the capacitive load driven with the supply of the clock signal can be reduced. As a result, the power consumption of the shift register can be reduced.

[0064] <Modification Example> The shift register described above is an example of an embodiment, and shift registers having points different from the above description are also included in this embodiment. The shift register described above is an example of an embodiment, and shift registers having points different from the above description are also included in this embodiment.

[0065] For example, in the shift register described above, a shift register in which two flip-flops are electrically connected to each pulse signal line is shown (see FIG. 1(A)). However, for each pulse For example, in the shift register described above, a shift register in which two flip-flops are electrically connected to each pulse signal line is shown (see FIG. 1(A)). However, for each pulse A configuration in which more flip - flops are electrically connected to the signal line may be used. Specifically, as shown in FIG. 5(A), a configuration in which x (x is a natural number of 3 or more) flip - flops are electrically connected to each pulse signal line can be adopted.

[0066] Also, in the shift register described above, although the shift register having six pulse signal lines has been shown (see FIG. 1(A)), a configuration having more pulse signal lines may be used. Specifically, as shown in FIG. 5(B), a first pulse signal line (PS1) to a y - th (y is a natural number of 4 or more) pulse signal line (PSy) that supplies a clock signal during a part of the operation period, and a (y + 1)-th pulse signal line (PSy + 1) to a 2y - th pulse signal line (PS2y) that supplies an inverted clock signal during a part of the operation period are provided, and a configuration in which two flip - flops are electrically connected to each pulse signal line can be adopted.

[0067] Also, in the shift register described above, although the shift register in which two flip - flops are electrically connected to each pulse signal line and which has six pulse signal lines has been shown (see FIG. 1(A)), a configuration in which more flip - flops are electrically connected to each pulse signal line and which has more pulse signal lines may be used. Specifically, as shown in FIG. 5(C), a first pulse signal line (PS1) to a y - th (y is a natural number of 4 or more) pulse signal line (PSy) that supplies a clock signal during a part of the operation period, and a (y + 1)-th pulse signal line (PSy + 1) to a 2y - th pulse signal line (PS2y) that supplies an inverted clock signal during a part of the operation period are provided. It may have a pulse signal line (PSy+1) to the 2y-th pulse signal line (PS2y), and x flip-flops may be electrically connected to each pulse signal line, etc. The structure may be such that x flip-flops are electrically connected to each pulse signal line.

[0068] In the shift register described above, a shift register in which the number of flip-flops electrically connected to each pulse signal line is equal has been shown (see FIGS. 1(A), 5(A) to (C)), but a configuration in which the number of flip-flops electrically connected is different for each pulse signal line may also be used. Specifically, as shown in FIG. 6(A), x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that the number of flip-flops electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4) is equal (see FIGS. 1(A), 5(A) and 6(A)), but the number of flip-flops electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4) may be different. Specifically, as shown in FIG. 6(B), x flip-flops are electrically connected to the first pulse signal line (PS1), and x + z flip-flops are electrically connected to the fourth pulse signal line (PS4), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc.

[0069] In the shift register described above, a shift register in which the number of flip-flops electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4) is equal has been shown (see FIGS. 1(A), 5(A) and 6(A)), but the number of flip-flops electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4) may be different. Specifically, as shown in FIG. 6(B), x flip-flops are electrically connected to the first pulse signal line (PS1), and x + z flip-flops are electrically connected to the fourth pulse signal line (PS4), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc. The structure may be such that x flip-flops are electrically connected to the first pulse signal line (PS1) and the fourth pulse signal line (PS4), and z (z is a natural number of 2 or more different from x) flip-flops are electrically connected to the second pulse signal line (PS2) and the fifth pulse signal line (PS5), etc.

[0070] In the shift register described above, the first period (t1) and the second period (t2) Although a non-overlapping shift register has been shown (see FIG. 1(B)), a configuration having a period in which the first period (t1) and the second period (t2) overlap may be used. Specifically, as shown in FIG. 6 (C), a configuration including a period (T ) in which the first period (t1) and the second period (t2) overlap can be adopted. Briefly stated, as shown in FIG. 1(B) and FIG. 6(C), at least one of the plurality of pulse signal lines of the shift register functions as a wiring for supplying a clock signal and at least one of the plurality of pulse signal lines functions as a wiring for supplying an inverted clock signal , and each period may be provided.

[0071] Also, the circuit configuration of the flip-flop shown in FIG. 2(A) is an example, and any circuit configuration may be used as long as it is a circuit that delays and outputs an input signal. Specifically, a circuit such as that shown in FIG. 7( A) can be applied to the flip-flop of the present embodiment.

[0072] The first flip-flop (FF1) shown in FIG. 7(A) includes transistors 131 to transistor 134. Here, it is assumed that transistors 131 to 134 are n-channel transistors.

[0073] The gate terminal and the first terminal of transistor 131 are electrically connected to the start pulse line.

[0074] The gate terminal of transistor 132 is electrically connected to the output terminal of the second flip-flop (FF2), the first terminal is electrically connected to the second terminal of transistor 131, and the second terminal is electrically connected to the low power supply potential line.

[0075] Transistor 133 has its gate terminal electrically connected to the second terminal of transistor 131 and the first terminal of transistor 132, and its first terminal is electrically connected to the first pulse signal line (PS1).

[0076] Transistor 134 has its gate terminal electrically connected to the output terminal of the second flip-flop (FF2), its first terminal electrically connected to the second terminal of transistor 133, and its second terminal electrically connected to the low power supply potential line.

[0077] In the following, for the sake of convenience, the point where the second terminal of transistor 131, the first terminal of transistor 132, and the gate terminal of transistor 133 are electrically connected is referred to as node C.

[0078] The operation of the first flip-flop (FF1) shown in FIG. 7(A) will be described below with reference to FIG. 7( B).

[0079] First, the potential of the start pulse line electrically connected to the first flip-flop (FF1) increases to the H level. As a result, an H-level signal is input to the gate terminal and the first terminal of transistor 131, and the diode-connected transistor 131 turns on. This causes the potential of node C to increase to the H level. Along with this, transistor 133 also turns on. As a result, the potential of the L level, which is the potential of the first pulse signal line (PS1) during this period, is output as the output signal (FF1out) of the first flip-flop.

[0080] In the subsequent period, the potential of the start pulse line decreases to the L level. Therefore, the transistor ​​​​​​​​Distorter 131 turns off. As a result, node C becomes floating. At this time, there is a potential difference from the L level to the H level between the source terminal and the gate terminal of the transistor 131, and since node C has become floating, this potential difference is maintained. That is, the transistor 131 continues to turn on regardless of the state of the potential of the source terminal. Also, the potential of the first pulse signal line (PS1) increases to the H level. As a result, the potential of node C, which is floating and electrically connected to the gate terminal of the transistor 133, further increases due to the H-level potential of the first pulse signal line (PS1) during this period. As described above, the H-level potential, which is the potential of the first pulse signal line (PS1), is output as the output signal (FF1out) of the first flip-flop. Also, the H-level signal, which is the output signal of the first flip-flop (FF1), is input to the second flip-flop (FF2). Here, the second flip-flop (FF2 ) has the same configuration as the first flip-flop

[0081] (FF1), except that the first pulse signal line (P S1) electrically connected to the first flip-flop (FF1) is replaced by the fourth pulse signal line (PS4). Therefore, for the detailed circuit operation, the above description will be referred to . During this period, the second flip-flop (FF2) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period. In the subsequent period, the potential of the first pulse signal line (PS1) decreases to the L level and at the same time the potential of the fourth pulse signal line (PS4) increases to the H level. As a result, the first flip -flop (FF1) outputs the L-level potential, which is the potential of the fourth pulse signal line (PS4) during this period.

[0082] In the subsequent period, as the potential of the first pulse signal line (PS1) decreases to the L level and at the same time the potential of the fourth pulse signal line (PS4) increases to the H level. As a result, the first flip -flop (FF1) The output signal (FF1out) of the flip-flop drops to the L level. Also, the fourth pulse The potential of the signal line (PS4), which is at the H level, is output as the output signal (F F2out) of the second flip-flop.

[0083] Note that the output signal (FF2out) of the second flip-flop is input to a third flip-flop (not shown) and is also input to the gate terminals of transistors 132 and 134 of the first flip-flop (FF1). Therefore, transistors 132 and 134 of the first flip-flop (FF1) turn on. As a result, the potential of the gate terminal (node C) of transistor 132 becomes the L level, and the output signal (FF1out) of the first flip-flop changes from the L level of the first pulse signal (PS1) via transistor 133 to the L level of the low power supply potential (VSS) via transistor 13 4 during that period. 4. On. As a result, the potential of the gate terminal (node C) of transistor 132 becomes the L level, and the output signal (FF1out) of the first flip-flop changes from the L level of the first pulse signal (PS1) via transistor 133 to the L level of the low power supply potential (VSS) via transistor 13 4 during that period. 4. 4 to the L level of the low power supply potential (VSS) via transistor 13

[0084] In the subsequent period, the potential of the fourth pulse signal line (PS4) drops to the L level. That is, the output signal (FF2out) of the second flip-flop drops to the L level. Therefore, transistors 132 and 134 of the first flip-flop (FF1) turn off. Note that this state is maintained until a potential at the H level is input again to the input terminal of the first flip-flop (FF1). That is, the output signal (FF2out) of the second flip-flop drops to the L level. Therefore, transistors 132 and 134 of the first flip-flop (FF1) turn off. Note that this state is maintained until a potential at the H level is input again to the input terminal of the first flip-flop (FF1). Therefore, transistors 132 and 134 of the first flip-flop (FF1) turn off. Note that this state is maintained until a potential at the H level is input again to the input terminal of the first flip-flop (FF1). off. to the input terminal of the first flip-flop (FF1).

[0085] The first flip-flop (FF1) shown in FIG. 7(A) can delay the input signal by half a clock cycle and output it by the operation described above. Therefore, it can be applied to the flip-flop of this embodiment. The input signal can be delayed by half a clock cycle and output. Therefore, it can be applied to the flip-flop of this embodiment. state flip-flop.

[0086] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content.

[0087] (Embodiment 2) In this embodiment, an example of a transistor applicable to the transistors constituting the shift register shown in Embodiment 1 will be described.

[0088] A structural example of the transistor in this embodiment will be described with reference to FIG. 8. FIG. 8 is a diagram showing an example of the structure of the transistor in this embodiment, FIG. 8(A) is a top view of the transistor, and FIG. 8(B) is a cross-sectional view taken along line segment Z1-Z2 in FIG. 8(A).

[0089] The transistor shown in FIGS. 8(A) and 8(B) includes a conductive layer 211 on a substrate 201, an insulating layer 202 on the conductive layer 211, an oxide semiconductor layer 213 on the insulating layer 202, and conductive layers 215a and 215b on the oxide semiconductor layer 213.

[0090] In the transistor, the conductive layer 211 functions as a gate terminal, the insulating layer 202 functions as a gate insulating layer, one of the conductive layers 215a and 215b functions as a source terminal, and the other functions as a drain terminal. Also, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration or dehydrogenation treatment during formation.

[0091] Furthermore, the transistor shown in FIGS. 8(A) and 8(B) has a structure in which the oxide semiconductor layer 213 is doped with Not only is a hydration treatment or dehydrogenation treatment performed, but also in contact with a part of the oxide semiconductor layer 213 an oxide insulating layer 207 is provided. After the dehydration or dehydrogenation treatment, the oxide semiconductor layer 213 on which the oxide insulating layer 207 is formed is used as a channel formation region, and the transistor is less likely to have a threshold voltage (Vth) shift due to long-term use or high load, so it has high reliability.

[0092] Note that a nitride insulating layer may be provided on the oxide insulating layer 207. The nitride insulating layer is preferably configured to be in contact with the insulating layer 202 provided below the oxide insulating layer 207 or the underlying insulating layer, blocking the intrusion of moisture, hydrogen ions, impurities such as OH from near the side surface of the substrate. In particular, it is effective to use a silicon nitride layer as the insulating layer 202 or the underlying insulating layer in contact with the oxide insulating layer 207. That is, when a silicon nitride layer is provided so as to surround the lower surface, upper surface, and side surface of the oxide semiconductor layer 213, the reliability of the transistor is improved. - In addition, a planarization insulating layer can be provided on the oxide insulating layer 207 (or on the nitride insulating layer when there is a nitride insulating layer).

[0093] Also, as shown in FIG. 8(C), in the transistor of this embodiment, an oxide conductive layer 214a and an oxide conductive layer 214b are provided on a part of the oxide semiconductor layer 21 3, a conductive layer 215a is provided in contact with the oxide conductive layer 214a, and a conductive layer 215b is provided in contact with the oxide conductive layer 214b

[0094]

[0095] The oxide conductive layer 214a and the oxide conductive layer 214b have higher conductivity than the oxide semiconductor layer 213. has an electrical resistivity and functions as the source region (also referred to as a low-resistance source region) and the drain region (also referred to as a low-resistance drain region) of the transistor 251.

[0096] As the oxide conductive film used to form the oxide conductive layer 214a and the oxide conductive layer 214b, for example, a conductive material having translucency to visible light, such as In-Sn-Zn -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, I n-Sn-O system, In-O system, Sn-O system, Zn-O system metal oxides can be applied, and the film thickness is appropriately selected within the range of 1 nm or more and 300 nm or less. Further, when using the sputtering method, film formation is performed using a target containing 2 wt% or more and 10 wt% or less of SiO2, and SiOx (X>0) that inhibits crystallization is included in the translucent conductive film, so that the oxide semiconductor layer 213 crystallizes during the heat treatment for dehydration or dehydrogenation performed in a later process. This can be suppressed.

[0097]

[0098]

[0099]

[0098]

[0099]

[0099] In addition, in this embodiment, the oxide conductive layer 214a and the oxide conductive layer 214b are n-Ga-Zn-O-based films and are assumed to contain at least an amorphous component. Further, the oxide conductive layer 214a and the oxide conductive layer 214b may contain crystallites (nanocrystals). The crystallites (nanocrystals) in the oxide conductive layer 214a and the oxide conductive layer 214b have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0100] The oxide conductive layer 214a and the oxide conductive layer 214b are not necessarily provided, but by providing the oxide conductive layer 214a and the oxide conductive layer 214b between the oxide semiconductor layer 213 that functions as a channel formation region and the conductive layers 215a and 215b that function as a source terminal and a drain terminal, a good electrical junction can be obtained, and the transistor 251 can perform stable operation. Also, it is possible to maintain good mobility even at a high drain voltage.

[0101] Further, the transistors shown in FIGS. 8(A) and 8(B) may have a structure in which a conductive layer 217 is provided on the oxide semiconductor layer 213 with an oxide insulating layer 207 (when having a nitride insulating layer, the oxide insulating layer 207 and the nitride insulating layer) interposed therebetween, as shown in FIGS. 9(A) and 9(B). FIGS. 9(A) and 9(B) are diagrams showing an example of the structure of the transistor of this embodiment. FIG. 9(A) is a top view of the transistor, and FIG. 9(B) is a cross-sectional view taken along the line segment Z1-Z2 of FIG. 9(A). The conductive layer 217 has a function as a second Thus, the threshold voltage of the transistor 251 can be controlled. Also, when providing the planarization insulating layer a conductive layer 217 can also be provided on the planarization insulating layer.

[0102] For example, if the potential of the second gate terminal is made higher than the potential of the source terminal, the threshold voltage of the transistor shifts in the negative direction and becomes lower than the potential of the source terminal. If it is made lower than the potential of the source terminal, the threshold voltage of the transistor shifts in the positive direction.

[0103] As shown as an example in FIGS. 8 and 9, the transistor of this embodiment is a transistor using an oxide semiconductor in the channel formation region. This transistor has a higher mobility than a conventional transistor using amorphous silicon in the channel formation region. Therefore, the shift register constituted by this transistor can perform high-speed operation. .

[0104] Next, a form when using a plurality of the transistors shown in FIGS. 8(A) and 8(C) will be described with reference to FIG. 10. FIG. 10 is a diagram showing an example of the structure of a plurality of transistors applicable to a shift register which is one aspect of the present invention. FIG. 10(A) is a top view of two transistors and FIG. 10(B) is a cross-sectional view taken along the line segment X1-X2 in FIG. 10(A). .

[0105] In FIG. 10(A), transistors 251 and 252 are shown. Here, as an example, a structure having an oxide conductive layer between an oxide semiconductor layer and a conductive layer functioning as a source terminal or a drain terminal is shown.

[0106] Transistor 251 is the transistor shown in FIGS. 8(A) and 8(C). Therefore, the above description is incorporated herein by reference. For this reason, the above description is incorporated herein by reference.

[0107] Transistor 252 includes a conductive layer 211 on a substrate 201, an insulating layer 202 on the conductive layer 211, an oxide semiconductor layer 213 on the insulating layer 202, oxide conductive layers 214a and 214b on the oxide semiconductor layer 213, and conductive layers 215a and 215b. In transistor 252, the conductive layer 211 functions as a gate terminal, the insulating layer 202 functions as a gate insulating layer, the oxide conductive layers 214a and 214b having a higher conductivity than the oxide semiconductor layer 213 function as a source region (also referred to as a low-resistance source region) or a drain region (also referred to as a low-resistance drain region), and the conductive layers 215a and 215b function as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. In transistor 252, the conductive layer 211 functions as a gate terminal, the insulating layer 202 functions as a gate insulating layer, the oxide conductive layers 214a and 214b having a higher conductivity than the oxide semiconductor layer 213 function as a source region (also referred to as a low-resistance source region) or a drain region (also referred to as a low-resistance drain region), and the conductive layers 215a and 215b function as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. has.

[0108] In transistor 252, the conductive layer 211 functions as a gate terminal, the insulating layer 202 functions as a gate insulating layer, the oxide conductive layers 214a and 214b having a higher conductivity than the oxide semiconductor layer 213 function as a source region (also referred to as a low-resistance source region) or a drain region (also referred to as a low-resistance drain region), and the conductive layers 215a and 215b function as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. 202 functions as a gate insulating layer, the oxide conductive layers 214a and 214b having a higher conductivity than the oxide semiconductor layer 213 function as a source region (also referred to as a low-resistance source region) or a drain region (also referred to as a low-resistance drain region), and the conductive layers 215a and 215b function as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. electric layers 214a and 214b function as a source region (also referred to as a low-resistance source region) or a drain region (also referred to as a low-resistance drain region), and the conductive layers 215a, conductive layer 2 15b functions as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. 15b functions as a source terminal or a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. annel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration treatment or a dehydrogenation treatment during formation. elementation treatment is performed.

[0109] Furthermore, in transistors 251 and 252 shown in FIGS. 10(A) and 10(B), not only is the oxide semiconductor layer subjected to a dehydration treatment or a dehydrogenation treatment, but an oxide insulating layer 207 is provided in contact with a part of the oxide semiconductor layer 213 and the oxide semiconductor layer 2132. 52, not only is the oxide semiconductor layer subjected to a dehydration treatment or a dehydrogenation treatment, but an oxide insulating layer 207 is provided in contact with a part of the oxide semiconductor layer 213 and the oxide semiconductor layer 2132. oxide semiconductor layer 213 and a part of the oxide semiconductor layer 2132, an oxide insulating layer 207 is provided in contact therewith. is provided.

[0110] Furthermore, the conductive layer 211 of transistor 251 is in contact with the conductive layer 215b through an opening provided in the insulating layer 202. Thereby, good contact can be obtained, and the contact resistance can be obtained, and the contact resistance can be reduced. Thus, reduction in the number of openings, reduction in the occupied area due to the reduction in the number of openings can be achieved. Thus, for example, a logic circuit can be configured using two transistors having this structure (e.g., an inverter).

[0111] As shown as an example in FIG. 10, in the shift register shown in Embodiment 1, a conductive layer that functions as a gate terminal of a certain transistor is provided in an insulating layer that functions as a gate insulating layer and is electrically connected to a conductive layer that functions as a source terminal or a drain terminal of another transistor through an opening provided therein and can have a structure in which they are electrically connected .

[0112] Next, an example of a method for manufacturing the transistor shown in FIG. 8(B) will be described with reference to FIGS. 11(A) to (D) . FIGS. 11(A) to (D) are cross-sectional views showing an example of the method for manufacturing the transistor shown in FIG. 8(B) .

[0113] Hereinafter, the "film" refers to a film formed over the entire surface of the substrate and is in a state before being processed into a desired shape by a photolithography process or the like . And the "layer" refers to a layer formed by processing a "film" into a desired shape by a photolithography process or the like, and a layer formed for the purpose of covering the entire surface of the substrate . First, a substrate 201 is prepared, and after forming a conductive film on the substrate 201, a conductive layer 211 is formed by a first photolithography process (see FIG. 11(A)). Note that the formed conductive layer 211 preferably has a tapered shape . By forming the conductive layer 211 in a tapered shape

[0114] , the adhesion to the film in contact with the upper portion can be enhanced . .

[0115] As the substrate 201, it is necessary to have an insulating surface and at least heat resistance enough to withstand subsequent heat treatment. As the substrate 201, for example, a glass substrate or the like can be used.

[0116] Also, when the temperature of the subsequent heat treatment is high for the glass substrate, it is preferable to use one with a strain point of 730 °C or higher. Further, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Generally, by including more barium oxide (BaO) compared to boric acid (B2O3), a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0117] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 201. Alternatively, crystallized glass or the like can be used.

[0118] Also, an insulating layer serving as an underlayer may be provided between the substrate 201 and the conductive layer 211. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 201, and is a layer composed of silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide, or a laminated structure formed by these layers.

[0119] As the material of the conductive film for forming the conductive layer 211, for example, metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these can be used. To form the conductive layer 211, The conductive film can be formed by a single-layer film or a laminated film of a film containing any one or more of these materials. It can be formed.

[0120] In addition, the conductive film for forming the conductive layer 211 has a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminated structure in which an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer. It is preferable. Of course, it may be a single layer, a two-layer structure, or a laminated structure of four or more layers as the conductive film. In addition, when a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film, it can be etched by a dry etching method using chlorine gas. It is preferable. Of course, it may be a single layer, a two-layer structure, or a laminated structure of four or more layers as the conductive film. In addition, when a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film, it can be etched by a dry etching method using chlorine gas. It can be etched by a dry etching method using chlorine gas.

[0121] Next, an insulating layer 202 is formed on the conductive layer 211.

[0122] The insulating layer 202 can be formed by a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the insulating layer 202 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second insulating layer having a film thickness of 5 nm or more and 300 nm or less are laminated on the first insulating layer. In addition, as the insulating layer 202, by using a silicon oxide film formed by using a silicon target material doped with phosphorus or boron, the intrusion of impurities (such as moisture, hydrogen ions, and OH) can be suppressed. It can be formed by a single layer or a laminate. For example, a silicon oxynitride layer may be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the insulating layer 202 is set to 100 nm or more and 500 nm or less. In the case of a laminate, for example, a first insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second insulating layer having a film thickness of 5 nm or more and 300 nm or less are laminated on the first insulating layer. In addition, as the insulating layer 202, by using a silicon oxide film formed by using a silicon target material doped with phosphorus or boron, the intrusion of impurities (such as moisture, hydrogen ions, and OH) can be suppressed. In addition, as the insulating layer 202, by using a silicon oxide film formed by using a silicon target material doped with phosphorus or boron, the intrusion of impurities (such as moisture, hydrogen ions, and OH) can be suppressed. (such as moisture, hydrogen ions, and OH) - The intrusion of It can be suppressed.

[0123] In this embodiment, as an example, silicon nitride with a film thickness of 200 nm is formed by plasma CVD to form the insulating layer 202.

[0124] Next, an oxide semiconductor film is formed on the insulating layer 202. The film thickness of the oxide semiconductor film is preferably 2 nm or more and 200 nm or less. For example, by making the film thickness as thin as 50 nm or less, even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film can be made amorphous. Also, by making the film thickness of the oxide semiconductor film thin, crystallization can be suppressed when heat treatment is performed after the formation of the oxide semiconductor film.

[0125] Before forming the oxide semiconductor film by sputtering, reverse sputtering may be performed by introducing argon gas to generate plasma to remove dust adhering to the surface of the insulating layer 202. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side. Note that nitrogen, helium, oxygen, etc. may be used instead of argon.

[0126] As the oxide semiconductor film, an In-Ga-Zn-O-based film, an In-Sn-Zn-O-based film, an In-Al-Zn-O-based film, a Sn-Ga-Zn-O-based film, an Al-Ga-Zn-O-based film, a Sn-Al-Zn-O-based film, an In-Zn-O-based film, a Sn-Zn-O-based film, an Al-Zn-O-based film, an In-Sn-O-based film, an In-O-based film, a Sn-O-based film, or a Zn-O-based oxide semiconductor film is used. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form a film by sputtering. ​​​​​​​​​​​​​​The oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 can be used for film formation, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in subsequent steps. Here, a metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [at]) is used, and film formation is performed at a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, it is preferable because the powdery substances (also called particles and dust) generated during film formation can be reduced and the film thickness distribution becomes uniform. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O-based film by sputtering as the oxide semiconductor film. In addition, as the metal oxide target, in addition to the target having the above composition, composition ratios such as In2O3:Ga2O3:ZnO = 1:1:0.5 [mol], In:Ga:Zn = 1 :1:0.25 [at] or In2O3:Ga2O3:ZnO = 1:1:2 [mol], In:Ga:Zn = 1:1:1 [at] etc. can also be used.

[0127] That is, the oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, film formation is performed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in subsequent steps. O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5 [at]) is used, and the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and film formation is performed in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O-based film by sputtering as the oxide semiconductor film. Here, a metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga2O3:ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [at]) is used, and film formation is performed at a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and in an oxygen (oxygen flow ratio 100%) atmosphere. When using a pulsed DC power supply, it is preferable because the powdery substances (also called particles and dust) generated during film formation can be reduced and the film thickness distribution becomes uniform. In this embodiment, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O-based film by sputtering as the oxide semiconductor film. Note that, as the metal oxide target, in addition to the target having the above composition, composition ratios such as In2O3:Ga2O3:ZnO = 1:1:0.5 [mol], In:Ga:Zn = 1 :1:0.25 [at] or In2O3:Ga2O3:ZnO = 1:1:2 [mol], In:Ga:Zn = 1:1:1 [at] etc. can also be used.

[0128] That is, the oxide semiconductor film can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. When using the sputtering method, film formation is performed using a target containing 2% by weight or more and 10% by weight or less of SiO2, and SiOx (x>0) that inhibits crystallization may be included in the oxide semiconductor film. This can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in subsequent steps. 、In2O3:Ga2O3:ZnO=1:1:0.5[mol]、In:Ga:Zn=1 :1:0.25[at] or In2O3:Ga2O3:ZnO=1:1:2[mol]、 In:Ga:Zn=1:1:1[at] etc. can also be used.

[0129] Sputtering methods include the RF sputtering method that uses a high-frequency power supply as the sputtering power supply, and the DC sputtering method. There is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films.

[0130] There is also a multi-source sputtering apparatus that can install multiple targets made of different materials. The multi-source sputtering apparatus can deposit different material films in a stacked manner in the same chamber, or discharge multiple types of materials simultaneously in the same chamber to form a film.

[0131] There is also a sputtering apparatus that uses the magnetron sputtering method with a magnet mechanism inside the chamber, and a sputtering apparatus that uses the ECR sputtering method that uses plasma generated using microwaves without using glow discharge. There is also a reactive sputtering method as a film deposition method using sputtering, in which a chemical reaction is caused between the target substance and the sputtering gas components during film deposition to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film deposition.

[0132] Also, as an exhaust means for the film deposition chamber where sputtering is performed, it is preferable to use a cryopump. By exhausting using a cryopump, impurities such as moisture in the film deposition chamber can be removed. Next, the oxide semiconductor film is processed into an island shape by a second photolithography process to form an oxide semiconductor layer 213 (see FIG. 11(B)). Note that the second photolithography process

[0133] Also, as an exhaust means for the film deposition chamber where sputtering is performed, it is preferable to use a cryopump. By exhausting using a cryopump, impurities such as moisture in the film deposition chamber can be removed. By exhausting using a cryopump, impurities such as moisture in the film deposition chamber can be removed.

[0134] Next, the oxide semiconductor film is processed into an island shape by a second photolithography process to form an oxide semiconductor layer 213 (see FIG. 11(B)). Note that the second photolithography process Subsequently, the oxide semiconductor layer 213 may be heat-treated (at 400 °C or higher and less than 750 °C) in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer.

[0135] Next, dehydration or dehydrogenation of the oxide semiconductor layer 213 is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400 °C or higher and less than 750 °C, preferably 425 °C or higher. If it is 425 °C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425 °C, the heat treatment time will be longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing heat treatment on the oxide semiconductor layer 213 in a nitrogen atmosphere, it is prevented from coming into contact with the atmosphere and from being contaminated with water or hydrogen in the oxide semiconductor layer 213. In this embodiment, the same furnace is used to gradually cool the oxide semiconductor layer 213 from the heat treatment temperature for dehydration or dehydrogenation to a sufficient temperature at which water does not enter again. Specifically, it is gradually cooled in a nitrogen atmosphere until the temperature drops by 100 °C or more from the heating temperature. Note that the atmosphere is not limited to a nitrogen atmosphere, and any inert gas atmosphere such as helium, neon, or argon may be used.

[0136] Note that the heat treatment apparatus is not limited to an electric furnace, and a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be provided. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Ga s Rapid Thermal Anneal) device or an LRTA (Lamp Rapi d Thermal Anneal) device An annealing device can be used. The LRTA device is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. As for the gas, an inert gas such as a noble gas like argon or nitrogen that does not react with the object to be processed by heat treatment is used. By heat-treating the oxide semiconductor layer 213 at a temperature of 400 °C or higher and less than 750 °C, dehydration and dehydrogenation of the oxide semiconductor layer can be achieved, and subsequent re-impregnation of water (H2O) can be prevented. Also, in the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Further, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 213, the oxide semiconductor layer 213 may be composed of fine crystal grains and an amorphous region or only crystal grains. For example, it may be an oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more of fine crystals. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 213, the oxide semiconductor layer 213 may be composed only of an amorphous region that does not contain crystal grains.

[0137]

[0138]

[0139] ​​​​​​​​​​​​​​​It may be configured as follows.

[0140] The oxide semiconductor layer 213 becomes oxygen-deficient after the first heat treatment and its resistance decreases. The oxide semiconductor film after the first heat treatment has a higher carrier concentration than the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10 / cm 18 / cm 3 or more, becoming an oxide semiconductor layer. .

[0141] Note that depending on the conditions of the first heat treatment or the material of the conductive layer 211, it may become a microcrystalline layer or a polycrystalline layer. For example, when an indium tin oxide alloy film is used as the conductive layer 211, it crystallizes with a heat treatment at 450°C for 1 hour, and when an indium tin oxide alloy film containing silicon oxide is used as the conductive layer 211, it does not crystallize. When using an indium tin oxide alloy film it crystallizes with a heat treatment at 450°C for 1 hour, and when using an indium tin oxide alloy film containing silicon oxide as the conductive layer 211, it does not crystallize.

[0142] Also, the first heat treatment of the oxide semiconductor layer 213 can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed. After the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed. Next, a conductive film is formed on the insulating layer 202 and the oxide semiconductor layer 213.

[0143] As the conductive film, an element selected from titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), and tantalum (Ta), or an alloy containing the above-described elements as components, or a compound combining the above-described elements, etc. are used.

[0144] The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment, a titanium film (film thickness 100 nm) and an aluminum film (film thickness 200 nm) are used. As the conductive film, an element selected from titanium (Ti), molybdenum (Mo), tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), and tantalum (Ta), or an alloy containing the above-described elements as components, or a compound combining the above-described elements, etc. are used. The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment, a titanium film (film thickness 100 nm) and an aluminum film (film thickness 200 A three-layer conductive film composed of an indium tin oxide film (film thickness: 100 nm) and a titanium film (film thickness: 100 nm) is formed. Also, a titanium nitride film may be used instead of the titanium film.

[0145] When heat treatment at 200°C to 600°C is performed later, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. For example, it is preferable to use an aluminum alloy added with an anti-hillock element or a conductive film laminated with a heat-resistant conductive film. The method for forming the conductive film is a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method. Also, it may be formed by discharging and baking using a screen printing method, an inkjet method, etc. using a conductive nanopaste such as silver, gold, or copper.

[0146] Next, a resist mask 233a and a resist mask 233b are formed by a third photolithography process, and the conductive film is selectively etched to form a conductive layer 215a and a conductive layer 215b (see Fig. 11(C)).

[0147] Also, in the third photolithography process, only the conductive film in contact with the oxide semiconductor layer 213 is selectively removed. For example, in order to selectively remove only the metal conductive film in contact with an In-Ga-Zn-O-based oxide semiconductor layer, ammonia peroxide (as a weight ratio of the composition, hydrogen peroxide: ammonia: water = 5:2:2) or the like is used as an alkaline etchant, and the conductive film can be selectively removed to leave an oxide semiconductor layer made of an oxide semiconductor.

[0148] Also, depending on the etching conditions, in the third photolithography process, the oxide semiconductor ​​​​​​​​​​​The exposed area of the layer 213 may be etched. In that case, the oxide semiconductor layer in the region sandwiched between the conductive layer 215a and the conductive layer 215b has a smaller film thickness than the oxide semiconductor layer in the region where the conductive layer 215a and the conductive layer 215b overlap on the conductive layer 211.

[0149] Next, an oxide insulating layer 207 is formed over the insulating layer 202 and the oxide semiconductor layer 213. At this stage, a part of the oxide semiconductor layer 213 is in contact with the oxide insulating layer 207. Note that the region of the oxide semiconductor layer that overlaps with the conductive layer 211 with the insulating layer 202 interposed therebetween serves as a channel formation region.

[0150] The oxide insulating layer 207 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer. In this embodiment, a silicon oxide film is formed as the oxide insulating layer by using sputtering. During film formation the substrate temperature may be equal to or higher than room temperature and equal to or lower than 300°C, and is set to 100°C in this embodiment. The silicon oxide film can be formed by sputtering in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by sputtering using a silicon target in an atmosphere of oxygen and a rare gas. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and uses an inorganic insulating film that blocks these from entering from the outside, typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film. Note that sputtering is typically used. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH - and uses an inorganic insulating film that blocks these from entering from the outside, typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film. Note that sputtering is typically used. The oxide insulating layer formed by the method is particularly dense and can be used as a single-layer protective film that suppresses the phenomenon of impurity diffusion into the adjacent layer. Also, by using a target doped with phosphorus (P) or boron (B), phosphorus (P) or boron (B) can be added to the oxide insulating layer.

[0151] In this embodiment, a columnar polycrystalline B-doped silicon target with a purity of 6N (resistivity 0.01 Ωcm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, a DC power supply of 6 kW, and film formation is carried out by pulsed DC sputtering in an oxygen (oxygen flow ratio 100%) atmosphere. The film thickness is 300 nm.

[0152] Note that the oxide insulating layer 207 is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 213 and also has a function as a channel protection layer.

[0153] Next, the second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) may be performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer 213 is heated in contact with the oxide insulating layer 207, and another part of the oxide semiconductor layer 213 is heated in contact with the conductive layers 215a and 215b.

[0154] When the second heat treatment is performed on the oxide semiconductor layer 213, which has been made low-resistance by the first heat treatment, in a state where it is in contact with the oxide insulating layer 207, the region in contact with the oxide insulating layer 207 is in an oxygen-excess state. As a result, from the region of the oxide semiconductor layer 213 that contacts the oxide insulating layer 207, the resistance increases (type I) in the depth direction of the oxide semiconductor layer 213 (see Fig. 11(D)). )

[0155] Note that the timing of the second heat treatment is not limited to immediately after the end of the third photolithography process, and is not particularly limited as long as it is a process after the third photolithography process.

[0156] As described above, the transistor shown in Fig. 8(B) can be fabricated.

[0157] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content.

[0158] (Embodiment 3) In this embodiment, an example of a transistor different from the transistor shown in Embodiment 2, which is applicable to the transistor constituting the shift register shown in Embodiment 1, will be described.

[0159] An example of the structure of the transistor in this embodiment will be described with reference to Fig. 12. Fig. 12 is a diagram showing an example of the structure of the transistor in this embodiment. Fig. 12(A) is a top view of the transistor, and Fig. 12(B) is a cross-sectional view taken along the line segment Z1-Z2 in Fig. 12(A).

[0160] The transistor shown in Figs. 12(A) and 12(B) includes a conductive layer 211 on a substrate 201, an insulating layer 202 on the conductive layer 211, conductive layers 215a and 215 b on the insulating layer 202, and an oxide semiconductor layer 213 on the insulating layer 202 and the conductive layers 215a and 215b. having

[0161] In this transistor, the conductive layer 211 functions as a gate terminal, the insulating layer 2 02 functions as a gate insulating layer, and one of the conductive layer 215a and the conductive layer 215b functions as a source terminal, and the other functions as a drain terminal. Further, the oxide semiconductor layer 213 has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to a dehydration or dehydrogenation treatment during formation.

[0162] Furthermore, in the transistors shown in FIGS. 12(A) and 12(B), not only is the oxide semiconductor layer 213 subjected to a dehydration treatment or a dehydrogenation treatment, but also an oxide insulating layer 207 is provided in contact with a part of the oxide semiconductor layer 213. After the dehydration or dehydrogenation treatment, a transistor using the oxide semiconductor layer 213 on which the oxide insulating layer 207 is formed as a channel formation region is less likely to have a threshold voltage (Vth) shift due to long-term use or high load, and thus has high reliability.

[0163] Note that a nitride insulating layer may be provided on the oxide insulating layer 207. The nitride insulating layer is preferably configured to be in contact with the insulating layer 202 provided below the oxide insulating layer 207 or the underlying insulating layer, and blocks the intrusion of moisture, hydrogen ions, OH and other impurities from the vicinity of the side surface of the substrate. In particular, it is effective to use a silicon nitride layer as the insulating layer 202 or the underlying insulating layer in contact with the oxide insulating layer 207. That is, when a silicon nitride layer is provided so as to surround the lower surface, upper surface, and side surfaces of the oxide semiconductor layer 213, the reliability of the transistor is improved. -

[0164] Further, a planarization insulating layer may be provided on the oxide insulating layer 207 (or on the nitride insulating layer when the nitride insulating layer is provided). )

[0165] Further, the transistor shown in FIG. 12, similar to FIGS. 9(A) and 9(B), has a structure in which a conductive layer is provided on the oxide insulating layer 207 in a region overlapping with the oxide semiconductor layer 213 (or on the planarization insulating layer when the planarization insulating layer is provided). The conductive layer functions as a second gate terminal. By applying a second gate voltage to the conductive layer, the threshold voltage of the transistor can be controlled.

[0166] Note that the planarization insulating layer is not necessarily provided. When the planarization insulating layer is not provided, a structure may be adopted in which a conductive layer having a function as a second gate terminal is provided on the oxide insulating layer 207 (or on the nitride insulating layer when the nitride insulating layer is provided).

[0167] For example, when the potential of the second gate terminal is made higher than the potential of the source terminal, the threshold voltage of the transistor shifts in the negative direction, and when the potential of the second gate terminal is made lower than the potential of the source terminal, the threshold voltage of the transistor shifts in the positive direction.

[0168] As shown in FIG. 12, the transistor of this embodiment is a so-called bottom-contact type transistor having an oxide semiconductor layer on a conductive layer that functions as a source terminal or a drain terminal. Compared with a conventional transistor using amorphous silicon in the channel formation region, this transistor has a high mobility. Therefore, a shift register configured by this transistor can operate at high speed. Further, the bottom-contact type transistor By applying a transistor, the contact area between the oxide semiconductor layer and the conductive layer functioning as a source terminal or a drain terminal can be increased, and peeling or the like can be prevented.

[0169] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content.

[0170] (Embodiment 4) In this embodiment, an example of a transistor different from the transistors shown in Embodiments 2 and 3, which can be applied to the transistors constituting the shift register shown in Embodiment 1, will be described.

[0171] An example of the structure of the transistor in this embodiment will be described with reference to FIG. 13. FIG. 13 is a diagram showing an example of the structure of the transistor in this embodiment. FIG. 13(A) is a top view of the transistor, and FIG. 13(B) is a cross-sectional view taken along the line segment Z1-Z2 of FIG. 13(A).

[0172] The transistor shown in FIGS. 13(A) and 13(B) is the same as the transistor shown in FIG. 8 and includes a conductive layer 211 on a substrate 201, an insulating layer 202 on the conductive layer 211, an oxide semiconductor layer 213 on the insulating layer 202, and conductive layers 215a and 215 b on the oxide semiconductor layer 213.

[0173] In the transistor, the conductive layer 211 functions as a gate terminal, the insulating layer 2 02 functions as a gate insulating layer, one of the conductive layers 215a and 215b functions as a source terminal, and the other functions as a drain terminal. Further, the oxide semiconductor layer 213 is a channel It has a channel formation region. Note that the oxide semiconductor layer 213 is subjected to dehydration or dehydrogenation treatment during formation. treatment.

[0174] Furthermore, the transistors shown in FIGS. 13(A) and 13(B) are not only subjected to dehydration treatment or dehydrogenation treatment on the oxide semiconductor layer 213, but also in contact with a part of the oxide semiconductor layer 213. An oxide insulating layer 207 is provided under the conductive layer 215a and the conductive layer 215b. FIG. 13(A) and the oxide insulating layer 207 shown in FIG. 13(B) function as a channel protection layer. have.

[0175] Note that a nitride insulating layer may be provided on the oxide insulating layer 207, the conductive layer 215a, and the conductive layer 215b. The nitride insulating layer is preferably configured to be in contact with the insulating layer 202 provided below the oxide insulating layer 207 or the underlying insulating layer, and blocks the intrusion of moisture, hydrogen ions, OH and other impurities from the vicinity of the side surface of the substrate. In particular, it is effective to use a silicon nitride layer as the insulating layer 202 in contact with the oxide insulating layer 207 or the underlying insulating layer. That is, providing a silicon nitride layer so as to surround the lower surface, upper surface, and side surface of the oxide semiconductor layer 213 - improves the reliability of the transistor.

[0176] Also, a planarization insulating layer can be provided on the oxide insulating layer 207 and the conductive layer 215a and the conductive layer 215b (on the nitride insulating layer when the nitride insulating layer is provided).

[0177] Also, on the oxide insulating layer 207 (on the planarization insulating layer when the planarization insulating layer is provided ), a structure having a conductive layer on the oxide semiconductor layer with the oxide insulating layer 207 interposed therebetween is formed. ​​​​​This is also possible. The conductive layer has a function as a second gate terminal. By applying a second gate voltage to the conductive layer, the threshold voltage of the transistor 251 can be controlled.

[0178] Note that the planarization insulating layer is not necessarily provided. When the planarization insulating layer is not provided, a structure having the conductive layer on the oxide insulating layer 207 (or on the nitride insulating layer when the nitride insulating layer is present) can also be adopted.

[0179] For example, when the potential of the second gate terminal is made higher than the potential of the source terminal, the threshold voltage of the transistor shifts in the negative direction, and when it is made lower than the potential of the source terminal, the threshold voltage of the transistor shifts in the positive direction.

[0180] Also, the transistor of this embodiment is similar to the transistor shown in FIG. 8(C), and a pair of oxide conductive layers functioning as a pair of buffer layers are provided on a part of the oxide semiconductor layer 213, and a structure in which a conductive layer 215a and a conductive layer 215b, which are a pair of electrodes, are provided so as to be in contact with the pair of oxide conductive layers respectively can also be adopted.

[0181] As described above, the transistor in this embodiment is a so-called channel protection type transistor having an insulating layer serving as a channel protection layer on a part of the oxide semiconductor layer. The transistor has a higher mobility than a conventional transistor using amorphous silicon in the channel formation region. Therefore, the shift register constituted by the transistor can operate at high speed.

[0182] ​​​​​​​​Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content. It is possible to freely combine.

[0183] (Embodiment 5) In this embodiment, an example of a display device having the shift register shown in Embodiment 1 will be described with reference to FIG. 14. It will be described with reference to FIG. 14.

[0184] Examples of the display device having the shift register shown in Embodiment 1 include various display devices such as a liquid crystal display device or an electroluminescence (hereinafter also referred to as EL) display device. Examples of the display device having the shift register shown in Embodiment 1 include various display devices such as a liquid crystal display device or an electroluminescence (hereinafter also referred to as EL) display device. The configuration of the display device in this embodiment will be described with reference to FIG. 14(A). FIG. 14(A) is a block diagram showing the configuration of the display device in this embodiment. FIG. 14(A) is a block diagram showing the configuration of the display device in this embodiment.

[0185] The display device shown in FIG. 14(A) includes a pixel portion 701, a scanning line driving circuit 702, and a signal line driving circuit 703. It has a pixel portion 701, a scanning line driving circuit 702, and a signal line driving circuit 703.

[0186] Furthermore, the pixel portion 701 has a dot matrix structure including a plurality of pixels 704. Specifically, a plurality of pixels 704 are arranged in a matrix direction. Each pixel 704 is electrically connected to the scanning line driving circuit 702 via a scanning line 705 and is electrically connected to the signal line driving circuit 703 via a signal line 706. Specifically, a plurality of pixels 704 are arranged in a matrix direction. Each pixel 704 is electrically connected to the scanning line driving circuit 702 via a scanning line 705 and is electrically connected to the signal line driving circuit 703 via a signal line 706. Specifically, a plurality of pixels 704 are arranged in a matrix direction. Each pixel 704 is electrically connected to the scanning line driving circuit 702 via a scanning line 705 and is electrically connected to the signal line driving circuit 703 via a signal line 706. Specifically, a plurality of pixels 704 are arranged in a matrix direction. Each pixel 704 is electrically connected to the scanning line driving circuit 702 via a scanning line 705 and is electrically connected to the signal line driving circuit 703 via a signal line 706.

[0187] The scanning line driving circuit 702 is a circuit that selects a pixel 704 that inputs a data signal and outputs a selection signal to the pixel 704 via the scanning line 705. The scanning line driving circuit 702 is a circuit that selects a pixel 704 that inputs a data signal and outputs a selection signal to the pixel 704 via the scanning line 705.

[0188] The signal line driving circuit 703 is a circuit that outputs data to be written to the pixel 704 as a signal and outputs pixel data to the pixel 704 selected by the scanning line driving circuit 702 via the signal line 706. The signal line driving circuit 703 is a circuit that outputs data to be written to the pixel 704 as a signal and outputs pixel data to the pixel 704 selected by the scanning line driving circuit 702 via the signal line 706. Outputs ta as a signal.

[0189] Pixel 704 has at least a display element and a switching element. As the display element For example, a light-emitting element such as a liquid crystal element or an EL element can be applied, and as the switching element For example, a transistor or the like can be applied.

[0190] Next, a configuration example of the scanning line driving circuit 702 and the signal line driving circuit 703 will be described with reference to FIGS. 14(B) , (C). FIGS. 14(B), (C) are block diagrams showing the configuration of the driving circuit. FIG. 14(B) is a block diagram showing the configuration of the scanning line driving circuit 702, and FIG. 14(C ) is a block diagram showing the configuration of the signal line driving circuit 703.

[0191] As shown in FIG. 14(B), the scanning line driving circuit 702 includes a shift register 900, a level shifter 901, and a buffer 902.

[0192] The shift register 900 receives signals such as a start pulse for the scanning line driving circuit (GSP) and a reference clock signal for the scanning line driving circuit (GCK), and sequentially selects signals are output in each sequential logic circuit. The shift register 900 of the present embodiment is the same as that shown in Embodiment 1 In this way, the reference clock signal for the scanning line driving circuit (GCK) has a plurality of wirings that supply the reference clock signal for the scanning line driving circuit during a part of the operation period.

[0193] As shown in FIG. 14(C), the signal line driving circuit 703 includes a shift register 903, a first latch circuit 904, a second latch circuit 905, a level shifter 906, and a buffer 907.

[0194] ​​​ The shift register 903 receives signals such as a start pulse for signal line drive circuit (SSP) and a reference clock signal for signal line drive circuit (SCK), and sequentially outputs selection signals in each sequential logic circuit. The shift register 903 of the present embodiment has a plurality of wirings that supply the reference clock signal for signal line drive circuit (SCK) during a part of the operation period, as shown in Embodiment 1. circuit reference clock signal (SCK), etc., are input, and selection signals are sequentially output in each sequential logic circuit. In the shift register 903 of the present embodiment, the reference clock signal for signal line drive circuit (SCK) is included in a part of the operation period, as shown in Embodiment 1. In the shift register 903 of the present embodiment, the reference clock signal for signal line drive circuit (SCK) is included in a part of the operation period, as shown in Embodiment 1. It has a plurality of wirings that supply the reference clock signal for signal line drive circuit during a part of the operation period.

[0195] Note that only one of the shift register 900 and the shift register 903 may be the shift register shown in Embodiment 1. Note that only one of the shift register 900 and the shift register 903 may be the shift register shown in Embodiment 1.

[0196] A data signal (DATA) is input to the first latch circuit 904. The first latch circuit 904 can be configured using a logic circuit. The first latch circuit 904 can be configured using a logic circuit.

[0197] The buffer 907 has a function of amplifying signals and includes an operational amplifier or the like. The buffer 907 can be configured using a logic circuit. The buffer 907 can be configured using a logic circuit.

[0198] The second latch circuit 905 can temporarily hold a latch (LAT) signal, and outputs the held latch signal to the pixel portion 701 in FIG. 14(A) all at once. This is called line sequential drive. Therefore, for pixels that perform dot sequential drive instead of line sequential drive, the second latch circuit 905 can be made unnecessary. Also, the second latch circuit 905 can be configured using a logic circuit. The second latch circuit 905 can temporarily hold a latch (LAT) signal, and outputs the held latch signal to the pixel portion 701 in FIG. 14(A) all at once. This is called line sequential drive. Therefore, for pixels that perform dot sequential drive instead of line sequential drive, the second latch circuit 905 can be made unnecessary. Also, the second latch circuit 905 can be configured using a logic circuit. The second latch circuit 905 can be configured using a logic circuit.

[0199] Next, the operation of the display device of the present embodiment will be described.

[0200] First, the scanning line driving circuit 702 selects the scanning line 705. The pixel 704 electrically connected to the selected scanning line 705 receives data signals from the signal line driving circuit 703 via the signal line 706. As a result, data is written to the pixel 704 and it enters the display state. The scanning line driving circuit 702 selects the scanning line 705, and data

[0201] writing is performed for all the pixels 704. The above is the operation of the display device in this embodiment. All the circuits of the display device shown in FIG. 14 can be provided on the same substrate. Further, they can be composed of transistors of the same conductivity type. By providing

[0202] them on the same substrate, miniaturization can be achieved, and by composing them of transistors of the same conductivity type, the

[0203] (Embodiment 6) In this embodiment, a liquid crystal display device will be described as an example of the display device shown in Embodiment 5 with reference to

[0204] FIG. 15. FIG. 15(A) shows a circuit diagram of a pixel included in the liquid crystal display device of this embodiment. The pixel shown in FIG. 15(A

[0205] has a transistor 821, a liquid crystal element 822, and a capacitor element 823. It functions as a selection transistor that controls the application of voltage to the element 822.

[0206] One terminal of the liquid crystal element 822 is electrically connected to the second terminal of the transistor 821, and the other terminal is electrically connected to a wiring (hereinafter also referred to as a common potential line) that supplies a common potential (Vcom). Note that the liquid crystal element 822 includes a first electrode that is part or all of one terminal, a second electrode that is part or all of the other terminal, and a layer (referred to as a liquid crystal layer) having liquid crystal molecules whose orientation changes when a voltage is applied between the first electrode and the second electrode. It is composed of

[0207] One terminal of the capacitor element 823 is electrically connected to the second terminal of the transistor 821, and the other terminal is electrically connected to the common potential line. Note that the capacitor element 823 includes a first electrode that is part or all of one terminal, a second electrode that is part or all of the other terminal, and a dielectric layer provided between the first electrode and the second electrode. Also, the capacitor element 823 functions as a holding capacitor of the pixel. Note that the capacitor element 823 is not necessarily provided, but by providing the capacitor element 823, the influence of the leakage current of the transistor 821 can be suppressed.

[0208] Note that as the driving method of the liquid crystal in the liquid crystal display device of the present embodiment, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, etc. can be used. ​​Patterned Vertical Alignment mode, ASM (Axial ly Symmetric aligned Micro-cell) mode, OCB ( Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFL C (AntiFerroelectric Liquid Crystal), etc. can be mentioned. And so on.

[0209] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the cholesteric liquid crystal is heated, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. And used in the liquid crystal layer. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependence. When a signal is input to a pixel, first, the pixel to which data is to be written is selected, and the selected pixel causes the transistor 821 to turn on by the signal input from the scanning line 804.

[0210] At this time, the data signal from the signal line 805 is input to the pixel through the transistor 821, and the potential of one terminal of the liquid crystal element 822 becomes the potential of the data signal. As a result, the liquid crystal element 822 is set to an alignment state according to the voltage applied between one terminal and the other terminal. After data writing, the transistor 821 is turned off by the signal input from the scanning line 804.

[0211] At this time, the data signal from the signal line 805 is input to the pixel through the transistor 821, and the potential of one terminal of the liquid crystal element 822 becomes the potential of the data signal. Thereby, the liquid crystal element 822 is set to an alignment state according to the voltage applied between one terminal and the other terminal. After data writing, the transistor 821 is turned off by the signal input from the scanning line 804. And the signal input from the scanning line 804 causes the transistor 821 to turn off. enters the "f" state, and the liquid crystal element 822 maintains the alignment state set during the display period, becoming the display state and so on. The above operations are sequentially performed for each scanning line 804, and the above operations are performed for all the pixels of the liquid crystal display device. The above operation is performed.

[0212] In the video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there is a problem that afterimages occur, or blurring of the video occurs. To improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion, in which full-screen black display is performed every other frame. There is also a driving technique called so-called double-speed driving, in which the response speed is improved by making the normal vertical synchronization frequency 1.5 times, preferably 2 times or more.

[0213] In addition, to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources as a backlight, and each light source constituting the surface light source is independently driven by intermittent lighting within one frame period. As for the surface light source, three or more types of LEDs may be used, or white light-emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the

[0214] light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. Since this driving technique can partially turn off the LEDs, particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. constituting the surface light source is independently driven by intermittent lighting within one frame period. As for the surface light source, three or more types of LEDs may be used, or white light-emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. Since this driving technique can partially turn off the LEDs, particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. Since this driving technique can partially turn off the LEDs, particularly in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved. By combining these driving techniques, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0215] By combining these driving techniques, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before. By combining these driving techniques, the display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0216] Next, the structure of the liquid crystal display device according to the present embodiment including the above pixels will be described with reference to FIGS. 15(B) , (C). FIGS. 15(B) and (C) are diagrams showing the structure of the pixels of the display device according to the present embodiment. FIG. 15(B) is a top view of the pixel, and FIG. 15(C) is a cross-sectional view taken along the line A1-A2 and B1-B2 in FIG. 1 5(B).

[0217] In the liquid crystal display device shown in FIGS. 15(B) and 15(C), in the cross section along A1-A2, there are a conductive layer 2001 on a substrate 2000, an insulating layer 2002 on the conductive layer 2001, an oxide semiconductor layer 2003 on the insulating layer 200 2, a conductive layer 2005a and a conductive layer 2005b on the oxide semiconductor layer 2003, an oxide insulating layer 2007 on the conductive layer 2005a, the conductive layer 2005b, and the oxide semiconductor layer 2003 , and a transparent conductive layer 2020 in contact with the conductive layer 2005b through an opening provided in the oxide insulating layer 2007.

[0218] Note that the conductive layer 2001 functions as a gate terminal, the insulating layer 2002 functions as a gate insulating layer, one of the conductive layer 2005a and the conductive layer 2005b functions as a first terminal, and the other functions as a second terminal. Here, the transistor (see FIG. 8(B)) described in Embodiment 2 is applied, but as the transistor, the transistors shown in Embodiment 3 or Embodiment 4 can also be applied.

[0219] Further, in the cross section along B1-B2 of the liquid crystal display device shown in FIGS. 15(B) and 15(C), there are a conductive layer 2008 on a substrate 2000, an insulating layer 2002 on the conductive layer 2008, an oxide insulating layer 2007 on the insulating layer 2002, and a transparent conductive layer 2020 on the oxide insulating layer 2007 . ​​​​​​​

[0220] Furthermore, the liquid crystal display device of the present embodiment functions as an electrode or wiring for connecting to an FPC (Flexible Printed Circuits), and includes a conductive layer 2022 and a transparent conductive layer 2029, a conductive layer 2023, a conductive layer 2024, and a transparent conductive layer 2028 .

[0221] The transparent conductive layers 2020, 2029, and 2028 are formed by a sputtering method, a vacuum deposition method, or the like using indium oxide (In2O3), an indium tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), or the like. The etching treatment of such materials is performed using a hydrochloric acid-based solution. However, since residues are likely to occur particularly in the etching of ITO, an indium zinc oxide alloy (In2 O3 - ZnO) may be used to improve the etching processability. O3 - ZnO) may be used to improve the etching processability.

[0222] Note that the content of the present embodiment or a part of the content can be freely combined with the content of another embodiment or a part of the content.

[0223] (Embodiment 7) In the present embodiment, as an example of the display device shown in Embodiment 5, a light-emitting display device having a light-emitting element using electroluminescence will be described with reference to FIGS. 16 and 17.

[0224] A light-emitting element using electroluminescence is classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0225] ​​​​​​​​An organic EL element emits light when a voltage is applied to a light-emitting element, causing electrons and positive holes to be injected into a layer containing a light-emitting organic compound, respectively, and a current to flow. Then, these carriers (electrons and positive holes) recombine to emit light. Based on such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0226] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element configurations. A dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination light emission that utilizes donor levels and acceptor levels. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0227] FIG. 16(A) is a circuit diagram showing the circuit configuration of a pixel of a light-emitting display device according to the present embodiment.

[0228] As shown in FIG. 16(A), a pixel of the display device according to the embodiment includes a transistor 85 1, a capacitor element 852 having a function as a holding capacitance of the pixel, a transistor 853, and a light-emitting element 854.

[0229] The gate terminal of the transistor 851 is electrically connected to the scanning line 855, and the first terminal is electrically connected to the signal line 856.

[0230] One terminal of the capacitor element 852 is electrically connected to the second terminal of the transistor 851, ​​​The terminal of the other party is electrically connected to the low power supply potential line.

[0231] The transistor 853 has its gate terminal electrically connected to one of the second terminal of the transistor 851 and the capacitor element 85 2, and its first terminal is electrically connected to the low power supply potential line.

[0232] The light emitting element 854 has its first terminal electrically connected to the second terminal of the transistor 853, and the second terminal is electrically connected to the high power supply potential line.

[0233] When a signal is input to the pixel, first, the pixel for data writing is selected. The selected pixel turns on the transistor 851 by the scanning signal input from the scanning line 855, and a video signal (also called a data signal), which is a voltage of a predetermined value, is input from the signal line 856 to the gate terminal of the transistor 853. The transistor 853 turns on or off according to the potential corresponding to the data signal input to the gate terminal. At this time, a current flows according to the voltage applied between one terminal and the other terminal of the light emitting element 854, and the light emitting element 854 emits light with a luminance corresponding to the amount of the flowing current.

[0234] The transistor 853 turns on or off according to the potential corresponding to the data signal input to the gate terminal. At this time, a current flows according to the voltage applied between one terminal and the other terminal of the light emitting element 854, and the light emitting element 854 emits light with a luminance corresponding to the amount of the flowing current. Also, since the gate voltage of the transistor 853 is held for a certain time by the capacitor element 852, the light emitting element 854 maintains the light emitting state for a certain time. Also, since the gate voltage of the transistor 853 is held for a certain time by the capacitor element 852, the light emitting element 854 maintains the light emitting state for a certain time.

[0235] Also, when the data signal input from the signal line 856 to the pixel is in digital format, the pixel controls the light emitting state by switching the on and off of the transistor. Therefore, gradation display can be performed using the area gradation method or the time gradation method. Note that in the area gradation method, one pixel is divided into a plurality of sub-pixels, and each sub-pixel has the circuit configuration shown in Fig. 16(A) and is independently data controlled. Thus, gradation display can be performed using the area gradation method or the time gradation method. Note that in the area gradation method, one pixel is divided into a plurality of sub-pixels, and each sub-pixel has the circuit configuration shown in Fig. 16(A) and is independently data controlled. Thus, gradation display can be performed using the area gradation method or the time gradation method. Note that in the area gradation method, one pixel is divided into a plurality of sub-pixels, and each sub-pixel has the circuit configuration shown in Fig. 16(A) and is independently data controlled. Each sub-pixel has the circuit configuration shown in Fig. 16(A) and is independently data A driving method for performing gradation display by driving based on a signal. Also, time gradation The method is a driving method for performing gradation display by controlling the period during which a pixel emits light.

[0236] Since the light-emitting element has a higher response speed than a liquid crystal element, etc., it is more suitable for the time gradation method than a liquid crystal element. When performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light emission state of the light-emitting element of the pixel is controlled in each sub-frame period. By dividing one frame period into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light during one frame period can be controlled by the video signal, and gradation can be displayed.

[0237] Next, the configuration of the light-emitting element will be described with reference to FIGS. 16(B) to 16(D). Here a case where the transistor 853 is an n-channel type will be taken as an example to describe the cross-sectional structure of the pixel. Note that the transistor 853 used in the light-emitting display device of FIGS. 16(B) to (D) is a driving transistor.

[0238] For the light-emitting element 854, at least one of the anode or the cathode may be transparent in order to extract light emission. Then, a transistor and a light-emitting element are formed on a substrate, and top emission for extracting light emission from the surface opposite to the substrate, bottom emission for extracting light emission from the surface on the substrate side, or a light-emitting element having a double-sided emission structure for extracting light emission from both the substrate side and the surface opposite to the substrate exist, and the pixel configuration of the present invention can be applied to light-emitting elements of any emission structure.

[0239] The light-emitting element having a top emission structure will be described with reference to FIG. 16(B). ​​​

[0240] Figure 16(B) shows a cross-sectional view of a pixel when the transistor 853, which is a driving transistor, is an n-channel type and the light emitted from the light-emitting element 854 escapes to the anode 7005 side. In Figure 16(B), the cathode 7003 of the light-emitting element 854 and the transistor 853, which is a driving transistor, are electrically connected, and the light-emitting layer 7004 and the anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a small work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter also referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc., and a conductive material having light-transmitting properties may be used.

[0241] The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 854. In the case of the pixel shown in Figure 16(B), the light emitted from the light-emitting element 854 is emitted to the anode 7005 side as indicated by the arrow.

[0242] ​​​​​​​​​​​​Next, the light-emitting element with a bottom emission structure will be described with reference to FIG. 16(C). The transistor 853 is an n-channel type, and the light emitted from the light-emitting element 854 is emitted toward the cathode 7013 side. FIG. 16(C) shows a cross-sectional view of the pixel in this case. In FIG. 16(C), the cathode 7013 of the light-emitting element 854 is formed on the conductive layer 7017 having translucency and electrically connected to the transistor 853. On the conductive layer 7017 having translucency and electrically connected to the transistor 853, the cathode 7013 of the light-emitting element 854 is formed. On the cathode 7013, the light-emitting layer 7014 and the anode 7015 are sequentially laminated. When the anode 7015 has translucency, a shielding layer 7016 for reflecting or shielding light may be formed so as to cover the anode. When the anode 7015 has translucency, a shielding layer 7016 for reflecting or shielding light may be formed so as to cover the anode. Similar to the case of FIG. 16(B), the cathode 7013 can be made of various conductive materials with a small work function. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum layer with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7014, similar to FIG. 16(B), may be composed of a single layer or may be configured such that a plurality of layers are laminated. The anode 7015 does not necessarily need to transmit light but can be formed using a conductive material having translucency, similar to FIG. 16(B). And the light-emitting layer 7014, similar to FIG. 16(B), may be composed of a single layer or may be configured such that a plurality of layers are laminated. The anode 7015 does not necessarily need to transmit light but can be formed using a conductive material having translucency, similar to FIG. 16(B). The shielding layer 7016 can be made of, for example, a metal that reflects light, but is not limited to metals. For example, a resin with a black pigment added can also be used. And the shielding layer 7016 can be made of, for example, a metal that reflects light, but is not limited to metals. For example, a resin with a black pigment added can also be used. For example, a resin with a black pigment added can also be used.

[0243] The region sandwiching the light-emitting layer 7014 between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 854. In the case of the pixel shown in FIG. 16(C), the light emitted from the light-emitting element 854 is emitted toward the cathode 7013 side as indicated by the arrow. In the case of the pixel shown in FIG. 16(C), the light emitted from the light-emitting element 854 is emitted toward the cathode 7013 side as indicated by the arrow.

[0244] Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 16(D). Fig. 16(D ) shows that on a translucent conductive layer 7027 electrically connected to the transistor 853, the cathode 7023 of the light-emitting element 854 is formed, and a light-emitting layer 7024 and an anode 7025 are sequentially laminated on the cathode 7023. Similar to the case of Fig. 16(B), the cathode 7023 can be made of various materials as long as they are conductive materials with a small work function. However, the film thickness should be such that it allows light to pass through. For example, an aluminum layer with a film thickness of 20 nm can be used as the cathode 702 3. And the light-emitting layer 7024, similar to Fig. 16(B), can be either composed of a single layer or configured with multiple layers laminated on each other . The anode 7025, similar to Fig. 16(B), can be formed using a translucent conductive material that allows light to pass through . . . . .

[0245] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 8 54. In the case of the pixel shown in Fig. 16(D), the light emitted from the light-emitting element 854 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0246] Here, although the organic EL element is described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0247] In this embodiment, an example where a transistor (also referred to as a driving transistor) that controls the driving of the light-emitting element is electrically connected to the light-emitting element is shown. However, a configuration in which a current control transistor is connected between the driving transistor and the light-emitting element may also be acceptable. .

[0248] Next, the appearance and cross section of the light-emitting display device (also called a light-emitting panel) in this embodiment will be described. FIG. 17(A) shows a transistor formed on a first substrate. FIG. 1 is a top view of a light-emitting display device in which a capacitor and a light-emitting element are sealed between a second substrate and the capacitor and a light-emitting element by a sealant. FIG. 17B corresponds to a cross-sectional view taken along line HI in FIG. 17A.

[0249] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 450 is provided to surround the gate driver circuits 4503a and 4504b, and the scanning line driver circuits 4504a and 4504b. 5. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. That is, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit The paths 4504a and 4504b are formed by a first substrate 4501, a sealant 4505, and a second substrate 4502. 4506 and the filler 4507 are sealed together. Highly airtight and low outgassing protective film (lamination film, UV curing film) It is preferable to package (enclose) the product in a resin film or a cover material.

[0250] In addition, a pixel portion 4502 and a signal line driver circuit 4503a are provided over a first substrate 4501. , 4503b, and the scanning line driver circuits 4504a, 4504b each have a plurality of transistors. In FIG. 17B, a transistor 4510 included in a pixel portion 4502 and a signal line The transistors 4509 and 4555 included in the driver circuit 4503a are shown as examples. is.

[0251] Transistors 4509, 4510, and 4555 include an oxide semiconductor layer as a semiconductor layer. Any of the transistors shown in Embodiments 2 to 4 with high reliability can be applied. In this embodiment, transistors 4509, 4510, and 4555 are n-channel type. Also, an insulating layer 45 42 is formed over transistors 4509, 4510, and 4555, an insulating layer 4544 is formed over insulating layer 4542, and a conductive layer 4540 is provided over transistor 4509 with insulating layer 4542 and insulating layer 4544 interposed therebetween. Conductive layer 4540 functions as a second gate terminal.

[0252] In the pixel portion 4502, a planarizing insulating layer 4545 is provided over insulating layer 4542, and an insulating layer 4543 is provided over planarizing insulating layer 4545.

[0253] Also, 4511 corresponds to a light-emitting element, and a first electrode 4517, which is a pixel electrode of light-emitting element 4511, is electrically connected to the second terminal of transistor 4510. Note that the structure of light-emitting element 4511 has a stacked structure of a first electrode 4517, a light-emitting layer 4512, and a second electrode 4513, but is not limited to the structure shown in this embodiment. The structure of light-emitting element 4511 can be appropriately changed according to the direction of light emitted from light-emitting element 4511 and the like.

[0254] Partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferably formed using a photosensitive material to form an opening over first electrode 4517 such that the sidewalls of the opening become inclined surfaces formed with a continuous curvature.

[0255] The light-emitting layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are stacked. Either is acceptable.

[0256] A protective layer may be formed on the second electrode 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer (Diamond like Carbon), etc. can be formed.

[0257] Also, various signals and voltages applied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504 b, or the pixel portion 4502 are supplied from the FPCs 4518a and 451 8b.

[0258] In the light-emitting display device shown in FIG. 17, the connection terminal electrode 4515 is formed of the same conductive film as the conductive film on which the first electrode 4517 of the light-emitting element 4511 is formed, and the terminal electrode 4516 is formed of the same conductive film as the conductive film on which the conductive layer that functions as the source electrode and the drain electrode of the transistors 4509, 4510, and 4555 is formed.

[0259] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via the anisotropic conductive layer 4519.

[0260] The substrate located in the light extraction direction from the light-emitting element 4511 needs to have translucency. In that case, as the substrate, a translucent material such as glass, plastic, a polyester film, or an acrylic film is used.

[0261] In addition, as the filler 4507, in addition to inert gases such as nitrogen and argon, ultraviolet curable resin or thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler 450 .

[0262] Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate ), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. can be appropriately provided . Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, the unevenness of the surface diffuses the reflected light, and an antiglare treatment that can reduce the reflection can be performed.

[0263] As the signal line drive circuits 4503a and 4503b and the scan line drive circuits 4504a and 4504b , a drive circuit formed using a single crystal semiconductor layer or a polycrystalline semiconductor layer on a separately prepared substrate may be mounted. Also, only the signal line drive circuits 4503a and 4503b, or a part thereof, or only the scan line drive circuits 4504a and 4504b, or only a part thereof may be separately formed and mounted, and this embodiment is not limited to the configuration of FIG. 17.

[0264] Through the above steps, a light-emitting display device (display panel) can be manufactured.

[0265] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content.

[0266] (Embodiment 8) In this embodiment, as an example of the display device shown in Embodiment 5, an electronic paper capable of displaying without requiring external continuous wiring such as an FPC will be described with reference to FIGS. 18 and 19.

[0267] Note that the electronic paper of this embodiment has an image holding period (period during which an image is held) and an image rewriting period (period during which an image is rewritten). Also, during the image holding period, no power is required to maintain the image display. Therefore, the electronic paper is a display device with low power consumption.

[0268] The electronic paper has, as a display element, an element that can control display by applying a voltage and hold the display in a state where no voltage is applied. For example, as such an element, there are an element using electrophoresis (electrophoretic element), a particle rotation element using a twisted ball, a particle movement element using a charged toner or electronic ink (registered trademark), a magnetophoretic element expressing gradation by magnetism, a liquid movement element, a light scattering element, a phase change element, and the like. In this embodiment, as an example of the electronic paper, an electronic paper having an electrophoretic element will be described.

[0269] Examples of the electrophoretic element include an element having microcapsules encapsulating a first particle charged with a positive charge, a second particle having a color different from that of the first particle and charged with a negative charge, and a liquid serving as a solvent. When a voltage is applied to the electrophoretic element, display can be performed by aggregating the first particle or the second particle on one side of the microcapsule. Note that in a state where no voltage is applied to the electrophoretic display element, the first particle ​​​​​​​​​​​​​​The first particles and the second particles do not move. In other words, the display of the electrophoretic element is maintained. The electrophoretic element is made up of positively or negatively charged particles and a liquid crystal display that exhibits a different color from the particles and dissolves the charged particles. It is also possible to use an element having a microcapsule in which a liquid medium is enclosed.

[0270] The positively or negatively charged particles enclosed in the microcapsules are conductive. Materials for electrodes, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescence A material selected from the group consisting of photoluminescent materials, electrochromic materials, and magnetophoretic materials, A composite material of these may be used.

[0271] Next, a structural example of electronic paper in this embodiment will be described with reference to FIG. FIG. 18(A) is a circuit diagram of a pixel of an electronic paper, and FIG. 18(B) is a circuit diagram of the pixel. 18(C) is a cross-sectional view taken along line AB in FIG. 18(B).

[0272] In the electronic paper pixel of this embodiment, the gate terminal is electrically connected to the scanning line 630, A transistor 601 having a first terminal electrically connected to a signal line 631 and a transistor The second terminal of the transistor 601 is electrically connected to the second terminal of the transistor 601, and the other terminal is electrically connected to the common potential line. A capacitor 602 connected to the second terminal of the transistor 601 and a capacitor 60 2 and the other terminal is electrically connected to a common potential line. In this embodiment, the common electrode Place (V com ) can be ground potential or 0V.

[0273] The pixel has a structure including a substrate 600 and a transistor 6 601 and a capacitor 602, and an electric field provided on the transistor 601 and the capacitor 602. The electrophoretic device has an electrophoretic element 603 and a substrate 604 provided on the electrophoretic element 603 (FIG. 18( 18B) and (C). Note that the electrophoretic element 603 is omitted in FIG.

[0274] The transistor 601 includes a conductive layer 610 electrically connected to a scan line 630 and a conductive layer 6 10, an insulating layer 611 on the insulating layer 611, a semiconductor layer 612 on the semiconductor layer 612, and a signal The conductive layer 613 and the conductive layer 614 are electrically connected to the line 631. The conductive layer 610 functions as a gate terminal, and the insulating layer 611 functions as a gate insulating layer. The conductive layer 613 functions as a first terminal, and the conductive layer 614 functions as a second terminal. The conductive layer 610 is a part of the scanning line 630, and the conductive layer 613 is a part of the signal line 631. It can also be expressed as being.

[0275] The capacitor 602 is electrically connected to a conductive layer 614, an insulating layer 611, and a common potential line 632. The conductive layer 614 functions as one terminal. 6, with insulating layer 611 acting as a dielectric and conductive layer 615 acting as the other terminal. The conductive layer 615 can also be expressed as a part of the common potential line 632 .

[0276] The electrophoretic element 603 is electrically connected to the conductive layer 614 through an opening provided in the insulating layer 620. A pixel electrode 616 is electrically connected to the conductive layer 615, and a counter electrode 617 is applied with the same potential as the conductive layer 615. and a layer 618 containing charged particles provided between the pixel electrode 616 and the counter electrode 617. It is configured as follows. The pixel electrode 616 functions as one terminal, and the counter electrode 617 functions as the other terminal.

[0277] The electronic paper of the present embodiment controls the voltage applied to the layer 618 containing charged particles to control the movement of the charged particles dispersed in the layer 618 containing charged particles. In addition, the electronic paper of the present embodiment has the counter electrode 617 and the substrate 604 with translucency. That is, the display device of the present embodiment is a reflective display device with the substrate 604 side as the display surface.

[0278] Hereinafter, materials applicable to each component of the electronic paper of the present embodiment will be listed.

[0279] Examples of the substrate 600 include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate , a glass substrate, a quartz substrate, a conductive substrate provided with an insulating layer on the surface, or a flexible substrate such as a plastic substrate , a laminated film, paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic.

[0280] Examples of the conductive layer 610, the conductive layer 615, the scanning line 630, and the common potential line 632 include aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). selected from​​​ The exposed element, an alloy containing the above-described element as a component, or a nitride containing the above-described element as a component can be applied. Also, a laminated structure of these materials can be applied.

[0281] As the insulating layer 611, an insulator such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, tantalum oxide, etc. can be applied. Also, a laminated structure of these materials can be applied. Note that silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and in the concentration range of oxygen being 55 - 65 atomic %, nitrogen being 1 - 20 atomic %, silicon being 25 - 35 atomic %, and hydrogen being 0.1 - 10 atomic %, with each element contained at an arbitrary concentration so as to total 100 atomic %. Also, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition, and in the concentration range of oxygen being 15 - 30 atomic %, nitrogen being 20 - 35 atomic %, Si being 25 - 35 atomic %, and hydrogen being 15 - 25 atomic %, with each element contained at an arbitrary concentration so as to total 100 atomic %.

[0282] As the semiconductor layer 612, a material mainly composed of a Group 14 element of the periodic table such as silicon (Si) or germanium (Ge), a compound such as silicon germanium (SiGe) or gallium arsenide (GaAs), an oxide such as zinc oxide (ZnO) or zinc oxide containing indium (In) and gallium (Ga), or an organic compound exhibiting semiconductor characteristics can be applied. Also, a laminated structure of layers made of these semiconductor materials can be applied.

[0283] As the conductive layer 613, the conductive layer 614, and the signal line 631, aluminum (Al), copper ( Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo) , an element selected from chromium (Cr), neodymium (Nd), scandium (Sc), or an alloy containing the above-described elements as components, or a nitride containing the above-described elements as components can be applied. Also, a laminated structure of these materials can be applied.

[0284] As the insulating layer 620, silicon oxide, silicon oxynitride, silicon nitride, or an insulator such as silicon oxynitride, aluminum oxide, tantalum oxide can be applied. In addition, organic materials such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic or epoxy, siloxane materials such as siloxane resin, or oxazole resin can also be applied. Here, the siloxane material corresponds to a material containing an Si-O-Si bond. Siloxane has a skeletal structure composed of a bond between silicon (Si) and oxygen (O). As substituents, an organic group (for example, an alkyl group, an aromatic hydrocarbon) or a fluoro group may be used. The organic group may have a fluoro group.

[0285] As the pixel electrode 616, aluminum (Al), copper (Cu), titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium ( Nd), an element selected from scandium (Sc), or an alloy containing the above-described elements as components , or a nitride containing the above-described elements as components can be applied. Also, a laminated structure of these materials can be applied. ​, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, a light-transmissive conductive material such as indium tin oxide added with silicon oxide can be applied. It can also be used.

[0286] As the charged particles contained in the layer 618 containing charged particles, titanium oxide can be applied as positively charged particles, and carbon black can be applied as negatively charged particles. Further, a conductive material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, a material selected from these, or a composite material thereof can also be applied. It can also be used. It can also be used.

[0287] As the counter electrode 617, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, a light-transmissive conductive material such as indium tin oxide added with silicon oxide can be applied. It can also be used. It can also be used.

[0288] As the substrate 604, a glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or soda lime glass, or a light-transmissive substrate typified by a flexible substrate such as polyethylene terephthalate (PET) can be applied. It can also be used. It can also be used.

[0289] Note that the electronic paper of this embodiment can be used in electronic devices in any field as long as it can display information. For example, using the electronic paper, an electronic book (e-book) can be made. , posters, in-vehicle advertisements on vehicles such as trains, and on various cards such as credit cards It can be applied to displays and the like. An example of an electronic device is shown in FIG. 19. FIG. 19 shows an example of the e-book 2700.

[0290] As shown in FIG. 19, the e-book 2700 is composed of two housings, namely, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711 and can perform an opening and closing operation about the shaft portion 2711 as an axis. With such a configuration, it becomes possible to perform operations similar to those of a paper book.

[0291] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display consecutive screens, or may be configured to display different screens. By adopting a configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 19), and an image can be displayed on the left display unit (display unit 2707 in FIG. 19).

[0292] Also, in FIG. 19, an example is shown in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2701, a power switch 2721, operation keys 2723, a speaker 2725, and the like are provided. The page can be turned by the operation keys 2723. In addition, the housing may be configured to be provided with a keyboard, a pointing device, or the like on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like are provided. It may also be configured to include. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. It may also be configured.

[0293] Also, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By wireless means, it is also possible to purchase and download desired book data, etc. from an electronic book server. It is also possible.

[0294] Note that the content of this embodiment or a part of the content can be combined with the content of other embodiments or a part of the content. It is possible to combine.

[0295] (Embodiment 9) The display device shown in the above-described Embodiments 5 to 8 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large gaming machine such as a pachinko machine, etc. a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large gaming machine such as a pachinko machine, etc. a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large gaming machine such as a pachinko machine, etc. a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large gaming machine such as a pachinko machine, etc. a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large gaming machine such as a pachinko machine, etc.

[0296] FIG. 20(A) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display video. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. It is shown.

[0297] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or by a separate remote control operation unit 9610. The operation keys provided in the remote control operation unit 9610 can be used to perform operations. -9609 can be used to operate channels and volume, and the video displayed on the display unit 9603 can be operated. Further, the remote control operation unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control operation unit 9610.

[0298] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a wired or wireless connection through the modem, one-way (from the sender to the receiver) or two-way information communication (between the sender and the receiver, or between the receivers, etc.) can also be performed.

[0299] Figure 20(B) shows an example of a digital photo frame. For example, in the digital photo frame 9700, a display unit 9703 is incorporated in a housing 9701. The display unit 97 03 can display various images, and by displaying image data taken with, for example, a digital camera, it can function in the same way as a normal photo stand.

[0300] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface to improve the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion unit of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703. ​​​​​​​​​​​

[0301] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It is also possible to configure it to capture and display desired image data wirelessly.

[0302] FIG. 21(A) shows a portable gaming machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected in an openable and closable manner by a connecting portion 9893. A display unit 9882 is incorporated in the casing 9881, and a display unit 9883 is incorporated in the casing 9891. Also, the portable gaming machine shown in FIG. 21(A) further includes a speaker 9884, a recording medium insertion portion 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration having at least a display device, and other accessory equipment may be appropriately provided. The portable gaming machine shown in FIG. 21(A) has a function of reading a program or data recorded on a recording medium and displaying it on the display unit, and a function of performing wireless communication with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in FIG. 21(A) are not limited to this, and it can have various functions.

[0303] FIG. 21(B) shows an example of a slot machine, which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a casing 9901. Also, the slot machine The 9900 also includes operating means such as a start lever and a stop switch, a coin insertion slot , a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be configured to include at least the display device shown in the above embodiment, and other accessory equipment can be appropriately provided.

[0304] FIG. 22(A) shows an example of a mobile phone. The mobile phone 9000 includes, in addition to a display unit 9002 incorporated in a housing 900 1, operation buttons 9003, an external connection port 9004, a speaker 9005, a microphone 9006, etc.

[0305] For the mobile phone 9000 shown in FIG. 22(A), information can be input by touching the display unit 9002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 9002 with a finger or the like.

[0306] The screen of the display unit 9002 mainly has three modes. The first mode is a display mode mainly for displaying images, and the second mode is an input mode mainly for inputting information such as characters. The third mode is a display + input mode in which the two modes of the display mode and the input mode are mixed.

[0307] For example, when making a call or creating an email, the display unit 9002 can be set to a character input mode mainly for character input, and an input operation of the characters displayed on the screen can be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 9002.

[0308] In addition, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 9000, the orientation (portrait or landscape) of the mobile phone 9000 can be determined, and the screen display of the display unit 9002 can be automatically switched.

[0309] Also, the switching of the screen mode is performed by touching the display unit 9002 or operating the operation button 9003 of the housing 9001. Also, it can be switched according to the type of image displayed on the display unit 9002. For example, if the image signal displayed on the display unit 9002 is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0310] Also, in the input mode, the signal detected by the light sensor of the display unit 9002 is detected, and when there is no input by the touch operation of the display unit 9002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0311] The display unit 9002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 9002 and imaging the palm print, fingerprint, etc., personal authentication can be performed. Also, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, finger vein, palm vein, etc. can also be imaged.

[0312] Figure 22(B) is also an example of a mobile phone. The mobile phone in Figure 22(B) includes a display device 9410 including a display unit 9412 and an operation button 9413 on the housing 9411, and an operation button 9402, an external input terminal 9403, a microphone 9404, and a speaker 94 on the housing 9401. 05, and a communication device 9400 including a light emitting unit 9406 that emits light upon incoming calls, and a display device 9410 having a display function is detachable from the communication device 9400 having a telephone function in two directions of the arrow. Therefore, the short axes of the display device 9410 and the communication device 9400 can be attached to each other, or the long axes of the display device 9410 and the communication device 9400 can be attached to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange image or input information by wireless communication or wired communication, and each has a rechargeable battery. The display device 9410 having a display function is detachable from the communication device 9400 having a telephone function in two directions of the arrow. Therefore, the short axes of the display device 9410 and the communication device 9400 can be attached to each other, or the long axes of the display device 9410 and the communication device 9400 can be attached to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange image or input information by wireless communication or wired communication, and each has a rechargeable battery.

[0313] Note that the content of this embodiment or a part of the content can be combined with the content of other embodiments or a part of the content.

Explanation of Reference Numerals

[0314] 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 111 Transistor for clock signal selection 112 Transistor for clock signal selection 113 Transistor for clock signal selection 114 Transistor for clock signal selection 115 Transistor for clock signal selection 116 Transistor for clock signal selection 121 Transistor for low power supply potential selection 122 Transistor for low power supply potential selection 123 Transistor for low power supply potential selection ​124 Transistor for low power supply potential selection 125 Transistor for low power supply potential selection 126 Transistor for low power supply potential selection 131 Transistor 132 Transistor 133 Transistor 134 Transistor 201 Substrate 202 Insulating layer 207 Oxide insulating layer 211 Conductive layer 213 Oxide semiconductor layer 214a Oxide conductive layer 214b Oxide conductive layer 215a Conductive layer 215b Conductive layer 215c Conductive layer 217 Conductive layer 233a Resist mask 233b Resist mask 251 Transistor 252 Transistor 600 Substrate 601 Transistor 602 Capacitor element 603 Electrophoretic element 604 Substrate 610 Conductive layer 611 Insulating layer 612 Semiconductor layer 613 Conductive layer 614 Conductive layer 615 Conductive layer 616 Pixel electrode 617 Counter electrode 618 Layer containing charged particles 620 Insulating layer 630 Scanning line 631 Signal line 632 Common potential line 701 Pixel section 702 Scanning line drive circuit 703 Signal line drive circuit 704 Pixel 705 Scanning line 706 Signal line 804 Scanning line 805 Signal line 821 Transistor 822 Liquid crystal element 823 Capacitive element 851 Transistor 852 Capacitive element 853 Transistor 854 Light-emitting element 855 Scanning line 856 Signal line 900 Shift register 901 Level shifter 902 Buffer 903 Shift register 904 Latch circuit 905 Latch circuit 906 Level shifter 907 Buffer 2000 Substrate 2001 Conductive layer 2002 Insulating layer 2003 Oxide semiconductor layer 2005a Conductive layer 2005b Conductive layer 2007 Oxide insulating layer 2008 Conductive layer 2020 Transparent conductive layer 2022 Conductive layer 2023 Conductive layer 2024 Conductive layer 2028 Transparent conductive layer 2029 Transparent conductive layer 2112 Conductive layer 2132 Oxide semiconductor layer 2142a Oxide conductive layer 2142b Oxide conductive layer 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft portion 2721 Power switch 2723 Operation key 2725 Speaker 4501 Substrate 4502 Pixel section 4503a Signal line drive circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light-emitting element 4512 Light-emitting layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Partition wall 4540 Conductive layer 4542 Insulating layer 4543 Insulating layer 4544 Insulating layer 4545 Planarizing insulating layer 4555 Transistor 7003 Cathode 7004 Light-emitting layer 7005 Anode 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding layer 7017 Conductive layer 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 9000 Mobile phone 9001 Housing 9002 Display section 9003 Operation button 9004 External connection port 9005 Speaker 9006 Microphone 9400 Communication device 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting part 9410 Display device 9411 Housing 9412 Display part 9413 Operation button 9600 Television device 9601 Housing 9603 Display part 9605 Stand 9607 Display part 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display part 9881 Housing 9882 Display part 9883 Display part 9884 Speaker 9885 Operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display part

Claims

1. a first conductive film having a region disposed on an insulating surface; a second conductive film having a region disposed on the insulating surface; a first silicon nitride film having a region disposed on the first conductive film and a region disposed on the second conductive film; a first oxide semiconductor film having a region disposed on the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film having a region disposed on the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film electrically connected to the first oxide semiconductor film and electrically connected to the second oxide semiconductor film; a fourth conductive film electrically connected to the first oxide semiconductor film; a fifth conductive film electrically connected to the second oxide semiconductor film; an oxide insulating film having a region disposed over the first oxide semiconductor film, a region disposed over the second oxide semiconductor film, a region disposed over the third conductive film, a region disposed over the fourth conductive film, and a region disposed over the fifth conductive film; a second silicon nitride film having a region disposed on the oxide insulating film; having the first conductive film functions as a gate of a first transistor; the second conductive film functions as a gate of a second transistor; the third conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the third conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the fourth conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the third conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as one of a source and a drain of the second transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor, the fifth conductive film functions as the other of the source and the drain of the second transistor, the third conductive film is electrically connected to the first conductive film through an opening in the first silicon nitride film; the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are separated from each other, a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level; Semiconductor device.

2. a first conductive film having a region disposed on an insulating surface; a second conductive film having a region disposed on the insulating surface; a first silicon nitride film having a region disposed on the first conductive film and a region disposed on the second conductive film; a first oxide semiconductor film having a region disposed on the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film having a region disposed on the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film electrically connected to the first oxide semiconductor film and electrically connected to the second oxide semiconductor film; a fourth conductive film electrically connected to the first oxide semiconductor film; a fifth conductive film electrically connected to the second oxide semiconductor film; an oxide insulating film having a region disposed over the first oxide semiconductor film, a region disposed over the second oxide semiconductor film, a region disposed over the third conductive film, a region disposed over the fourth conductive film, and a region disposed over the fifth conductive film; a second silicon nitride film having a region disposed on the oxide insulating film; having the first conductive film functions as a gate of a first transistor; the second conductive film functions as a gate of a second transistor; the third conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the third conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the fourth conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the third conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as one of a source and a drain of the second transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor, the fifth conductive film functions as the other of the source and the drain of the second transistor, the third conductive film is electrically connected to the first conductive film through an opening in the first silicon nitride film; the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first oxide semiconductor film contains In, Ga, and Zn; the second oxide semiconductor film contains In, Ga, and Zn, the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are separated from each other, a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level; Semiconductor device.

3. a first conductive film having a region disposed on an insulating surface; a second conductive film having a region disposed on the insulating surface; a first silicon nitride film having a region disposed on the first conductive film and a region disposed on the second conductive film; a first oxide semiconductor film having a region disposed on the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film having a region disposed on the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film electrically connected to the first oxide semiconductor film and electrically connected to the second oxide semiconductor film; a fourth conductive film electrically connected to the first oxide semiconductor film; a fifth conductive film electrically connected to the second oxide semiconductor film; an oxide insulating film having a region disposed over the first oxide semiconductor film, a region disposed over the second oxide semiconductor film, a region disposed over the third conductive film, a region disposed over the fourth conductive film, and a region disposed over the fifth conductive film; a second silicon nitride film having a region disposed on the oxide insulating film; having the first conductive film functions as a gate of a first transistor; the second conductive film functions as a gate of a second transistor; the third conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the third conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the fourth conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the third conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as one of a source and a drain of the second transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor, the fifth conductive film functions as the other of the source and the drain of the second transistor, the third conductive film is electrically connected to the first conductive film through an opening in the first silicon nitride film; the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are separated from each other, a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level; a power supply potential is applied to the fifth conductive film; Semiconductor device.

4. a first conductive film having a region disposed on an insulating surface; a second conductive film having a region disposed on the insulating surface; a first silicon nitride film having a region disposed on the first conductive film and a region disposed on the second conductive film; a first oxide semiconductor film having a region disposed on the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film having a region disposed on the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film electrically connected to the first oxide semiconductor film and electrically connected to the second oxide semiconductor film; a fourth conductive film electrically connected to the first oxide semiconductor film; a fifth conductive film electrically connected to the second oxide semiconductor film; an oxide insulating film having a region disposed over the first oxide semiconductor film, a region disposed over the second oxide semiconductor film, a region disposed over the third conductive film, a region disposed over the fourth conductive film, and a region disposed over the fifth conductive film; a second silicon nitride film having a region disposed on the oxide insulating film; having the first conductive film functions as a gate of a first transistor; the second conductive film functions as a gate of a second transistor; the third conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the third conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the fourth conductive film has a region in contact with an upper surface and a side surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface and a side surface of the second oxide semiconductor film, the third conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as one of a source and a drain of the second transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor, the fifth conductive film functions as the other of the source and the drain of the second transistor, the third conductive film is electrically connected to the first conductive film through an opening in the first silicon nitride film; the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first oxide semiconductor film contains In, Ga, and Zn; the second oxide semiconductor film contains In, Ga, and Zn, the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are separated from each other, a period during which the potential of the fourth conductive film is at a high level and a period during which the potential of the fourth conductive film is at a low level; a power supply potential is applied to the fifth conductive film; Semiconductor device.

Images