Self-aligned wide backside power rail contacts to multiple transistor sources

Abstract

A semiconductor device and method for its manufacture are described. The method includes front-side processing to form deep source / drain cavities and filling the cavities with a sacrificial material. The sacrificial material is then removed during back-side processing to form back-side power rail vias filled with a metal fill.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More particularly, embodiments of the present disclosure are directed to power rail architecture, 3D packaging, and methods of manufacturing semiconductor devices.

Background Art

[0002]

[0002] The semiconductor processing industry continues to strive for greater production yields while increasing the uniformity of layers deposited on substrates having larger surface areas. The combination of these same elements with new materials also improves the integration of circuits per unit area of the substrate. As circuit integration improves, the need for higher uniformity and process control with respect to layer thickness increases. As a result, various techniques have been developed for depositing layers on substrates in a cost-effective manner while maintaining control of the layer characteristics.

[0003]

[0003] Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, patterning the various material layers using lithography, and forming circuit components and elements thereon. The conductive layer facilitates electrical wiring to various electrical components including transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors, inductors, resistors, and the like.

[0004]

[0004] Transistors are important components of most integrated circuits. Since the drive current of a transistor, and thus its speed, is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Therefore, there is a trade-off between the size and speed of transistors, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the transistor size without significantly increasing the installation area of the transistor, and are currently applied to many integrated circuits. However, finFETs also have drawbacks.

[0005]

[0005] To achieve improved circuit density and high performance, the feature size of transistor devices has been continuously reduced. Therefore, it is necessary to improve the electrostatic coupling and optimize the structure of transistor devices to reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, horizontal gate all-around (hGAA) structures, etc. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure provides good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0006]

[0006] Connecting a semiconductor to a power rail is usually done at the front of the cell, but this requires a large cell area. Therefore, there is a need for semiconductor devices that are connected to the power rail using less cell area.

Summary of the Invention

[0007]

[0007] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes forming a superlattice structure on an upper surface of a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately such that the superlattice structure is a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material within the source cavity and within the drain cavity; forming a source region and a drain region; forming CT and CG in electrical contact with the source region and the drain region; forming a damascene trench through the substrate; at least partially removing the sacrificial material to form at least one opening extending to the damascene trench; and depositing a metal within the at least one opening and within the damascene trench.

[0008]

[0008] Additional embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes forming a superlattice structure on an upper surface of a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately such that the superlattice structure is a plurality of stacked pairs; forming a gate structure on an upper surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material within the source cavity and the drain cavity; forming an inner spacer layer on each of the plurality of horizontal channel layers; forming a source region and a drain region; forming an interlayer dielectric layer on the substrate; forming a replacement metal gate; forming CT and CG in electrical contact with the source region and the drain region; forming a first metal line; rotating the semiconductor device 180 degrees; planarizing the substrate; depositing an interlayer dielectric material on the substrate; forming a backside power rail via in the substrate; expanding the backside power rail via to form a damascene trench; removing the sacrificial material to form at least one opening; and depositing a metal within the at least one opening and within the damascene trench.

[0009]

[0009] To understand the features of the present disclosure in detail, a more specific description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that since the present disclosure may admit other equally effective embodiments, the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure.

Brief Description of the Drawings

[0010]

Figure 1A

Figure 1B

[0011] Continuation of the process flow diagram of FIG. 1A showing a method according to one or more embodiments.

Figure 2A

[0012] Cross-sectional view of a device according to one or more embodiments.

Figure 2B

[0013] Cross-sectional view of a device according to one or more embodiments.

Figure 2C

[0014] Cross-sectional view of a device according to one or more embodiments.

Figure 2D

[0015] Cross-sectional view of a device according to one or more embodiments.

Figure 2E

[0016] Cross-sectional view of a device according to one or more embodiments.

Figure 2F

[0017] Cross-sectional view of a device according to one or more embodiments.

Figure 2G

[0018] Cross-sectional view of a device according to one or more embodiments.

Figure 2H

[0019] Cross-sectional view of a device according to one or more embodiments.

Figure 2I

[0020] Cross-sectional view of a device according to one or more embodiments.

Figure 2J

[0021] Cross-sectional view of a device according to one or more embodiments.

Figure 2K

[0022] Cross-sectional view of a device according to one or more embodiments.

Figure 2L

[0023] Cross-sectional view of a device according to one or more embodiments.

Figure 2M

[0024] Cross-sectional view of a device according to one or more embodiments.

Figure 2N

[0025] Cross-sectional view of a device according to one or more embodiments.

Figure 2O

[0026] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2P

[0027] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2Q

[0028] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2R

[0029] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2S

[0030] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2T

[0031] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 2U

[0032] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 3

[0033] Shows a process flow diagram of a method according to one or more embodiments.

Figure 4A

[0034] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 4B

[0035] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 4C

[0036] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 4D

[0037] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 4E

[0038] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 5A

[0039] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 5B

[0040] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 5C

[0041] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 5D

[0042] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 6

[0043] Shows a process flow diagram of a method according to one or more embodiments.

Figure 7A

[0044] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 7B

[0045] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 7C

[0046] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 7D

[0047] Shows a cross-sectional view of a device according to one or more embodiments.

Figure 8

[0048] Shows a cluster tool according to one or more embodiments.

Best Mode for Carrying Out the Invention

[0011]

[0049] For ease of understanding, where possible, the same reference numbers are used to denote the same elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation.

[0012]

[0050] Before describing some exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0051] As used in this specification and the appended claims, the term "substrate" refers to the surface or a portion of the surface on which processing acts. It will be understood by those skilled in the art that, unless the context clearly indicates otherwise, a reference to a substrate may also refer to only a portion of the substrate. Further, a reference to deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed on the surface.

[0014]

[0052] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pre-treatment processes for polishing, etching, reducing, oxidizing, hydroxylation (or otherwise generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed in an underlying layer formed on the substrate, as will be disclosed in more detail below. And the term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface includes depends on what films are deposited and the specific chemistry used.

[0015]

[0053] As used in this specification and the appended claims, terms such as "precursor", "reactant", "reactive gas" are used interchangeably and refer to any gas species that can react with the substrate surface.

[0016]

[0054] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines or other elements, transistors are formed on the semiconductor device. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located over the channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0017]

[0055] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by an electric field within the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G) that adjusts the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and the source is denoted as VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0018]

[0056] A metal-oxide semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage on the insulated gate determines the conductivity of the device. This ability to vary the conductivity according to the amount of voltage applied is used to amplify or switch electronic signals. The MOSFET is based on the modulation of the charge concentration by a metal-oxide semiconductor (MOS) capacitor between the body electrode and the gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared with a MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to an individual highly doped region separated by the body region. These regions can be either p-type or n-type, but both are of the same type and of the opposite type to the body region. The source and drain are (unlike the body) highly doped, and a "+" symbol is attached after the type of doping.

[0019]

[0057] When the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p region. When the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n region. The source is the source of the charge carriers flowing through the channel (electrons in the case of an n-channel and holes in the case of a p-channel), and similarly, the drain is where the charge carriers exit the channel, so it is named as such.

[0020]

[0058] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate where the gate is disposed on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are so named because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0021]

[0059] As used herein, the term "gate all around (GAA)" is used to refer to an electronic device such as a transistor in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include a nanowire or a nanoslab or a nanosheet, a rod-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of horizontally spaced vertical nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0022]

[0060] As used herein, the term "nanowire" refers to a nanostructure having a diameter on the order of 1 nanometer (10 -9 meters). A nanowire can also be defined as having a length-to-width ratio exceeding 1000. Alternatively, a nanowire can be defined as a structure in which the thickness or diameter is restricted to tens of nanometers or less and the length is not restricted. Nanowires are used in transistors and some laser applications and, in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in the range of about 0.1 nm to about 1000 nm.

[0023]

[0061] Embodiments of the present disclosure are illustrated by figures showing devices (e.g., transistors) according to one or more embodiments of the present disclosure and processes for forming the transistors. The processes illustrated are merely examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0024]

[0062] Referring to the figures, one or more embodiments of the present disclosure will be described. In the method of one or more embodiments, transistors, such as gate-all-around transistors, are fabricated using a standard process flow. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, such as epitaxial silicon, is deposited. Thereafter, the wafer undergoes device and front-end processing. After front-end processing, the wafer is hybrid bonded, for example, bonded to copper or oxide, and then the wafer is advantageously thinned. Thinning the wafer provides the desired flatness and bonding to realize a backside power rail. To thin the wafer, a silicon substrate layer having an initial first thickness is polished to a second thickness smaller than the first thickness. After polishing, in some embodiments, the silicon wafer is subjected to chemical mechanical planarization (CMP), and then etching and CMP buffing are performed to reduce the thickness of the silicon to a third thickness smaller than the second thickness. In one or more embodiments, the etching stops at the buried etch stop layer. Thereafter, the contacts are pre-filled with metal and metallization is performed.

[0025]

[0063] In alternative embodiments, transistors, such as gate-all-around transistors, are manufactured using a standard process flow. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, such as epitaxial silicon, is deposited. Thereafter, the wafer undergoes device and front-end processing. After front-end processing, the wafer is hybrid bonded, for example to copper or oxide, and then the wafer is advantageously thinned. Thinning the wafer provides the desired flatness and bonding to implement a backside power rail. To thin the wafer, a silicon substrate layer having an initial first thickness is polished down to a second thickness that is less than the first thickness. After polishing, a large mask is deposited and vias are formed within the mask. The wafer is then etched through the vias to the buried etch stop layer, after which the etch stop layer is selectively removed and liftoff is performed.

[0026]

[0064] In the method of one or more embodiments, transistors, such as gate-all-around transistors, are manufactured using a standard process flow. After the source / drain cavities are recessed, the dimensions of the source / drain cavities are expanded and a sacrificial filler is deposited. The manufacturing continues with internal spacer formation, source / drain epitaxy, interlayer dielectric formation, replacement gate formation, CT and CG formation, and front-side metal line formation. Thereafter, the substrate is inverted and planarized. An interlayer dielectric is deposited on the backside, backside power rail vias are patterned, and the interlayer dielectric is etched. Damascene trenches are formed and the sacrificial fill is removed to form openings. Metal is deposited in the openings to form backside metal lines. In one or more embodiments, the sacrificial filler is advantageously selective such that self-aligned trenches and / or vias are formed during etching, thus avoiding misalignment.

[0027]

[0065] In the method of one or more embodiments, transistors, such as gate-all-around transistors, are manufactured using a standard process flow. Deep vias are etched with a separate mask or etched with a normal contact or via mask. After etching the normal vias, a mask is placed and the power rail vias are etched down to a depth under the device to facilitate backside connection. The standard and deep vias / contacts are simultaneously filled with titanium nitride / tungsten (TiN / W) or titanium nitride / ruthenium (TiN / Ru) or molybdenum (Mo) contact fill and then planarized. The wafer may optionally be thinner. On the backside, vias are etched to connect to the deep vias. Thereafter, metallization is performed.

[0028]

[0066] FIG. 1A shows a process flow diagram for a method 6 for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 1B shows a continuation of the process flow diagram of FIG. 1A showing method 6 according to one or more embodiments. FIGS. 2A-2U show the manufacturing stages of a semiconductor structure according to some embodiments of the present disclosure. Method 6 is described below with respect to FIGS. 2A-2U. FIGS. 2A-2U are cross-sectional views of an electronic device (e.g., GAA) according to one or more embodiments. Method 6 can be part of a multi-step manufacturing process of a semiconductor device. Thus, method 6 can be executed in any suitable process chamber connected to a cluster tool. The cluster tool can include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the manufacture of semiconductor devices.

[0029]

[0067] Figures 2A - 2U are the manufacturing steps of steps 8 - 54 in Figures 1A - 1B. Referring to Figure 1A, method 6 for forming device 100 starts by providing substrate 102 in step 8. In some embodiments, substrate 102 can be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate whose entire body is made of semiconductor material. The bulk semiconductor substrate can include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can include one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, semiconductor substrate 102 includes a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials for forming the substrate are described, any material that can function as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) is included within the spirit and scope of the present disclosure.

[0030]

[0068] In some embodiments, the semiconductor material can be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during manufacture. The term n-type is derived from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge (or holes) in the well. In contrast to an n-type semiconductor, a p-type semiconductor has a hole concentration greater than the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0031]

[0069] Referring to FIG. 1A, in some non-illustrated embodiments, in step 10, an etch stop layer can be formed on the upper surface of the substrate. The etch stop layer can include any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer includes silicon germanium (SiGe). In one or more embodiments, the etch stop layer has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without wishing to be bound by theory, it is believed that having a germanium content in the range of 30% to 50% increases the selectivity of the etch stop layer and minimizes stress defects. In one or more embodiments, the etch stop layer has a thickness in the range of 5 nm to 30 nm. The etch stop layer can function as an etch stop for planarization (e.g., CMP), dry or wet etching during backside processing.

[0032]

[0070] In one or more embodiments not shown, in step 12, an epitaxial layer, such as epitaxial silicon, may be deposited on the etch stop layer. The epitaxial layer may have a thickness in the range of 20 nm to 100 nm.

[0033]

[0071] Referring to FIGS. 1A and 2A, in one or more embodiments, in step 14, at least one superlattice structure 101 is formed on the upper surface of the substrate 102, or on the upper surfaces of the etch stop layer and the epitaxial layer. The superlattice structure 101 includes a plurality of semiconductor material layers 106 and a corresponding plurality of horizontal channel layers 104, which are arranged alternately to form a plurality of stacked pairs. In some embodiments, the plurality of stacked groups include silicon (Si) and silicon germanium (SiGe) groups. In some embodiments, the plurality of semiconductor material layers 106 include silicon germanium (SiGe), and the plurality of horizontal channel layers 104 include silicon (Si). In other embodiments, the plurality of horizontal channel layers 104 include silicon germanium (SiGe), and the plurality of semiconductor material layers 106 include silicon (Si).

[0034]

[0072] In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 may include any number of pairs of lattice-matched materials suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 include from about 2 to about 50 pairs of lattice-matched materials.

[0035]

[0073] In one or more embodiments, the thicknesses of the plurality of semiconductor material layers 106 and the plurality of horizontal channel layers 104 are in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0036] Referring to FIGS. 1A and 2B, in one or more embodiments, in step 16, the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105. The patterning can be performed by any suitable means known to those skilled in the art. When used in this context, the term "opening" means any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two sidewalls, and a bottom. The openings can have any suitable aspect ratio (the ratio of the width of the feature to the depth of the feature). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater.

[0037]

[0074] Referring to FIGS. 1A and 2C, in step 18, shallow trench isolation (STI) 110 is formed. As used herein, the term "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill the trench or opening 108 and removing excess dielectric using techniques such as chemical mechanical planarization.

[0038]

[0075] Referring to FIGS. 1A and 2D, in some embodiments, a replacement gate structure 113 (e.g., a dummy gate structure) is formed on and adjacent to the superlattice structure 101. The dummy gate structure 113 defines the channel region of the transistor device. The dummy gate structure 113 can be formed using any suitable conventional deposition and patterning processes known in the art.

[0039]

[0076] In one or more embodiments, the dummy gate structure includes one or more of gate 114 and polysilicon layer 112. In one or more embodiments, the dummy gate structure includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

[0040]

[0077] Referring to FIGS. 1A and 2E, in some embodiments, in step 22, sidewalls 116 are formed along the outer sidewalls of the dummy gate structure 113 on the superlattice 101. The sidewall spacers 116 can include any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or isotropic deposition.

[0041]

[0078] Referring to FIGS. 1A and 2F, in step 24, in one or more embodiments, source / drain trenches 118 are formed adjacent to (i.e., on both sides of) the superlattice structure 101.

[0042]

[0079] Referring to FIGS. 1A and 2G, in step 26, in one or more embodiments, the source / drain trenches 118 are deeply extended to form a cavity 119 under the superlattice structure 101. The cavity 119 can have any suitable depth and width. In one or more embodiments, the cavity 119 extends into the substrate 102 through the shallow trench isolation 110. In one or more embodiments, the etching and dummy filling of the cavity 119 pass under the shallow trench isolation 110 and extend up to the silicon germanium (SiGe) etch stop layer at most, enabling self-aligned contacts without touching the device.

[0043]

[0080] The cavity 119 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, a hard mask 117 is deposited to block non-Vss / Vdd source / drain. In one or more embodiments, the hard mask 117 can include any suitable material known to those skilled in the art. In some embodiments, the hard mask 117 is a resist. Once the hard mask 117 is formed, the cavity 119 is formed by etching.

[0044]

[0081] The etching process of step 26 can include any suitable etching process that is selective with respect to the source drain trench 118. In some embodiments, the etching process of step 26 includes one or more of a wet etching process or a dry etching process. The etching process can be a directional etching.

[0045]

[0082] In some embodiments, the dry etching process may include a conventional plasma etching or a remote plasma assisted dry etching process such as the SiCoNi® etching process available from Applied Materials, Inc. of Santa Clara, California. In the SiCoNi® etching process, the device is exposed to H2, NF3, and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be exposed to simultaneous exposure to H2, NF3, NH3 plasma. The SiCoNi® etching process is performed in a SiCoNi® Preclean chamber and may be incorporated into one of various multi-processing platforms, including the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®. The wet etching process may include a hydrofluoric acid (HF) acid last process, i.e., the so-called "HF last" process. In this process, HF etching of the surface is performed and the surface remains hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be used. In some embodiments, the process includes sublimation etching to remove the native oxide film. The etching process may be plasma-based or heat-based. The plasma process may be any suitable plasma (e.g., capacitively coupled plasma, inductively coupled plasma, microwave plasma).

[0046]

[0083] Referring to FIGS. 1A and 2H, in step 28, a sacrificial material 120 is deposited within the cavity 119. The sacrificial material can include any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 120 includes silicon germanium (SiGe). In one or more embodiments, the sacrificial material 120 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without being bound by theory, it is believed that having the germanium content in the range of 30% to 50% increases the selectivity of the sacrificial material and minimizes stress defects.

[0047]

[0084] In one or more embodiments, the sacrificial material 120 is doped with a dopant for lower contact resistance. In some embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In a specific embodiment, the sacrificial material 120 is silicon germanium having a germanium content in the range of 30% to 50% and doped with a dopant selected from one or more of boron (B), gallium (Ga), phosphorus (P), and arsenic (As).

[0048]

[0085] Referring to FIGS. 1A and 2I, in step 30, an inner spacer layer 121 is formed over each of the horizontal channel layers 104. The inner spacer layer 121 can include any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer layer 121 includes a nitride material. In a specific embodiment, the inner spacer layer 121 includes silicon nitride.

[0049]

[0086] Referring to FIGS. 2J and 1A, in step 32, in some embodiments, the embedded source / drain regions 122 are formed within the source / drain trenches 118. In some embodiments, the source region 122 is formed adjacent to the first end of the superlattice structure 101, and the drain region 122 is formed adjacent to the second end on the opposite side of the superlattice structure. In some embodiments, the source region and / or drain region 122 is formed from any suitable semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorus (SiP), silicon arsenic (SiAs), etc. In some embodiments, the source / drain regions 122 can be formed using any suitable deposition process such as an epitaxial deposition process. In some embodiments, the source / drain regions 122 are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0050]

[0087] In some embodiments, referring to FIGS. 1A and 2K, in step 34, an interlayer dielectric (ILD) layer 124 is blanket deposited over the substrate 102 including the source / drain regions 122, the dummy gate structure 113, and the sidewall spacers 116. The ILD layer 124 can be deposited using conventional chemical vapor deposition methods (e.g., plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one or more embodiments, the ILD layer 124 is formed from any suitable dielectric material such as undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride, but is not limited thereto. In one or more embodiments, the ILD layer 124 is then polished again using a conventional chemical mechanical planarization method to expose the top surface of the dummy gate structure 113. In some embodiments, the ILD layer 124 is polished to expose the top surface of the dummy gate structure 113 and the top surface of the sidewall spacers 116.

[0051]

[0088] To expose the channel region 108 of the superlattice structure 101, the dummy gate structure 101 can be removed. The ILD layer 124 protects the source / drain regions 122 while the dummy gate structure 113 is removed. The dummy gate structure 113 can be removed using conventional etching methods such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 comprises polysilicon and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 comprises polysilicon and the superlattice structure 101 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0052]

[0089] Referring to FIGS. 1B and 2L, in step 38, the formation of a semiconductor device, such as a GAA, continues according to a conventional procedure involving nanosheet release and replacement metal gate formation. Specifically, in one or more illustrated embodiments, a plurality of semiconductor material layers 106 are selectively etched between a plurality of horizontal channel layers 104 within a superlattice structure 101. For example, if the superlattice structure 101 consists of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The plurality of semiconductor material layers 106, such as silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the plurality of semiconductor material layers 106 such that the etchant etches the plurality of semiconductor material layers 106 significantly faster than the plurality of horizontal channel layers 104. In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, when the plurality of horizontal channel layers 104 are silicon (Si) and the plurality of semiconductor material layers 106 are silicon germanium (SiGe), the silicon germanium layer can be selectively removed using a wet etchant such as, but not limited to, an aqueous solution of carboxylic acid / nitric acid / HF and an aqueous solution of citric acid / nitric acid / HF. By removing the plurality of semiconductor material layers 106, voids remain between the plurality of horizontal channel layers 104. The voids between the plurality of horizontal channel layers 104 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 104 form a vertical array of channel nanowires connected to the source / drain regions 122. The channel nanowires run parallel to the upper surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0053]

[0090] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric can be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric of some embodiments includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (TiN), tungsten (W), cobalt (Co), aluminum (Al), etc. is deposited on the high-k dielectric to form a replacement metal gate 128. To ensure the formation of a layer with a uniform thickness around each of the plurality of channel layers, the conductive material can be formed using any suitable deposition process such as atomic layer deposition (ALD), etc. (not limited thereto).

[0054]

[0091] Referring to FIGS. 1B and 2M, in step 38, a contact to transistor (CT) 132 and a contact to gate (CG) 134 are formed to the transistor.

[0055]

[0092] Referring to FIGS. 1B and 2N, in step 40, a metal (M0) line 142 is formed and electrically connected to a via (V1) 144. This is the same as the conventional process, but since there is no power rail in the M0 line, sufficient space is ensured for the signal line.

[0056]

[0093] Referring to FIG. 2O, in step 42, the device 100 is rotated or inverted 180 degrees such that the substrate 102 comes to the top of the figure here. Further, in one or more embodiments, the substrate 102 is planarized. The planarization can be any suitable planarization process known to those skilled in the art including, but not limited to, chemical mechanical planarization (CMP). In one or more embodiments, before rotation, the front surface is bonded to the last layer with copper (Cu) metallization by hybrid bonding (oxide-to-oxide and Cu-to-Cu), or electrostatic dummy wafer bonding.

[0057]

[0094] Referring to FIGS. 1B and 2P, in step 44, the interlayer dielectric 146 / 148 is deposited on the back side. The interlayer dielectric material 146 / 148 can be deposited by any suitable means known to those skilled in the art. The interlayer dielectric material 146 / 148 can include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric material 146 / 148 includes one or more of silicon nitride (SiN), carbide, or boron carbide, enabling high aspect ratio etching and metallization.

[0058]

[0095] As shown in FIG. 2Q, in step 46, in one or more embodiments, the back-side power rail via 152 is formed. The via 152 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, the via 152 can be formed by patterning and etching the interlayer dielectric material 146 / 148.

[0059]

[0096] Referring to FIGS. 1B and 2R, in step 48, the damascene trench 154 is formed by extending the via 152 to the contacts 120, 122. When the via 152 is extended to form the trench 154, the size of the opening is at least doubled, enabling self-alignment. In one or more embodiments, the via 152 has a starting size of about 16 nm × about 26 nm and is extended to form a trench 154 having a size of about 90 nm × about 74 nm.

[0060]

[0097] The damascene trench 154 stops at the contacts 120, 122. The damascene trench 154 can have any suitable aspect ratio known to those skilled in the art. In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or more. In one or more embodiments, the critical dimensions of the damascene 154 are about 16 nm × about 26 nm, or about 10 nm × about 30 nm, or about 15 nm × about 30 nm. In one or more embodiments, the height of the back-side via depends on the thickness of the original epitaxial layer deposited on the etch stop layer.

[0061]

[0098] As shown in FIG. 2S, in step 50, the sacrificial layer 120 is selectively removed, and an opening 156 is formed on the source / drain 122. In one or more embodiments, if the sacrificial layer 120 is doped with one or more of Ga, B, and P, the sacrificial layer 120 can be partially removed leaving a portion thereof. The partial removal of the sacrificial layer 120 enables the formation of a low-resistance contact to the remaining sacrificial layer 120 (e.g., SiGe).

[0062]

[0099] In step 52, as shown in FIG. 2T, a metal fill 156 is deposited in the opening 156 formed by the removal of the sacrificial layer 120. The metal fill 156 can include any suitable material known to those skilled in the art. In one or more embodiments, the metal fill 156 is selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), etc.

[0063]

[0100] Referring to FIGS. 1B and 2U, in step 54, a backside metal line (M0) 160 is formed. Without intending to be bound by theory, it is believed that by placing the power rails on the backside, the cell area can be expanded in the range of 20% to 30%.

[0064]

[0101] FIG. 3 shows a process flow diagram of a method 60 for thinning a semiconductor wafer, according to some embodiments of the present disclosure. FIGS. 4A-4E show the stages of wafer thinning, according to some embodiments of the present disclosure. Method 60 is described below with respect to FIGS. 4A-4E. FIGS. 4A-4E are cross-sectional views of an electronic device (e.g., GAA) according to one or more embodiments. Method 60 can be part of a multi-step manufacturing process of a semiconductor device. Thus, method 60 can be performed in any suitable process chamber connected to a cluster tool. The cluster tool can include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the manufacture of semiconductor devices.

[0065]

[0102] FIGS. 4A-4E are the manufacturing steps of steps 62-76 in FIG. 3. Referring to FIG. 3, method 60 for thinning device 400 starts at step 62. Referring to FIGS. 3 and 4A-4E, in one or more embodiments of the method, a transistor, such as a gate-all-around transistor, is manufactured using a standard process flow.

[0066]

[0103] In some embodiments, a silicon wafer 402 is provided, and at step 62, a buried etch stop layer 404 is formed on the silicon wafer. The buried etch stop layer 404 can include any suitable material known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 includes silicon germanium (SiGe). In one or more embodiments, the buried etch stop layer 404 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without being bound by theory, it is believed that having the germanium content in the range of 30% to 50% increases the selectivity of the buried etch stop layer 404 and minimizes stress defects.

[0067]

[0104] In one or more non - illustrated embodiments, in step 64, an epitaxial layer, such as epitaxial silicon, is deposited. In step 66, the wafer then undergoes device and front - end processing. The front - end processing can be the process described above with respect to method 6 as shown in FIGS. 1A - 1B and in the cross - sectional views of FIGS. 2A - 2U.

[0068]

[0105] Referring to FIGS. 3 and 4B, in step 68, in one or more embodiments, after front - end processing, the wafer 400 undergoes, for example, hybrid bonding to copper or an oxide, and then the wafer is advantageously thinned. Without wishing to be bound by theory, it is believed that thinning the wafer advantageously provides the desired flatness and bonding for enabling a back - side power rail.

[0069]

[0106] In one or more embodiments, referring to FIGS. 3 and 4C, in order to thin the wafer, in step 70, a silicon substrate layer 402 having an initial first thickness t1 is polished to a second thickness t2 that is less than the first thickness. The silicon substrate layer 402 can be polished by any suitable means known to those skilled in the art. In some embodiments, the silicon substrate layer 402 is subjected to chemical - mechanical planarization (CMP), and then etching and CMP buffing are performed to reduce the thickness of the silicon substrate layer 402 to a third thickness t3 that is less than the second thickness. In one or more embodiments, the first thickness is in the range of 500 μm to 1000 μm. In one or more embodiments, the second thickness is in the range of 20 μm to 100 μm. In one or more embodiments, the third thickness is in the range of 1 μm to 20 μm.

[0070]

[0107] Referring to FIGS. 3 and 4D, in step 72, the buried etching stop layer 404 is selectively removed, exposing the source / drain 408. Next, in step 74, the contact 410 is pre-filled with metal and metallization is performed as shown in FIG. 4E. In one or more embodiments, the contact 410 is pre-filled with a metal selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), etc.

[0071]

[0108] FIGS. 5A - 5E show alternative manufacturing steps for steps 78 - 80 of FIG. 3. Referring to FIG. 3, a method 60 of thinning the device 400 begins at step 62 and proceeds to step 70 as illustrated in detail in FIGS. 4A - 4C.

[0072]

[0109] After the silicon substrate 402 is thinned by silicon polishing in step 70, the method proceeds to step 78 where a large mask 502 is formed over the buried etching stop layer 404. The mask 502 can include any suitable material known to those skilled in the art. In one or more embodiments, the mask 502 is selected from one or more of carbides, boron carbide, and silicon nitride.

[0073]

[0110] In step 80, the mask 502 is etched to form a plurality of through - silicon vias (TSVs) 508 that extend to the buried etching stop layer 404. The vias 508 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, the vias 508 are formed by etching. The nanometer - sized TSVs enable high - density packaging of this device or other chips connected to this device without the need for conventional large TSVs that add cost and space in normal 3D packaging.

[0074]

[0111] In operation 82, referring to FIGS. 3 and 5C, the buried etch stop layer 404 is selectively removed to form an opening 510. The buried etch stop layer 404 can be selectively removed by any suitable means known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 is selectively removed by etching the sides of the device.

[0075]

[0112] Referring to FIGS. 3 and 5D, in operation 84, the mask 502 having the vias 508 is lifted off (lifted off) from the device. The lift off can be performed by any suitable means known to those skilled in the art. In one or more embodiments, the lift off can thin the wafer to a thickness in the range of 50 nm to 100 nm. In one or more embodiments, as a result of the lift off, a thinned wafer with substantially no defects and scratches in the device 500 is obtained. In one or more embodiments, the lift off requires isotropic etching of the lateral portions of the sacrificial layer 120 across the entire wafer, which is achieved by Selectra (registered trademark) etching.

[0076]

[0113] FIG. 6 shows a process flow diagram for a method 600 of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIGS. 7A - 7D show the steps of forming deep vias and backside contacts according to some embodiments of the present disclosure. Method 600 will be described below with respect to FIGS. 7A - 7D. FIGS. 7A - 7D are cross-sectional views of an electronic device (e.g., GAA) 700 according to one or more embodiments. Method 600 can be part of a multi-step manufacturing process of a semiconductor device. Thus, method 600 can be executed in any suitable process chamber connected to a cluster tool. The cluster tool can include process chambers for semiconductor device manufacturing, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the manufacture of semiconductor devices.

[0077]

[0114] Figures 7A - 7D illustrate the manufacturing steps of steps 602 - 614 of FIG. 6. Referring to FIG. 6, method 600 for forming deep vias and backside contacts begins at step 602. Referring to FIGS. 6 and 7A - 7D, in method 600 of one or more embodiments, at step 602, using a standard process flow, transistors, such as gate - all - around transistors, are fabricated. Device 700 can be formed according to the methods described with respect to FIGS. 1A - 1B and 2A - 2Q.

[0078]

[0115] As shown in FIG. 7A, at step 604, at least one deep via 702 is formed on the front side. The deep via 702 can have any suitable size or shape. The deep via 702 can have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or more. In one or more embodiments, the critical dimensions of the deep via 702 are about 16 nm×about 16 nm, or about 10 nm×about 10 nm, or about 15 nm×about 15 nm, or about 20 nm×about 20 nm.

[0079]

[0116] Referring to FIGS. 6 and 7B, at step 606, the deep via 702 can be filled with metal 704. The metal 704 can be any suitable metal known to those skilled in the art. In one or more embodiments, the metal 704 is selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), etc.

[0080]

[0117] Referring to FIGS. 6 and 7C, in step 608, the bonding wafer 706 is bonded to the front side. In step 610, the substrate 708 can optionally be thinned according to one or more of the methods described above with respect to FIG. 3. As shown in FIG. 7D, in step 612, contacts 710 are then formed and electrically connected to the metal 704 within the deep vias 702. The contacts 710 can include any suitable material known to those skilled in the art. In one or more embodiments, the contacts 710 are selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), etc. and include metals. As shown in FIG. 7D, in step 614, metallization is performed.

[0081]

[0118] In some embodiments, the method is integrated such that there is no vacuum break. In one or more embodiments, method 60 is via etching (step 80), removal of the buried sacrificial layer (step 82), and substrate release lift-off (step 84), and can be integrated such that there is no vacuum break between steps.

[0082]

[0119] Additional embodiments of the present disclosure are directed to the processing tool 300 and the described method for GAA device formation shown in FIG. 8. Various multi-processing platforms can be utilized, including Applied Materials® Reflexion® CMP, Selectra® Etch, Centura® Dual ACP, Producer® GT, and Endura® platforms, as well as other processing systems. The cluster tool 300 includes at least one central transfer station 314 having a plurality of sides. A robot 316 is positioned within the central transfer station 314 and is configured to move the robot blade and the wafer to each of the plurality of sides.

[0083]

[0120] The cluster tool 300 includes a plurality of processing chambers 308, 310, 312, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing areas separated from adjacent processing stations. The processing chambers can be any suitable chambers, such as a pre-cleaning chamber, a deposition chamber, an annealing chamber, an etching chamber, etc., but are not limited thereto. The specific arrangement of the processing chambers and components can be changed according to the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0084]

[0121] In the embodiment shown in FIG. 8, a factory interface 318 is connected to the front surface of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and un-loading on the front surface 319 of the factory interface 318.

[0085]

[0122] The size and shape of the loading chamber and the un-loading chamber 302 can vary, for example, according to the substrate processed by the cluster tool 300. In the illustrated embodiment, the loading chamber and the un-loading chamber 302 are sized to hold a wafer cassette in which a plurality of wafers are positioned within the cassette.

[0086]

[0123] The robot 304 is within the factory interface 318 and can move between the loading chamber 302 and the un-loading chamber 302. The robot 304 can transfer wafers from the cassette in the loading chamber 302 through the factory interface 318 to the load lock chamber 320. Also, the robot 304 can transfer wafers from the load lock chamber 320 through the factory interface 318 to the cassette in the un-loading chamber 302.

[0087]

[0124] The robot 316 of some embodiments is a multi-arm robot capable of independently moving multiple wafers at once. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transfer blade located at the distal end of a first robotic mechanism.

[0088]

[0125] The system controller 357 communicates with the robot 316 and the plurality of processing chambers 308, 310, 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, a memory 394, an input / output 396, appropriate circuitry 398, and storage.

[0089]

[0126] The process can generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the processing chambers to execute the processes of the present disclosure. The software routines can be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Thus, the process can be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or in a combination of software and hardware. When executed by a processor, the software routines convert a general-purpose computer into a special-purpose computer (controller) that controls chamber operation so that the process is executed.

[0090]

[0127] In some embodiments, the system controller 357 has a configuration for controlling a rapid thermal processing chamber to crystallize a template material.

[0091]

[0128] In one or more embodiments, the processing tool includes a central transfer station having a robot configured to move wafers, a plurality of process stations, each process station being connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a template deposition chamber and a template crystallization chamber, and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to activate the robot to move wafers between the process stations and to control the processes performed at each of the process stations.

[0092]

[0129] As used in the context of describing the materials and methods discussed herein (in particular, in the context of the following claims), the use of "a", "an", "the", and similar referents should be construed to include both the singular and the plural unless otherwise indicated herein or clearly contradicted by the context. The recitation of numerical ranges herein is merely intended to serve as a shorthand for referring individually to each separate value falling within the range unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and is not intended to limit the scope unless otherwise claimed. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0093]

[0130] Throughout this specification, references to "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0094]

[0131] The disclosure herein has been described with reference to particular embodiments, but those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure can include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a superlattice structure on an upper surface of a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately so as to form a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material within the source cavity and within the drain cavity; forming a source region and a drain region; forming a contact to a transistor (CT) and a contact to a gate (CG) that are in electrical contact with the source region and the drain region; depositing an interlayer dielectric material on a lower surface of the substrate; forming a backside power rail via within the interlayer dielectric material; expanding the backside power rail via to form a damascene trench that penetrates the substrate; at least partially removing the sacrificial material to form at least one opening extending to the damascene trench; depositing a metal within the at least one opening and within the damascene trench A method comprising.

2. Expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches includes depositing a hard mask on at least one of the plurality of source trenches and at least one of the plurality of drain trenches, and not depositing a hard mask on the other source trenches of the plurality of source trenches and the other drain trenches of the plurality of drain trenches, and etching the unmasked source trenches and the unmasked drain trenches to form source cavities and drain cavities. The method according to claim 1, comprising:

3. The method according to claim 1, wherein the sacrificial material is completely removed.

4. The method according to claim 1, wherein the sacrificial material comprises silicon germanium (SiGe).

5. The method according to claim 4, wherein the silicon germanium (SiGe) has a germanium (Ge) content in the range of 30% to 50%.

6. The method according to claim 4, wherein the silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof.

7. The method according to claim 1, wherein forming the damascene trench further comprises etching the backside power rail via in the interlayer dielectric material deposited on the lower surface of the substrate.

8. The method according to claim 1, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently include one or more of silicon germanium (SiGe) and silicon (Si).

9. The method according to claim 1, wherein forming the source region and the drain region includes growing an epitaxial layer thereon.

10. The method according to claim 1, wherein one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga) are independently doped into the source region and the drain region.

11. The method according to claim 1, further comprising forming a gate structure on the upper surface of the superlattice structure.

12. The method according to claim 11, further comprising forming a dielectric layer on the gate structure and on the superlattice structure.

13. The method according to claim 12, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-type doped polysilicon.

14. The method according to claim 1, wherein the metal comprises one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), and ruthenium (Ru).

15. A method of forming a semiconductor device, the method comprising: forming a superlattice structure on an upper surface of a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately so as to form a plurality of stacked pairs; forming a gate structure on an upper surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial material in the source cavity and in the drain cavity; Forming an inner spacer layer on each of the plurality of horizontal channel layers; Forming source and drain regions; Forming an interlayer dielectric layer on the upper surface of the substrate, including the source region, the drain region, and the gate structure; Forming a replacement metal gate; Forming a contact to the transistor (CT) and a contact to the gate (CG) that are in electrical contact with the source region and the drain region; Rotating the formation 180 degrees so that the upper surface of the substrate is inverted downward; Planarizing the lower surface of the inverted substrate; Depositing an interlayer dielectric material on the lower surface of the substrate; Forming a backside power rail via in the interlayer dielectric material; Expanding the backside power rail via downward in a direction toward the upper surface of the substrate to form a damascene trench; Removing the sacrificial material to form at least one opening; Depositing a metal in the at least one opening and in the damascene trench A method comprising.

16. Expanding at least one of the plurality of source trenches and at least one of the plurality of drain trenches includes depositing a hard mask on at least one of the plurality of source trenches and at least one of the plurality of drain trenches, and not depositing a hard mask on the other source trenches of the plurality of source trenches and the other drain trenches of the plurality of drain trenches, and etching the unmasked source trenches and the unmasked drain trenches to form source cavities and drain cavities The method according to claim 15, comprising.

17. The method according to claim 15, wherein the sacrificial material comprises silicon germanium (SiGe). **Claim 18** The method according to claim 17, wherein the silicon germanium (SiGe) has a germanium (Ge) content in the range of 30% to 50%. **Claim 19** The method according to claim 17, wherein the silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof. **Claim 20** The method according to claim 15, wherein forming the source region and the drain region comprises growing an epitaxial layer thereon.

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