Simulation device and simulation method

Abstract

To perform a simulation with high accuracy and reduce a time required for the simulation in a simulation apparatus that simulates a system including a semiconductor memory apparatus.SOLUTION: A simulation apparatus 100 is a simulation apparatus that simulates a system 20 including a semiconductor apparatus 21, and includes a table 12 representing a relationship between a burst length of a command for an access request to the semiconductor memory apparatus from an arithmetic apparatus 29 that accesses to the semiconductor memory apparatus and a command interval, a counter 13 that holds an elapsed cycle number from an issuance of a prior command, and a protocol control unit 11 for issuing a command that determines the command interval using the table and the counter when newly issuing a command, and newly issues a command after elapsing the determined command interval from the issuance of the prior command.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to simulation.

Background Art

[0002] There are cases where a system including a SoC (System On a Chip) and a semiconductor memory device is modeled and performance verification is performed by simulation. The model is realized by simplifying the operations performed by the hardware constituting the system. In the simulation, the timing of access requests from the controller to the semiconductor memory device is determined so that the processing time in the simulation approaches the processing time in the hardware. In the simulation device described in Patent Document 1 below, the relationship between the type of command to be processed and the processing time is set in advance as a table, and the processing time is derived without performing the processing in the hardware, thereby shortening the processing time by simulation and approaching the processing time in the hardware.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, since the processing time in the hardware varies depending not only on the type of command but also on various factors related to command issuance, it is difficult for the simulation device described in Patent Document 1 to derive an accurate processing time.

Means for Solving the Problems

[0005] According to one embodiment of the present disclosure, a simulation device (100) is provided. The simulation device is a simulation device that simulates a system (20) having a semiconductor memory device (21), and includes a table (12) representing the relationship between the burst length and the command interval of commands for access requests from an arithmetic device (29) accessing the semiconductor memory device to the semiconductor memory device, a counter (13) that holds the number of elapsed cycles since the previous issuance of the command, and a protocol control unit (11) that issues the command. When newly issuing the command, the protocol control unit determines the command interval using the table and the counter, and newly issues the command after the determined command interval has elapsed since the previous issuance of the command.

[0006] According to the simulation device of this embodiment, since the command interval is determined according to the burst length of the previously issued command, it is not necessary to simulate and execute the processing on the semiconductor memory device, so the time required for simulation can be shortened. In addition, simulation can be performed with high accuracy.

Brief Description of the Drawings

[0007]

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MODE FOR CARRYING OUT THE INVENTION

[0008] A. First Embodiment: The simulation device 100 shown in FIG. 1 simulates the processing in the system 20 including the semiconductor memory device 21 for verifying the performance of the arithmetic device 29 shown in FIG. 2. The arithmetic device 29 corresponds to, for example, a CPU or a GPU (Graphics Processing Unit). "Simulation of the system 20" includes simulating the command issuance operation to the semiconductor memory device 21 in response to an access request to the semiconductor memory device 21 issued from the arithmetic device 29. In the present embodiment, the access request is a write access request for requesting writing of data to the semiconductor memory device 21 and a read access request for requesting reading of data from the semiconductor memory device 21. The write access request corresponds to the "first access request" in the present disclosure. Also, the read access request corresponds to the "second access request" in the present disclosure. As shown in FIG. 2, in the present embodiment, the semiconductor memory device 21 includes a plurality of banks 211, 212,... 21n (n is an integer).

[0009] As shown in FIG. 1, the simulation apparatus 100 is configured by a computer including a CPU 110, a ROM 120, and a RAM 130. The CPU 110, the ROM 120, and the RAM 130 are each connected to an internal bus 140 and are configured to communicate with each other via the internal bus 140. The CPU 110 functions as the system function unit 10 by expanding and executing a computer program stored in advance in the ROM 120 in the RAM 130. The system function unit 10 includes a protocol control unit 11, a table 12, and a counter 13.

[0010] The protocol control unit 11 issues a command to the semiconductor memory device 21 in response to an access request to the semiconductor memory device 21 issued from the arithmetic unit 29. Further, the protocol control unit 11 determines the number of cycles from the previous command issuance to the newly issued command this time (hereinafter referred to as "command interval Ic"). Specifically, when receiving an access request, the protocol control unit 11 determines the command interval Ic using the relationship between the burst length Lb of the access request recorded as the table 12 and the command interval Ic. The burst length Lb means the number of consecutive data read and written in one access to the semiconductor memory device 21. The relationship between the burst length Lb and the command interval Ic has been specified in advance by experiments or the like so that the processing time in the simulation is close to the processing time in the hardware.

[0011] In FIG. 3, the horizontal axis represents the burst length Lb, and the vertical axis represents the command interval Ic. In the first embodiment, in the table 12, the command interval Ic is represented by an integer, and the table 12 is set such that the command interval Ic gradually decreases as the burst length Lb increases. More specifically, the command interval Ic1 at the burst length Lb1 is equal to or greater than the command interval Ic2 at the burst length Lb2 that is longer than the burst length Lb1.

[0012] In the system 20 including the semiconductor memory device 21, the inventors of the present disclosure have found that by setting the command interval Ic in the table 12 such that the command interval Ic1 at the burst length Lb1 is equal to or greater than the command interval Ic2 at the burst length Lb2 that is longer than the burst length Lb1, the processing time in the simulation tends to be close to the processing time in the hardware. By reflecting such a tendency in the simulation, the simulation can be performed with higher accuracy. Note that the burst length Lb1 corresponds to the "first burst length" in the present disclosure. Also, the burst length Lb2 corresponds to the "second burst length" in the present disclosure.

[0013] The counter 13 holds the number of elapsed cycles since the protocol control unit 11 issued the previous command.

[0014] A simulation method in the simulation device 100 of the first embodiment will be described with reference to FIG. 4.

[0015] In step S110, the counter 13 sets the counter value Ct to the counter maximum value Ctmax.

[0016] When there is no access request from the arithmetic unit 29 (step S120: No), if the counter value Ct is not the counter maximum value Ctmax (step S121: No), the counter 13 increments the counter value Ct by 1 after the elapse of one cycle (step S123). If the counter value Ct is the counter maximum value Ctmax (step S121: Yes), the counter 13 holds the counter value Ct as the counter maximum value Ctmax.

[0017] When there is an access request (step S120: Yes), the protocol control unit 11 determines the command interval Ic using the table 12 according to the burst length Lb of the access request (step S130).

[0018] In step S140, the protocol control unit 11 compares the counter value Ct with the command interval Ic. When the counter value Ct is smaller than the command interval Ic of the access request (step S140: No), the counter 13 increments the counter value Ct by 1 (step S141). The simulation device 100 repeatedly performs the processes of step S140 and step S141 until the counter value Ct becomes equal to or greater than the command interval Ic of the access request.

[0019] When the counter value Ct is equal to or greater than the command interval Ic of the access request (step S140: Yes), the protocol control unit 11 issues a command to the semiconductor memory device 21 (step S150). After issuing the command, the counter 13 resets the counter value Ct to 0 (step S160).

[0020] When the issuance of all the predetermined commands is completed (step S170: Yes), the simulation device 100 terminates the simulation. When there are still commands to be issued (step S170: No), the simulation device 100 continues the simulation and repeatedly performs the processes from step S120 to step S160.

[0021] According to the simulation device 100 of the first embodiment described above, by determining the command interval Ic according to the burst length Lb of the access request, it is not necessary to simulate and execute the processing on the semiconductor memory device 21, so the time required for the simulation can be shortened. Further, by setting the command interval Ic in the table 12 so that the command interval Ic1 at the burst length Lb1 is equal to or greater than the command interval Ic2 at the burst length Lb2 that is longer than the burst length Lb1, the tendency in the relationship between the burst length Lb and the command interval Ic described above can be reflected in the simulation, so that the simulation can be performed with high accuracy.

[0022] B. Second Embodiment: As shown in FIG. 5, the simulation apparatus 100a of the second embodiment is different from the simulation apparatus 100 of the first embodiment in that it includes a table 12a in addition to the table 12 in FIG. 1. Since the other configurations of the simulation apparatus 100a of the second embodiment are the same as those of the simulation apparatus 100 of the first embodiment, detailed description thereof will be omitted.

[0023] The inventors of the present disclosure have found that in the system 20 including the semiconductor memory device 21, when the ratio of either the received write access request or read access request becomes high, the number of times of switching from one command to the other command per unit time decreases, so that the processing time tends to be shortened. In the second embodiment, by reflecting this tendency in the simulation, the simulation can be performed with higher accuracy.

[0024] The simulation apparatus 100a of the second embodiment records the types of past access requests and the burst length Lb for a predetermined number of times in the protocol control unit 11, and calculates the ratio of the total burst length Lb of the past access requests for a predetermined number of times that is the total of the burst lengths Lb of the write access requests. Note that this ratio is also referred to as the "write access request ratio". In the present embodiment, when the calculated write access request ratio exceeds a predetermined threshold Th, the protocol control unit 11 determines the command interval Ic with reference to the table 12a instead of the table 12. In the present embodiment, for the same burst length Lb, the numerical values are set so that the command interval Ic of the table 12a is equal to or less than the command interval Ic of the table 12. In FIG. 6, the horizontal axis represents the write access request ratio, and the vertical axis represents the command interval Ic. When the write access request ratio exceeds the threshold Th, the command interval Ic becomes smaller than when the write access request ratio is equal to or less than the threshold Th.

[0025] The simulation device 100a of the second embodiment described above has the same effects as the simulation device 100 of the first embodiment. In addition, when the light access request ratio exceeds the threshold Th, the simulation device 100a of the second embodiment can reflect the above tendency in the simulation by determining the command interval Ic with reference to the table 12a, so that the simulation can be performed with higher accuracy.

[0026] C. Third Embodiment: The simulation device 100 of the third embodiment has the same device configuration as the simulation device 100 of the first embodiment. The simulation method of the third embodiment shown in FIGS. 7 and 8 is different from the simulation method of the first embodiment in that steps S122 and S124 are added after step S120 of FIG. 4. Since the other procedures of the simulation method of the third embodiment are the same as those of the first embodiment, the same reference numerals are given to the same processes, and the detailed description thereof is omitted.

[0027] The inventors of the present disclosure have found that in the system 20 including the semiconductor memory device 21, if the page address of the access request is the same as the page address at the previous access, the sense amplifier included in the semiconductor memory device 21 does not need to newly read data of a different page address, so the processing time tends to be shortened. In the third embodiment, the simulation can be performed with higher accuracy by reflecting this tendency in the simulation.

[0028] When there is an access request in step S120, step S122 is executed. In step S122, the protocol control unit 11 determines whether the page address at the previous access for each of the plurality of banks 211 to 21n included in the semiconductor memory device 21 recorded in the protocol control unit 11 matches the page address of the new access request.

[0029] If the page address at the previous access does not match the page address of the new access request (step S122: No), step S130 is executed. The processing after step S130 is the same as the simulation method of the first embodiment.

[0030] On the other hand, if the page address at the previous access matches the page address of the new access request (step S122: Yes), the protocol control unit 11 doubles the burst length Lb (step S124).

[0031] In step S130, the protocol control unit 11 determines the command interval Ic based on the doubled burst length Lb. However, if the doubled burst length Lb exceeds the maximum value of the burst length Lb set in the table 12 in advance, the command interval Ic is determined based on the maximum value of the burst length Lb set in the table 12 in advance. The processing after step S140 shown in FIG. 8 is the same as the simulation method of the first embodiment.

[0032] As described above, the command interval Ic is set in the table 12 so as to gradually decrease as the burst length Lb increases. Therefore, the command interval Ic determined by referring to the table 12 with the burst length Lb as a doubled value is a smaller value than the command interval Ic determined by referring to the table 12 with the original burst length Lb.

[0033] The simulation device 100 of the third embodiment described above has the same effects as the simulation device 100 of the first embodiment. In addition, when the page address of the new access request matches the page address at the previous access for each of the plurality of banks 211 to 21n, the simulation device 100 of the third embodiment doubles the burst length Lb of the access request and refers to the table 12 to determine the command interval Ic, so that the above tendency can be reflected in the simulation, and the simulation can be performed accurately.

[0034] D. Fourth Embodiment: The simulation apparatus 100 according to the fourth embodiment is different from the simulation apparatus 100 according to the first embodiment in that the command interval Ic is set as a decimal number on the table 12 and the counter 13 performs a counting operation different from that of the first embodiment. In this embodiment, the decimal number is represented by 2 or 3 bits in fixed-point notation. Also, as shown in FIGS. 9 and 10, the simulation method according to the fourth embodiment is different from the simulation method according to the first embodiment in that steps S152 and S154 are performed after step S150 in FIG. 4. Since the other configurations and other procedures of the simulation apparatus 100 according to the fourth embodiment are the same as those of the simulation apparatus 100 according to the first embodiment, detailed description thereof will be omitted.

[0035] The processing from step S110 to step S141 shown in FIG. 9 is the same as the simulation method according to the first embodiment. As shown in FIG. 10, after the command is issued in the above-described step S150, the counter 13 performs a counting operation. When the command interval Ic is greater than the counter value Ct at the time of determining the command interval Ic (step S152: No), in other words, when the command interval Ic becomes less than or equal to the counter value Ct after the increase of the counter value Ct, the counter 13 newly holds a value obtained by subtracting the command interval Ic from the counter value Ct at the time of command issuance (step S154). The processing after step S170 is the same as the simulation method according to the first embodiment.

[0036] On the other hand, when the command interval Ic is less than or equal to the counter value Ct at the time of determining the command interval Ic (step S152: Yes), the above-described step S160 is executed and the counter value Ct is reset to 0. The processing after step S170 is the same as the simulation method according to the first embodiment.

[0037] The counting operation of the counter 13 in the fourth embodiment will be described more specifically. In FIGS. 11 and 12, the numbers attached to "command issuance" mean that the command issuance corresponds to the access request with the same number.

[0038] Taking the case where access request 1 with a command interval Ic of 4.1, access request 2 with a command interval Ic of 2.3, and access request 3 with a command interval Ic of 1.5 are sequentially issued from the arithmetic unit 29 as an example. As shown in FIG. 11, in the simulation device 100 of the fourth embodiment, when the number of elapsed cycles from the start of simulation is 7, the command issuance for all access requests is completed.

[0039] On the other hand, in the configuration where the command interval Ic is set as a decimal in the table 12 and the counter 13 performs the same counting operation as in the first embodiment, as shown in FIG. 12, the command issuance for all access requests is completed when the number of elapsed cycles from the start of simulation is 8.

[0040] As described above, even when the same access request is processed, the processing by the counting operation of the counter 13 in the fourth embodiment can end the processing in a shorter number of cycles than the configuration where the command interval Ic is set as a decimal and the counter 13 performs the same counting operation as in the first embodiment. Therefore, the time required for the simulation can be shortened.

[0041] The simulation device 100 of the fourth embodiment described above has the same effects as the simulation device 100 of the first embodiment. In addition, the simulation device 100 of the fourth embodiment determines the command interval Ic using the table 12 in which the command interval Ic represented by a decimal is set, and the counter 13 holds the value obtained by subtracting the command interval Ic from the counter value Ct at the time of command issuance. Therefore, the relationship between the burst length Lb and the command interval Ic can be simulated with higher accuracy, and the simulation can be performed with higher accuracy. In addition, the time required for the simulation can be further shortened.

[0042] E. Other Embodiments: (E1) In the above embodiment, the counter 13 increases by 1 for each counting operation, but the present disclosure is not limited thereto. The counter 13 may increase by any preset number for each counting operation.

[0043] (E2) In the above embodiment, the semiconductor memory device 21 has a plurality of banks 211 to 21n, but the present disclosure is not limited thereto. The semiconductor memory device 21 may have only one bank.

[0044] (E3) In the above first embodiment, the command interval Ic is set in Table 12 so as to gradually decrease as the burst length Lb increases, but the present disclosure is not limited thereto. As shown in FIG. 13, the command interval Ic may be set in Table 12 so as to continuously decrease as the burst length Lb increases.

[0045] (E4) In the above first embodiment, the counter 13 starts the counting operation from the counter maximum value Ctmax at the start of the simulation, but the present disclosure is not limited thereto. The counter 13 may start the counting operation from 0 at the start of the simulation.

[0046] (E5) In the above second embodiment, Table 12a is referred to when the threshold Th is exceeded, but the present disclosure is not limited thereto. A plurality of thresholds may be set, and for each of the plurality of thresholds, corresponding different tables may be set respectively. In this case, the relationship between the write access request ratio and the command interval Ic is such that as the write access request ratio increases, the command interval Ic gradually decreases, similar to the relationship shown in FIG. 3.

[0047] (E6) In the above-described Embodiment 3, the command interval Ic is determined by referring to Table 12 with the burst length Lb of the access request doubled when the page address of a new access request matches the page address at the previous access for each of the plurality of banks 211 to 21n. However, the present disclosure is not limited to this. The command interval Ic may be determined by referring to a table different from the preset Table 12 when the page address of a new access request matches the page address at the previous access for each of the plurality of banks 211 to 21n. Further, the command interval Ic may be determined with the burst length Lb of the access request being an integer multiple greater than 2.

[0048] (E7) In the above-described Third Embodiment, the calculated ratio is the ratio of the total burst length Lb of write access requests among the total burst lengths Lb of past access requests for a predetermined number of times. However, the present disclosure is not limited to this. The calculated ratio may be the ratio of the total burst length Lb of read access requests among the total burst lengths Lb of past access requests for a predetermined number of times.

[0049] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features of the embodiments corresponding to the technical features in each form described in the summary of the invention can be appropriately replaced or combined in order to solve part or all of the above-described problems or to achieve part or all of the above-described effects. Further, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

Explanation of Reference Numerals

[0050] 11…Protocol control unit, 12…Table, 13…Counter, 20…System, 21…Semiconductor memory device, 29…Arithmetic unit, 100…Simulation device

Claims

1. A simulation device (100) for simulating a system (20) having a semiconductor memory device (21), a table (12) representing the relationship between the burst length and the command interval of commands for access requests from an arithmetic unit (29) accessing the semiconductor memory device to the semiconductor memory device, a counter (13) for holding the number of cycles elapsed since the previous issuance of the command, a protocol control unit (11) for issuing the command, which determines the command interval using the table and the counter when newly issuing the command, and newly issues the command after the determined command interval has elapsed since the previous issuance of the command; A simulation device comprising the above.

2. The simulation device according to claim 1, wherein the counter starts a counting operation from a predetermined maximum value, compares the determined command interval with the number of elapsed cycles when the access request is issued, increases the number of elapsed cycles when the determined command interval is greater than the number of elapsed cycles, and when the determined command interval is less than or equal to the number of elapsed cycles, executes issuing the command and resetting the number of elapsed cycles to 0. A simulation device.

3. The simulation device according to any one of claims 1 or 2, wherein in the table, the command interval at the first burst length is greater than or equal to the command interval at a second burst length that is longer than the first burst length. A simulation device.

4. The simulation device according to any one of claims 1 to 3, Calculate either the ratio of the total burst length of the first access requests that request writing data to the semiconductor memory device or the ratio of the total burst length of the second access requests that request reading data from the semiconductor memory device among the access requests of a predetermined number of times, and when the ratio is equal to or greater than a predetermined threshold value, make the command interval smaller than when the ratio is less than the threshold value. Simulation device.

5. The simulation device according to any one of claims 1 to 4, wherein the semiconductor memory device has a plurality of banks. Store the page address accessed last for each bank, and when the page address of the new access request matches the page address accessed last, make the command interval smaller than when they do not match. Simulation device.

6. The simulation device according to any one of claims 1 to 5, wherein The command interval set in the table is represented by a decimal number. When determining the command interval, the counter executes resetting the issuance of the command and the number of elapsed cycles to 0 when the determined command interval is less than or equal to the number of elapsed cycles, and after the number of elapsed cycles increases, when the determined command interval becomes less than or equal to the number of elapsed cycles, executes holding a value obtained by subtracting the command interval from the issuance of the command and the number of elapsed cycles. Simulation device.

7. A simulation method in which a computer simulates a system having a semiconductor memory device under software control. When newly issuing a command for an access request from an arithmetic unit accessing the semiconductor memory device to the semiconductor memory device, a step of determining, by the computer, the command interval using a table representing the relationship between the burst length and the command interval of the command, and a counter that holds the number of cycles elapsed since the previous issuance of the command; A step of the computer newly issuing the command after the determined command interval has elapsed since the previous issuance of the command; A simulation method comprising:

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