Impedance detection circuit, impedance control circuit, and Doherty amplifier circuit

Abstract

This impedance detection circuit includes: a first wave detector for detecting a first voltage amplitude at one end, of an inverter circuit, to which a high-frequency signal is inputted and another end, of said inverter circuit, from which the signal is outputted; a second wave detector for detecting a second voltage amplitude at the other end of the inverter circuit; and a phase difference detector for detecting the phase difference between the phase of a voltage at the one end of the inverter circuit and the phase of a voltage at the other end of inverter circuit. Regarding a dependent parameter of the inverter circuit, an absolute value of a product of diagonal components is less than an absolute value of a product of non-diagonal components.

Description

Technical Field

[0001] The present invention relates to an impedance detection circuit, an impedance control circuit, and a Doherty amplifier circuit.

Background Art

[0002] Patent Document 1 describes an amplifier device that adjusts the phase or amplitude of a second signal input to a second amplifier unit using the reflection coefficients of the outputs of a first amplifier unit and a second amplifier unit, respectively.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the amplifier device described in Patent Document 1 requires two directional couplers to detect the reflection coefficients of the outputs of the first amplifier unit and the second amplifier unit, respectively. Since a directional coupler is large in structure, it cannot be used, for example, in a mobile communication terminal or the like.

[0005] The present invention has been made in view of the above, and an object thereof is to detect impedance while suppressing an increase in the size of a circuit.

Means for Solving the Problems

[0006] An impedance detection circuit according to one aspect of the present invention includes a first detector that detects a first voltage amplitude at one end of an inverter circuit to which a high-frequency signal is input at one end and outputs a signal from the other end, a second detector that detects a second voltage amplitude at the other end of the inverter circuit, and a phase difference detector that detects a phase difference between the phase of the voltage at one end of the inverter circuit and the phase of the voltage at the other end of the inverter circuit. The parameters of the inverter circuit Vertical connection parameter(So-called F parameter) The absolute value of the product of the diagonal components is smaller than the absolute value of the product of the off-diagonal components.

[0007] The impedance control circuit according to one aspect of the present invention includes the impedance detection circuit of the present disclosure, a first transistor in which a first signal based on a first voltage amplitude and a second voltage amplitude is input to a base or a gate and a first current is output from a collector to one end of an inverter circuit, and at least one of a second transistor in which a second signal based on the first voltage amplitude and the second voltage amplitude is input to the base or the gate and a second current is output from the collector to the other end of the inverter circuit.

[0008] The Doherty amplifier circuit according to one aspect of the present invention includes a carrier amplifier that amplifies an input high-frequency signal, a peak amplifier that amplifies the input high-frequency signal, and the impedance control circuit of the present disclosure. The inverter circuit also serves as a Doherty synthesizer that synthesizes the signal output from the carrier amplifier and the signal output from the peak amplifier.

Advantages of the Invention

[0009] According to the present invention, it is possible to detect impedance while suppressing an increase in the size of the circuit.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of the amplifier circuit according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the circuit simulation result of the amplifier circuit according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing the circuit simulation result of the amplifier circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of the amplifier circuit according to the first example of the second embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of the amplifier circuit according to the second example of the second embodiment. [Figure 6] FIG. 6 is a diagram showing the configuration of the amplifier circuit according to the third example of the second embodiment. [Figure 7] FIG. 7 is a diagram showing the circuit simulation result of the amplifier circuit of the third example of the second embodiment. [Figure 8] FIG. 8 is a diagram showing the circuit simulation result of the amplifier circuit of the third example of the second embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of the inverter circuit of the first example of the third embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of the inverter circuit of the second example of the third embodiment. [Figure 11] FIG. 11 is a diagram showing the configuration of the inverter circuit of the third example of the third embodiment. [Figure 12] FIG. 12 is a diagram showing the configuration of the inverter circuit of the fourth example of the third embodiment. [Figure 13] FIG. 13 is a diagram showing the configuration of the inverter circuit of the fifth example of the third embodiment. [Figure 14] FIG. 14 is a diagram showing the configuration of the amplifier circuit of the fourth embodiment. [Figure 15] FIG. 15 is a diagram showing the circuit simulation result of the amplifier circuit of the fourth embodiment. [Figure 16] FIG. 16 is a diagram showing the circuit simulation result of the amplifier circuit of the fourth embodiment. [Figure 17] FIG. 17 is a diagram showing the configuration of the amplifier circuit of the fifth embodiment. [Figure 18] FIG. 18 is a diagram showing the configuration of the amplifier circuit of the sixth embodiment. [Figure 19] FIG. 19 is a diagram showing the configuration of the amplifier circuit of the seventh embodiment. [Figure 20] FIG. 20 is a diagram showing the configuration of the equivalent circuit of the amplifier circuit of the seventh embodiment. [Figure 21] FIG. 21 is a diagram showing the configuration of the amplifier circuit of the eighth embodiment. [Figure 22] FIG. 22 is a diagram showing the configuration of a modified example of the amplifier circuit of the eighth embodiment.

Best Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the impedance detection circuit, impedance control circuit, and Doherty amplifier circuit of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited by this embodiment. Each embodiment is an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. In the following second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only different points will be described. In particular, the same operational effects due to the same configuration will not be sequentially mentioned for each embodiment.

[0012] <First Embodiment> FIG. 1 is a diagram showing the configuration of the amplifier circuit according to the first embodiment.

[0013] The amplifier circuit 1 includes an amplifier 2, an inverter circuit 3, a 90° phase shift circuit 4, and an impedance control circuit 10.

[0014] The amplifier 2 amplifies the high-frequency signal RF IN and outputs the high-frequency signal RF1 to one end 3a of the inverter circuit 3. The inverter circuit 3 receives the high-frequency signal RF1 at one end 3a and outputs the high-frequency signal RF2 from the other end 3b to the load 150.

[0015] The amplifier 2 is premised on the impedance Z L ' seen from the output terminal side to the load 150 being the value assumed at the time of design. Examples of the amplifier 2 include a general emitter-grounded or source-grounded single-ended amplifier, differential amplifier, Doherty amplifier, envelope tracking amplifier, etc., but the present disclosure is not limited thereto.

[0016] Let the output voltage of the amplifier 2 be the voltage V L ' and the output current be the current I L '.

[0017] The inverter circuit 3 has an impedance Z of the load 150L Convert it to the reciprocal (admittance). The inverter circuit 3 is a 1 / 4 wavelength line of the characteristic impedance Z0, but the present disclosure is not limited thereto.

[0018] Let the voltage input to one end 3a of the inverter circuit 3 be the voltage V I1 and the input current be the current I I1 Let the voltage output from the other end 3b of the inverter circuit 3 be the voltage V I2 and the output current be the current I I2 .

[0019] Let the voltage input to the load 150 be the voltage V L and the current input to the load 150 be the current I L .

[0020] The impedance control circuit 10 controls the impedance Z L '. Note that the impedance Z L ' is also the input impedance of the inverter circuit 3.

[0021] (Configuration of impedance control circuit) The impedance control circuit 10 includes transistors Q1 and Q2, variable phase control circuits 11 and 15, variable gain control circuits 12 and 16, capacitors 13 and 17, resistors 14 and 18, a control circuit 19, and an impedance detection circuit 20.

[0022] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited thereto. As an example of the bipolar transistor, a heterojunction bipolar transistor (HBT) is given, but the present disclosure is not limited thereto. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The unit transistor refers to the minimum configuration of which the transistor is composed.

[0023] When each transistor is an FET, the drain of the FET corresponds to the collector of the bipolar transistor, the gate corresponds to the base, and the source corresponds to the emitter.

[0024] Transistor Q1 corresponds to an example of the "first transistor" of the present disclosure. Transistor Q2 corresponds to an example of the "second transistor" of the present disclosure. Variable gain control circuit 12 corresponds to an example of the "first variable gain control circuit" of the present disclosure. Variable gain control circuit 16 corresponds to an example of the "second variable gain control circuit" of the present disclosure. Variable phase control circuit 11 corresponds to an example of the "first variable phase control circuit" of the present disclosure. Variable phase control circuit 15 corresponds to an example of the "second variable phase control circuit" of the present disclosure.

[0025] Impedance detection circuit 20 includes detectors 21 and 22 and a phase difference detector 23.

[0026] Detector 21 corresponds to an example of the "first detector" of the present disclosure. Detector 22 corresponds to an example of the "second detector" of the present disclosure.

[0027] Detector 21 detects the voltage V at one end 3a of inverter circuit 3 I1 and outputs the voltage amplitude |V I1 | to control circuit 19.

[0028] The voltage amplitude |V I1 | corresponds to an example of the "first voltage amplitude" of the present disclosure.

[0029] Detector 22 detects the voltage V at the other end 3b of inverter circuit 3 I2 and outputs the voltage amplitude |V I2 | to control circuit 19.

[0030] The voltage amplitude |V I2 | corresponds to an example of the "second voltage amplitude" of the present disclosure.

[0031] Phase difference detector 23 receives voltage V I1 and voltage VI2 the phase difference (arg(V I1 )) - arg(V I2 )) between them is detected and output to the control circuit 19.

[0032] Based on the voltage amplitudes |V I1 | and |V I2 |, and the phase difference (arg(V I1 )) - arg(V I2 ))), the control circuit 19 outputs a phase control signal S1 to the variable phase control circuit 11, outputs a gain control signal S2 to the variable gain control circuit 12, and outputs a bias control signal S3 to one end of the resistor 14. Alternatively, based on the voltage amplitudes |V I1 | and |V I2 |, and the phase difference (arg(V I1 )) - arg(V I2 ))), the control circuit 19 outputs a phase control signal S4 to the variable phase control circuit 15, outputs a gain control signal S5 to the variable gain control circuit 16, and outputs a bias control signal S6 to one end of the resistor 18.

[0033] Based on the phase control signal S1, the variable phase control circuit 11 changes the phase of the high-frequency signal RF IN by the phase θ1 and outputs the high-frequency signal RF 11 to the variable gain control circuit 12.

[0034] Based on the gain control signal S2, the variable gain control circuit 12 changes the amplitude of the high-frequency signal RF 11 by the gain G1 and outputs the high-frequency signal RF 12 to the base of the transistor Q1 via the capacitor 13 which is a DC cut capacitor.

[0035] The other end of the resistor 14 is electrically connected to the base of the transistor Q1. From the other end of the resistor 14, a bias voltage B1 is input to the base of the transistor Q1.

[0036] The emitter of transistor Q1 is electrically connected to a reference potential. Although the reference potential is exemplified by the ground potential, the present disclosure is not limited thereto. The collector of transistor Q1 is electrically connected to the power supply potential VCC via the choke coil 31 and is supplied with power.

[0037] Transistor Q1 outputs a current I 12 corresponding to the high-frequency signal RF add1 and the bias voltage B1 from the collector to one end 3a of the inverter circuit 3. In other words, transistor Q1 outputs a high-frequency signal obtained by amplifying the high-frequency signal RF 12 from the collector to one end 3a of the inverter circuit 3.

[0038] The current I add1 corresponds to an example of the "first current" of the present disclosure.

[0039] Note that when compensation for the reactance component (imaginary component) of the impedance Z L ' is not required, the variable phase control circuit 11 may be omitted. That is, the variable gain control circuit 12 changes the amplitude of the high-frequency signal RF IN by the gain G1 based on the gain control signal S2 and outputs the high-frequency signal RF 12 to the base of transistor Q1 via the capacitor 13 which is a DC cut capacitor.

[0040] Also, both the variable gain control circuit 12 and the resistor 14 may be present, or only one of them may be present. That is, both the high-frequency signal RF 12 and the bias voltage B1 may be input to the base of transistor Q1, or only one of them may be input.

[0041] One or both of the high-frequency signal RF 12 and the bias voltage B1 correspond to an example of the "first signal" of the present disclosure. Specifically, the high-frequency signal RF 12 has a voltage amplitude |V I1 | and |V I2A phase control signal S1 based on |, and a signal whose phase or gain is controlled by a gain control signal S2, with a voltage amplitude |V I1 | and |V I2 | is the "first signal" based on |. Also, the bias voltage B1, as described above, is a signal controlled by a bias control signal S3 based on the voltage amplitudes |V I1 | and |V I2 | and is the "first signal" based on |V I1 | and |V I2 |.

[0042] The 90° phase shift circuit 4 shifts the phase of the high-frequency signal RF IN by 90° and outputs the high-frequency signal RF3 to the variable phase control circuit 15.

[0043] The variable phase control circuit 15 changes the phase of the high-frequency signal RF3 by a phase θ2 based on the phase control signal S4 and outputs the high-frequency signal RF 13 to the variable gain control circuit 16.

[0044] Note that the 90° phase shift circuit 4 may be omitted if the control circuit 19 adds a 90° offset to the phase control signal S4.

[0045] The variable gain control circuit 16 changes the amplitude of the high-frequency signal RF 13 by a gain G2 and outputs the high-frequency signal RF 14 to the base of the transistor Q2 via a capacitor 17 which is a DC cut capacitor.

[0046] The other end of the resistor 18 is electrically connected to the base of the transistor Q2. A bias voltage B2 is input to the base of the transistor Q2 from the other end of the resistor 18.

[0047] The emitter of the transistor Q2 is electrically connected to the reference potential. The collector of the transistor Q2 is electrically connected to the power supply potential VCC via a choke coil 32 and power is supplied.

[0048] Transistor Q2 outputs a current I corresponding to a high-frequency signal RF 14 and a bias voltage B2 from the collector to the other end 3b of the inverter circuit 3. add2

[0049] The current I add2 corresponds to an example of the "second current" of the present disclosure.

[0050] Note that when the compensation of the reactance component (imaginary component) of the impedance Z L ' is not required, the variable phase control circuit 15 may be omitted. That is, the variable gain control circuit 16 changes the amplitude of the high-frequency signal RF3 with a gain G2 based on the gain control signal S5, and outputs the high-frequency signal RF 14 to the base of the transistor Q2 via the capacitor 17 which is a DC cut capacitor.

[0051] Also, both the variable gain control circuit 16 and the resistor 18 may be provided, or only one of them may be provided. That is, both the high-frequency signal RF 14 and the bias voltage B2 may be input to the base of the transistor Q2, or only one of them may be input.

[0052] The high-frequency signal RF 14 and / or the bias voltage B2 corresponds to an example of the "second signal" of the present disclosure.

[0053] (Control target of impedance control circuit) If the impedance Z L ' deviates from the value assumed at the time of design, the characteristics of the amplifier 2 may deteriorate. For example, if the impedance Z L ' deviates significantly from the value assumed at the time of design, large distortion may occur in the high-frequency signals RF1 and RF2, leading to malfunction of surrounding communication devices. In particular, when the amplifier 2 is a Doherty amplifier, it is said that the tolerance to changes in the impedance Z L ' is low.

[0054] Therefore, the impedance control circuit 10 controls so that the impedance Z L ’ approaches the value assumed at the time of design. Thereby, the impedance control circuit 10 can suppress the distortion of the high-frequency signals RF1 and RF2.

[0055] (Operation of impedance control circuit) [1] The inverter circuit 3 has a proportional relationship between the voltage V I2 and the current I I1 at the carrier frequency. That is, the following equation (1) holds. V I2 =-j*Z INV *I I1 ···(1)

[0056] In equation (1), Z INV is called the inverter impedance and is a positive or negative real number. Note that the inverter impedance corresponds to the image impedance of the two-terminal pair network.

[0057] Also, the inverter circuit 3 has a proportional relationship between the current I I2 and the voltage V I1 at the carrier frequency. That is, the following equation (2) holds. I I2 =-j*1 / Z INV *V I1 ···(2)

[0058] The control circuit 19 detects the voltage amplitudes |V I1 | and |V I2 | of the voltages V I1 and V I2 , and the phase difference (arg(V I1 ) - arg(V I2 )) between the voltage V I1 and the voltage V I2 ) to calculate the impedance Z INV . Specifically, the control circuit 19 calculates the voltage amplitudes |V I1 | and |V I2 of the voltages V I1|and| V I2 |are detected using detectors 21 and 22. Also, the control circuit 19 uses the voltage V derived from equations (1) and (2) I1 and the voltage V I2 to detect the phase difference (arg(V I1 ) - arg(V I2 )) using the phase difference detector 23. The control circuit 19 uses these detected voltage amplitudes |V I1 |and| V I2 , and the phase difference (arg(V I1 ) - arg(V I2 )) to calculate the impedance Z INV .

[0059] Furthermore, the impedance control circuit 10 can control the impedance Z add1 ' seen from the amplifier 2 by outputting a high-frequency current I add2 or I L to one end of the inverter circuit 3.

[0060] Specifically, when the impedance Z L ' is low, the impedance control circuit 10 outputs the current I add1 to one end 3a of the inverter circuit 3. The current I add1 flows through the inverter circuit 3. Therefore, the current I L ' decreases by the amount of the current I add1 . That is, the impedance control circuit 10 can reduce the current I L ' output by the amplifier 2. As a result, the impedance control circuit 10 can increase the impedance Z L ' seen from the amplifier 2 to the load 150 side, and can suppress fluctuations in the impedance Z L '.

[0061] Also, when the impedance Z L ' is high, the impedance control circuit 10 outputs the current I add2 to the other end 3b of the inverter circuit 3. The current I add2 flows through the load 150. Therefore, the current I I2 is the current Iadd2 decreases by that amount. That is, the impedance control circuit 10 can reduce the current I output by the inverter circuit 3. I2 When the current I I2 decreases, due to the characteristics of the inverter circuit 3, the voltage V' output by the amplifier 2 becomes low. As a result, the impedance control circuit 10 can lower the impedance Z' seen from the amplifier 2 to the load 150 side, and can suppress fluctuations in the impedance Z'. L Moreover, if the impedance control circuit 10 includes the variable phase control circuits 11 and 15, the following operation can be obtained. That is, the impedance control circuit 10 controls the phases of the currents I and I based on the phase difference (arg(V)-arg(V)). By doing so, the control of the impedance Z' can also act on the reactance component (imaginary component). As a result, the impedance control circuit 10 can further suppress fluctuations in the impedance Z'. L L

[0062] In FIG. 1, as an example, the inverter circuit 3 has a characteristic impedance Z0 and is a line that becomes 1 / 4 wavelength at the carrier frequency (resonance frequency). However, the inverter circuit 3 is not limited to this, and it is sufficient that the above equations (1) and (2) hold at the carrier frequency. I1 I2 add1 and I add2 L L

[0063] [2] Circuits that are already known to satisfy equations (1) and (2) include circuits composed of lumped constant elements, circuits combining transmission lines and lumped constant elements, and circuits using transformers. These circuits will be described in other embodiments.

[0064]

[0065] ​​​​​​​​From Equation (1) and Equation (2), the inverter circuit 3 is a circuit in which the following Equation (3) holds near the carrier frequency.

Equation

[0066] For example, it is assumed that the amplifier 2 is designed with the impedance Z L ’ being 50 Ω (ohms), and the characteristic impedance Z0 is also 50 Ω, but the present disclosure is not limited thereto. When the characteristic impedance Z0 is different from the assumption of the impedance Z L ’ (50 Ω), the voltage amplitude |V I1 | or |V I2 | can be multiplied by a constant and the following processing can be performed.

[0067] [3] First, the control of the impedance control circuit 10 when the impedance Z L ’ becomes low will be described. When the impedance Z L ’ is lower than the assumption (for example, 50 Ω), the voltage amplitude |V I1 | is observed to be smaller than the voltage amplitude |V I2 |.

[0068] In that case, the impedance control circuit 10 outputs a high-frequency current I add1 to one end 3a of the inverter circuit 3 to reduce the current I L ’. Thereby, the impedance control circuit 10 can increase the impedance Z L ’.

[0069] For example, the control circuit 19 controls the gain G1 of the variable gain control circuit 12 by the following Equation (4). In Equation (4), α1 is the sensitivity (coefficient, constant) for controlling the gain G1 and is determined in view of the gain of the transistor Q1.

Equation

[0070] As shown in Equation (4), as the difference between the voltage amplitudes |V I2 | and |V I1 | increases, the amplitude of the high-frequency signal RF input to the base of the transistor Q1 is increased, and the high-frequency current I 12 output from the collector of the transistor Q1 is increased. add1

[0071] Equation (4) is the simplest equation for the impedance control circuit 10 to achieve the control target, and the present disclosure is not limited thereto. The impedance control circuit 10 may use the ratio between the voltage amplitudes |V I2 | and |V I1 | instead of the difference therebetween. Further, the impedance control circuit 10 may use a combination thereof or a higher-order function such as a quadratic function. I2 | and |V I1 |.

[0072] By performing the control shown in Equation (4), when the output impedance of the amplifier circuit 1 deviates from the assumed value and the impedance Z L ' seen from the amplifier 2 tends to be a low impedance, the impedance Z L ' can be automatically increased. Thereby, the amplifier 2 is released from the low impedance state.

[0073] Furthermore, when a reactance component (imaginary component) occurs in the inverter circuit 3, the phase difference (arg(V I1 ) - arg(V I2 )) deviates from 90°. The control circuit 19 controls the phase θ1 based on the amount by which the phase difference (arg(V I1 ) - arg(V I2 )) deviates from 90°. Thereby, the impedance control circuit 10 can control the phase of the high-frequency signal RF 12 input to the base of the transistor Q1. Therefore, the impedance control circuit 10 can also compensate for the reactance component of the impedance Z L '.

[0074] For example, the control circuit 19 controls the phase θ1 by the following equation (5). In equation (5), β1 is the sensitivity (coefficient, constant) for controlling the phase. θ1(deg)=-β1(arg(V I1 )-arg(V I2 )-90) ···(5)

[0075] [4] Next, the control of the impedance control circuit 10 when the impedance Z L ’ becomes high will be described. When the impedance Z L ’ is higher than the assumption (for example, 50 Ω), the voltage amplitude |V I1 | is observed to be larger than the voltage amplitude |V I2 |.

[0076] In that case, the impedance control circuit 10 outputs a high-frequency current I add2 to the other end 3b of the inverter circuit 3, thereby reducing the current I I2 . When the current I I2 decreases, due to the characteristics of the inverter circuit 3, the voltage V I1 decreases. As a result, the impedance control circuit 10 can lower the voltage V L ’, and can lower the impedance Z L ’.

[0077] For example, the control circuit 19 controls the gain G2 of the variable gain control circuit 16 by the following equation (6). In equation (6), α2 is the sensitivity (coefficient, constant) for controlling the gain G2, and is determined in view of the gain of the transistor Q2.

Equation

[0078] As shown in equation (6), the impedance control circuit 10 compares the voltage amplitude |V I1 | with the voltage amplitude |V I2The greater the difference from [a certain value], the greater the amplitude of the high-frequency signal RF input to the base of transistor Q2 14 and the greater the high-frequency current I add2 output from the collector of transistor Q2.

[0079] Equation (6) is the simplest equation for the impedance control circuit 10 to achieve the control target, and the present disclosure is not limited thereto. The impedance control circuit 10 may use the ratio between the voltage amplitude |V I1 | and the voltage amplitude |V I2 | instead of the difference therebetween. Further, the impedance control circuit 10 may use their combination or a higher-order function such as a quadratic function. I1 | and the voltage amplitude |V I2 |.

[0080] By performing the control shown in Equation (6), when the output impedance of the amplifier circuit 1 deviates from the assumed value and the impedance Z L ' seen from the amplifier 2 tends to be a high impedance, the impedance control circuit 10 can automatically lower the impedance Z L '. As a result, the amplifier 2 is released from the high-impedance state.

[0081] Furthermore, when a reactance component (imaginary component) occurs in the inverter circuit 3, the phase difference (arg(V I1 ) - arg(V I2 )) deviates from 90°. The control circuit 19 controls the phase θ2 based on the amount by which the phase difference (arg(V I1 ) - arg(V I2 )) deviates from 90°. Thereby, the impedance control circuit 10 can control the phase of the high-frequency signal RF 14 input to the base of the transistor Q2. Therefore, the impedance control circuit 10 can also compensate for the reactance component of the impedance Z L '.

[0082] For example, the control circuit 19 controls the phase θ2 according to the following equation (7): In equation (7), β2 is a sensitivity (coefficient, constant) for controlling the phase. θ2(deg)=β2(arg(V I1 )-arg(V I2 )-90) (7)

[0083] (Results of circuit simulation of impedance control circuit) 2 and 3 are diagrams showing the results of a circuit simulation of the amplifier circuit according to the first embodiment.

[0084] In the circuit simulations of Figures 2 and 3, the reflection coefficient of the load 150 was set to 0.25 (RL (return loss) = -12.0 dB, VSWR (voltage standing wave ratio) = 1.67), and the reflection phase was changed from 0° to 360° to perform the above-mentioned impedance control.

[0085] FIG. 2 is a Smith chart of the circuit simulation results. In FIG. 2, a waveform 200 is a Smith chart of the impedance Z L The waveform 201 represents the impedance Z L '.

[0086] 3, the horizontal axis represents the load phase and the vertical axis represents the return loss. In FIG. 3, a waveform 210 represents the return loss of the load 150, and a waveform 211 represents the return loss of the inverter circuit 3 as viewed from the amplifier 2.

[0087] Waveform 201 is located inside waveform 200. Waveform 211 is located below waveform 210. In other words, it can be seen that the return loss is lower. Therefore, the impedance Z L It can be seen that ' is approaching the value assumed at the time of design.

[0088] However, at the point 212 where the load phase is 90° and the point 213 where the load phase is 270°, |V I1 |=|V I2As a result, the gain G1 of the variable gain control circuit 12 and the gain G2 of the variable gain control circuit 16 both become 0. That is, the impedance control circuit 10 cannot sufficiently control the impedance Z L ’. However, when the load phase is 90° and 270°, there may be cases where it does not significantly degrade the performance of the amplifier 2 and is acceptable.

[0089] (Summary) As described above, the impedance detection circuit 20 can detect the impedance of the inverter circuit 3 while suppressing the increase in the circuit size by detecting the voltage amplitudes |V I1 | and |V I2 |, and the phase difference (arg(V I1 ) - arg(V I2 ))).

[0090] Also, when the impedance Z L ’ becomes low, the impedance control circuit 10 outputs the current I add1 to one end 3a of the inverter circuit 3, thereby increasing the impedance Z L ’ to the value assumed at the design time.

[0091] Also, when the impedance Z L ’ becomes high, the impedance control circuit 10 outputs the current I add2 to the other end 3b of the inverter circuit 3, thereby decreasing the impedance Z L ’ to the value assumed at the design time.

[0092] In this way, since the impedance Z L ’ seen from the load 150 side of the amplifier 2 in the amplifier circuit 1 is controlled to the value assumed at the design time, the distortion of the high-frequency signals RF1 and RF2 can be suppressed.

[0093] <Second Embodiment> Among the components of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

[0094] In the first embodiment, the case where all of the gain G1 and phase θ1 of the low-impedance compensation path and the gain G2 and phase θ2 of the high-impedance compensation path are controlled was described. However, partial effects can be obtained by performing any one or more of the controls.

[0095] (First example) Impedance Z L If it is only necessary to compensate only when ’becomes low, the 90° phase shift circuit 4, transistor Q2, variable phase control circuit 15, variable gain control circuit 16, capacitor 17, and resistor 18 may be omitted.

[0096] FIG. 4 is a diagram showing the configuration of the amplifier circuit of the first example of the second embodiment.

[0097] The amplifier circuit 1A does not include the 90° phase shift circuit 4 as compared with the amplifier circuit 1 (see FIG. 1). Further, the amplifier circuit 1A includes an impedance control circuit 10A instead of the impedance control circuit 10 as compared with the amplifier circuit 1.

[0098] The impedance control circuit 10A does not include the transistor Q2, variable phase control circuit 15, variable gain control circuit 16, capacitor 17, and resistor 18 as compared with the impedance control circuit 10.

[0099] The impedance control circuit 10A has an impedance Z L When ’becomes low, the current I add1 is output to one end 3a of the inverter circuit 3. As a result, the impedance control circuit 10A can increase the impedance Z L ’ and control it to the value assumed at the time of design.

[0100] (Second example) Impedance Z L If it is only necessary to compensate only when ’becomes high, the transistor Q1, variable phase control circuit 11, variable gain control circuit 12, capacitor 13, and resistor 14 may be omitted.

[0101] FIG. 5 is a diagram showing the configuration of the amplifier circuit according to the second example of the second embodiment.

[0102] The amplifier circuit 1B includes an impedance control circuit 10B instead of the impedance control circuit 10 as compared with the amplifier circuit 1 (see FIG. 1).

[0103] The impedance control circuit 10B does not include the transistor Q1, the variable phase control circuit 11, the variable gain control circuit 12, the capacitor 13, and the resistor 14 as compared with the impedance control circuit 10.

[0104] The impedance control circuit 10B outputs the current I L to the other end 3b of the inverter circuit 3 when the impedance Z add2 ' becomes high. Thereby, the impedance control circuit 10B can lower the impedance Z L ' and control it to the value assumed at the time of design.

[0105] (Third Example) FIG. 6 is a diagram showing the configuration of the amplifier circuit according to the third example of the second embodiment.

[0106] The amplifier circuit 1C includes an impedance control circuit 10C instead of the impedance control circuit 10 as compared with the amplifier circuit 1 (see FIG. 1).

[0107] The impedance control circuit 10C does not include the variable phase control circuit 11 and the variable phase control circuit 15 as compared with the impedance control circuit 10. Further, the impedance control circuit 10C includes an impedance detection circuit 20C instead of the impedance detection circuit 20 as compared with the impedance control circuit 10. The impedance detection circuit 20C does not include the phase difference detector 23 as compared with the impedance detection circuit 20.

[0108] FIGS. 7 and 8 are diagrams showing the circuit simulation results of the amplifier circuit according to the third example of the second embodiment.

[0109] In the circuit simulations of FIGS. 7 and 8, the reflection coefficient of the load 150 was set to 0.25 (R.L. (return loss)=-12.0 dB, VSWR (voltage standing wave ratio)=1.67), and the reflection phase was changed from 0° to 360° to perform impedance control.

[0110] FIG. 7 is a Smith chart of the circuit simulation results. In FIG. 7, waveform 200 represents the impedance Z of the load 150. L Waveform 221 represents the impedance Z' when looking from the amplifier 2 towards the load 150. L '

[0111] FIG. 8 is a diagram with the horizontal axis representing the load phase and the vertical axis representing the return loss. In FIG. 8, waveform 210 represents the return loss of the load 150, and waveform 211 represents the return loss of the inverter circuit 3 when viewed from the amplifier 2.

[0112] Waveform 221 is generally inside waveform 200. Also, waveform 221 is generally below waveform 210. That is, it can be seen that the return loss has decreased. Therefore, it can be seen that the impedance Z' is approaching the value assumed at the time of design. L '

[0113] However, in the vicinity of the point 223 where the load phase is 90° and in the vicinity of the point 224 where the load phase is 270°, instead of reducing the impedance mismatch in the real part, the impedance mismatch in the imaginary part increases. As a result, the return loss of the inverter circuit 3 is larger than the return loss of the load 150. However, it can be seen that the impedance mismatch in the real axis direction (real part) is sufficiently low and is sufficiently practical.

[0114] <Third Embodiment> Among the components of the third embodiment, for the components that are the same as those in other embodiments, the same reference numerals are given and the description is omitted.

[0115] In the first and second embodiments, the inverter circuit 3 is a 1 / 4 wavelength line. However, the inverter circuit 3 Vertical connection only needs the diagonal components of the parameters ( So-called F parameter see the right side of Equation (3)) to be 0 at the operating frequency, and various variations are conceivable. The diagonal components being 0 is an ideal discussion. At the frequency used, it is only necessary that the absolute value of the product of the diagonal components is smaller than the absolute value of the product of the off-diagonal components. Circuits having such characteristics will be exemplified below.

[0116] (First Example) FIG. 9 is a diagram showing the configuration of the inverter circuit of the first example of the third embodiment.

[0117] The inverter circuit 3A includes inductors 41 and 42 and a capacitor 43.

[0118] One end of the inductor 41 is electrically connected to one end 3a of the inverter circuit 3A. The other end of the inductor 41 is electrically connected to one end of the inductor 42 and one end of the capacitor 43.

[0119] The other end of the capacitor 43 is electrically connected to the reference potential.

[0120] The other end of the inductor 42 is electrically connected to the other end 3b of the inverter circuit 3A.

[0121] The inverter circuit 3A can also be regarded as a T-type low-pass filter.

[0122] (Second Example) FIG. 10 is a diagram showing the configuration of the inverter circuit of the second example of the third embodiment.

[0123] The inverter circuit 3B includes an inductor 44 and capacitors 45 and 46.

[0124] One end of the inductor 44 is electrically connected to one end 3a of the inverter circuit 3B and one end of the capacitor 45. The other end of the inductor 44 is electrically connected to the other end 3b of the inverter circuit 3B and one end of the capacitor 46.

[0125] The other ends of the capacitor 45 and the capacitor 46 are electrically connected to the reference potential.

[0126] The inverter circuit 3B can also be regarded as a π-type low-pass filter.

[0127] (Third Example) FIG. 11 is a diagram showing the configuration of the inverter circuit of the third example of the third embodiment.

[0128] The inverter circuit 3C includes capacitors 47 and 48 and an inductor 49.

[0129] One end of the capacitor 47 is electrically connected to one end 3a of the inverter circuit 3C. The other end of the capacitor 47 is electrically connected to one end of the capacitor 48 and one end of the inductor 49.

[0130] The other end of the inductor 49 is electrically connected to the reference potential.

[0131] The other end of the capacitor 48 is electrically connected to the other end of the inverter circuit 3C.

[0132] The inverter circuit 3C can also be regarded as a T-type high-pass filter.

[0133] (Fourth Example) FIG. 12 is a diagram showing the configuration of the inverter circuit of the fourth example of the third embodiment.

[0134] The inverter circuit 3D includes a capacitor 50 and inductors 51 and 52.

[0135] One end of the capacitor 50 is electrically connected to one end 3a of the inverter circuit 3D and one end of the inductor 51. The other end of the capacitor 50 is electrically connected to the other end 3b of the inverter circuit 3D and one end of the inductor 52.

[0136] The other ends of the inductor 51 and the inductor 52 are electrically connected to the reference potential.

[0137] The inverter circuit 3D can also be regarded as a π-type high-pass filter.

[0138] (Example 5) FIG. 13 is a diagram showing the configuration of the inverter circuit according to the fifth example of the third embodiment.

[0139] The inverter circuit 3E includes a first winding 53, a second winding 54, and capacitors 55 and 56.

[0140] The first winding 53 and the second winding 54 are electromagnetically coupled.

[0141] The capacitor 55 is electrically connected in parallel to the first winding 53.

[0142] The capacitor 56 is electrically connected in parallel to the second winding 54.

[0143] One end of the first winding 53 and one end of the capacitor 55 are electrically connected to one end 3a of the inverter circuit 3E. The other end of the first winding 53 and the other end of the capacitor 55 are electrically connected to the reference potential.

[0144] One end of the second winding 54 and one end of the capacitor 56 are electrically connected to the other end 3b of the inverter circuit 3E. The other end of the second winding 54 and the other end of the capacitor 56 are electrically connected to the reference potential.

[0145] The inverter circuit 3E can also be regarded as a transformer.

[0146] In this way, the inverter circuit 3 can be replaced with various circuits, and in some cases, broadband and miniaturization can be expected.

[0147] <Fourth Embodiment> Among the components of the fourth embodiment, the same components as those in other embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0148] For an inverter circuit having a configuration that can also be used as a balun, such as the inverter circuit 3E (see FIG. 13), as shown in FIG. 14 below, the current I L ’ (or the voltage Vadd converted from the current I L ’) is injected in series, impedance control can be achieved.

[0149] FIG. 14 is a diagram showing the configuration of the amplifier circuit according to the fourth embodiment.

[0150] The amplifier circuit 1D includes an inverter circuit 3E instead of the inverter circuit 3 as compared with the amplifier circuit 1 (see FIG. 1). Further, the amplifier circuit 1D further includes a scalar circuit 5 as compared with the amplifier circuit 1.

[0151] One end of the first winding 53 of the inverter circuit 3E and one end of the capacitor 55 are electrically connected to the first terminal 3c of the inverter circuit 3E. The other end of the first winding 53 and the other end of the capacitor 55 are electrically connected to the second terminal 3d of the inverter circuit 3E.

[0152] One end of the second winding 54 of the inverter circuit 3E and one end of the capacitor 56 are electrically connected to the third terminal 3e of the inverter circuit 3E. The other end of the second winding 54 and the other end of the capacitor 56 are electrically connected to the fourth terminal 3f of the inverter circuit 3E.

[0153] The first terminal 3c of the inverter circuit 3E is electrically connected to the output terminal of the amplifier 2, and the high-frequency signal RF1 is input thereto. The second terminal 3d of the inverter circuit 3E is electrically connected to the load 150, and outputs the high-frequency signal RF2.

[0154] The third terminal 3e of the inverter circuit 3E is electrically connected to the reference potential. The fourth terminal 3f of the inverter circuit 3E is electrically connected to the collector of the transistor Q2, and the current I add2 is input.

[0155] The voltage between the third terminal 3e and the fourth terminal 3f of the inverter circuit 3E is the voltage V I2 is.

[0156] The scaler circuit 5 includes a first winding 61, a second winding 62, and capacitors 63 and 64.

[0157] One end of the first winding 61 is electrically connected to the first terminal 5a of the scaler circuit 5. The other end of the first winding 61 is electrically connected to one end of the capacitor 63 which is a DC cut capacitor.

[0158] The other end of the capacitor 63 is electrically connected to the second terminal 5b of the scaler circuit 5.

[0159] One end of the second winding 62 and one end of the capacitor 64 are electrically connected to the third terminal 5c of the scaler circuit 5. The other end of the second winding 62 and the other end of the capacitor 64 are electrically connected to the fourth terminal 5d of the scaler circuit 5.

[0160] The first terminal 5a and the third terminal 5c of the scaler circuit 5 are electrically connected to the reference potential.

[0161] The fourth terminal 5d of the scaler circuit 5 is electrically connected to the collector of the transistor Q1, and the current I add1 is input. The second terminal 5b of the scaler circuit 5 is electrically connected to the output terminal of the amplifier 2 and the first terminal 3c of the inverter circuit 3E, and outputs the current I add1 '.

[0162] The voltage between the third terminal 5c and the fourth terminal 5d of the scaler circuit 5 is the voltage V I1 is.

[0163] Unlike the inverter circuit 3E, the scaler circuit 5 Vertical connection parameter (So-called F parameter) is a circuit in which the absolute value of the product of the diagonal components is greater than the absolute value of the product of the off-diagonal components.

[0164] The scaler circuit 5 may be included in the impedance detection circuit 20.

[0165] The scaler circuit 5, when the current I add1 is not large, can output a current I add1 ' which is a constant multiple (for example, equal multiple, twice, etc.) of the current I add1 to the first terminal 3c of the inverter circuit 3E.

[0166] Note that when the current I add1 is sufficiently large, the scaler circuit 5 is unnecessary, and the collector of the transistor Q1 is electrically connected to the output terminal of the amplifier 2 and the first terminal 3c of the inverter circuit 3E, and the current I add1 may be connected so as to be directly output from the collector of the transistor Q1 to the first terminal 3c of the inverter circuit 3E.

[0167] Also, the scaler circuit 5, when the voltage V L ' is large, can reduce the voltage V L ' to one constant fraction (for example, one-half, etc.) and output it to the collector of the transistor Q1 and the detector 21. Thereby, the scaler circuit 5 can suppress the transistor Q1 from being damaged and can change the detectable range of the detector 21.

[0168] FIG. 15 and FIG. 16 are diagrams showing the circuit simulation results of the amplifier circuit according to the fourth embodiment.

[0169] In the circuit simulations of FIGS. 15 and 16, the reflection coefficient of the load 150 was set to 0.25 (R.L. (return loss) = -12.0 dB, VSWR (voltage standing wave ratio) = 1.67), the reflection phase was changed from 0° to 360°, and impedance control was performed.

[0170] FIG. 15 is a Smith chart of circuit simulation results. In FIG. 15, waveform 200 represents the impedance Z of load 150 L and waveform 231 represents the impedance Z L ' as seen from the side of load 150 looking into amplifier 2.

[0171] FIG. 16 is a diagram with the horizontal axis representing the load phase and the vertical axis representing the return loss. In FIG. 16, waveform 210 represents the return loss of load 150, and waveform 241 represents the return loss of inverter circuit 3E as seen from amplifier 2.

[0172] In the configuration of amplifier circuit 1D, the injection location of current I add1 and the detection location of voltage V I1 can be freely selected to be on the side of load 150 or on the side of amplifier 2, rather than on the side of inverter circuit 3E.

[0173] <Fifth Embodiment> Among the components of the fifth embodiment, components identical to those in other embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0174] In the first, second, and fourth embodiments, the case where any one of inverter circuits 3 to 3E is additionally provided on the side of load 150 rather than on the side of amplifier 2 has been described. However, when amplifier 2 is a Doherty amplifier, any one of inverter circuits 3 to 3E is included in a Doherty combiner, and the Doherty combiner can be shared for impedance control.

[0175] FIG. 17 is a diagram showing the configuration of the amplifier circuit of the fifth embodiment. Amplifier circuit 1E is a Doherty amplifier circuit.

[0176] Amplifier circuit 1E includes a carrier amplifier 6, a peak amplifier 7, and a Doherty combiner 8, instead of amplifier 2, as compared with amplifier circuit 1 (see FIG. 1).

[0177] The Doharty synthesizer 8 includes an inverter circuit 3.

[0178] Each of the carrier amplifier 6 and the peak amplifier 7 has two stages, but the present disclosure is not limited thereto. Each of the carrier amplifier 6 and the peak amplifier 7 may have one stage or three or more stages.

[0179] The carrier amplifier 6 amplifies the high-frequency signal RF IN and outputs the high-frequency signal RF 21 to one end 3a of the inverter circuit 3.

[0180] Let the impedance seen from the side of the load 150 of the carrier amplifier 6 be the impedance Z C Let the output voltage of the carrier amplifier 6 be the voltage V C and the output current be the current I C .

[0181] The connection relationship of the carrier amplifier 6, the variable phase control circuit 11, the variable gain control circuit 12, the capacitor 13, the resistor 14, and the transistor Q1 is the same as the connection relationship of the amplifier 2, the variable phase control circuit 11, the variable gain control circuit 12, the capacitor 13, the resistor 14, and the transistor Q1 (see FIG. 1), so the description is omitted.

[0182] In the inverter circuit 3, the high-frequency signal RF 21 is input to one end 3a, and the high-frequency signal RF 22 is output from the other end 3b to the node N1.

[0183] The peak amplifier 7 amplifies the high-frequency signal RF3 and outputs the high-frequency signal RF 23 to the node N1.

[0184] Let the impedance seen from the side of the load 150 of the peak amplifier 7 be the impedance Z P Let the output voltage of the peak amplifier 7 be the voltage V P and the output current be the current I P .

[0185] The connection relationships of the peak amplifier 7, variable phase control circuit 15, variable gain control circuit 16, capacitor 17, resistor 18, and transistor Q2 are the same as those of the amplifier 2, variable phase control circuit 11, variable gain control circuit 12, capacitor 13, resistor 14, and transistor Q1 (see Fig. 1), so the description thereof will be omitted.

[0186] At node N1, the high-frequency signal RF 22 and the high-frequency signal RF 23 are combined to generate a high-frequency signal RF 24 . The combined high-frequency signal RF 24 is output to the load 150.

[0187] By sharing the inverter circuit 3 for the combination of the high-frequency signal RF 22 and the high-frequency signal RF 23 and impedance control, miniaturization can be achieved.

[0188] However, in the Doherty amplifier circuit, the impedance Z C seen from the side of the carrier amplifier 6 to the load 150 varies with the input power (the power of the high-frequency signal RF IN ), which is a characteristic of high efficiency. Therefore, if the techniques of the first, second, and fourth embodiments are directly used in the amplifier circuit 1E, the impedance Z C will be controlled to be constant, and the efficiency may decrease.

[0189] Therefore, the control circuit 19 may change the control of the gains G1 and G2 and the control of the bias voltages B1 and B2 according to the input power (the power of the high-frequency signal RF IN or the power of the high-frequency signal RF3) or the output power (the power of the high-frequency signal RF 21 , RF 22 , or RF 24 ).

[0190] Specifically, for the control of the gains G1 and G2, controls such as the following equations (8) and (9) can be considered.

[0191] [Number]

[0192] [Number]

[0193] In Expressions (8) and (9), V offset is a parameter that varies depending on the input power or the output power.

[0194] As a result, the amplifier circuit 1E can match the impedance Z C seen from the carrier amplifier 6 to the load 150 to different impedances according to the input power or the output power.

[0195] <Sixth Embodiment> Among the components of the sixth embodiment, the same components as those in other embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0196] In the fifth embodiment, each of the carrier amplifier 6 and the peak amplifier 7 has a single-ended output, and the case where the Doherty synthesizer 8 performs parallel synthesis of the high-frequency signal RF 21 and the high-frequency signal RF 23 has been described. However, the present disclosure is not limited thereto. Each of the carrier amplifier and the peak amplifier may have a differential output, and the Doherty synthesizer may perform serial synthesis of two differential signals.

[0197] FIG. 18 is a diagram showing the configuration of the amplifier circuit according to the sixth embodiment. The amplifier circuit 1F is a Doherty amplifier circuit.

[0198] Amplifier circuit 1F includes carrier amplifiers 6-1 and 6-2 instead of carrier amplifier 6 as compared with amplifier circuit 1E (see FIG. 17). Further, amplifier circuit 1F includes peak amplifiers 7-1 and 7-2 instead of peak amplifier 7 as compared with amplifier circuit 1E. Further, amplifier circuit 1F includes Doherty synthesizer 8F instead of Doherty synthesizer 8 as compared with amplifier circuit 1E. Doherty synthesizer 8F includes inverter circuit 3E and scaler circuit 5. Further, amplifier circuit 1F further includes baluns 71 and 72 as compared with amplifier circuit 1E.

[0199] Carrier amplifiers 6-1 and 6-2 constitute differential carrier amplifiers. Carrier amplifier 6-1 is a positive-polarity carrier amplifier. Carrier amplifier 6-2 is a negative-polarity carrier amplifier.

[0200] Peak amplifiers 7-1 and 7-2 constitute differential peak amplifiers. Peak amplifier 7-1 is a positive-polarity peak amplifier. Peak amplifier 7-2 is a negative-polarity peak amplifier.

[0201] Each of carrier amplifiers 6-1 and 6-2 and peak amplifiers 7-1 and 7-2 has two stages, but the present disclosure is not limited thereto. Each of carrier amplifiers 6-1 and 6-2 and peak amplifiers 7-1 and 7-2 may have one stage or three or more stages.

[0202] Balun 71 constitutes differential signals RF and RF based on high-frequency signal RF3 and outputs them. 31 and RF 32 for output.

[0203] Carrier amplifier 6-1 amplifies high-frequency signal RF and outputs it to one end of the second winding 62 of scaler circuit 5. 31 to 33 output.

[0204] Let the impedance seen from the side of load 150 of carrier amplifier 6-1 be impedance Z. C Let the output voltage of carrier amplifier 6-1 be voltage V.C and set the output current to current I C and set it as such.

[0205] Since the connection relationships of the carrier amplifier 6-1, variable phase control circuit 11-1, variable gain control circuit 12-1, capacitor 13-1, resistor 14-1, and transistor Q1 are the same as those of the amplifier 2, variable phase control circuit 11, variable gain control circuit 12, capacitor 13, resistor 14, and transistor Q1 (see Figure 1), the description thereof is omitted.

[0206] The carrier amplifier 6-2 amplifies the high-frequency signal RF 32 and outputs the amplified high-frequency signal RF 34 to the other end of the second winding 62 of the scalar circuit 5.

[0207] Let the impedance seen from the side of the load 150 of the carrier amplifier 6-2 be impedance Z C '. Let the output voltage of the carrier amplifier 6-2 be voltage V C ' and the output current be current I C '.

[0208] Since the connection relationships of the carrier amplifier 6-2, variable phase control circuit 11-2, variable gain control circuit 12-2, capacitor 13-2, resistor 14-2, and transistor Q1' are the same as those of the amplifier 2, variable phase control circuit 11, variable gain control circuit 12, capacitor 13, resistor 14, and transistor Q1 (see Figure 1), the description thereof is omitted.

[0209] The balun 72 forms differential signals based on the high-frequency signal RF IN and outputs the high-frequency signals RF 35 and RF 36 that constitute the differential signals.

[0210] The peak amplifier 7-1 amplifies the high-frequency signal RF 35 and outputs the amplified high-frequency signal RF 37 to one end of the first winding 53 of the inverter circuit 3E.

[0211] Let the impedance seen from the side of the load 150 of the peak amplifier 7-1 be the impedance Z. P Let the output voltage of the peak amplifier 7-1 be the voltage V. P Let the output current be the current I. P

[0212] The connection relationships of the peak amplifier 7-1, the variable phase control circuit 15-1, the variable gain control circuit 16-1, the capacitor 17-1, the resistor 18-1, and the transistor Q2 are the same as those of the amplifier 2, the variable phase control circuit 11, the variable gain control circuit 12, the capacitor 13, the resistor 14, and the transistor Q1 (see Fig. 1), so the description is omitted.

[0213] The peak amplifier 7-2 amplifies the high-frequency signal RF. 36 and outputs the high-frequency signal RF 38 to the other end of the first winding 53 of the inverter circuit 3E.

[0214] Let the impedance seen from the side of the load 150 of the peak amplifier 7-2 be the impedance Z P ’. Let the output voltage of the peak amplifier 7-2 be the voltage V P ’ and the output current be the current I P ’.

[0215] The connection relationships of the peak amplifier 7-2, the variable phase control circuit 15-2, the variable gain control circuit 16-2, the capacitor 17-2, the resistor 18-2, and the transistor Q2’ are the same as those of the amplifier 2, the variable phase control circuit 11, the variable gain control circuit 12, the capacitor 13, the resistor 14, and the transistor Q1 (see Fig. 1), so the description is omitted.

[0216] One end of the second winding 54 of the inverter circuit 3E is electrically connected to the reference potential. The other end of the second winding 54 of the inverter circuit 3E is electrically connected to one end of the first winding 61 of the scaler circuit 5. From the capacitor 63 of the scaler circuit 5, differential signals (high-frequency signals RF 33 and RF 34 ) and differential signals (high-frequency signals RF 37 and RF 38 ​The high-frequency signal RF synthesized in series with 39 is output to the load 150.

[0217] In the present embodiment, the phase difference detector 23 is the high-frequency signal RF which is the output signal of the positive-polarity carrier amplifier 6-1 33 and the high-frequency signal RF which is the output signal of the positive-polarity peak amplifier 7-1 37 and the phase difference (arg(V C ) - arg(V P )) is to be detected, but the present disclosure is not limited thereto. The phase difference detector 23 may detect the phase difference between the high-frequency signal RF which is the output signal of the negative-polarity carrier amplifier 6-2 34 and the high-frequency signal RF which is the output signal of the negative-polarity peak amplifier 7-2 38 . Further, the phase difference detector 23 may detect the phase difference between the high-frequency signal RF which is the output signal of the positive-polarity carrier amplifier 6-1 33 and the high-frequency signal RF which is the output signal of the negative-polarity peak amplifier 7-2 38 . Further, the phase difference detector 23 may detect the phase difference between the high-frequency signal RF which is the output signal of the negative-polarity carrier amplifier 6-2 34 and the high-frequency signal RF which is the output signal of the positive-polarity peak amplifier 7-1 37 . Further, the phase difference detector 23 may average two or more of the above phases.

[0218] Furthermore, the phase difference detector 23 may calculate the phase difference between the carrier side and the peak side using the amplitudes and phases of the differential signal on the carrier side (the high-frequency signals RF 33 and RF 34 ) and the differential signal on the peak side (the high-frequency signals RF 37 and RF 38 ).

[0219] The phase control signal S input to the variable phase control circuit 11-2 on the negative-polarity side 1-2 , the gain control signal S input to the variable gain control circuit 12-2 2-2 and the bias control signal S input to the resistor 14-2 3-2is the phase control signal S input to the variable phase control circuit 11-1 on the positive polarity side 1-1 and the gain control signal S input to the variable gain control circuit 12-1 2-1 and the bias control signal S input to the resistor 14-1 3-1 may be the same as each other, but the present disclosure is not limited thereto.

[0220] High-frequency signal RF 33 and the high-frequency signal RF 34 As a result of comparing (for example, comparison between |V C | and |V C ’|, arg(V C ) - arg(V C ’), etc.), the gain, phase difference, and bias point may be controlled. Thereby, the amplifier circuit 1F can mitigate the influence on the differential pair generated by load fluctuations.

[0221] The phase control signal S input to the variable phase control circuit 15-2 4-2 and the gain control signal S input to the variable gain control circuit 16-2 5-2 and the bias control signal S input to the resistor 18-2 6-2 are also the same as above.

[0222] <Seventh Embodiment> Among the components of the seventh embodiment, the same components as those in other embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0223] The load detection technique in the first to sixth embodiments can also be combined with other control techniques. For example, the case where the target amplifier is a Doherty amplifier will be described. Generally, as described above, a Doherty amplifier may greatly change its characteristics (performance degradation) with respect to load fluctuations. The amplifier circuit 1F of the sixth embodiment described above can improve the above characteristics, but the seventh embodiment can also improve the above characteristics.

[0224] FIG. 19 is a diagram showing the configuration of the amplifier circuit of the seventh embodiment. The amplifier circuit 1G is a Doherty amplifier circuit.

[0225] The amplifier circuit 1G includes a first bias circuit 81 as compared with the amplifier circuit 1E (see FIG. 17). The first bias circuit 81 variably controls the bias of the carrier amplifier 6. Further, the amplifier circuit 1G includes a second bias circuit 82 as compared with the amplifier circuit 1E. The second bias circuit 82 variably controls the bias of the peak amplifier 7.

[0226] The first bias circuit 81 outputs a bias signal B I1 | and a voltage amplitude |V I2 | to the base (or gate) of the first-stage amplifier 6a of the carrier amplifier 6, and outputs the bias signal B CD to the base (or gate) of the final-stage amplifier 6b. CF

[0227] The second bias circuit 82 outputs a bias signal B I1 | and a voltage amplitude |V I2 | to the base (or gate) of the first-stage amplifier 7a of the peak amplifier 7, and outputs the bias signal B PD to the base (or gate) of the final-stage amplifier 7b. PF

[0228] Generally, it is known that the characteristic variation of a Doherty amplifier with respect to load variation can be improved by controlling the bias of any one or more bases (or gates) of the amplifiers of each stage of the carrier amplifier and the amplifiers of each stage of the peak amplifier. The amplifier circuit 1G can provide a high-performance Doherty amplifier even when a load variation occurs by controlling the bias of any one or more of the first-stage amplifier 6a and the final-stage amplifier 6b of the carrier amplifier 6, and the first-stage amplifier 7a and the final-stage amplifier 7b of the peak amplifier 7 according to the load situation.

[0229] Hereinafter, the control of the amplifier circuit 1G will be described taking the case of low impedance as an example. In the case of high impedance, the same effect can be obtained by controlling so as to perform the reverse operation.

[0230] When the load 150 has a low impedance, for example, |V I2 | > |V I1 |. In that case, the impedance Z seen from the carrier amplifier 6 to the load 150 side C becomes a high impedance. When the impedance Z C becomes a high impedance, the gain of the carrier amplifier 6 changes to a higher value, and the saturation power changes to a lower value. The amplifier circuit 1G can suppress characteristic variations due to load fluctuations by performing control to compensate for this.

[0231] Specifically, the first bias circuit 81 suppresses an increase in the gain of the carrier amplifier 6 by reducing the bias signals B CD and B CF below the case of the assumed impedance (for example, when |V I2 | = |V I1 |). In addition, the second bias circuit 82 increases the bias signals B PD and B PF above the case of the assumed impedance. Thereby, it is possible to compensate for the fact that the peak amplifier 7 rises and the carrier amplifier 6 saturates early because the saturation power of the carrier amplifier 6 is low.

[0232] In the seventh embodiment, the case where the amplifier circuit 1G performs parallel synthesis of the high-frequency signal RF 21 and the high-frequency signal RF 23 has been described, but the present disclosure is not limited to this. When the amplifier circuit 1G performs serial synthesis of the high-frequency signal RF 21 and the high-frequency signal RF 23 , the polarity of the detected voltage and the polarity of the bias control become opposite to those in the above-described parallel synthesis case.

[0233] Note that the bias point of the peak amplifier 7 may utilize control techniques such as those described in U.S. Patent Application Publication No. 2021 / 0036661 and U.S. Patent Application Publication No. 2016 / 0241209. By reflecting the comparison result of the voltage amplitude or the comparison result of the voltage phase in the bias point of the peak amplifier 7, a Doherty amplifier compensated for load fluctuations can be obtained.

[0234] (Equivalent Circuit) FIG. 20 is a diagram showing the configuration of an equivalent circuit of the amplifier circuit according to the seventh embodiment.

[0235] The amplifier 91 in FIG. 20 corresponds to the combination of the capacitor 13, the resistor 14, and the transistor Q1 in FIG. 19. The amplifier 92 corresponds to the combination of the capacitor 17, the resistor 18, and the transistor Q2 in FIG. 19.

[0236] It can be seen that the amplifier 91 (transistor Q1) for impedance control is connected in parallel with the final-stage amplifier 6b of the carrier amplifier 6.

[0237] It can be seen that the amplifier 92 (transistor Q2) for impedance control is connected in parallel with the final-stage amplifier 7b of the peak amplifier 7.

[0238] <Eighth Embodiment> Among the components of the eighth embodiment, the same components as those in other embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0239] FIG. 21 is a diagram showing the configuration of the amplifier circuit according to the eighth embodiment. The amplifier circuit 1H is a Doherty amplifier circuit.

[0240] The amplifier circuit 1H includes a variable attenuator 101 and a detector 102 instead of the second bias circuit 82 as compared with the amplifier circuit 1G (see FIG. 19).

[0241] The variable attenuator 101 attenuates the high-frequency signal RF3 based on the signal S7 and outputs it to the detector 102. The signal S7 is a signal representing the drive level of the final-stage amplifier 6b of the carrier amplifier 6, and examples thereof include a saturation signal or a load detection signal, but the present disclosure is not limited thereto. The signal S7 is also a signal representing the level of the input power (the power of the high-frequency signal RF IN (the power of).

[0242] The detector 102 detects the high-frequency signal attenuated by the variable attenuator 101 and outputs bias signals B PD and B PF to the first-stage amplifier 7a and the final-stage amplifier 7b, respectively.

[0243] Even when the input power (the power of the high-frequency signal RF IN (the power of)) is not large, the amplification circuit 1H can perform circuit operation reflecting the load state, so that delay in control can be suppressed.

[0244] (Modification example) FIG. 22 is a diagram showing a configuration of a modification example of the amplification circuit according to the eighth embodiment.

[0245] The amplification circuit 1I further includes a drive level detector 111 and an envelope modulation circuit 112 as compared with the amplification circuit 1H (see FIG. 21).

[0246] The drive level detector 111 detects the drive level of the final-stage amplifier 6b of the carrier amplifier 6 and outputs a signal S DL representing the drive level to the envelope modulation circuit 112. The drive level detector 111 is exemplified as detecting the drive level of the final-stage amplifier 6b based on the voltage or current of the amplification transistor in the final-stage amplifier 6b or the voltage or current of the transistor in the first bias circuit 81, but the present disclosure is not limited thereto. The signal S DL is also a signal representing the level of the input power (the power of the high-frequency signal RF IN (the power of)).

[0247] The envelope modulation circuit 112 has a voltage amplitude |VI1 |, voltage amplitude |V I2 |, phase difference (arg(V I1 ) - arg(V I2 )), and based on the signal S DL outputs the signal S7 to the variable attenuator 101.

[0248] The amplifier circuit 1I can realize an adaptive Doherty amplifier with controllable impedance.

[0249] Note that the above-described embodiments are for facilitating the understanding of the present invention and are not for limiting the interpretation of the present invention. The present invention can be changed / improved without departing from its gist, and the equivalents of the present invention are also included therein.

Explanation of Reference Numerals

[0250] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H amplifier circuits 2, 91, 92 amplifiers 3, 3A, 3B, 3C, 3D, 3E inverter circuits 4 90° phase shift circuit 5 scaler circuit 6, 6-1, 6-2 carrier amplifiers 7, 7-1, 7-2 peak amplifiers 8, 8F Doherty synthesizer 10, 10A, 10B, 10C impedance control circuits 11, 11-1, 11-2, 15, 15-1, 15-2 variable phase control circuits 12, 12-1, 12-2, 16, 16-1, 16-2 variable gain control circuits 13, 13-1, 13-2, 17, 17-1, 17-2 capacitors 14, 14-1, 14-2, 18, 18-1, 18-2 resistors 19 control circuit 20, 20C impedance detection circuits 21, 22, 102 detectors 23 phase difference detector 71, 72 baluns 81 First bias circuit 82 Second bias circuit 101 Variable attenuator 111 Drive level detector 112 Envelope modulation circuit

Claims

1. A first detector for detecting a first voltage amplitude at one end of an inverter circuit that receives a high-frequency signal at one end and outputs a signal from the other end; A second detector for detecting a second voltage amplitude at the other end of the inverter circuit; A phase difference detector for detecting a phase difference between the phase of the voltage at one end of the inverter circuit and the phase of the voltage at the other end of the inverter circuit; comprising The absolute value of the product of the diagonal components of the cascaded connection parameters of the inverter circuit is smaller than the absolute value of the product of the off-diagonal components; Impedance detection circuit.

2. The impedance detection circuit according to claim 1, further comprising a scaler circuit having one end electrically connected to one end of the inverter circuit and the other end electrically connected to the first detector; comprising The absolute value of the product of the diagonal components of the cascaded connection parameters of the scaler circuit is larger than the absolute value of the product of the off-diagonal components; Impedance detection circuit.

3. The impedance detection circuit according to claim 1 or 2, and A first transistor in which a first signal based on the first voltage amplitude and the second voltage amplitude is input to a base or gate, and a first current is output from a collector or drain to one end of the inverter circuit, and a second signal based on the first voltage amplitude and the second voltage amplitude is input to a base or gate, and at least one of a second transistor that outputs a second current from a collector or drain to the other end of the inverter circuit; comprising Impedance control circuit.

4. The impedance control circuit according to claim 3, The first transistor outputs the first current to one end of the inverter circuit when the input impedance of the inverter circuit is low; Impedance control circuit.

5. The impedance control circuit according to claim 4, a first variable gain control circuit that changes the amplitude of a high-frequency signal based on the first voltage amplitude and the second voltage amplitude and outputs the changed signal to the base or gate of the first transistor further comprising an impedance control circuit.

6. The impedance control circuit according to claim 5, a first variable phase control circuit that changes the phase of the high-frequency signal based on the first voltage amplitude, the second voltage amplitude, and the phase difference between the voltage phase at one end of the inverter circuit and the voltage phase at the other end of the inverter circuit further comprising an impedance control circuit.

7. The impedance control circuit according to claim 3, wherein the second transistor outputs the second current to the other end of the inverter circuit when the input impedance of the inverter circuit is high an impedance control circuit.

8. The impedance control circuit according to claim 7, a second variable gain control circuit that changes the amplitude of a high-frequency signal based on the first voltage amplitude and the second voltage amplitude and outputs the changed signal to the base or gate of the second transistor further comprising an impedance control circuit.

9. The impedance control circuit according to claim 8, a second variable phase control circuit that changes the phase of the high-frequency signal based on the first voltage amplitude, the second voltage amplitude, and the phase difference between the voltage phase at one end of the inverter circuit and the voltage phase at the other end of the inverter circuit further comprising an impedance control circuit.

10. A carrier amplifier that amplifies an input high-frequency signal, A peak amplifier that amplifies an input high-frequency signal, The impedance control circuit according to any one of claims 3 to 9, Including, The inverter circuit also serves as a Doherty combiner that combines the signal output by the carrier amplifier and the signal output by the peak amplifier. Doherty amplifier circuit.

11. The Doherty amplifier circuit according to claim 10, wherein At least one of the carrier amplifier and the peak amplifier is biased based on the first voltage amplitude and the second voltage amplitude. Doherty amplifier circuit.

12. The Doherty amplifier circuit according to claim 10 or 11, wherein The peak amplifier is biased based on the power of the input high-frequency signal. Doherty amplifier circuit.

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