Memory System Including Non-Volatile Memory Device and Erasing Method Thereof

Abstract

To provide a memory system including a nonvolatile memory device, and an erasing method thereof.SOLUTION: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, includes the steps of: counting, by the memory controller, a number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, every time when the number of erases reaches a reference value; applying a voltage, by the nonvolatile memory device, in response to the first erase command, so that a gate-source potential difference Vgs of the pass transistor becomes a first value; detecting, by the memory controller, a leakage current in a word line, after the application of the voltage; and performing, by the memory controller, failure processing to the word line when a leakage voltage caused by the leakage current exceeds a first threshold value.SELECTED DRAWING: Figure 4A

Description

Technical Field

[0001] The present invention relates to a memory system, and more particularly, to a method for erasing a memory system including a non-volatile memory device and a memory controller in which a not-open string exists.

Background Art

[0002] Recently, due to an increase in the size of data processed by electronic devices, more storage space is required, and a three-dimensional memory device having a high integration degree is used. There is a possibility that a not-open string in which interference between strings occurs due to a process error exists in the three-dimensional memory device. Since the reliability of data stored in the not-open string is not high, a technique for detecting the occurrence of the not-open string and performing defective processing is required.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the technical idea of the present invention is to provide a method for erasing a memory system for detecting the occurrence of a not-open string and performing defective processing on it.

Means for Solving the Problems

[0004] A method for detecting defects in a memory system including a non-volatile memory device and a memory controller according to the technical idea of the present invention includes: a step in which the memory controller counts the number of erasure times of a word line connected to a pass transistor; a step in which the memory controller issues a first erasure command each time the number of erasure times reaches a reference value; a step in which the non-volatile memory device applies a voltage so that a gate-source potential difference Vgs of the pass transistor becomes a first value in response to the first erasure command; a step in which, as a result of the voltage being applied, the memory controller detects a leakage current generated in the word line; and a step in which the memory controller performs defective processing on the word line when a leakage voltage induced by the leakage current becomes greater than a first threshold value.

[0005] A method for erasing a non-volatile memory device according to the technical idea of the present invention includes: a step of receiving an erasure command; a step of applying a voltage so that a gate-source potential difference Vgs of a pass transistor connected to a word line becomes a first value in a first erasure mode based on the erasure command; a step of detecting a leakage current generated in the word line depending on whether the pass transistor is on or off; and a step of erasing a memory block connected to the word line by applying a voltage so that the gate-source potential difference becomes a second value greater than the first value in a second erasure mode.

[0006] The memory system according to the technical idea of the present invention includes a non-volatile memory device and a memory controller for controlling the non-volatile memory device. The non-volatile memory device includes a memory cell region including a first metal pad, a peripheral region including a second metal pad and connected to the memory cell region by the first metal pad and the second metal pad, a plurality of memory cells constituting a plurality of strings in a direction perpendicular to a substrate, a memory cell array included in the memory cell region, a pass transistor configured to switch each of a plurality of word lines individually connected to each of the plurality of memory cells, a row decoder included in the peripheral region and configured to select a memory block included in the memory cell array through the plurality of word lines, a voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor, and a control logic included in the peripheral region and configured to decrease a gate-source potential difference Vgs of the pass transistor for detecting a leakage current of a word line where the memory block is located based on a first erase command. The memory controller can count the number of erase times of the memory block, issue the first erase command in response to the number of erase times reaching a reference value, and detect the leakage current.

Effect of the Invention

[0007] The non-volatile memory device or memory system according to the technical idea of the present invention can detect a leakage current generated by a not-open string when performing an erase operation and perform defective processing on a memory block where the leakage current has occurred.

[0008] In addition, the non-volatile memory device or memory system according to the technical idea of the present invention can grasp in advance a word line where a leakage current has occurred before programming data, so that an uncorrectable error of a memory block induced by being programmed into a not-open string can be prevented.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

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Figure 9

Figure 10A

Figure 10B

Figure 10C

Figure 11

Figure 12

Figure 13A

Figure 13B

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Figure 15

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present invention, embodiments of the present invention are described by exemplifying a NAND flash memory as a non-volatile memory device. However, the technical idea of the present invention is not limited to the NAND flash memory, and can be applied to various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NOR flash memory device, PRAM (Phase-change RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), MRAM (Magnetic RAM), spin-transfer torque MRAM (Spin-Transfer Torque MRAM), Conductive bridging RAM (CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase RAM), resistive memory RAM (Nano tube RAM), nanotube RAM (Nanottube RAM), polymer RAM (Polymer RAM: PoRAM), nano floating gate memory (Nano Floating Gate Memory: NFGM), holographic memory, molecular electronics memory element (Molecular Electronics Memory), or insulator resistance change memory (Insulator Resistance Change Memory).

[0011] FIG. 1 is a block diagram showing a memory system 10 including a non-volatile memory device and a memory controller according to an exemplary embodiment of the present invention.

[0012] The memory system 10 can communicate with a host through various interfaces. The host can request data processing operations of the memory system 10, such as data read operations, data write operations, and data erase operations. In an exemplary embodiment, the host corresponds to a CPU (Central Processing Unit), a microprocessor, or an application processor (AP).

[0013] The memory system 10 may be implemented as a recording device such as an SSD (Solid-State Drive). However, the present invention is not limited thereto, and the memory system 10 may be implemented as various types of devices such as an eMMC (embedded multimedia card), a UFS (universal flash storage), or a CF (Compact Flash), an SD (Secure Digital), a Micro-SD (Micro Secure Digital), a Mini-SD (Mini Secure Digital), an xD (extreme Digital), or a Memory Stick. Also, the memory system 10 may be implemented as a PC (personal computer) or a data server, a laptop computer, or a portable device. The portable device may be implemented by a mobile phone, a smart phone, a tablet PC, a PDA (personal digital assistant), an EDA (enterprise digital assistant), a digital still camera, a digital video camera, a PMP (portable multimedia player), a PND (personal navigation device or portable navigation device), a handheld game console, or an e-book. According to an exemplary embodiment, the memory system 10 is also implemented by a System-On-a-Chip (SoC).

[0014] The memory system 10 may include a non-volatile memory device 100 and a memory controller 200.

[0015] The non-volatile memory device 100 may include a memory cell array 110, a row decoder 120, a voltage generator 130, and a control logic 160.

[0016] The memory cell array 110 may include a plurality of strings (or cell strings) arranged along row and column directions on a substrate. The memory cell array 110 may include a 2-D NAND memory array or a 3-D (or vertical type, Vertical) NAND (VNAND) memory array.

[0017] In an exemplary embodiment, each of the strings of the 3-D type memory cell array 110 may include a plurality of memory cells stacked along a direction perpendicular to the substrate. That is, the memory cells can be stacked in a direction perpendicular to the substrate to form a three-dimensional structure. The 3-D type memory cell array 110 is an array of memory cells having active regions disposed on a silicon substrate, or a circuit related to the operation of the memory cells, and can be formed monolithically at at least one physical level of the circuit formed on or within the substrate. The term "monolithic" means that the layers of each level constituting the array are stacked directly above the layers of each lower level in the array. In an exemplary embodiment, the 3-D type memory cell array 110 may include Vertical NAND strings arranged vertically such that at least one memory cell is located on top of another memory cell.

[0018] Each memory cell can be used as a cell type such as a single level cell (SLC), a multi-level cell (MLC), or a triple level cell (TLC). The technical idea of the present invention can be flexibly applied depending on various cell types of memory cells.

[0019] In an exemplary embodiment of the present invention, the memory cell array 110 includes a 3D memory cell array disclosed in U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648, which is configured in multiple levels, and a word line WLs and / or a bit line BLs are shared between levels. A suitable configuration for the 3-D memory cell array 110 is detailed and incorporated herein by reference. Also, U.S. Patent Application Publication Nos. 2012-0051138 and 2011-0204420 are incorporated herein by reference. However, the memory cell array 110 according to the technical idea of the present disclosure is not limited to the aforementioned 3-D type.

[0020] In an exemplary embodiment of the present invention, the memory cell array 110 may include a not open string. The not open string is generated by an error in the process of the 3-D type memory cell array 110. In order to increase the integration degree of the memory, the channel is formed deeply, and the interval between channels is narrowed. Due to the physical limitations of the semiconductor process, the upper surface of the substrate has a relatively large channel width compared to the lower surface of the substrate. At this time, among the channels formed perpendicular to the substrate, a hole break of the channel may occur due to a leakage current generated between adjacent channels. In the present invention, a string in which a leakage current is generated between adjacent channels is also referred to as a not open string. The generation of the leakage current will be described in more detail with reference to FIGS. 13A and 13B.

[0021] The row decoder 120 can supply the voltage signal supplied from the voltage generator 130 to the word line WLs. In an exemplary embodiment, the row decoder 120 can apply an operating voltage and a verification voltage to the word line selected for the memory operation, and a pass voltage to the non-selected word lines.

[0022] The voltage generator 130 can regulate the voltage signal for the memory operation.

[0023] The control logic 160 can control the overall operation of the non-volatile memory device 100. In an exemplary embodiment, the control logic 160 can output various internal control signals to program data into the memory cell array 110, read data from the memory cell array 110, or erase the data stored in the memory cell array 110 based on a command CMD, an address ADDR, and / or a control signal CTRL received from a memory controller (not shown).

[0024] The memory controller 200 can control the non-volatile memory device 100 to read the data stored in the non-volatile memory device 100 or write data to the non-volatile memory device 100 in response to a write / read request from a host. Specifically, the memory controller 200 can control program (or write), read, and erase operations on the non-volatile memory device 100 by providing a command CMD, an address ADD, and a control signal CTRL to the non-volatile memory device 100. Also, the data DATA to be programmed and the data DATA read can be transmitted and received between the memory controller 200 and the non-volatile memory device 100.

[0025]

[0026] The erase counter 210 can count the number of erase operations performed in the non-volatile memory device 100. In an exemplary embodiment, the erase counter 210 can determine when the number of times the erase operation has been performed reaches a preset reference value (e.g., a multiple of 10, or a multiple of 100, etc.), and can notify the memory controller 200 to enter the first erase mode.

[0027] ​The error detector 230 can detect a word line in which a leakage current has occurred among a plurality of word lines included in the memory cell array 110. In an exemplary embodiment, the error detector 230 can detect the occurrence of a leakage current based on whether a word line is activated or whether a pass transistor included in the row decoder 120 is turned off. For example, when the leakage current reaches a certain threshold or more, the error detector 230 can confirm whether a word line is defective based on the activation of the transistor that is turned off.

[0028] The erase counter 210 and the error detector 230 may be implemented as separate hardware processing circuits such as those distinct from the memory controller 200, or may also be implemented by a combination of hardware and software such as a processor that executes software for performing the erase counting function and the error detection function. In particular, the processing circuit may also be implemented by, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU) that performs arithmetic and logical operations, bit shifts, etc., a digital signal processor (DSP), a microprocessor, an application specific integrated circuit (ASIC), etc.

[0029] On the one hand, the memory controller 200 can communicate with an external host through various standard interfaces. For example, the memory controller 200a includes a host interface (not shown), and the host interface provides various standard interfaces between the host and the memory controller 200a. The standard interfaces may include various interface methods such as ATA (advanced technology attachment), SATA (serial ATA), e-SATA (external SATA), SCSI (small computer small interface), SAS (serial attached SCSI), PCI (peripheral component interconnection), PCI-E (PCI express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multimedia card), eMMC (embedded multimedia card), universal flash storage device (UFS), CF (compact flash) card interface.

[0030] FIG. 2 is a block diagram showing a non-volatile memory device 100 according to an exemplary embodiment of the present invention. In the description of the memory cell array 110, row decoder 120, voltage generator 130, and control logic 160 in FIG. 2, the description overlapping with the memory cell array 110, row decoder 120, and voltage generator 130 in FIG. 1 may be omitted.

[0031] Referring to FIG. 2 together with FIG. 1, the non-volatile memory device 100 may include a memory cell array 110, a row decoder 120, a voltage generator 130, a page buffer circuit 140, an input / output circuit 150, and control logic 160. Although not shown in FIG. 2, the memory device 100 may further include various other functional blocks related to the memory operation.

[0032] The memory cells of the memory cell array 110 can be connected to word lines WLs, string selection lines SSL, ground selection lines GSL, and bit lines BLs. The memory cell array 110 can be connected to the row decoder 120 through the word lines WLs, string selection lines SSL, and ground selection lines GSL, and can be connected to the page buffer circuit 140 through the bit lines BLs.

[0033] In an exemplary embodiment, the memory cell array 110 can be provided with a word line voltage Vwl through the word lines WLs, string selection lines SSL, and ground selection lines GSL. In an exemplary embodiment, the memory cell array 110 can be directly provided with an erase voltage Vers generated from the voltage generator 130, or can be indirectly provided through the word lines WLs.

[0034] The memory cell array 110 can have an address area 111 as a storage space. The address area 111 can store the position information (e.g., address) of the word lines WLs where leakage current has occurred. However, this is only an exemplary embodiment, and the memory cell array 110 may not include the address area 111.

[0035] When the memory cell array 110 does not include the address area 111, the position information of the word lines WLs can be separately processed by the firmware of the electronic device including the non-volatile memory device 100. For example, the position information (e.g., address) of the word lines WLs where leakage current has occurred can be transmitted to the memory controller 200 and processed by the firmware (e.g., erase counter 210 and error detector 230) mounted on the memory controller 200.

[0036] The row decoder 120 can select a specific word line from among a plurality of word lines WLs based on the row address R_ADDR and provide a signal for activating the selected word line. The row decoder 120 can apply a word line voltage Vwl corresponding to the operation mode through the word line of the selected memory cell or memory block.

[0037] According to an exemplary embodiment, the row decoder 120 can apply an erase voltage and an erase verification voltage to the word line WL selected for the erase operation, and an erase pass voltage to the non-selected word lines. Similarly, during a read operation, the row decoder 120 can transmit a read voltage to the selected word line and a read pass voltage to the non-selected word lines.

[0038] The row decoder 120 may include a pass transistor 121. The pass transistor 121 is connected to the word line and can determine whether to supply a signal transmitted to the memory cell through the word line. For example, corresponding to a memory cell array 110 including m word lines, the row decoder 120 may include m pass transistors 121. The structure of the pass transistor 121 will be described in more detail in FIG. 3.

[0039] The voltage generator 130 may include one or more pumps (not shown) and can generate a voltage Vwl having various levels by a pumping operation based on a voltage control signal VC.

[0040] In an exemplary embodiment, the voltage generator 130 can generate a word line voltage Vwl based on the voltage control signal VC. The word line voltage Vwl may include various types of voltages for managing data in the memory cell.

[0041] In an exemplary embodiment, the voltage generator 130 receives the voltage control signal VC of the control logic 160 and can generate the word line voltage Vwl and the erase voltage Vers according to the type of the control signal VC. For example, the voltage generator 130 can generate a program voltage for storing data in the memory cell, a read voltage for reading the data written in the memory cell, and an erase voltage for erasing the data written in the memory cell. Further, the voltage generator 130 can generate a voltage (e.g., an erase word line voltage, a block word line voltage) for activating the pass transistor 121. The word line voltage Vwl is provided to the row decoder 120, and the erase voltage Vers can be provided to the memory cell array 110.

[0042] The page buffer circuit 140 can temporarily store the data programmed in the memory cell array 110 and the data read from the memory cell array 110. The page buffer circuit 140 may include a plurality of latch portions (or page buffers). In an exemplary embodiment, each latch portion may include a plurality of latches corresponding to a plurality of bit lines BLs and can store data in page units. In an exemplary embodiment, the page buffer circuit 140 may include a sensing latch portion, and the sensing latch portion may include a plurality of sensing latches corresponding to a plurality of bit lines BLs. Also, each sensing latch can be connected to a sensing node where data is detected through a corresponding bit line.

[0043] The page buffer circuit 140 can be connected to the input / output circuit 150 through a plurality of data lines DLs.

[0044] The page buffer circuit 140 can select some of the bit lines BLs in response to the column address signal C-ADDR. In an exemplary embodiment, the page buffer circuit 140 can operate as a write driver or a sense amplifier depending on the operation mode. For example, during a read operation, the page buffer circuit 140 operates as a sense amplifier to output the data stored in the memory cell array 110, and during a program operation, the page buffer circuit 140 operates as a write driver and can input the data to be stored in the memory cell array 110.

[0045] According to an exemplary embodiment of the present invention, the page buffer circuit 140 can provide the control logic 160 with a result signal RS output from the bit lines BLs when a word line voltage Vwl for an erase operation is applied to a plurality of memory cells. The control logic 160 can detect the occurrence of a not-open string among a plurality of strings based on the result signal RS received from the page buffer circuit 140.

[0046] The input / output circuit 150 can receive data DATA from the outside or transmit data DATA to the outside. In an exemplary embodiment, the input / output circuit 150 can perform a read operation by converting the binary data signal received from the page buffer circuit 140 through the data lines DLs and transmitting the converted signal to the outside as the data DATA. In an exemplary embodiment, the input / output circuit 150 can perform a program operation by receiving data DATA from the outside and transmitting the data DATA to the page buffer circuit 140 through the data lines DLs.

[0047] The various internal control signals output from the control logic 160 can be provided to the row decoder 120, the voltage generator 130, and the page buffer circuit 140. Specifically, the control logic 160 can provide the row address signal R_ADDR to the row decoder 120, the voltage control signal VC to the voltage generator 130, and the column address signal C_ADDR to the page buffer circuit 140, respectively.

[0048] According to an exemplary embodiment of the present invention, the control logic 160 may include an erase counter 161 and an error detector 163. The control logic 160 can drive the erase counter 161 and the error detector 163 based on the second erase command CMD_E and / or the address ADDR.

[0049] The erase counter 161 can count the number of erases of the memory blocks included in the memory cell array 110. Since the number of erases of the memory blocks is the same as the number of erases of the word lines connected to each memory cell, even if the number of erases of each word line among the plurality of word lines WLs is counted, the same technical effect can be obtained.

[0050] According to an exemplary embodiment of the present invention, the control logic 160 can determine whether to enter the first erase mode based on the number of erases of the memory blocks (i.e., the number of erases of the word lines) counted by the erase counter 161 based on the second erase command CMD_E. The control logic 160 can enter the first erase mode each time the number of erases reaches a reference value. For example, the control logic 160 can enter the first erase mode each time the number of erases reaches a multiple of 10. In another example, the control logic 160 can enter the first erase mode each time the number of erases reaches a multiple of 100 for power management of the non-volatile memory device 100. However, the technical idea of the present invention is not limited to the above-described numerical values (multiples of 10 or multiples of 100).

[0051] In an exemplary embodiment of the present invention, as a result of entering the first erasure mode, the control logic 160 can apply a voltage such that the gate-source potential difference of the pass transistor 121 reaches a first level. In an exemplary embodiment, the gate-source potential difference in the first erasure mode can be decreased compared to the normal erasure mode. As a result, the leakage current generated between the channels can be sensed more sensitively.

[0052] In an exemplary embodiment of the present invention, the error detector 163 can detect the leakage current generated on the word line by sensing the leakage current. According to an exemplary embodiment, the error detector 163 is provided with a result signal RS, and can detect the leakage current generated on the word line based on the threshold voltage of the pass transistor 121, the gate-source potential difference, the drain-source potential difference, and the leakage voltage which is the voltage change value due to the leakage current.

[0053] According to an exemplary embodiment, the error detector 163 can detect the word line on which the leakage current has occurred among a plurality of word lines WLs based on the result signal RS. In an exemplary embodiment, when the leakage voltage due to the leakage current is greater than a first threshold value, the error detector 163 can confirm that the pass transistor 121 is turned off. As a result, the error detector 163 can perform defective processing on the word line where the leakage current has occurred.

[0054] In an exemplary embodiment of the present invention, after confirming the leakage current, the control logic 160 can enter the second erasure mode without receiving a separate command. By entering the second mode, the control logic 160 can apply a voltage such that the gate-source potential difference of the pass transistor 121 reaches a second value. In an exemplary embodiment, the gate-source potential difference in the second erasure mode can increase again. The gate-source potential difference is described in more detail in FIG. 3, and the first erasure mode and the second erasure mode are described in more detail in FIG. 7. In an exemplary embodiment, the erase counter 161 and the error detector 163 are implemented as a processing circuit such as hardware including the control logic 160, or are also implemented by a combination of hardware and software such as a processor that executes software performing an erase counting function and an error detection function. In particular, the processing circuit may also be implemented by, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU) that performs arithmetic and logical operations, bit shifts, etc., a digital signal processor (DSP), a microprocessor, an application specific integrated circuit (ASIC), etc.

[0055] In an exemplary embodiment, the erase counter 161 that counts the number of erasures of a memory block and the error detector 163 that detects an error in the memory block in the control logic 160 may be performed separately outside the non-volatile memory device 100 instead of being performed in the control logic 160. According to an exemplary embodiment, an erase counter 210 that counts the number of erasures of a memory block and an error detector 230 that detects an error in the memory block may be operated by the firmware of the memory controller 200. The erase counter 210 and the error detector 230 are implemented by separate hardware included in the memory controller 200 or are also functional units implemented software-wise inside the processor. The operation in which erase counting and error detection are performed in the non-volatile memory device 100 will be described in more detail with reference to FIG. 4B.

[0056] A case where an erase counter 210 that counts the number of erasures of a memory block and an error detector 230 that detects an error in the memory block are operated by the firmware of the memory controller 200 will be described later according to an exemplary embodiment.

[0057] According to an exemplary embodiment of the present invention, the control logic 160 can enter a first erasure mode based on a first erasure command CMD_SE. The control logic 160 can apply a voltage so that the gate-source potential difference of the pass transistor 121 reaches a first level in the first erasure mode. In an exemplary embodiment, the gate-source potential difference in the first erasure mode can be lowered compared to the normal erasure mode. As a result, the leakage current generated between the channels can be sensed more sensitively.

[0058] According to an exemplary embodiment of the present invention, the control logic 160 can enter a second erasure mode based on a second erasure command CMD_E. By entering the second mode, the control logic 160 can apply a voltage so that the gate-source potential difference of the pass transistor 121 reaches a second value. In an exemplary embodiment, the gate-source potential difference in the second erasure mode can rise again.

[0059] The erasure counter 210 and the error detector 230 can determine whether the pass transistor 121 is turned off based on the word line voltage signal included in the data DATA, and as a result, can confirm the occurrence of leakage current. In an exemplary embodiment, the error detector 230 can perform defective processing on the word line where leakage current has occurred and the memory block connected to the word line without delay. In that case, the memory controller 200 can mark the address so as not to write data to the memory block determined to be defective, and adjust the mapping between the logical address and the physical address so that data is written to other addresses excluding the address of the defective memory block. The operation of the erasure counter 210 that counts the number of erasures of the memory block and the error detector 230 that detects errors in the memory block when operated by the firmware of the memory controller 200 will be described in more detail with reference to FIG. 4A.

[0060] As the size of data processed by electronic devices increases, even more storage space is required, and 3D memory devices with high integration are increasingly being used. Since the reliability of data stored in a not-open string due to process errors in a 3D memory device is not high, a technique for detecting the occurrence of a not-open string and performing defective processing is required.

[0061] When performing an erase operation, the non-volatile memory device 100 according to the technical idea of the present invention can detect a leakage current generated by a not-open string and perform defective processing on the memory block in which the leakage current has occurred. Further, since the word line in which the leakage current has occurred can be grasped in advance before programming data in the non-volatile memory device 100 according to the technical idea of the present invention, it is possible to prevent an uncorrectable error of a memory block induced by being programmed in a not-open string.

[0062] FIG. 3 is a circuit diagram showing a pass transistor 121 and a memory cell according to an exemplary embodiment of the present invention.

[0063] Referring to FIG. 3, the pass transistor 121 can be connected through one memory cell included in the memory cell array 110 and a word line WL. The pass transistor 121 is provided with a word line voltage Vwl generated by the voltage generator 130, and the memory cell can be provided with an erase voltage Vers generated by the voltage generator 130. In an exemplary embodiment, the word line voltage Vwl supplied to the pass transistor 121 includes an erase word line voltage Verswl and a block word line voltage Vblkwl. For example, the erase word line voltage Verswl can be directly applied to the source terminal S of the pass transistor 121, and the block word line voltage Vblkwl can be directly applied to the gate terminal G of the pass transistor 121. The erase voltage Vers can be directly provided from the voltage generator 130, but is not limited thereto, and can be provided through the word line WL after being once transmitted to the row decoder 120.

[0064] Due to the physical limitations of the 3-D memory cell array process, leakage current may occur between strings. The leakage current causes the charge of the memory cell to move onto the word line WL, resulting in potential fluctuations on the word line WL. For example, the voltage of the word line WL can increase due to the leakage current.

[0065] The voltage generator 130 can generate a voltage (e.g., an erase word line voltage, a block word line voltage) to activate the pass transistor 121.

[0066] In an exemplary embodiment, an erase word line voltage Verswl can be applied to the source terminal S of the pass transistor 121, and a block word line voltage Vblkwl can be applied to the gate terminal G. The drain terminal D of the pass transistor 121 can be connected to the word line WL. In the present invention, for the sake of convenience of explanation, it is illustrated that the source terminal S is represented on the left side of the drawing and the drain terminal D is represented on the right side of the drawing. However, the technical idea of the present invention is not limited thereto, and the positions of the source terminal S and the drain terminal D can be interchanged depending on the flow of the leakage current and various channel formation methods.

[0067] If the block word line voltage Vblkwl provided to the gate terminal G exceeds the threshold voltage of the pass transistor 121, the pass transistor 121 becomes active and a channel can be formed. For example, if the block word line voltage Vblkwl is 3 [V] (volts) and the threshold voltage Vth of the pass transistor 121 is 1.4 [V], the pass transistor 121 can become active.

[0068] According to an exemplary embodiment, when the erase word line voltage Verswl applied to the source terminal S of the pass transistor 121 is less than the difference between the block word line voltage Vblkwl and the threshold voltage, the channel formed in the pass transistor 121 can be retained. However, when there is a leakage current, the potential of the word line WL is increased, whereby the erase word line voltage Verswl of the pass transistor approaches the difference between the block word line voltage Vblkwl and the threshold voltage. In that case, the pass transistor 121 enters a deep-triode state or a floating state. For example, if the difference between the block word line voltage Vblkwl and the threshold voltage is 1.6 [V] and the erase word line voltage Verswl is 0.7 [V], the potential of the word line WL increased by the leakage current approaches 0.9 [V], whereby the pass transistor 121 can be turned off by entering a floating state.

[0069] According to the technical idea of the present invention, the non-volatile memory device (FIG. 1, 100) performs different erase operations by two erase modes, and the pass transistor 121 can be switched differently by the two erase modes.

[0070] The first erasure mode is described. According to an exemplary embodiment of the present invention, the gate-source potential difference Vgs, which is the potential difference between the source terminal S to which the erasure word line voltage Verswl is applied and the gate terminal G to which the block word line voltage Vblkwl is applied, can be dropped from a first value to a second value lower than the first value. In an exemplary embodiment of the present invention, the block word line voltage Vblkwl is constant, but the erasure word line voltage Verswl can rise so that the gate-source potential difference Vgs can drop. In an exemplary embodiment of the present invention, the erasure word line voltage Verswl is constant, but the gate-source potential difference Vgs drops as the block word line voltage Vblkwl drops. Also, according to an exemplary embodiment of the present invention, the erasure word line voltage Verswl rises and the block word line voltage Vblkwl drops, so that the gate-source potential difference Vgs drops.

[0071]

Number

[0072] Referring to Equation 1 according to an exemplary embodiment of the present invention, although the block word line voltage Vblkwl is constant, when the erase word line voltage Verswl increases (i.e., the gate-source potential difference Vgs decreases), the left side of Equation 1 becomes relatively large. Therefore, even for a relatively small change in the leakage voltage Vleak, the pass transistor 121 can be easily turned off.

[0073] Referring again to Equation 1 according to an exemplary embodiment of the present invention, although the erase word line voltage Verswl is constant, when the block word line voltage Vblkwl decreases, the right side of Equation 1 becomes relatively small. Therefore, even for a relatively small change in the leakage voltage Vleak, the pass transistor 121 can be easily turned off.

[0074] According to an exemplary embodiment of the present invention, in the first erase mode, the erase word line voltage Vblkwl rises to 1.4 [V], and the voltage reference level of the first verify voltage Vvrf1 for detecting a word line defect can be set to 1.6 [V]. Even if a leakage voltage Vleak of 0.2 [V] occurs, since it exceeds the first verify voltage level, a word line defect can be easily detected by an error detector (FIG. 1, 163).

[0075] Also, Equation 1 can be arranged as follows

[0076]

Number

[0077] According to an exemplary embodiment of the present invention, when the leakage voltage Vleak is greater than the gate-source potential difference Vgs (i.e., the overdrive voltage), the pass transistor 121 can be turned off (or can enter the deep diode state). As a result, by reducing the gate-source potential difference Vgs, the sensing sensitivity of the leakage current generated in the word line WL can be improved.

[0078] A second erase mode is described. According to an exemplary embodiment, the gate-source potential difference Vgs can rise from a second value to a first value higher than the second value. In that case, the erase operation of the memory cell can be performed by the erase voltage Vers. For example, the erase word line voltage Verswl drops to 0.7 [V] in the second erase mode, whereas it was 1.4 [V] in the first erase mode. Different from the first verify voltage Vvrf1 for detecting a defect in the word line, the voltage reference level of the second verify voltage Vvrf2 for verifying the erase operation can be set to 0.8 [V]. Therefore, in the second erase mode, the relatively low erase word line voltage Verswl can perform a normal erase operation.

[0079] According to an exemplary embodiment of the present invention, the non-volatile memory device 100 performs two erase operations. In the first erase mode, a defective word line (or defective memory block) in which leakage current flows equal to or more than a threshold value is detected, and after only the word line is processed as defective, a normal erase operation is performed. Therefore, the processing speed can be improved compared to determining defects in all word lines.

[0080] FIG. 4A is a flowchart for explaining a method of detecting a defect in a memory system according to an exemplary embodiment of the present invention, and FIG. 4B is a flowchart for explaining a method of detecting a defect in a non-volatile memory device according to an exemplary embodiment of the present invention. FIGS. 4A and 4B are referred to together with FIGS. 1 and 2.

[0081] FIG. 4A shows a case where an erase counter 210 that counts the number of erase operations of a memory block and an error detector 230 that detects an error in the memory block are operated by the firmware of the memory controller 200.

[0082] Referring to FIG. 4A, in step S105, an erase counter 210 included in the memory controller 200 can count the number of erase operations performed in the non-volatile memory device (NVM) 100.

[0083] In step S110, the erase counter 210 can determine when the number of times the erase operation has been performed reaches a preset reference value (for example, a multiple of 10 or a multiple of 100). If the number of times the erase operation has been performed does not reach the preset reference value, the execution of step S155 is awaited, and if the preset reference value is reached, the process moves to step S115.

[0084] In step S115, the memory controller 200 can issue a first erase command CMD_SE. The first erase command CMD_SE is a signal that instructs the non-volatile memory device 100 to enter the first erase operation.

[0085] In step S120, when the first erase command CMD_SE is issued, the first erase command CMD_SE is transmitted to the non-volatile memory device 100.

[0086] In step S125, the non-volatile memory device 100 can enter the first erase mode by receiving the first erase command CMD_SE. By entering the first erase mode, the non-volatile memory device 100 can check the state of the memory cells by applying a dummy voltage. In an exemplary embodiment, the control logic 160 provides a voltage control signal VC for generating a dummy voltage to the voltage generator 130, and the row decoder 120 can provide the dummy voltage to the memory cell array 110 through a plurality of word lines WLs.

[0087] In step S130, as the first erase mode, the non-volatile memory device 100 can apply a voltage so that the potential difference Vgs between the gate terminal and the source terminal of the pass transistor 121 becomes a first value. In an exemplary embodiment, the control logic 160 provides a voltage control signal VC for lowering the voltage of the gate terminal of the pass transistor 121 or raising the voltage of the source terminal to the voltage generator 130, and the voltage generator 130 provides the word line voltage Vwl to the row decoder 120. As a result, the potential of the gate terminal of the pass transistor 121 may decrease or the potential of the source terminal may increase.

[0088] In step S135, the leakage current generated in the word line can be detected. In an exemplary embodiment, when the potential of the gate terminal of the pass transistor 121 decreases or the potential of the source terminal increases, the sensing sensitivity of the leakage current increases, and even the generation of a relatively low magnitude of leakage voltage can cause the pass transistor 121 to turn off or enter the deep-triode region. As a result of the pass transistor 121 being turned off, it can be confirmed that the leakage current has exceeded the threshold value. If the leakage current is not detected, the process moves to step S165, and if the leakage current is detected, the process moves to step S140.

[0089] In step S140, defective information including the word line where a leakage current has occurred and the position information of the memory block connected to the word line can be generated.

[0090] In step S145, the defective information can be included in the data DATA and transmitted to the memory controller 200.

[0091] In step S150, the memory controller 200 can check for a leakage current based on the data DATA and perform defective processing on the word line. According to an exemplary embodiment, the error detector 230 can detect the occurrence of a leakage current based on whether the word line is activated or whether the pass transistor included in the row decoder 120 is turned off. For example, when the leakage current reaches a certain threshold value or more, the error detector 230 can check for a defect in the word line from the activation state of the transistor that is turned off, and thereby perform defective processing on the word line and / or the memory block connected to the word line.

[0092] In step S155, after checking for the presence or absence of a leakage current in the word line, the memory controller 200 can issue a second erase command CMD_E.

[0093] In step S160, by issuing the second erase command CMD_E, the second erase command CMD_E can be transmitted to the non-volatile memory device 100.

[0094] In step S165, the non-volatile memory device 100 enters the second erasure mode by receiving the second erasure command CMD_E, and applies a voltage so that the gate-source potential difference Vgs becomes a second value. In an exemplary embodiment, the control logic 160 provides a voltage control signal VC to the voltage generator 130 to increase the voltage at the gate terminal of the pass transistor 121 or to decrease the voltage at the source terminal, and the voltage generator 130 can provide the word line voltage Vwl to the row decoder 120. As a result, the gate-source potential difference Vgs has a second value that is larger than the first value in the first erasure mode.

[0095] In step S170, the non-volatile memory device 100 can complete the erasure operation of the memory block.

[0096] FIG. 4B is a drawing showing a case where erasure counting and error detection are performed by the non-volatile memory device 100 itself. Referring to FIG. 4B, in step S210, data can be repeatedly written / erased to the memory cells of the non-volatile memory device 100. The erasure counter 161 of the control logic 160 can count the number of erasures of the word line WL connected to the memory cell in order to determine the number of erasures of the memory cell.

[0097] In step S220, the erasure counter 161 can determine whether the number of erasures has reached a reference value. In an exemplary embodiment, the reference value can be predetermined as a multiple of 10 or a numerical value such as a multiple of 100. The reference value is not limited to the above-described numerical values and can be variously changed for leakage current detection and / or power control efficiency.

[0098] If the leakage current has not reached the reference value, it can be transferred to the second erasure mode (to S270).

[0099] In step S230, when the number of erasures reaches a reference value, the control logic 160 can apply a dummy voltage to the memory cell. In an exemplary embodiment, the dummy voltage applied to the memory cell is also a means for sensing the leakage current generated on the word line WL by temporarily programming data into the memory cell.

[0100] In step S240, the non-volatile memory device 100 can lower the gate-source potential difference Vgs of the pass transistor 121 as a first erasure mode. According to an exemplary embodiment, the control logic 160 provides a voltage control signal VC for reducing the gate-source potential difference Vgs to the voltage generator 130, and the voltage generator 130 can provide the word line voltage Vwl generated to reduce the gate-source potential difference Vgs to the row decoder 120 and / or the memory cell array 110.

[0101] In step S250, the error detector 163 can detect the leakage current. Since the leakage current generated between adjacent strings raises the voltage of the word line WL and the gate-source potential difference Vgs is lowered to more precisely sense the leakage current, the occurrence of the leakage current can be detected more easily.

[0102] If no leakage current is detected, it can be transferred to the second erasure mode (to S270).

[0103] In step S260, if the leakage voltage Vleak due to the leakage current exceeds the threshold value, the pass transistor 121 can be turned off. In an exemplary embodiment, when the pass transistor 121 is turned off, the word line voltage Vwl cannot be applied to the memory cell, and the error detector 163 can perform defective processing on the word line WL. The information (e.g., address, etc.) of the memory cell connected to the word line WL is directly stored in the address area 111 included in the memory cell array 110 or stored outside the nonvolatile memory device 100, and is referenced by the firmware. As a result, the nonvolatile memory device 100 can be processed so as not to write data to the defective memory cell.

[0104] In step S270, the nonvolatile memory device 100 enters the second erase mode. By being transferred to the second erase mode, the control logic 160 can increase the gate-source potential difference Vgs of the pass transistor 121.

[0105] In step S280, the nonvolatile memory device 100 can perform a normal erase operation on the memory cell. In an exemplary embodiment, the verification of the erase operation can be performed based on the voltage reference level of the second verify voltage Vvrf2.

[0106] FIG. 5 is a flowchart for explaining a method for detecting a defect in a nonvolatile memory device according to an exemplary embodiment of the present invention. FIG. 5 is a flowchart for explaining step S130 in FIG. 4A or S240 in FIG. 4B in more detail. FIGS. 1 and 3 are both referred to together with FIG. 4.

[0107] After step S125 (or S230) is performed, the control logic 160 of the nonvolatile memory device 100 can be in the first erase mode and can lower the gate-source potential difference Vgs of the pass transistor 121. Two methods for lowering the gate-source potential difference Vgs are illustrated.

[0108] According to step S131, the voltage of the source terminal S of the pass transistor 121 can be increased by a method for decreasing the gate-source potential difference Vgs. Referring again to Equation 1, by increasing the voltage of the erase word line voltage Verswl applied to the voltage of the source terminal S, the generation of a relatively small leakage current can be easily detected.

[0109] According to step S133, the voltage of the gate terminal G of the pass transistor 121 can be decreased by another method for decreasing the gate-source potential difference Vgs. Referring again to Equation 1, by decreasing the voltage of the block word line voltage Vblkwl applied to the voltage of the gate terminal G, the generation of a relatively small leakage current can be easily detected.

[0110] After steps S131 and S133 are performed, step S135 (or S250) can be performed.

[0111] FIG. 6 is a flowchart for explaining a defective detection method of a nonvolatile memory device according to an exemplary embodiment of the present invention. FIG. 6 is a flowchart for explaining step S135 of FIG. 4A or S250 of FIG. 4B in more detail. In the description of FIG. 6, FIG. 2 is referred to in both cases.

[0112] In step S137 following step S130 (or S240), the error detector 163 included in the control logic 160 or the error detector 230 included in the memory controller 200 can each compare the difference between the gate-source potential difference Vgs and the threshold voltage Vth with the leakage voltage induced by the leakage current in order to detect the leakage current.

[0113] In an exemplary embodiment, since the erase word line voltage Verswl is the voltage at the source terminal S of the pass transistor 121 and the block word line voltage Vblkwl is the voltage at the gate terminal G of the pass transistor 121, it can be reduced to the gate-source potential difference Vgs as described above. In an exemplary embodiment, the difference between the gate-source potential difference Vgs and the threshold voltage Vth is the overdrive voltage. As a result, the error detector 163 compares the overdrive voltage with the leakage voltage Vleak, and can detect the occurrence of a leakage current when the leakage voltage Vleak is greater than or equal to the overdrive voltage. Thereafter, if the leakage voltage Vleak is greater than the overdrive voltage, the process moves to step S140 (or S260); otherwise, it moves to step S165 (or S270).

[0114] FIG. 7 is a flowchart for explaining a defective detection method of a nonvolatile memory device according to an exemplary embodiment of the present invention. FIG. 7 is a flowchart for explaining step S150 in FIG. 4A or step S260 in FIG. 4B in more detail. In the description of FIG. 7, both FIG. 1 and FIG. 3 are referred to.

[0115] At step S151, which is after step S145 (or S250) is performed, it can be confirmed that the pass transistor 121 is turned off due to the occurrence of a leakage current. The turn-off of the pass transistor 121 is achieved by floating the pass transistor 121 when the leakage voltage Vleak becomes greater than the overdrive voltage (i.e., Vgs - Vth).

[0116] In step S153, the error detector 163 or 230 can determine that the word line WL connected to the floating pass transistor 121 is defective. At this time, the information (e.g., address) of the memory cell connected to the word line WL determined to be defective is stored in the address area 111 or can be processed by the firmware operating externally, as described above. Then, it can move to step S155 (or S270).

[0117] FIG. 8 is a graph showing the voltages applied to the pass transistor and the memory cell over time according to an exemplary embodiment of the present invention. The horizontal axis of the graph in FIG. 8 represents time, and the vertical axis represents voltage. In FIG. 8, among the erase voltage Vers applied to the memory cell and the word line voltage Vwl applied to the pass transistor 121, the block word line voltage Vblkwl and the erase word line voltage Vwerswl are shown along the same time axis. FIGS. 2 and 3 are both referred to.

[0118] At time point T1, by entering the first erase mode, the erase voltage Vers can be ramped up steadily. The ramping time of the erase voltage Vers that is ramped up steadily between time point T1 and time point T2 is the first ramping time Trp1. Since the pass transistor 121 has already been activated by the repetitive operation of the memory cell, the block word line voltage Vblkwl provided to the gate terminal S of the pass transistor 121 can maintain the conventional voltage level. On the other hand, the erase word line voltage Verswl can transition to a level higher than the low level by entering the first erase operation. Between time points T1 and T2, the gate-source potential difference Vgs can hold the first value Vgs1.

[0119] At time T2, the erasure voltage Vers can hold the voltage level at time T2 by reaching the first voltage level Vers1 corresponding to the first erasure mode. The holding time of the erasure voltage Vers that is held constantly between time T2 and time T3 is the first erasure time Ters1. That is, during the first erasure time Ters1, the erasure operation of the non-volatile memory device 100 in the first erasure mode can be performed. The block word line voltage Vblkwl drops after the arrival of time T2, or the erasure word line voltage Verswl rises after the arrival of time T2. In FIG. 7, for convenience of explanation, the drop of the block word line voltage Vblkwl and the rise of the erasure word line voltage Verswl are illustrated simultaneously, but the technical idea of the present invention includes only the change of either one of the block word line voltage Vblkwl and the erasure word line voltage Verswl as described above. As a result, the gate-source potential difference Vgs can be dropped from the first value Vgs1 to the second value Vgs2.

[0120] At time T3, the erasure voltage Vers can drop constantly and be restored to the voltage level before entering the first erasure mode. The time for the erasure voltage Vers to drop and restore the conventional voltage level is the first recovery time Trc1. At time T3, between time T3 and time T4, the voltage levels of the block word line voltage Vblkwl and the erasure word line voltage Verswl can be held.

[0121] At time T4, the erasure voltage Vers can hold the low level. To verify the erasure operation in the first erasure mode, the block word line voltage Vblkwl rises and the erasure word line voltage Verswl drops. That is, between time T4 and time T5, a verification operation for the erasure operation in the first erasure mode can be performed.

[0122] At time T5, by entering the second erasure mode, the erasure voltage Vers can be ramped at a constant rate. The ramping time of the erasure voltage Vers that is ramped at a constant rate between time T5 and time T6 is the second ramping time Trp1. In an exemplary embodiment, the ramping times of the first erasure mode and the second erasure mode may be different from each other.

[0123] At time T6, the erasure voltage Vers can hold the voltage level at time T2 by reaching the second voltage level Vers2 corresponding to the second erasure mode. The holding time of the erasure voltage Vers that is held at a constant rate between time T6 and time T7 is the second erasure time Ters2. In an exemplary embodiment, the second voltage level Vers2 is different from the first voltage level Vers1, and the second erasure time Ters2 is different from the first erasure time Ters1. That is, during the second erasure time Ters2, the normal erasure operation of the non-volatile memory device 100 in the second erasure mode can be performed.

[0124] At time T7, the erasure voltage Vers can decrease at a constant rate and be restored to the voltage level before entering the second erasure mode. The time for the erasure voltage Vers to decrease and restore the conventional voltage level is the second recovery time Trc2. In an exemplary embodiment, the second recovery time Trc2 may be different from the first recovery time Trc1.

[0125] Between time T5 and T8, the block word line voltage Vblkwl and the erasure word line voltage Verswl provided to the gate terminal S of the pass transistor 121 can hold the previous voltage level. That is, between time T5 and T8, the gate-source potential difference Vgs holds the third value Vgs3, which may be different from the decrease in the gate-source potential difference Vgs in the first erasure mode.

[0126] FIG. 9 is a drawing showing a memory cell array 110 according to an exemplary embodiment of the present invention.

[0127] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz can have a three-dimensional structure (or a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include a structure extending along the first to third directions. Each of the memory blocks BLK1 to BLKz may include a plurality of cell strings (not shown) extending along the second direction. The plurality of cell strings (not shown) can be spaced apart from each other along the first and third directions. The cell strings (not shown) of one memory block are connected to a plurality of bit lines BLs, a plurality of string selection lines SSL, a plurality of word lines WLs, one ground selection line or a plurality of ground selection lines GSL, and a common source line (not shown). The cell strings (not shown) of the plurality of memory blocks BLK1 to BLKz can share the plurality of bit lines BLs. For example, the plurality of bit lines BL extend along the second direction and can be shared by the plurality of memory blocks BLK1 to BLKz.

[0128] The memory blocks BLK1 to BLKz can be selected by the row decoder 120 illustrated in FIG. 1. For example, the row decoder 120 can be configured to select the memory block corresponding to the received address ADDR among the memory blocks BLK1 to BLKz. The program operation, read operation, and erase operation can be performed on the selected memory block.

[0129] FIGS. 10A to 10C are graphs for explaining the erase operation of the nonvolatile memory device according to an exemplary embodiment of the present invention. The horizontal axis of the graph represents the threshold voltage Vth, and the vertical axis represents the number of operating cells. FIGS. 1 to 3 and FIG. 8 are both referred to.

[0130] Referring to FIG. 10A, when the memory cell type is a single-level cell (SLC), the memory cell can correspond to either the erased state E or the first program state P1. The not-open memory cells (N / O String Cells) included in the not-open string generated by the presence of leakage current are considered to have a threshold voltage greater than the threshold voltage of the memory cell in the top program state P1, regardless of the actual threshold voltage, because no channel is formed. As a result, the verify voltage Vvrfa can have a level higher than the reference voltage VP1 for verifying the top program state P1.

[0131] Referring to FIG. 10B, when the memory cell type is a multi-level cell (MLC), the memory cell can correspond to either the erased state E or any one of the first to third program states P1 to P3. The memory cells (N / O Sting Cells) included in the not-open string are considered to have a threshold voltage greater than the threshold voltage of the memory cell in the top program state P3, regardless of the actual threshold voltage, because no channel is formed. As a result, the verify voltage Vvrfb can have a level higher than the reference voltage VP3 for verifying the top program state P3.

[0132] Referring to FIG. 10C, when the memory cell type is a triple-level cell (TLC), the general memory cell can correspond to either the erased state E or any one of the first to seventh program states P1 to P7, and the memory cells (N / O Sting Cells) included in the not-open string are considered to have a threshold voltage greater than the threshold voltage of the memory cell in the top program state P7, regardless of the actual threshold voltage, because no channel is formed. As a result, the first check voltage Vvrfc can have a level higher than the reference voltage VP7 for verifying the top program state P7.

[0133] (a) and (b) of FIG. 11 are graphs for explaining the erasure operation of the nonvolatile memory device according to the exemplary embodiment of the present invention. The graph of FIG. 11 is illustrated in comparison with FIGS. 10A to 10C. FIGS. 1 to 3 and FIGS. 10A to 10C are both referred to.

[0134] Referring to FIG. 11(a), by entering the first erasure mode, a dummy voltage for verification can be programmed. The programmed dummy voltage is higher than the first verify voltage Vvrf1. According to an exemplary embodiment, the erasure word line voltage Verswl can be increased by the first erasure mode. Since the first verify voltage Vvrf1 for detecting the leakage current is higher than the upper limit of the erasure word line voltage Verswl, if the leakage voltage Vleak induced by the generation of the leakage current does not occur, the word line can be determined to be normal. However, when the generation of the leakage voltage exceeds a first threshold (for example, the overdrive voltage), a further potential increase due to the leakage voltage Vleak occurs in the erasure word line voltage Verswl, so that a voltage increase exceeding the first verify voltage Vvrf1 can be detected. In that case, the error detector 163 can determine that the word line WL is defective FAIL.

[0135] Referring to FIG. 11(b), by entering the second erasure mode, the erasure word line voltage Verswl can be decreased. In that case, although it depends on the memory type (for example, SLC, MLC, TLC) of the memory cell array 110, an operation for normally erasing the memory cells can be performed. At this time, a second verify voltage Vvrf2 lower than the first verify voltage Vvrf1 can be used for the erasure operation.

[0136] FIG. 12 is a table for explaining the erasure operation of the nonvolatile memory device 100 according to the exemplary embodiment of the present invention.

[0137] When the erasure operation in the first erasure mode is performed and no defect is detected (PASS), the erasure operation in the second erasure mode can be continuously performed.

[0138] When no defect is detected in either the first erasure mode or the second erasure mode (PASS), the leakage current is interpreted as not being detected, and as a result, it can be understood that no leakage current flows on adjacent strings on the memory cell array (PASS).

[0139] In the first erasure mode, no defect is detected (PASS), but in the second erasure mode, when a defect is detected (FAIL), a leakage current has occurred but may be interpreted as not being correctly detected. To more precisely sense the leakage current according to an exemplary embodiment of the present invention, when the gate-source potential difference Vgs is increased but the leakage current is not detected, it is also referred to as an uncorrectable error.

[0140] When a defect is detected in the first erasure mode (FAIL), the memory block connected to the word line WL can be treated as a bad block (BAD BLOCK). As a result, by taking measures to not use the memory block in which the defect has occurred in advance before new data is written, the reliability of the data can be improved.

[0141] FIGS. 13A and 13B are various examples of perspective cross-sectional views of a memory cell array according to an exemplary embodiment of the present invention. FIG. 1 is referred to in both cases.

[0142] Referring further to FIGS. 13A and 13B, a substrate 1110 is provided. Exemplarily, the substrate 1110 may be a well having a first conductive type. On the substrate 1110, a plurality of common source regions CSR extending along a first direction and spaced apart from each other along a second direction may be provided. The plurality of common source regions CSR may be commonly connected to form a common source line. The plurality of common source regions CSR have a second conductive type different from that of the substrate 1110.

[0143] Among a plurality of common source regions CSR, between two adjacent common source regions, a plurality of insulating materials 1120, 1120a can be sequentially provided on a substrate 1110 along a third direction (i.e., a direction perpendicular to the substrate). The plurality of insulating materials 1120, 1120a can be spaced apart from each other along the third direction. The plurality of insulating materials 1120, 1120a extend along a first direction.

[0144] Between two adjacent common source regions, a plurality of pillars PL can be provided that are sequentially arranged along the first direction and penetrate the plurality of insulating materials 1120, 1120a along a second direction. Exemplarily, the plurality of pillars PL can penetrate the insulating materials 1120, 1120a and contact the substrate 1110. Exemplarily, between two adjacent common source regions, the pillars PL can be spaced apart from each other along the first direction. The pillars PL can be arranged in a row along the first direction.

[0145] Exemplarily, the plurality of pillars PL may include a plurality of materials. For example, the pillar PL may include a channel film 1140 and an internal material 1150. The channel film 1140 may include a semiconductor material having a first conductivity type (e.g., silicon). The channel film 1140 may include a semiconductor material having the same conductivity type as the substrate 1110 (e.g., silicon). The channel film 1140 may include an intrinsic semiconductor having no conductivity type.

[0146] The internal material 1150 may include an insulating material. For example, the internal material 1150 may include an insulating material such as Silicon Oxide. For example, the internal material 1150 may include an air gap. Between two adjacent common source regions, an information storage film 1160 can be provided on the exposed surfaces of the insulating materials 1120, 1120a and the pillars PL. The information storage film 1160 can store information by capturing or discharging charges.

[0147] Between two adjacent common source regions and between the insulating materials 1120 and 1120a, conductive materials CM1 to CM8 are provided on the exposed surface of the information storage film 1160. The conductive materials CM1 to CM8 extend along the first direction. On the common source region CSR, the conductive materials CM1 to CM8 can be separated by the word line cut WL cut. The word line cut WL cut can expose the common source region CSR. The word line cut WL cut extends along the first direction. Exemplarily, the conductive materials CM1 to CM8 may include metallic conductive materials. The conductive materials CM1 to CM8 may include non-metallic conductive materials such as polysilicon.

[0148] Exemplarily, the information storage film 1160 provided on the upper surface of the uppermost insulating material among the insulating materials 1120 and 1120a can be removed. Exemplarily, the information storage film 1160 provided on the side surface of the insulating materials 1120 and 1120a that faces the pillar PL can be removed.

[0149] A plurality of drains 1200 can be provided on the plurality of pillars PL. Exemplarily, the drain 1200 may include a semiconductor material (e.g., silicon) having a second conductivity type. For example, the drain 1200 may include a semiconductor material (e.g., silicon) having an N conductivity type.

[0150] On the drain 1200, bit lines BL that extend in the second direction and are spaced apart from each other along the first direction can be provided. The bit lines BL are connected to the drain 1200. Exemplarily, the drain 1200 and the bit lines BL can be connected through a contact plug (not shown). Exemplarily, the bit lines BL1 and BL2 may include metallic conductive materials. Exemplarily, the bit lines BL1 and BL2 may include non-metallic conductive materials such as polysilicon. The conductive materials CM1 to CM8 can have first to eighth heights according to the order from the substrate 1110.

[0151] A plurality of pillars PL can form a plurality of strings together with the information storage film 1160 and the plurality of conductive substances CM1 to CM8. Each of the plurality of pillars PL constitutes one string together with the information storage film 1160 and the adjacent conductive substances CM1 to CM8. On the substrate 1110, the pillars PL can be provided along the row direction and the column direction. The eighth conductive substance CM8 can constitute a row. The pillars connected to the same eighth conductive substance can constitute one row. The bit line BL can constitute a column. The pillars connected to the same bit line can constitute one column. The pillars PL, together with the information storage film 1160 and the plurality of conductive substances CM1 to CM8, constitute a plurality of strings arranged along the row and column directions. Each string may include a plurality of cell transistors CT (or memory cells) stacked in a direction perpendicular to the substrate.

[0152] Leakage current may occur between the A part and the B part of FIG. 13B. Due to the physical characteristics of generating a string perpendicular to the substrate 1110, the diameter (or width) of the pillar PL becomes wider as it rises in the three-dimensional direction. With the trend of the miniaturized memory technology, the interval between the pillars PL gradually becomes narrower, so that a knot open string in which the pillar PL in the A part and the pillar PL in the B part come into contact may be formed. When the knot open string is formed, the leakage current generated from the voltage applied to any one of the pillars PL flows to the other one. For example, the leakage current flows from the A part to the B part or from the B part to the A part.

[0153] FIG. 14 is a drawing showing an equivalent circuit of memory cells constituting a memory block BLK1 according to an exemplary embodiment of the present invention. FIGS. 1 and 8 are both referred to.

[0154] Referring to FIG. 14, cell strings CS11, CS12, CS21, CS22 can be positioned between bit lines BL1, BL2 and a common source line CSL. Cell strings CS11, CS21 can be connected between the first bit line BL1 and the common source line CSL. Cell strings CS12, CS22 can be connected between the second bit line BL2 and the common source line CSL. A common source region CSR (FIG. 13B) can be commonly connected to form the common source line CSL.

[0155] Memory cells of the same height are commonly connected to one word line, and when a voltage is supplied to the word line of a specific height, a voltage can be supplied to all strings CS11, CS12, CS21, CS22. Strings in different rows can be connected to different string selection lines SSL1, SSL2 respectively. By selecting and deselecting the first and second string selection lines SSL1, SSL2, strings CS11, CS12, CS21, CS22 can be selected and deselected in row units. For example, strings CS11 and CS12, or CS21 and CS22 connected to the deselected string selection line SSL1 or SSL2 can be electrically separated from the bit lines BL1, BL2. Strings CS21 and CS22, or CS11 and CS12 connected to the selected string selection line SSL2 or SSL1 can be electrically connected to the bit lines BL1, BL2.

[0156] Strings CS11, CS12, CS21, and CS22 can be connected to bit lines BL1 and BL2 in column units. String CS11 and CS21 can be connected to the first bit line BL1, and string CS12 and CS22 can be connected to the second bit line BL2. By selecting and deselecting bit lines BL1 and BL2, strings CS11, CS12, CS21, and CS22 can be selected and deselected in column units. Hereinafter, the program operation according to the exemplary embodiment of the present invention will be described centering on the structure of the first memory block BLK1 illustrated in FIG. 14, but this is merely an exemplary embodiment, and it is obvious that the technical idea of the present invention can also be applied to the first memory block BLK1 having other structures.

[0157] FIG. 15 is a drawing for explaining a C2C (Chip to Chip) structure applied to a memory device 400 according to an exemplary embodiment of the present invention.

[0158] Referring to FIG. 15, the memory device 400 also has a C2C structure. The C2C structure means that an upper chip including a cell region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method. As an example, the bonding method can mean a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method is also a Cu-Cu bonding method, and the bonding metal can also be formed of aluminum or tungsten.

[0159] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 400 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0160] The peripheral circuit region PERI may include a first substrate 210z, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, 220c formed on the first substrate 210z, first metal layers 230a, 230b, 230c respectively connected to the plurality of circuit elements 220a, 220b, 220c, and second metal layers 240a, 240b, 240c formed on the first metal layers 230a, 230b, 230c. In one embodiment, the first metal layers 230a, 230b, 230c may be formed of relatively high-resistance tungsten, and the second metal layers 240a, 240b, 240c may be formed of relatively low-resistance copper.

[0161] In this specification, only the first metal layers 230a, 230b, 230c and the second metal layers 240a, 240b, 240c are illustrated and described, but it is not limited thereto, and at least one or more metal layers may be further formed on the second metal layers 240a, 240b, 240c. Among the one or more metal layers formed on the upper part of the second metal layers 240a, 240b, 240c, at least a part may also be formed of aluminum or the like having a lower resistance than the copper forming the second metal layers 240a, 240b, 240c.

[0162] The interlayer insulating layer 215 is disposed on the first substrate 210z so as to cover the plurality of circuit elements 220a, 220b, 220c, the first metal layers 230a, 230b, 230c, and the second metal layers 240a, 240b, 240c, and may include an insulating material such as silicon oxide or silicon nitride.

[0163] Lower bonding metals 271b, 272b may be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b, 272b of the peripheral circuit region PERI are electrically connected to the upper bonding metals 371b, 372b of the cell region CELL by a bonding method, and the lower bonding metals 271b, 272b and the upper bonding metals 371b, 372b may be formed of aluminum, copper, tungsten, or the like.

[0164] The cell region CELL can provide at least one memory block. The cell region CELL may include a common source line 320 with the second substrate 310. On the second substrate 310, a plurality of word lines (331-338; 330) can be stacked along the vertical direction (Z-axis direction) on the upper surface of the second substrate 310. A string selection line and a ground selection line are arranged respectively above and below the word line 330, and a plurality of word lines 330 can be arranged between the string selection line and the ground selection line.

[0165] In the bit line bonding region BLBA, the channel structure CH can extend vertically on the upper surface of the second substrate 310 and penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, an embedded insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c is also a bit line contact, and the second metal layer 360c is also a bit line. In one embodiment, the bit line 360c extends along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0166] In one embodiment illustrated in FIG. 15, the region where the channel structure CH, the bit line 360c, etc. are arranged can be defined as the bit line bonding region BLBA. The bit line 360c can be electrically connected to a circuit element 320c that provides a page buffer 393 in the peripheral circuit region PERI in the bit line bonding region BLBA. As an example, the bit line 360c is connected to the upper bonding metals 371c, 372c in the peripheral circuit region PERI, and the upper bonding metals 371c, 372c can be connected to the lower bonding metals 271c, 272c connected to the circuit element 320c of the page buffer 393.

[0167] In the word line bonding area WLBA, the word line 330 extends along a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and can be connected to a plurality of cell contact plugs (341 - 347; 340). The word line 330 and the cell contact plug 340 can be connected to each other by pads provided such that at least a part of the word line 330 extends with different lengths from each other along the second direction. On the upper part of the cell contact plug 340 connected to the word line 330, the first metal layer 350b and the second metal layer 360b can be sequentially connected. The cell contact plug 340 can be connected to the peripheral circuit area PERI through the upper bonding metals 371b, 372b of the cell area CELL and the lower bonding metals 271b, 272b of the peripheral circuit area PERI in the word line bonding area WLBA.

[0168] The cell contact plug 340 can be electrically connected to a circuit element 220b that provides a row decoder 394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit element 220b that provides the row decoder 394 can be different from the operating voltage of the circuit element 320c that provides the page buffer 393. As an example, the operating voltage of the circuit element 320c that provides the page buffer 393 may be greater than the operating voltage of the circuit element 220b that provides the row decoder 394.

[0169] A common source line contact plug 380 can be arranged in the external pad bonding area PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon and can be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a can be sequentially laminated on the upper part of the common source line contact plug 380. As an example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are arranged can be defined as the external pad bonding area PA.

[0170] On one hand, input / output pads 205 and 305 can be arranged in the external pad bonding region PA. A lower insulating film 501 covering the lower surface of the first substrate 210z is formed under the first substrate 210z, and the first input / output pad 205 can be formed on the lower insulating film 201. The first input / output pad 205 is connected to at least one of a plurality of circuit elements 220a, 220b, and 220c arranged in the peripheral circuit region PERI through the first input / output contact plug 203, and can be separated from the first substrate 210z by the lower insulating film 201. Also, a side insulating film is arranged between the first input / output contact plug 203 and the first substrate 210z, and the first input / output contact plug 203 and the first substrate 210z can be electrically separated.

[0171] An upper insulating film 301 covering the upper surface of the second substrate 310 is formed on the upper part of the second substrate 310, and the second input / output pad 305 can be arranged on the upper insulating film 301. The second input / output pad 305 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c arranged in the peripheral circuit region PERI through the second input / output contact plug 303.

[0172] According to an embodiment, the second substrate 310, the common source line 320, etc. may not be arranged in the region where the second input / output contact plug 303 is arranged. Also, the second input / output pad 305 may not overlap with the word line 330 in the third direction (Z-axis direction). The second input / output contact plug 303 is separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can penetrate the interlayer insulating layer 615 of the cell region CELL and be connected to the second input / output pad 305.

[0173] According to an embodiment, the first input / output pad 205 and the second input / output pad 305 can be selectively formed. As an example, the memory device 400 may include only the first input / output pad 205 arranged on the upper part of the first substrate 201, or may include only the second input / output pad 305 arranged on the upper part of the second substrate 301. Or, the memory device 400 may include both the first input / output pad 205 and the second input / output pad 305.

[0174] In the external pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI respectively, the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0175] In the external pad bonding region PA of the memory device 400, a lower metal pattern 273a having the same form as the upper metal pattern 372a of the cell region CELL can be formed on the top metal layer of the peripheral circuit region PERI corresponding to the upper metal pattern 372a formed on the top metal layer of the cell region CELL. The lower metal pattern 273a formed on the top metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, corresponding to the lower metal pattern formed on the top metal layer of the peripheral circuit region PERI in the external pad bonding region PA, an upper metal pattern having the same form as the lower metal pattern of the peripheral circuit region PERI may be formed on the upper metal layer of the cell region CELL.

[0176] Lower bonding metals 271b, 272b may be formed on the second metal layer 240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b, 272b of the peripheral circuit region PERI may be electrically connected to each other in a bonding manner with the upper bonding metals 371b, 372b of the cell region CELL.

[0177] Also, in the bit line bonding region BLBA, an upper metal pattern 392 having the same form as the lower metal pattern 252 of the peripheral circuit region PERI can be formed on the top metal layer of the cell region CELL corresponding to the lower metal pattern 252 formed on the top metal layer of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 392 formed on the top metal layer of the cell region CELL.

[0178] As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in this specification to describe the embodiments, these are merely used for the purpose of explaining the technical idea of the present invention and are not used for meaning limitation or for limiting the scope of the present invention described in the claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

Explanation of Reference Numerals

[0179] 10 Memory System 100 Non-volatile Memory Device 110 Memory Cell Array 120 Row Decoder 121 Pass Transistor 130 Voltage Generator 140 Page Buffer Circuit 150 Input / Output Circuit 160, 200 Memory Controller 161, 210 Erase Counter 163, 230 Error Detector

Claims

1. In a method for detecting a defect in a memory system including a non-volatile memory device and a memory controller, the memory controller counting the number of erase operations of a word line connected to a pass transistor; the memory controller issuing a first erase command when the number of erase operations reaches a reference value; the non-volatile memory device applying a first voltage having a first value to a gate-source potential difference of the pass transistor in response to the first erase command; after the first voltage is applied, the memory controller detecting a leakage current in the word line; the memory controller performing a defective process on the word line when a leakage voltage induced by the leakage current is greater than a first threshold value. A method for detecting a defect, comprising:

2. The step of applying the first voltage includes a step of increasing a source terminal voltage of the pass transistor. The method for detecting a defect according to claim 1, characterized in that.

3. The step of applying the first voltage includes a step of decreasing a gate terminal voltage of the pass transistor. The method for detecting a defect according to claim 1 or 2, characterized in that.

4. the non-volatile memory device applying a second voltage having a second value higher than the first value to the gate-source potential difference; the non-volatile memory device further performing an erase operation on a memory block connected to the word line. The method for detecting a defect according to any one of claims 1 to 3, characterized in that.

5. The step of performing a defective process on the word line includes a step of confirming that the pass transistor is turned off; Determining that a word line connected to a turned-off pass transistor is a defective word line, the defective detection method according to any one of claims 1 to 4, characterized by including.

6. Applying a dummy voltage for checking the state of a memory block connected to the word line when the number of erasures reaches a reference value, Further including buffering a program voltage, the defective detection method according to any one of claims 1 to 5, characterized by including.

7. The step of detecting the leakage current, The defective detection method according to any one of claims 1 to 6, characterized by including determining that a difference between the gate-source potential difference and the threshold voltage of the pass transistor is smaller than or equal to the leakage voltage.

8. The first threshold value is an overdrive voltage, the defective detection method according to any one of claims 1 to 7, characterized by this.

9. In a method for erasing a non-volatile memory device, Receiving an erase command, In a first erase mode based on the erase command, applying a first voltage so that a gate-source potential difference of a pass transistor connected to a word line becomes a first value, Detecting a leakage current generated in the word line depending on whether the pass transistor is on / off, In a second erase mode, erasing a memory block connected to the word line by applying a second voltage so that the gate-source potential difference becomes a second value greater than the first value, an erasing method including.

10. The step of applying the first voltage, The erasing method according to claim 9, characterized by including raising a source terminal voltage of the pass transistor.

11. The step of applying the first voltage includes the step of reducing the gate terminal voltage of the pass transistor, and is characterized in that the erasing method according to claim 9 or 10.

12. The first erasing mode and the second erasing mode are entered by the erasing command, and the erasing method according to any one of claims 9 to 11 is characterized.

13. The step of detecting the leakage current includes the step of maintaining the erasing voltage applied to the memory cell at a first voltage level, The step of erasing the memory block includes the step of maintaining the erasing voltage at a second voltage level different from the first voltage level, and is characterized in that the erasing method according to any one of claims 9 to 12.

14. The step of detecting the leakage current includes the step of confirming that the erasing voltage applied to the memory cell is higher than a first verify voltage level, and is characterized in that the erasing method according to any one of claims 9 to 13.

15. The step of detecting the leakage current includes the step of confirming that the pass transistor is turned off, and the step of determining the word line connected to the turned-off pass transistor as a defective word line, and is characterized in that the erasing method according to any one of claims 9 to 14.

16. further includes the step of counting the number of erasing times of the word line, The first erasing mode is entered when the number of erasing times reaches a reference value, and is characterized in that the erasing method according to any one of claims 9 to 15.

17. The step of applying a dummy voltage for checking the state of the memory block when the number of erasing times reaches the reference value, The erasing method according to claim 16, further comprising a step of buffering a program voltage.

18. A non-volatile memory device, A memory controller for controlling the non-volatile memory device, The non-volatile memory device includes A memory cell region including a first metal pad, A peripheral region including a second metal pad and connected to the memory cell region by the first metal pad and the second metal pad, A memory cell array including a plurality of memory cells constituting a plurality of strings in a direction perpendicular to a substrate, the memory cell array being included in the memory cell region, A pass transistor configured to switch each of a plurality of word lines individually connected to each of the plurality of memory cells, the row decoder being included in the peripheral region and configured to select a memory block included in the memory cell array through the plurality of word lines, A voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor, A control logic included in the peripheral region and configured to reduce a gate-source potential difference Vgs of the pass transistor for detecting a leakage current of a word line where the memory block is located based on a first erase command, The memory controller Counts the number of erasures of the memory block, issues the first erase command in response to the number of erasures reaching a reference value, and is configured to detect the leakage current, a memory system.

19. The voltage generator The memory system according to claim 18, characterized in that a voltage applied to a source end of the pass transistor is increased.

20. The voltage generator The memory system according to claim 18 or 19, characterized in that a voltage applied to a gate terminal of the pass transistor is decreased.

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