Memory Word Line Isolation for Improvement of Reliability, Availability, and Scalability (RAS)

Abstract

To provide an architecture to improve error handling overhead of a memory device.SOLUTION: A memory device that performs internal ECC (error checking and correction) treats an N-bit channel as two N / 2-bit channels for application of ECC. Each N / 2-bit portion of ECC can be separately correctable when treated as two N / 2-bit portions. The memory device includes additional hardware for the application of ECC to the channel as two sub-channels. The memory device includes an additional subarray to store ECC bits for internal ECC to enable the application of ECC to two sub-channels of the N-bit channel. The memory device includes an additional driver to access the additional subarray when applied.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Priority This application is a non-provisional application and claims the benefit of priority of U.S. Provisional Application No. 62 / 927,116, filed on October 28, 2019.

[0002] The description generally relates to memory devices, and more specifically, the description relates to an architecture for improving RAS (reliability, availability, and scalability) through error handling.

Background Art

[0003] The overhead required to perform error handling in a memory channel continues to increase as narrower channels are used. Error handling overhead can be referred to as RAS (reliability, availability, serviceability) overhead, which refers to the fact that error handling is used to meet RAS expectations. RAS expectations often include the expectation for maximum SDDC (single device data correction) capabilities where errors due to maximum device faults can be corrected.

[0004] Legacy SDDC operations have 8 ECC (error checking and correction, also often referred to as error correction coding) bits per 64 data bits, with a 12.5% overhead. Newer memory systems with narrower channels still require 8 ECC bits for SDDC operations, but with a 32-bit channel, the overhead becomes 25%.

Brief Description of the Drawings

[0005] The following description includes a discussion of figures with illustrations provided as examples of implementations. The drawings are to be understood as examples and not as limitations. As used herein, references to one or more examples are to be understood as describing particular features, structures, or characteristics included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" that appear herein provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive either.

[0006]

Figure 1

[0007]

Figure 2

[0008]

Figure 3

[0009]

Figure 4

[0010]

Figure 5

[0011]

Figure 6

[0012]

Figure 7

[0013]

Figure 8

[0014] A non-limiting description of the figures that may illustrate some or all of the examples, as well as other possible implementations, and a description of specific details and implementations follows. DETAILED DESCRIPTION OF THE INVENTION

[0015] As described herein, a memory device is divided into a plurality of individual parts for ECC (Error Checking and Correction) separation for the application of internal or on-die ECC. The plurality of different parts can still be processed as one segment for external or system-level ECC by a memory controller at the system level. Thus, the internal ECC can correct two sub-channels individually while the system-level ECC will correct the entire channel. The internal ECC separation enables the memory device to use less overhead to provide the same level of ECC. The additional available ECC bits can be used as additional metadata.

[0016] A memory device that executes internal ECC can process an N-bit channel as two N / 2-bit channels for the application of ECC. The splitting of the N-bit channel can refer to processing the data bits for the N signal lines of the channel as each of two groups of N / 2 bits or two portions of N / 2 signal lines. The memory device applies ECC to the N bits of ECC data corresponding to the N signal lines of the channel. The ECC for the N / 2-bit channel is simpler than the ECC for the N bits, and thus each N / 2-bit portion may be individually correctable when processed as two N / 2-bit portions. The memory device can include additional hardware for applying ECC to the channel as two sub-channels. For example, the memory device can include an additional sub-array to store ECC bits for internal ECC that enables the application of ECC to two sub-channels of the N-bit channel. The memory device can include an additional driver for accessing the additional sub-array when applied.

[0017] For example, an x4 memory device can be treated internally as two x2 devices. Error correction for the x2 device requires less RAS (reliability, availability, and serviceability) overhead than for the x4 device. The RAS code can be targeted at determining a common memory error type, such as a single bit, a single sub-word line (SWL) driver, or one arm of an SWL driver. The reference to a sub-word line can refer to an architecture that subdivides the word line to reduce the driver load and may be referred to as a local word line (LWL). Experiments have shown that a device-wide (e.g., die-wide) failure is very rare compared to the above failures. The provided architecture enables correction of device-wide failures while at the same time enabling low-cost correction of more common failures.

[0018] SWL or LWL can be considered as part of the master word line (MWL) or global word line (GWL), depending on the terminology used. Generally, the MWL / GWL is divided into smaller chunks within the memory device until the driver can meet the latency requirements for the memory device. The device partitioning can vary depending on the memory type, by the memory manufacturer, or by the driver design.

[0019] The RAS overhead for the overall SDDC (single device data correction) continues to increase as the memory system uses a narrower channel or a chipkill solution. The RAS overhead can alternatively be referred to as the ECC (error checking and correction) overhead. The expression RAS overhead refers to the overall goal for error correction, while the expression ECC overhead more specifically refers to the correction mechanism for achieving the desired RAS goal.

[0020] The ECC separation described can reduce the ECC overhead by half for internal ECC and reduce the DIMM (dual in-line memory module) power. A memory device implementing ECC separation can be described as having a failure mode that is separated into a limited number of I / O (input / output) pins. For example, a DRAM device in an x4 implementation can be limited to having a failure mode that is separated in two DQs instead of having a failure across the entire span of all 4 DQ signal lines. In one example, different implementations can have different separation granularities for each device. The separation granularity can be defined by a standard.

[0021] The channel width for DDR5 is half that of DDR4 (e.g., 32 bits vs. 64 bits), enabling the memory core to maintain the same internal cycle time while transferring externally at a higher speed. Changing the internal core cycle time is significantly more costly than adjusting the I / O cycle time. DDR5 has a burst length of BL18 and transmits 64 bits per device in addition to the ECC bits. The overall interface will be a 32-bit wide channel split between four devices for an x8 implementation or eight devices for an x4 implementation.

[0022] Generally, to implement SDDC, the system requires a number of ECC bits equal to twice the device interface. Thus, an x4 implementation requires 8 ECC bits on the channel and an x8 interface requires 16 ECC bits. SDDC can be impractical for x8 but is more manageable for an x4 implementation. As the channel moves from 64b data + 8b ECC to 32b data + 8b ECC, additional ECC devices will be required to meet the same RAS performance as legacy systems.

[0023] Figure 1 is a block diagram of an example of a memory architecture with additional drivers for separating data for a conventional architecture. Memory segment 102 represents a part of the memory array for providing data to the data channels to which the memory devices are connected. The DDR5 (Double Data Rate version 5) data channel has a 32-bit data bus width with 16b for ECC, which will result in a 25% RAS / ECC overhead. On the other hand, the DDR4 (Double Data Rate version 4) data channel has a 64b data bus width with 8 bits for ECC, which results in a 12.5% overhead.

[0024] Segment 102 can include a sub-word line (SWL) driver that drives 8 bits of data on each side. As shown, the dashed box indicates 16 bits of data driven by a driver (DRVR) at the center of the bits. The bits on the left side of the driver can be regarded as the left sub-array or left arm of the driver. Similarly, the bits on the right side of the driver can be regarded as the right sub-array or right arm of the driver. It will be understood that left and right are relative terms and only refer to the orientation of the figure. In an actual implementation, the bits regarded as left or right can be switched. Thus, the description of the left and right arms refers only to the fact that the driver between the groups of bits or memory cells or memory positions drives the bits at any physical position on the driver circuit side, reducing the length of the signal lines that need to be driven between the driver circuit and the bit cells of the memory cell or memory array. There are bits driven in each direction from the active component of the driver. As shown, it will be understood that a failure of one arm (SWL arm) results in an 8b failure because one sub-array becomes inaccessible when one arm fails. A failure of the driver (SWL driver failure) results in a 16b failure because both arms become inaccessible.

[0025] Segment 104 shows a channel similar to that for segment 102 but has additional drivers and additional sub - arrays. Segment 104 can be considered to have separations between sub - channels and to be further divided or partitioned into sub - channel A and sub - channel B. Each driver in segment 104 includes at least a left sub - array or a right sub - array, and most drivers have both left and right sub - arrays. The drivers at the ends may have only one arm. The separation in the center can be considered a logical separation and does not have to be a physical separation of hardware. Thus, for example, separation can refer to the fact that for ECC purposes, one ECC circuit provides ECC for one sub - channel and a separate ECC circuit provides ECC for the other sub - channel. With separation hardware, the memory can provide ECC protection for the entire channel as two separate sub - parts, simplifying the ECC overhead.

[0026] Segment 104 provides separation of data fetched from the memory array. In one example, the additional drivers enable a single channel to be processed as two separate parts. Adding drivers can enable access to data in two separate parts for ECC operations. The additional drivers enable the channel to be subdivided for the purpose of applying internal ECC to smaller parts of the data, thus limiting errors to sub - parts of the overall memory interface. Figure 106 shows further details of a driver having a left arm on one side and a right arm on the other side. The right arm drives the right sub - array and the left arm drives the left sub - array.

[0027] In one example, the memory segment 104 can be part of a memory device having a common die implementation. The common die implementation refers to a memory device designed to be configurable as either an x4 or x8 device. Such a device will have internal logic for routing bits to selected I / O pins. The internal logic can include control logic along with hardware circuitry for routing bits to segments of the memory. In the common die implementation, in one example, an additional driver is not required if ECC separation is not used, for example, in the x8 implementation of the device. The memory array can be designed to allow selective utilization of the additional driver for ECC separation without significant waste of the addressable memory space. Thus, the additional sub-array can be used in other ways without the need to activate the driver. Alternatively, the selected driver can be designed as a dual driver for different implementations, which drives only one arm instead of two arms.

[0028] Figure 2 is a block diagram of an example of a data architecture for the memory architecture of FIG. 1. Graphic 202 represents the core memory architecture, such as a DDR5 implementation. As shown, the memory core performs a 128b internal prefetch and includes 8b ECC for internal ECC. The x8 implementation uses all 128 bits of data, while the x4 implementation prefetches 128 bits and only 64 bits are used in any given memory access (e.g., read or write) operation. The x4 implementation refers to an implementation in which a memory device having the array of Graphic 202 includes an interface to four data signal lines or four bits of a data bus, which can be said to be an implementation where M = 4, where M represents the number of signal lines. The x8 implementation refers to an implementation in which a memory device having the array of Graphic 202 includes an interface to eight data signal lines or eight bits of a data bus, which can be said to be an implementation where M = 8.

[0029] In an x8 implementation, since 128 bits is 8×16 = 128, for each memory access transaction, it can be exchanged with the host or an associated memory controller based on eight signal lines with a burst length (BL16) of 16. Thus, as shown, both the upper half and the lower half of the array each provide 64b of data. The upper half can be based on the memory architecture and addressing structure, which is not specifically shown in FIG. 202. If the slightly shaded block in FIG. 202 represents the upper half, the unshaded block represents the lower half, and vice versa. The dark shaded bits represent ECC bits. For an x4 implementation, 64 bits can be exchanged with the host or an associated memory controller for each memory access transaction based on four signal lines via BL16 (4×16 = 64). As shown, 64b of data can be fetched from the lower half or the upper half, or can be split between the upper half and the lower half. The splitting of multiple halves implies the use of only 4b out of each 8b from a subarray. In such an implementation, ECC would not target the SWL driver or MWL faults.

[0030] Figure 204 shows a similar architecture to FIG. 202 but includes separation. Specifically, FIG. 204 shows the application of a memory device 210 having an I / O circuit 250 for interfacing with four DQ (data) signal lines, DQ[3:0]. The memory device 210 includes a memory array 220 shown in a prefetch 230 that is separated into a plurality of different subarrays.

[0031] The graphic 204 can correspond to the memory segment 104 of FIG. 1. As shown, the graphic 204 includes a memory array that provides data for prefetching. The prefetch includes 128 bits of data, similar to the graphic 202, and includes either 4 bits or 8 bits of ECC data for each separated part. As shown, 8 bits of ECC data are shown for each sub-part or sub-array. In one example, only 4 bits of ECC are provided for each sub-part. In one example, additional ECC bits can be used for other purposes such as directory information, two-level memory (2LM) metadata, data integrity features, or some other purposes. In other examples, the ECC bits can be used for on-die single-bit error correction and are not transferred to the host. In such examples, the data can be transferred to the host via BL16.

[0032] It will be understood that when not all of the prefetched data is used, all of the prefetched data is placed in the sense amplifiers and then only the selected data is used for memory access. Thus, the prefetch 230 represents the data in the sense amplifiers, and the selection 240 represents the data from the sense amplifiers that is sent to the I / O for a read operation.

[0033] For example, the data is placed in the sense amplifiers, and then the addressing operates to select a particular portion of the data that is written for a write operation or read for a read operation. The addressing can select the data in any manner meaningful for the architecture. In one example, additional hardware (e.g., drivers and other logic) for separation in each bank (e.g., edge sub-word line driver) can add only approximately 1-2 percent of the die size.

[0034] In one example, a portion of the prefetched data is selected for the access operation. As shown, 4 bits out of 8 bits are selected from each subarray. The selection for each subarray enables the internal ECC operation to correct errors that occur in the driver as well as in the driver arms. A failure of the SWL arm or SWL driver will only affect two of the DQ bits (either the upper or lower 2DQ). Such a failure will not result in a loss in the bank resources for a x4 implementation.

[0035] For the write operation, the arrows in FIG. 204 can be in the reverse direction, where the selected data is received from the I / O circuit 250 and provided from the I / O circuit to the selected locations of the sense amplifier circuits at 230. Instead of being prefetched to the sense amplifiers for the write operation, the sense amplifier array can be driven to the corresponding selected subarray of the memory array 220. Similar to the read operation, the addressing of the sense amplifier elements can determine what is written to the memory array.

[0036] In one example, the routing in the spine of the memory device 210 for a dedicated x4 device is 72b versus 136b for a common x4 / x8 device, resulting in a die savings of 2 - 3%. The implementation of the dedicated portion can thus offset the die area cost for the separation.

[0037] As shown in FIG. 204, the selected data and ECC bits can be routed to the I / O circuit 250 of the memory device 210. The arrows indicate the illustrated readout downward, but for writing, it will be understood that the data will be the selected bits written to the memory device 210 and returning to the memory array 220. In one example, 36 bits for each separate plane are transferred via BL18 for each of the two DQ signal lines. The illustration of BL18 is only an example. In other examples, the system transfers bits via BL16. The total for the device is 72 bits via 4 DQ signal lines and is handled internally as two x2 interfaces. Although not specifically shown, the I / O circuit can include an ECC circuit, or the ECC circuit can be placed on the input / output path between the sense amplifier and the I / O circuit 250. The result of the architecture of FIG. 204 is 8b ECC for every 64b of data available on BL18, having a 12.5% RAS overhead, similar to legacy systems.

[0038] It will be understood that specific examples may include ECC bits for a specific number of data and a specific number of I / O signal lines. These specific examples are illustrated without limitation. In general, an N-bit channel can be subdivided into different parts for internal ECC, such as two N / 2-bit sub-parts or sub-channels. The N bits can be the total amount of data transferred over a burst length (e.g., 64 bits of pure data bits excluding ECC bits). The subdivision can alternatively be considered with respect to the interface width (e.g., an x4 channel is treated as two individual x2 sub-channels). Thus, an N-bit channel generally refers to N bits of data transmitted over a plurality of M signal lines over a burst length. In one example, the channel interface is alternatively referred to and refers to an M-bit interface through which data bits are transmitted or received. Typically, the ECC bits are applied to the entire payload of data bits received over all signal lines for a burst length, and a reference to the application of ECC bits to a channel will generally be understood to refer to all bits covered by the ECC bits.

[0039] Segmentation can handle bits or interfaces to a data bus such that multiple different parts are separated, which can refer to the separation for the purpose of performing ECC operations. System-level ECC implemented by an associated memory controller or host can process all bits or signal lines as a single channel, instead of processing bits or signal lines as two separate channels as shown in FIG. 204. Thus, for example, a memory device can process N bits as two parts of N / 2 bits with individual ECC, while at the same time, a host can process N bits as N bits for system-level ECC. Such an approach enables correction within a memory device of a portion of the channel and makes it possible to reconstruct data with less ECC overhead. The separation enables the memory device to separate errors, more specifically, for the purpose of ECC correction. As another example, a memory device can process N signal lines of a data bus interface as two parts of N / 2 signal lines with individual ECC, while at the same time, a host can process N signal lines of the data bus interface as an N-bit channel for system-level ECC. Implementations can vary depending on different interfaces and sizes of internal arrays, but the result will be to provide the ability to perform internal ECC with higher performance and at the same time reduce ECC overhead at the system level. System-level ECC refers to the ECC provided by a host or an associated memory controller, which provides ECC operations on data from multiple memory devices in parallel.

[0040] FIG. 3 is a flow diagram of an example of a process for applying ECC for a read command in a system having ECC sub-channel separation. Process 300 provides an example of performing a read operation in a memory device having ECC with sub-channel separation. Process 300 can be implemented, for example, by memory device 210 of FIG. 204 of FIG. 2.

[0041] The memory device receives a read command from the host at block 302. In one example, the memory device prefetches data at block 304 in an amount of data equal to or greater than N bits to assist with the read. In one example, at block 306, the memory device selects a portion of the data prefetched for the read operation, where the amount of data selected is N bits.

[0042] In one example, the memory device can be configured to either apply sub-channel separation for ECC or not apply sub-channel separation. The system can determine the configuration of the memory device at block 308. If sub-channel separation is not applied, at the NO branch of block 310, the memory device can perform ECC on N bits as an N-bit channel at block 312.

[0043] If sub-channel separation is applied, at the YES branch of block 310, the memory device can perform ECC on N bits as two N / 2-bit channels at block 314. Similar to what was described above, the application of ECC for N / 2 bits can be to those of the total bits themselves or to a portion of the bits of the data bus.

[0044] When ECC is applied as either one channel or two sub-channels, the memory device provides data to the I / O circuit at block 316 to send the data to the host. In one example, the host applies system ECC to the N bits of data as a single N-bit channel at block 318.

[0045] FIG. 4 is a flow diagram of an example of a process for applying ECC for a write command in a system having ECC sub-channel separation. Process 400 provides an example of performing a write operation on a memory device having ECC including sub-channel separation. Process 400 can be implemented, for example, by memory device 210 of FIG. 2 of FIG. 204.

[0046] In one example, a host or an associated memory controller applies ECC to N bits of data addressed to the memory device at block 402. The host transmits a write command received by the memory device at block 404. The memory device receives N bits of data from the host associated with the write command at block 406, either with the write command or with some time delay after the command.

[0047] In one example, the memory device can be configured to either apply sub-channel separation for ECC or not apply sub-channel separation. The system can determine the configuration of the memory device at block 408. If sub-channel separation is not applied, at the NO branch of block 410, the memory device can calculate ECC for the N bits of data as an N-bit channel at block 412.

[0048] If sub-channel separation is applied, at the YES branch of block 410, the memory device can calculate ECC for the N bits of data as two N / 2-bit channels at block 414. Similar to what was described above, the application of ECC to the N / 2 bits can be for the total bits themselves or for a portion of the bits of the data bus. Once the ECC is calculated as either one channel or two sub-channels, the memory device stores the data and associated ECC bits in the memory array of the memory device at block 418.

[0049] FIG. 5 is a block diagram of an example of an on-die error checking and correction (ECC) subsystem for implementing ECC sub-channel separation. System 500 provides an example of an on-die ECC circuit for a system according to a system compatible with FIG. 202. Host 510 includes a memory controller or equivalent or alternative circuit or component that manages access to memory 520. Host 510 performs external ECC on data read from memory 520. Memory 520 implements on-die ECC and checks and corrects the data before sending it to host 510.

[0050] System 500 shows a write path 532 in memory 520, which represents the path of data written from host 510 to memory 520. Host 510 provides data 542 to memory 520 for writing to the memory array. In one example, memory 520 generates check bits 544 with a check bit generator 522 for storing with the data in the memory. The check bits 544, also referred to as ECC bits, can enable memory 520 to correct errors that may occur during writing to and reading from the memory array. Data 542 and check bits 544 can be included as a codeword input 546, which is written to the memory resources.

[0051] The read path 534 represents a path for data read from the memory 520 to the host 510. In one example, at least some of the hardware components of the write path 532 and the read path 534 are the same hardware. In one example, the memory 520 fetches a codeword output 552 in response to a read command from the host 510. The codeword can include data 554 and check bits 556. The data 554 and the check bits 556 can respectively correspond to the data 542 and the check bits 544 written to the write path 532. Thus, the read can access the data and the ECC bits. Error correction in the read path 534 can include the application of an XOR (exclusive OR) tree to the corresponding H matrix to detect an error and selectively correct the error (in the case of a single-bit error). As will be understood in the art, the H matrix refers to a Hamming code parity check matrix that indicates how a linear combination of the digits of a codeword equals zero. Thus, the rows of the H matrix identify the coefficients of the parity check equations that must be satisfied for the components or digits that are part of the codeword. In one example, the memory 520 includes a syndrome decode 524 that enables the memory to apply the check bits 556 to the data 554 to detect an error in the read data. The syndrome decode 524 can generate a syndrome 558 for use in generating appropriate error information about the read data. The data 554 can also be transferred to an error correction 528 for correction of the detected error.

[0052] In one example, syndrome decoder 524 passes syndrome 558 to syndrome generator 526 to generate an error vector. In one example, check bit generator 522 and syndrome generator 526 are fully specified by corresponding H matrices for the memory device. In one example, if there are no errors in the read data (e.g., zero syndrome 558), syndrome generator 526 does not generate an error signal 562. In one example, if there are multiple errors in the read data (e.g., non-zero syndrome 558 that does not match any of the columns in the corresponding H matrix), syndrome generator 526 generates a DUE (detected uncorrected error) signal 564, which indicates the detected uncorrected error. The DUE signal 564 can indicate a multi-bit error that memory 520 could not correct with internal ECC.

[0053] In one example, if there is a single-bit error (e.g., non-zero syndrome 558 that matches one of the columns of the corresponding H matrix), syndrome generator 526 can generate a CE (corrected error) signal at error location 560, which is an indicator of the corrected error for error correction logic 528. Error correction 528 can apply the corrected error to the specified location in data 554 and generate corrected data 566 for output to host 510. In one example, error correction 528 also generates check bits 568, which include check bits for the read data.

[0054] Check bits 568 can be considered an error vector indicating the state of errors in the read data transmitted to host 510. It will be understood that the zero syndrome (no error 562) condition, and the corrected SBE that results in corrected data 566, have the same check bits 568 indicating no error to host 510. Thus, check bits 568 provide information only about multi-bit errors, not about SBEs in memory 520. In one example, system 500 writes the corrected data back to the memory array.

[0055] In one example, for each part of the array, system 500 includes an internal ECC write path 532 and an internal ECC read path 534. In accordance with a system compatible with FIG. 202, memory device 520 can include one path for half of its I / O pins and a second path for the other half of its I / O pins. Thus, memory 520 can perform ECC separation with hardware resources and separate the application of ECC to individual sub-parts of the overall data provided by the memory device.

[0056] FIG. 6 is a block diagram of an example of a memory subsystem in which ECC sub-channel separation can be implemented. System 600 includes elements of a memory subsystem and a processor in a computing device. System 600 is an example of a system that can incorporate a system compatible with FIG. 202.

[0057] In one example, memory device 640 includes ECC separation 680 in memory array 660. ECC separation 680 represents the hardware and logic for implementing ECC separation inside the memory device within the channel subdivision according to any example herein. The ECC separation includes additional hardware resources to provide more driver circuits for managing multiple parts of the memory array as individual sub-channels for the purpose of internal ECC operations. ECC separation 680 can control the application of ECC by an on-die ECC circuit.

[0058] Processor 610 represents the processing unit of a computing platform capable of executing an operating system (OS) and applications, and the processing units can collectively be referred to as the host or user of the memory. The OS and applications execute operations that result in memory access. Processor 610 can include one or more individual processors. Each individual processor can include a single processing unit, a multi-core processing unit, or a combination. The processing unit can be a primary processor such as a CPU (Central Processing Unit), a peripheral processor such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access can also be initiated by a device such as a network controller or a hard disk controller. Such devices can be integrated with the processors of some systems or connected to the processors via a bus (e.g., PCI Express), or a combination thereof. System 600 can be implemented as a System-on-Chip (SOC) or as a stand-alone component.

[0059] References to a memory device can apply to different memory types. A memory device often refers to volatile memory technology. Volatile memory is memory whose state (and thus the data stored therein) becomes indeterminate if power to the device is interrupted. Non-volatile memory refers to memory whose state remains determined even if power to the device is interrupted. Dynamic volatile memory requires refreshing the data stored within the device to maintain its state. An example of dynamic volatile memory includes some variation such as DRAM (Dynamic Random Access Memory), or Synchronous DRAM (SDRAM). A memory subsystem as described herein can be compatible with a number of memory technologies such as DDR4 (Double Data Rate (DDR) version 4, initially published in September 2012 by JEDEC, JESD79-4), LPDDR4 (Low Power DDR version 4, initially published in August 2014 by JEDEC, JESD209-4), WIO2 (Wide I / O2, initially published in August 2014 by JEDEC, JESD229-2), HBM (High Bandwidth Memory DRAM, initially published in November 2015 by JEDEC, JESD235A), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (LPDDR version 5, initially published in February 2019 by JEDEC, JESD209-5), HBM2 (HBM version 2, currently under discussion by JEDEC), or others, or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0060] In one example, in addition to, or alternatively to, volatile memory, a reference to a memory device can refer to a non-volatile memory device whose state is determined even when power to the device is cut off. In one example, the non-volatile memory device is a block-addressable memory device such as NAND or NOR technology. Thus, the memory device can also include next-generation non-volatile devices such as three-dimensional cross-point memory devices, other byte-addressable non-volatile memory devices. The memory device can include a non-volatile byte-addressable medium that stores data based on the resistance state or phase of the memory cells. In one example, the memory device can use a chalcogenide phase change material (such as chalcogenide glass). In one example, the memory device can be, or can include, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or phase change memory with switch (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetic random access memory (MRAM) memory incorporating memristor technology, or spin transfer torque (STT)-MRAM, or any combination of the above, or other memory.

[0061] Memory controller 620 represents one or more memory controller circuits or devices for system 600. Memory controller 620 represents control logic that generates memory access commands in response to execution of operations by processor 610. Memory controller 620 accesses one or more memory devices 640. Memory device 640 can be a DRAM device according to any of those referred to above. In one example, memory devices 640 are configured and managed as different channels, and each channel is coupled to a bus and signal lines that couple to multiple memory devices in parallel. Each channel is operable independently. Thus, each channel is accessed and controlled independently, and timings, data transfers, command and address exchanges, and other operations are individual for each channel. Coupling can refer to an electrical coupling, a communication coupling, a physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes an interface or interconnection that enables an electrical flow between components, enables signal transmission between components, or both. Communication coupling includes a connection including wired or wireless that enables components to exchange data.

[0062] In one example, the settings for each channel are controlled by individual mode registers or other register settings. In one example, each memory controller 620 manages an individual memory channel, but system 600 can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, memory controller 620 is part of host processor 610, such as logic implemented on the same die or implemented in the same package space as the processor.

[0063] Memory controller 620 includes I / O interface logic 622 for coupling to a memory bus such as the memory channels mentioned above. I / O interface logic 622 (as well as the I / O interface logic 642 of memory device 640) can include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or combinations thereof. I / O interface logic 622 can include a hardware interface. As shown, I / O interface logic 622 includes at least a driver / transceiver for signal lines. Generally, wires within an integrated circuit interface couple to pads, pins, or connectors to interface signal lines or traces or other wires between devices. I / O interface logic 622 includes drivers, receivers, transceivers, or terminations, or other circuits or combinations of circuits, and can exchange signals on signal lines between devices. The exchange of signals includes at least one of transmission or reception. While shown coupling I / O 622 from memory controller 620 to I / O 642 of memory device 640, in an implementation of system 600 where a group of memory devices 640 are accessed in parallel, it will be understood that multiple memory devices can include I / O interfaces to the same interface of memory controller 620. In an implementation of system 600 including one or more memory modules 670, I / O 642 can include the interface hardware of the memory module in addition to the interface hardware on the memory device itself. Other memory controllers 620 include individual interfaces to other memory devices 640.

[0064] The bus between the memory controller 620 and the memory device 640 can be implemented as a plurality of signal lines coupling the memory controller 620 to the memory device 640. The bus typically includes at least a clock (CLK) 632, a command / address (CMD) 634, write data (DQ) and read data (DQ) 636, and zero or more other signal lines 638. In one example, the bus or connection between the memory controller 620 and the memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal lines of CMD can be referred to by some other name indicating the transfer of "C / A bus" (or ADD / CMD bus, or command (C or CMD) and address (A or ADD) information), and the signal lines of write and read DQ can be referred to as the "data bus". In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Thus, the system 600 can be considered to have multiple "buses" in the sense that independent interface paths can be considered individual buses. In addition to the explicitly shown lines, it will be understood that the bus can include at least one of strobe signaling lines, warning lines, auxiliary lines, or other signal lines, or combinations thereof. It will also be understood that serial bus technology can be used for the connection between the memory controller 620 and the memory device 640. An example of serial bus technology is the 8B10B encoding and transmission of high-speed data with an embedded clock via a single differential pair of signals in each direction. In one example, CMD 634 represents signal lines shared in parallel with a plurality of memory devices. In one example, a plurality of memory devices share the encoding command signal lines of CMD 634 and each has an individual chip select (CS_n) signal line for selecting an individual memory device.

[0065] In an example of system 600, it will be understood that the bus between memory controller 620 and memory device 640 includes a slave command bus (CMD634) and an auxiliary bus to carry write and read data, DQ636. In one example, the data bus can include bidirectional lines for read data and write / command data. In other examples, the auxiliary bus DQ636 can include unidirectional write signal lines for writes from the host to the memory and for data, and can include unidirectional lines for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 638 can be associated with a bus or sub-bus such as strobe line DQS. Based on the design or implementation of system 600, if the design supports multiple implementations, the data bus can have more or less bandwidth per memory device 640. For example, the data bus can support memory devices having any of an x4 interface, an x8 interface, an x16 interface, or other interfaces. In the convention “xW”, W is an integer that refers to the interface size or width of the interface of memory device 640 and represents the number of signal lines for exchanging data with memory controller 620. The interface size of a memory device is a control factor as to how many memory devices can be used simultaneously per channel in system 600 or can be coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices, or stacked memory configurations, or combinations thereof, can enable the use of wider interfaces such as an x128 interface, an x256 interface, an x512 interface, an x1024 interface, or other data bus interface widths.

[0066] In one example, the memory device 640 and the memory controller 620 exchange data via the data bus in bursts or in a series of consecutive data transfers. A burst corresponds to the number of transfer cycles associated with the bus frequency. In one example, a transfer cycle can be all clock cycles of a transfer that occur at the same clock or strobe signal edge (e.g., rising edge). In one example, all clock cycles referring to cycles of the system clock are divided into a plurality of unit intervals (UIs), and each UI is a transfer cycle. For example, double data rate transfer is triggered at both edges of the clock signal (e.g., rising and falling). A burst can last for a configured number of UIs, which can be a configuration stored in a register or a configuration triggered on-the-fly. For example, a series of eight consecutive transfer periods can be considered a burst length 8 (BL8), and each memory device 640 can transfer data on each UI. Thus, an x8 memory device operating at BL8 can transfer 64 bits of data ([8 data signal lines] × [8 data bits transferred per line via the burst]). This simple example is merely illustrative and is understood not to be limiting.

[0067] Memory device 640 represents the memory resources for system 600. In one example, each memory device 640 is an individual memory die. In one example, each memory device 640 can interface with multiple (e.g., two) channels per device or per die. Each memory device 640 includes I / O interface logic 642 having a bandwidth (e.g., x16 or x8 or some other interface bandwidth) determined by the implementation of the device. The I / O interface logic 642 enables the memory device to interface with the memory controller 620. The I / O interface logic 642 can include a hardware interface and can follow the I / O 622 of the memory controller, but can be at the memory device end. In one example, multiple memory devices 640 are connected in parallel to the same command and data buses. In other examples, multiple memory devices 640 are connected in parallel to the same command bus and to different data buses. For example, system 600 can be composed of multiple memory devices 640 coupled in parallel, and each memory device responds to commands and accesses each internal memory resource 660. In the case of a write operation, an individual memory device 640 can write a portion of an entire data word, and in the case of a read operation, an individual memory device 640 can fetch a portion of an entire data word. The remaining bits of the word are provided or received in parallel by other memory devices.

[0068] In one example, the memory device 640 is placed directly on the motherboard of the computing device or the host system platform (e.g., the printed circuit board (PCB) on which the processor 610 is located). In one example, the memory device 640 can be configured into a memory module 670. In one example, the memory module 670 represents a dual in-line memory module (DIMM). In one example, the memory module 670 represents another organization of a plurality of memory devices that share at least a portion of the access or control circuitry and can be an individual circuit, an individual device, or an individual board from the host system platform. The memory module 670 can include a plurality of memory devices 640, and the memory module can include support for a plurality of individual channels to the memory devices already disposed therein. In other examples, the memory device 640 can be incorporated into the same package as the memory controller 620 by techniques such as multi-chip modules (MCMs), package-on-package, through-silicon vias (TSVs), or other techniques or combinations thereof. Similarly, in one example, a plurality of memory devices 640 can be incorporated into the memory module 670, but these themselves can be incorporated into the same package as the memory controller 620. In these and other implementations, it will be understood that the memory controller 620 can be part of the host processor 610.

[0069] Memory devices 640 each include one or more memory arrays 660. Memory arrays 660 represent addressable memory locations or storage locations for data. Typically, memory arrays 660 are managed as rows of data and are accessed via word line (row) and bit line (individual bits within a row) control. Memory arrays 660 can be configured as individual channels, ranks, and banks of memory. A channel can refer to an independent control path to storage locations within a memory device 640. A rank can refer to a common location across multiple parallel memory devices (e.g., the address of the same row in different devices). A bank can refer to a sub-array of memory locations within a memory device 640. In one example, a bank of memory is divided into sub-banks having at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks, enabling individual addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other configurations of memory locations, and combinations of those configurations, may overlap in their application to physical resources. For example, the same physical memory location can be accessed via a particular channel as a particular bank that can also belong to a rank. Thus, the configuration of memory resources will be understood in an inclusive rather than an exclusive manner.

[0070] In one example, the memory device 640 includes one or more registers 644. The registers 644 represent one or more storage devices or storage locations that provide configurations or settings for the operation of the memory device. In one example, the registers 644 can provide storage locations of the memory device 640 that store data for access by the memory controller 620 as part of a control or management operation. In one example, the registers 644 include one or more mode registers. In one example, the registers 644 include one or more general-purpose registers. The configuration of the positions within the registers 644 can configure the memory device 640 to operate in different “modes,” and command information can trigger different operations within the memory device 640 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. The settings of the registers 644 can indicate configurations of I / O settings (e.g., timing, termination, or ODT (on-die termination) 646, driver configuration, or other I / O settings).

[0071] In one example, the memory device 640 can include the ODT 646 as part of the interface hardware associated with the I / O 642. The ODT 646 can be configured as described above and provides settings for the impedance applied to the interface for a particular signal line. In one example, the ODT 646 is applied to the DQ signal line. In one example, the ODT 646 is applied to the command signal line. In one example, the ODT 646 is applied to the address signal line. In one example, the ODT 646 can be applied to any combination of the above. The ODT setting can be changed based on whether the memory device is the selected target of the access operation or a non-target device. The setting of the ODT 646 can affect the timing and reflection of signaling on the termination line. By carefully controlling the ODT 646, the applied impedance and load matching can be improved, enabling high-speed operation. The ODT 646 can be applied to specific signal lines of the I / O interfaces 642, 622 (e.g., ODT for DQ lines or ODT for CA lines) and not necessarily to all signal lines.

[0072] The memory device 640 includes a controller 650 that represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 650 decodes commands sent by the memory controller 620 and generates internal operations for executing or fulfilling the commands. The controller 650 can be referred to as an internal controller and is separate from the host's memory controller 620. Based on the register 644, the controller 650 determines which mode is selected and can configure operations for accessing the memory resources 660 or internal executions for other operations based on the selected mode. The controller 650 generates control signals that control the routing of bits within the memory device 640 to provide an interface appropriate for the selected mode and send commands to the appropriate memory location or address. The controller 650 includes command logic 652 that can decode the command encodings received on the command and address signal lines. Thus, the command logic 652 can be or include a command decoder. Using the command logic 652, the memory device can identify commands and generate internal operations for executing the requested commands.

[0073] Referring again to memory controller 620, memory controller 620 includes command (CMD) logic 624, which represents logic or circuitry for generating commands to be sent to memory device 640. The generation of commands refers to commands prior to scheduling or prior to preparation of commands placed in a queue ready for transmission. Generally, signaling in the memory subsystem includes address information within or associated with a command to indicate or select one or more memory locations at which the memory device is to execute the command. In response to scheduling of transactions of memory device 640, memory controller 620 can issue a command via I / O 622 to cause memory device 640 to execute the command. In one example, controller 650 of memory device 640 receives and decodes the command and address information received from memory controller 620 via I / O 642. Based on the received command and address information, controller 650 can control the timing of the operations of the logic and circuitry within memory device 640 for executing the command. Controller 650 serves to comply with the standards or specifications within memory device 640, such as timing and signaling requirements. Memory controller 620 can implement compliance with the standards or specifications through access scheduling and control.

[0074] Memory controller 620 includes a scheduler 630, which represents logic or circuitry for generating and ordering transactions to be sent to memory device 640. From one perspective, the main function of memory controller 620 can be said to be scheduling memory accesses and other transactions to memory device 640. Such scheduling can include generating the transactions themselves, implementing requests for data by processor 610, and maintaining data integrity (e.g., using commands related to refresh). A transaction can include one or more commands, and as a result, commands or data, or both, are transferred over one or more timing cycles such as clock cycles or unit intervals. Transactions are for access such as read or write, or related commands, or combinations thereof, and other transactions can include memory management commands for configuration, setting, data integrity, or other commands or combinations thereof.

[0075] Memory controller 620 typically includes logic such as a scheduler 630 that enables selection and ordering of transactions to improve the performance of system 600. Thus, memory controller 620 can select which of the outstanding transactions should be sent to memory device 640 and in what order, which is typically accomplished with logic much more complex than a simple first-in-first-out algorithm. Memory controller 620 manages the transmission of transactions to memory device 640 and manages the timing associated with the transactions. In one example, the transactions have deterministic timing that can be used by memory controller 620 to manage them and to determine how to schedule the transactions using scheduler 630.

[0076] In one example, memory controller 620 includes refresh (REF) logic 626. Refresh logic 626 can be used for memory resources that are volatile and need to be refreshed to maintain a defined state. In one example, refresh logic 626 indicates the location of the refresh and the type of refresh to be performed. Refresh logic 626 can trigger self-refresh within memory device 640, or perform an external refresh (which can be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, a controller 650 within memory device 640 includes refresh logic 654 for applying a refresh within memory device 640. In one example, refresh logic 654 can generate internal operations to perform a refresh according to an external refresh received from memory controller 620. Refresh logic 654 can determine that the refresh is targeted at memory device 640 and which memory resources 660 to refresh in response to the command.

[0077] FIG. 7 is a block diagram of an example of a computing system in which ECC sub-channel separation can be implemented. System 700 represents a computing device according to any example herein and can be a laptop computer, a desktop computer, a tablet computer, a server, a game or entertainment control system, an embedded computing device, or other electronic device. System 700 provides an example of a system that can incorporate a system compatible with FIG. 202.

[0078] In one example, memory subsystem 720 includes ECC separation 790 in memory 730. ECC separation represents the hardware and logic for implementing ECC separation inside a memory device within the channel subdivision according to any example herein. ECC separation includes additional hardware resources to provide more driver circuits for managing multiple portions of the memory array as individual subchannels for the purpose of internal ECC operations. ECC separation 790 can control the application of ECC by the on-die ECC circuit.

[0079] System 700 includes a processor 710 of any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combinations thereof, to provide for the processing or execution of instructions for system 700. Processor 710 controls the overall operation of system 700 and can be, or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or combinations of such devices.

[0080] In one example, system 700 includes an interface 712 coupled to a processor 710, which can represent a higher speed interface or a high throughput interface for system components that require a higher bandwidth connection, such as memory subsystem 720 or graphics interface component 740. Interface 712 can represent an interface circuit that can be a stand-alone component or integrated into the processor die. Interface 712 may be integrated into the processor die as a circuit or integrated into the system-on-chip as a component. If present, graphics interface 740 interfaces to a graphics component to provide a visual display to a user of system 700. Graphics interface 740 can be a stand-alone component or integrated into the processor die or system-on-chip. In one example, graphics interface 740 can drive a high definition (HD) display or an ultra high definition (UHD) display that provides output to a user. In one example, the display can include a touch screen display. In one example, graphics interface 740 generates a display based on data stored in memory 730, based on operations executed by processor 710, or based on both.

[0081] Memory subsystem 720 represents the main memory of system 700 and provides storage for code to be executed by processor 710 or data values to be used in the execution of routines. Memory subsystem 720 can include one or more memory devices 730, such as read-only memory (ROM), flash memory, one or more variations of random access memory (RAM) such as DRAM, 3DXP (three-dimensional cross-point), or other memory devices, or combinations of such devices. Memory 730 stores, among other things, operating system (OS) 732, acts as its host, and provides a software platform for the execution of instructions within system 700. Further, application 734 can execute on the software platform of OS 732 from memory 730. Application 734 represents a program having its own operation logic for performing the execution of one or more functions. Process 736 represents an agent or routine that provides auxiliary functions to OS 732 or one or more applications 734, or combinations thereof. OS 732, application 734, and process 736 provide software logic that provides functions for system 700. In one example, memory subsystem 720 includes memory controller 722, which is a memory controller that generates and issues commands to memory 730. It will be understood that memory controller 722 can be a physical part of processor 710 or a physical part of interface 712. For example, memory controller 722 can be an integrated memory controller and can be integrated into a circuit having processor 710 so as to be integrated into the processor die or system-on-chip.

[0082] Although not specifically shown, it will be understood that system 700 may include one or more buses or bus systems, such as a memory bus, a graphics bus, or an interface bus, between devices. The bus or other signal lines can couple components to communicate with each other or electrically, or can couple components both communicatively and electrically. The bus can include physical communication lines, point-to-point connections, circuits such as bridges, adapters or controllers, or combinations thereof. The bus can include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or combinations of one or more of them.

[0083] In one example, system 700 includes an interface 714 that can be coupled to interface 712. Interface 714 can be an interface with a lower speed than interface 712. In one example, interface 714 represents an interface circuit that can include stand-alone components and integrated circuits. In one example, a plurality of user interface components or peripheral devices, or both, are coupled to interface 714. Network interface 750 provides system 700 with the ability to communicate with remote devices (e.g., servers, or other computing devices) via one or more networks. Network interface 750 can include an Ethernet (registered trademark) adapter, a wireless interconnect component, a cellular network interconnect component, a USB (Universal Serial Bus), or other wired or wireless standard-based or proprietary interfaces. Network interface 750 can exchange data with remote devices that can include transmitting data stored in memory or receiving data to be stored in memory.

[0084] In one example, system 700 includes one or more input / output (I / O) interfaces 760. The I / O interfaces 760 can include one or more interface components for a user to interact with the system 700 (e.g., audio, alphanumeric, tactile / touch, or other interface methods). The peripheral interface 770 can include any hardware interface not specifically mentioned above. Peripheral devices generally refer to a plurality of devices that are connected to the system 700 in a subordinate manner. The subordinate connection is provided by the system 700 for a software platform or a hardware platform or both on which the operations are executed and with which the user interacts.

[0085] In one example, system 700 includes a storage subsystem 780 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least a particular component of the storage 780 can overlap with a component of the memory subsystem 720. The storage subsystem 780 can include a storage device 784 which can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, 3DXP, or optical-based disks, or combinations thereof. The storage 784 holds the code or instructions and data 786 in a persistent state (i.e., the values are retained even when the power to the system 700 is cut off). Although the memory 730 is typically the memory for executing or operating to provide instructions to the processor 710, the storage 784 can generally be regarded as a "memory". The storage 784 is non-volatile, while the memory 730 can include volatile memory (i.e., the value or state of the data is indeterminate when the power to the system 700 is cut off). In one example, the storage subsystem 780 includes a controller 782 that interfaces with the storage 784. In one example, the controller 782 can be a physical part of the interface 714 or the processor 710, or can include circuitry or logic in both the processor 710 and the interface 714.

[0086] Power source 702 provides power to the components of system 700. More specifically, power source 702 typically interfaces with one or more power supply devices 704 in system 700 to provide power to the components of system 700. In one example, power supply device 704 includes an AC-DC (alternating current to direct current) adapter that connects to a wall outlet. Such AC power can be a renewable energy (e.g., solar power) source 702. In one example, power source 702 includes a direct current power source, such as an external AC-DC converter. In one example, power source 702 or power supply device 704 includes wireless charging hardware for charging in proximity to a charging field. In one example, power source 702 can include an internal battery or fuel cell power source.

[0087] FIG. 8 is a block diagram of an example of a mobile device in which ECC subchannel separation can be implemented. System 800 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wearable computing device, or other mobile device, or an embedded computing device. Some of the multiple components are generally shown, and it will be understood that not all components of such a device are shown in system 800. System 800 provides an example of a system that can incorporate a system compatible with FIG. 202.

[0088] In one example, memory subsystem 860 includes ECC separation 890 in memory 862. ECC separation represents the hardware and logic for implementing ECC separation inside a memory device within the channel subdivision according to any example herein. ECC separation includes additional hardware resources to provide more driver circuits for managing multiple portions of a memory array as individual subchannels for the purpose of internal ECC operations. ECC separation 890 can control the application of ECC by an on-die ECC circuit.

[0089] System 800 includes a processor 810 that executes the main processing operations of system 800. Processor 810 may include one or more physical devices such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. The processing operations executed by processor 810 include the execution of an operating platform or operating system on which application and device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting system 800 to other devices, or combinations thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or combinations thereof. Processor 810 may execute data stored in memory. Processor 810 may write to or edit data stored in memory.

[0090] In one example, system 800 includes one or more sensors 812. Sensors 812 represent an interface to embedded sensors or external sensors, or a combination thereof. Sensors 812 enable system 800 to monitor or detect one or more states of the environment or device in which system 800 is implemented. Sensors 812 can include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors for detecting physiological attributes, heart rate monitors, or other sensors), or other sensors, or combinations thereof. Sensors 812 can also include sensors for biometric systems such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user characteristics. Sensors 812 are to be broadly understood and are not limited to many different types of sensors that can be implemented in system 800. In one example, one or more sensors 812 are coupled to processor 810 via a front-end circuit integrated with processor 810. In one example, one or more sensors 812 are coupled to processor 810 via other components of system 800.

[0091] In one example, system 800 includes an audio subsystem 820 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components related to providing audio functionality to a computing device. The audio functionality can include speaker or headphone output, as well as microphone input. Devices for such functionality can be integrated within system 800 or connected to system 800. In one example, a user interacts with system 800 by providing audio commands that are received and processed by processor 810.

[0092] The display subsystem 830 represents hardware components (e.g., a display device) and software components (e.g., a driver) that provide a visual display for presentation to a user. In one example, the display includes a tactile component or touch screen element for a user to interact with the computing device. The display subsystem 830 includes a display interface 832, which includes a particular screen or hardware device used to provide a display to the user. According to one example, the display interface 832 includes logic circuitry separate from the processor 810 (such as a graphics processor) to perform at least some of the processing related to the display. In one example, the display subsystem 830 includes a touch screen device that provides both output and input to the user. In one example, the display subsystem 830 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touch screen display. In one example, the display subsystem 830 generates display information based on data stored in memory, or based on operations performed by the processor 810, or both.

[0093] The I / O controller 840 represents hardware devices and software components related to user interaction. The I / O controller 840 may operate to manage hardware that is part of the audio subsystem 820 or the display subsystem 830 or both. Further, the I / O controller 840 indicates connection points for additional devices that can be connected to the system 800 for the user to interact with the system. For example, devices that can be attached to the system 800 may include a microphone device, a speaker or stereo system, a video system, or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with a particular application such as a card reader or other device.

[0094] As described above, the I / O controller 840 can communicate with the audio subsystem 820 or the display subsystem 830 or both. For example, input through a microphone or other audio device can provide input or commands to one or more applications or functions of the system 800. Further, audio output can be provided instead of, or in addition to, the display output. In other examples, where the display subsystem includes a touch screen, the display device can also operate as an input device that is at least partially managed by the I / O controller 840. Additional buttons or switches may also be present on the system 800 to provide I / O functions managed by the I / O controller 840.

[0095] In one example, the I / O controller 840 manages devices, or sensors 812, such as an accelerometer, a camera, a light sensor or other environmental sensor, a gyroscope, a global positioning system (GPS), or other hardware that may be included in the system 800. The input can be part of a direct user interaction and can also be provided to affect the operation of the system (such as filtering noise, adjusting the display for luminance detection, applying a flash for the camera, or other features).

[0096] In one example, system 800 includes a power management 850 that manages functions related to battery power usage, battery charging, and power-saving operations. Power management 850 manages power from power source 852 and provides power to components of system 800. In one example, power source 852 includes an AC-DC (alternating current to direct current) adapter that connects to a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion-based power). In one example, power source 852 includes only a DC power source provided by a DC power supply, such as an external AC-DC converter. In one example, power source 852 includes wireless charging hardware for charging in proximity to a charging field. In one example, power source 852 can include an internal battery or a fuel cell power source.

[0097] Memory subsystem 860 includes a memory device 862 for storing information within system 800. Memory subsystem 860 can include non-volatile (states do not change when power to the memory device is cut off) or volatile (states are indeterminate when power to the memory device is cut off) memory devices or combinations thereof. Memory 860 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of multiple applications and multiple functions of system 800. In one example, memory subsystem 860 includes a memory controller 864 (which can be considered part of the control of system 800 and potentially part of processor 810). Memory controller 864 includes a scheduler for generating and issuing commands to control access to memory device 862.

[0098] The connection function 870 includes a hardware device (e.g., a wireless or wired connector and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that enable the system 800 to communicate with external devices. The external device can be another computing device, an individual device such as a wireless access point or base station, and a peripheral device such as a headset printer or other device. According to one example, the system 800 exchanges data with the external device for storage in memory or for display on a display device. The data to be exchanged can include data to be stored in memory for reading, writing, or editing of the data, or data already stored in memory.

[0099] The connection function 870 can include a plurality of different types of connection functions. Generally speaking, the system 800 is shown with a cellular connection function 872 and a wireless connection function 874. The cellular connection function 872 generally refers to cellular network connectivity provided by a wireless carrier, such as GSM (registered trademark) (global system for mobile communications), a variant or derivative thereof, CDMA (code division multiple access), a variant or derivative thereof, TDM (time division multiplexing), a variant or derivative thereof, LTE (long term evolution, also referred to as "4G"), 5G, or other cellular service standards. The wireless connection function 874 refers to a non-cellular wireless connection function and can include a personal area network (such as Bluetooth (registered trademark)), a local area network (such as WiFi), a wide area network (such as WiMax), or other wireless communications, or combinations thereof. Wireless communication refers to the transfer of data through the use of modulated radio wave emissions through a non-solid medium. Wired communication is performed through a solid communication medium.

[0100] Peripheral connection 880 includes a hardware interface and connector, as well as software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that system 800 can either serve as a peripheral device to other computing devices ( "outward" 882) or have peripheral devices connected to system 800 ( "inward" 884). System 800 generally has a "docking" connector for connecting to other computing devices for the purpose of managing content (e.g., downloading, uploading, modifying, synchronizing) on system 800. Further, the docking connector may enable system 800 to connect to certain peripheral devices that allow system 800 to control content output, for example, to an audio-visual or other system.

[0101] In addition to a dedicated docking connector or other dedicated connection hardware, system 800 can make peripheral connections 880 via common or standard-based connectors. Common types can include universal serial bus (USB) connectors (which can include any of several different hardware interfaces), display ports including mini display port (MDP), high-definition multimedia interface (HDMI (registered trademark)), or other types.

[0102] Generally with respect to the description herein, in one example, a memory device includes additional drivers and additional sub-arrays per channel, and the channels are processed as two sub-channels at the system level overall on the channel by error checking and correction for each sub-part within the memory device.

[0103] In one example, the additional sub-array stores additional ECC (Error Checking and Correction) data. In one example, the data bus is x4 or x8, and the additional sub-array and the additional driver are for x4 implementation only. In one example, the channel is 64 bits over the burst length. In one example, 128 bits are prefetched and only 64 bits are transferred to the I / O (Input / Output) circuit. In one example, the memory device includes a dynamic random access memory (DRAM) device. In one example, the DRAM device includes a synchronous DRAM (SDRAM) device compatible with the double data rate (DDR) standard.

[0104] Generally regarding the description in this specification, in one example, the system has a controller and a memory device including an additional driver and an additional sub-array for each channel, and the channel is processed as two sub-channels by error checking and correction for each sub-part inside the memory device at the system level overall on the channel.

[0105] In one example, the additional sub-array stores additional ECC (Error Checking and Correction) data. In one example, the data bus is x4 or x8, and the additional sub-array and the additional driver are for x4 implementation only. In one example, the channel is 64 bits over the burst length. In one example, 128 bits are prefetched and only 64 bits are transferred to the I / O (Input / Output) circuit. In one example, the memory device includes a dynamic random access memory (DRAM) device. In one example, the DRAM device includes a synchronous DRAM (SDRAM) device compatible with the double data rate (DDR) standard. In one example, the system further includes one or more of a host processor device coupled to the memory device, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that supplies power to the system.

[0106] Generally, with respect to the description in this specification, in one example, a memory device includes a hardware interface coupled to a data signal line for exchanging data with a host, and error checking and correction (ECC) hardware for applying ECC to N data bits as two groups of N / 2 bits within the memory device.

[0107] In one example, N is equal to 64. In one example, the memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to the I / O (input / output) circuit of the hardware interface. In one example, the memory device further includes a memory array, the memory array includes a plurality of sub-arrays for providing N data bits, and the memory array includes additional sub-arrays beyond the N data bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, and the memory device includes additional drivers for controlling access to the additional sub-arrays. In one example, the hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface is coupled to an x4 data bus. In one example, the N data bits include a channel, and the ECC hardware processes the channel as two sub-channels each having N / 2 bits, and the host processes the channel as an N-bit channel for system-level ECC. In one example, the N data bits include a channel, and the ECC hardware processes the channel as two sub-channels each having N / 2 bits, and each sub-channel is individually correctable. In one example, the memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

[0108] Generally, with respect to the description of this specification, in one example, the system includes a plurality of memory devices. The memory devices have a hardware interface for coupling to data signal lines for exchanging data with a host, and error checking and correction (ECC) hardware for applying ECC to N data bits as two groups of N / 2 bits within the memory devices. The system also includes a memory controller coupled to the memory devices, and the memory controller provides system-level ECC for the data bits received from the memory devices.

[0109] In one example, N is equal to 64. In one example, the memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to the I / O (input / output) circuitry of the hardware interface. In one example, the memory device includes a memory array, the memory array includes a plurality of sub-arrays for providing N data bits, and the memory array includes additional sub-arrays beyond the N data bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, and the memory device includes additional drivers for controlling access to the additional sub-arrays. In one example, the hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface is coupled to an x4 data bus. In one example, the N data bits include a channel, and the ECC hardware processes the channel as two sub-channels each having N / 2 bits, and the memory controller provides system-level ECC for the N data bits. In one example, the N data bits include a channel, and the ECC hardware processes the channel as two sub-channels each having N / 2 bits, and each sub-channel is individually correctable. In one example, the memory device includes a synchronous dynamic random access memory (SDRAM) device that is compatible with the double data rate (DDR) standard. In one example, the system further includes one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery for powering the system.

[0110] Generally with respect to the description herein, in one example, a method includes receiving a data access command for accessing N data bits of a memory array of a memory device, and applying error checking and correction (ECC) to the N data bits as two groups of N / 2 bits within the memory device.

[0111] In one example, N is equal to 64. In one example, the step of internally applying ECC to N data bits includes the step of applying ECC to the N data bits transmitted in response to a read command, and includes the step of performing error correction on individual groups of N / 2 bits. In one example, the step of internally applying ECC to N data bits includes the step of applying ECC to the N data bits received with a write command, and includes the step of writing error codes to individual groups of N / 2 bits. In one example, 128 bits of data are prefetched and only 64 bits of the data are transferred to the I / O (input / output) circuit of the memory device. In one example, the memory array includes a plurality of sub-arrays for providing N bits, and the memory array includes additional sub-arrays beyond N bits for storing additional ECC data. In one example, the memory device includes drivers associated with the sub-arrays, and the memory device includes additional drivers for controlling access to the additional sub-arrays. In one example, the memory device includes a hardware interface that couples to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface couples to an x4 data bus. In one example, the N data bits include a channel, and the step of applying ECC includes the step of treating the channel as two sub-channels each having N / 2 bits, and a host coupled to the memory device treats the channel as an N-bit channel for system-level ECC. In one example, the N data bits include a channel, and the ECC hardware treats the channel as two sub-channels each having N / 2 bits, and each sub-channel is individually correctable. In one example, the memory device includes a synchronous dynamic random access memory (SDRAM) device that is compatible with the double data rate (DDR) standard.

[0112] The flowcharts shown in this specification provide examples of a series of various processing operations. The flowcharts can show operations to be executed by software or firmware routines and physical operations. The flowcharts can show examples of implementations of states of a finite state machine (FSM) that can be implemented in hardware and / or software. Although shown in a particular order or sequence, the order of operations can be modified unless otherwise specified. Accordingly, the illustrated diagrams should be understood as merely examples, and the processing can be executed in a different order, and some actions can be executed in parallel. Further, one or more operations can be omitted, and thus not all implementations execute all operations.

[0113] As long as various operations or functions are described in this specification, they can be described or defined as software code, instructions, configurations, and / or data. The content can be in a directly executable form ("object" or "executable" form), source code, or delta code ("delta" or "patch" code). The software content described in this specification can be provided via a product in which the content is stored, or via a communication interface by operating a communication interface for transmitting data. A machine-readable storage medium stores information in a form that can be accessed by a machine (e.g., a computing device, an electronic system, etc.) and can cause the described functions or operations to be executed by the machine, and includes any mechanism such as a recordable / non-recordable medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage medium, optical storage medium, flash memory device, etc.). A communication interface includes any mechanism such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc., that interfaces with any of a wired-connected medium, a wireless medium, an optical medium, etc. and communicates with other devices. The communication interface can be configured by providing a plurality of configuration parameters and / or by preparing to transmit a signal to provide a data signal in which the communication interface describes software content. The communication interface can be accessed via one or more commands or signals transmitted to the communication interface.

[0114] The various components described in this specification can be means for performing the described operations or functions. Each component described in this specification includes software, hardware, or a combination thereof. The component can be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuit (ASIC), digital signal processor (DSP), etc.), an embedded controller, a wired-connected circuit, etc.

[0115] In addition to the content described in this specification, various modifications can be made to the disclosed content and the implementation of the present invention without departing from their scope. Therefore, the illustrative examples and embodiments in this specification should be construed in an illustrative sense and not in a limiting sense. The scope of the present invention should be determined only by reference to the following claims. Other possible claims [Item 1] A memory device, a hardware interface coupled to a data signal line for exchanging data with a host, and error checking and correction (ECC) hardware for applying ECC to N data bits as two groups of N / 2 bits inside the memory device. A memory device. [Item 2] N is equal to 64 The memory device according to Item 1. [Item 3] The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to the I / O (input / output) circuit of the hardware interface. The memory device according to Item 2. [Item 4] The memory device further includes a memory array, the memory array includes a plurality of sub-arrays for providing the N data bits, and the memory array includes additional sub-arrays beyond the N data bits for storing additional ECC data. The memory device according to Item 1. [Item 5] The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array. The memory device according to Item 4. [Item 6] The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-array and additional driver are applied only when the hardware interface is coupled to an x4 data bus. The memory device according to item 5. [Item 7] The N data bits include channels, and the ECC hardware applies ECC to the channels in sub-channels each having N / 2 data bits, and each sub-channel is individually correctable. The memory device according to item 1. [Item 8] The memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. The memory device according to item 1. [Item 9] A plurality of memory devices, the memory device having a hardware interface for coupling to data signal lines for exchanging data with a host, and Error checking and correction (ECC) hardware for applying ECC to N data bits as two groups of N / 2 bits inside the memory device, the plurality of memory devices, and A memory controller coupled to the memory device, the memory controller providing system-level ECC for data bits received from the memory device, the memory controller, and A system. [Item 10] N is equal to 64 The system according to item 9. [Item 11] The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to the I / O (input / output) circuit of the hardware interface. The system according to item 10. [Item 12] The memory device includes a memory array, the memory array includes a plurality of sub-arrays for providing the N data bits, and the memory array includes additional sub-arrays beyond the N data bits for storing additional ECC data The system according to item 9 [Item 13] The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array The system according to item 12 [Item 14] The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-array and additional driver are applied only when the hardware interface is coupled to an x4 data bus The system according to item 13 [Item 15] The N data bits include channels, and the ECC hardware applies ECC to the channels in two sub-channels each having N / 2 data bits, and each sub-channel is individually correctable The system according to item 9 [Item 16] The memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard The system according to item 9 [Item 17] The system further includes one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery for supplying power to the system The system according to item 9 [Item 18] Receiving a data access command for accessing N data bits of a memory array of a memory device A method comprising applying error checking and correction (ECC) inside a memory device to N data bits as two groups of N / 2 bits each. Method. [Item 19] The step of applying ECC internally to the N data bits has a step of applying ECC to the N data bits for transmission in response to a read command, and includes a step of performing error correction for each group of N / 2 bits. The method according to Item 18. [Item 20] The step of applying ECC internally to the N data bits has a step of applying ECC to the N data bits received with a write command, and includes a step of writing an error code for each individual group of N / 2 bits. The method according to Item 18.

Claims

1. A memory device, comprising: A hardware interface coupled to a plurality of data signal lines for exchanging data with a host; Error checking and correcting hardware (ECC hardware) for applying ECC to N data bits as two groups of N / 2 bits inside the memory device; The hardware interface exchanges the two groups of N / 2 bits with the host via the data signal lines corresponding to each of the two groups of N / 2 bits Memory device.

2. N is equal to 64 The memory device according to claim 1.

3. The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to an I / O (input / output) circuit of the hardware interface The memory device according to claim 2.

4. The memory device further includes a memory array, the memory array includes a plurality of sub-arrays for providing the N bits, and the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data The memory device according to any one of claims 1 to 3.

5. The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array The memory device according to claim 4.

6. The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-array and the additional driver are applied only when the hardware interface is coupled to an x4 data bus The memory device according to claim 5.

7. A memory device, a hardware interface coupled to a plurality of data signal lines for exchanging data with a host, error checking and correcting hardware (ECC hardware) that applies ECC as two groups of N / 2 bits to N data bits inside the memory device, the memory device further includes a memory array, the memory array includes a plurality of sub-arrays for providing the N bits, the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data, the memory device includes drivers associated with the sub-arrays, the memory device includes additional drivers for controlling access to the additional sub-arrays, the hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface is coupled to an x4 data bus Memory device.

8. N is equal to 64 The memory device according to claim 7.

9. The memory device includes hardware for prefetching 128 bits of data and transferring only 64 bits of the data to the I / O (input / output) circuit of the hardware interface. The memory device according to claim 8.

10. The N data bits include a channel, the ECC hardware processes the channel as two sub-channels each having N / 2 data bits, and the host processes the channel as an N-bit channel for system-level ECC. The memory device according to any one of claims 1 to 9.

11. The memory device includes a synchronous dynamic random access memory (SDRAM) device that is compatible with the double data rate (DDR) standard. The memory device according to any one of claims 1 to 10. **Claim 12** A system having a memory, wherein the system A plurality of memory devices, each of the memory devices having a hardware interface for coupling to a plurality of data signal lines for exchanging data with a host, and error checking and correction hardware (ECC hardware) for applying ECC to N data bits as two groups of N / 2 bits inside the memory device; and A memory controller coupled to the memory device, the memory controller providing system-level ECC for data bits received from the memory device. The hardware interface exchanges the two groups of N / 2 bits with the host via the data signal lines corresponding to each of the two groups of N / 2 bits. System. **Claim 13** The memory device includes a memory array, the memory array includes a plurality of sub-arrays for providing the N bits, and the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data. The system according to claim 12. **Claim 14** The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array. The system according to claim 13. **Claim 15** A system having a memory, wherein the system A plurality of memory devices, wherein each of the memory devices includes a hardware interface for coupling to a plurality of data signal lines for exchanging data with a host, and error checking and correction hardware (ECC hardware) for applying ECC to N data bits as two groups of N / 2 bits within the memory device, and the plurality of memory devices; A memory controller coupled to the memory device, the memory controller providing system-level ECC for data bits received from the memory device; The memory device includes a memory array, the memory array includes a plurality of sub-arrays for providing the N bits, and the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data; The memory device includes drivers associated with the sub-arrays, and the memory device includes additional drivers for controlling access to the additional sub-arrays; The hardware interface is for coupling to a data bus that is x4 or x8, and the additional sub-arrays and additional drivers are applied only when the hardware interface is coupled to an x4 data bus; A system.

16. The N data bits include a channel, the ECC hardware processes the channel as two sub-channels each having N / 2 bits, and the host processes the channel as an N-bit channel for system-level ECC. The system according to any one of claims 12 to 15.

17. The system further comprises one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery for supplying power to the system. The system according to any one of claims 12 to 16.

18. A method for a memory device, comprising: receiving a memory access command from a memory controller, wherein the memory device is coupled to the memory controller by a plurality of data signal lines; applying error checking and correction (ECC) by hardware inside the memory device in response to the memory access command, the applying of the ECC including applying the ECC as two groups of N / 2 bits to N data bits; exchanging the two groups of N / 2 bits via the data signal lines corresponding to each of the two groups of N / 2 bits. A method.

19. The step of applying ECC as two groups of N / 2 bits to the N data bits includes accessing the N bits from a plurality of sub-arrays and driving the N bits with more than N / 2 + 1 drivers. The method according to claim 18.

20. A method for a memory device, comprising: receiving a memory access command from a memory controller, wherein the memory device is coupled to the memory controller by a plurality of data signal lines; applying error checking and correction (ECC) by hardware inside the memory device in response to the memory access command, the applying of the ECC including applying the ECC as two groups of N / 2 bits to N data bits; The memory device further includes a memory array, the memory array includes a plurality of sub-arrays for providing the N bits, and the memory array includes additional sub-arrays beyond the N bits for storing additional ECC data. The memory device includes a driver associated with the sub-array, and the memory device includes an additional driver for controlling access to the additional sub-array. The memory device is coupled to a data bus that is x4 or x8, and the additional sub-array and the additional driver are applied only when the memory device is coupled to an x4 data bus. Method.

21. The N data bits include a channel. The step of applying the ECC to the N data bits as two groups of N / 2 bits includes the step of applying the ECC to the channel as two sub-channels each having N / 2 bits. The memory controller applies the ECC to the channel as an N-bit channel for system-level ECC. The method according to any one of claims 18 to 20.

22. N is equal to 64, and the method includes: a step of prefetching 128 bits of data; a step of transferring only 64 bits of the data to the memory controller. The method according to any one of claims 18 to 21.

Images