A power electronics assembly in which a power electronics device is incorporated within a flip chip

Abstract

To provide power electronics assemblies.SOLUTION: The invention provides a power electronics assembly including a circuit board assembly including a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, and a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive logic layers. The laminate panel includes a power electronics device assembly including a substrate and a power electronics device. The substrate includes a graphite layer and a metal layer covering the graphite layer. A recess is formed in an outer surface of the metal layer. The power electronics device is bonded within the recess of the outer surface of the substrate. Each electrically conductive logic layer is provided at a first surface of the laminate panel, and each electrically conductive power layer is provided at a second surface of the laminate panel opposite the first surface of the laminate panel.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification generally relates to power electronics assemblies, and more particularly, to apparatuses and methods for power electronics assemblies having a low overall thermal resistance while achieving a compact package size.

Background Art

[0002] Due to the increasing use of electronics in vehicles, there is a need to make electronics systems more compact. One of the components of such an electronics system is a power electronics device that can be used as a switch in an inverter. Power electronics devices require a lot of cooling because heat is generated.

[0003] Furthermore, conventional power electronics assemblies include multiple layers formed from different materials, which results in different coefficients of expansion at each interface of the layers. Thus, in order to reduce stress accumulation and warping, the same number of layers can be provided on each side of the power electronics device. However, this requires additional layers that are otherwise unnecessary, and thus can increase the overall footprint of the power electronics assembly. For these and other reasons, there is a need to improve the cooling of power electronics devices while maintaining a compact package size.

Summary of the Invention

[0004] In one embodiment, the power electronics assembly includes a circuit board assembly including a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, and a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers. The laminate panel includes a substrate and a power electronics device assembly including a power electronics device. The substrate includes a graphite layer and a metal layer covering the graphite layer, the metal layer having a recess formed in an outer surface thereof. The power electronics device is joined within the recess in the outer surface of the substrate. Each of the electrically conductive logic layers is provided on a first surface of the laminate panel, and each of the electrically conductive power layers is provided on a second surface of the laminate panel opposite the first surface of the laminate panel.

[0005] In another embodiment, the power electronics assembly includes a circuit board assembly including a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, and a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers, and a cooling plate. The circuit board assembly is mounted on a surface of the cooling plate. The laminate panel includes a substrate and a power electronics device assembly including a power electronics device. The substrate includes a graphite layer and a metal layer covering the graphite layer, the metal layer having a recess formed in an outer surface thereof. The power electronics device is joined within the recess in the outer surface of the substrate. A plurality of vias thermally connect each of the power electronics devices to the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers. Each of the electrically conductive logic layers is provided on a first surface of the laminate panel, and each of the electrically conductive power layers is provided on a second surface of the laminate panel opposite the first surface of the laminate panel.

[0006] In yet another embodiment, the method includes providing a first electrical insulating layer on a first surface of the cooling plate and providing a circuit board assembly on the first electrical insulating layer opposite the cooling plate. The circuit board assembly includes a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, and a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers. The laminate panel includes a power electronics device assembly including a substrate and a power electronics device. The substrate includes a graphite layer and a metal layer covering the graphite layer, the metal layer having a recess formed in an outer surface thereof. The power electronics device is joined within the recess on the outer surface of the substrate. Each of the electrically conductive logic layers is provided on a first surface of the laminate panel, and each of the electrically conductive power layers is provided on a second surface of the laminate panel opposite the first surface of the laminate panel.

[0007] These features and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description in conjunction with the drawings.

Brief Description of the Drawings

[0008] The embodiments depicted in the drawings are essentially exemplary and illustrative and are not intended to limit the subject matter defined by the claims. The following detailed description of the exemplary embodiments can be understood when read in conjunction with the following drawings, in which like structures are denoted by like reference numerals.

[0009]

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Embodiments for Carrying Out the Invention

[0010] The embodiments described in this specification generally target a power electronics assembly in which a circuit board assembly is connected to a cooling plate. The circuit board assembly includes a substrate and an inverted power electronics device assembly that may be referred to as a flip chip in this specification. The power electronics device may be incorporated into the substrate. As described herein, the inverted power electronics device assembly arranges the power electronics device incorporated into the substrate so as to face the cooling plate rather than in the direction opposite to the cooling plate.

[0011] The power electronics device assembly of the present disclosure includes a power electronics device attached to a substrate. As described in more detail below, the substrate includes a graphite layer that provides improved heat dissipation capabilities. Further, embodiments of the present disclosure include one or more electrical insulation layers that electrically insulate the power electronics device from the cooling plate. Since electrical insulation is provided by the substrate itself, for example, it becomes possible to remove the electrical insulation layer between the printed circuit board and the cooling plate by the electrical insulation layer of the substrate.

[0012] As described in more detail below, the substrate of the present disclosure provides improved thermal properties by means of a graphite layer that promotes the heat flux flow towards the cooling plate. The substrate described herein includes stacked metals, graphite, and one or more electrical insulating layers within a compact package. The bonding material described herein for bonding the substrate is configured to increase the thermal conductivity relative to other bonding techniques while maintaining the ability to electrically insulate the substrate. The devices, systems, and apparatuses described herein improve the heat flux from the substrate to the cooling plate, thereby increasing the thermal dissipation performance and cooling performance for the circuit board assembly.

[0013] The cooling plates, power electronics device assemblies, circuit board assemblies, power electronics assemblies, and the like described herein can be used in, but are not limited to, electrified vehicles such as electric vehicles, hybrid electric vehicles, any electric motor, generator, industrial tool, household appliance, and the like. The various assemblies described herein may be electrically connected to an electric motor and / or a battery and may be configured as an inverter circuit operable to convert direct current (DC) power to alternating current (AC) power.

[0014] As used herein, "power electronics device" means any electrical component used to convert DC power to AC power and vice versa. Embodiments may also be employed in AC-AC converter and DC-DC converter applications. Non-limiting examples of power electronics devices include power metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), thyristors, and power transistors.

[0015] As used herein, the phrase "fully incorporated" means that each side of the component is surrounded by the substrate. For example, when a power electronics device assembly is fully incorporated by a circuit board, it means that the material of the circuit board covers each side of the circuit board. If one or more sides of the component are exposed, the component is "partially incorporated".

[0016] As used herein, "substrate" is a mounting substrate operable to be attached to a power electronics device and includes one or more of a metal layer, a graphite layer, and an electrical insulation layer.

[0017] Various embodiments of a power electronics assembly, a power electronics device assembly, and a cooling plate are described in detail below. To refer to the same or similar parts, the same reference numbers are used throughout the drawings as much as possible.

[0018] Referring now to FIGS. 1 and 2, an exemplary power electronics assembly 100 is generally shown in an assembled view and an exploded view, respectively. The power electronics assembly 100 shown in FIGS. 1 and 2 includes a cooling plate 102 and a circuit board assembly 106. The cooling plate 102 can be any device capable of removing heat flux from a power electronics device 140 (see FIG. 4) connected to the substrate material of the circuit board assembly 106. Non-limiting examples of the cooling plate 102 include a heat sink, single-phase liquid cooling, two-phase liquid cooling, and a vapor chamber. FIGS. 1 and 2 show the cooling plate 102 configured as a single-phase liquid cooling device. The cooling plate 102 includes a fluid inlet 132 and a fluid outlet 134 fluidly connected to a fluid chamber 115 (FIG. 12) within the cooling plate 102. FIGS. 1 and 2 show the fluid inlet 132 and the fluid outlet 134 on the same side of the cooling plate 102, but the present disclosure is not limited to such embodiments. That is, in other embodiments, the fluid inlet 132 and the fluid outlet 134 can be located on other sides.

[0019] Referring back to FIGS. 1 and 2, circuit board assembly 106 is connected (e.g., attached) to the first surface 107 of cooling plate 102. FIGS. 1 and 2 show circuit board assembly 106 as being attached to the first surface 107 of cooling plate 102 by fasteners 101 (e.g., bolts and nuts) that extend through through-holes 105 in cooling plate 102 and through-holes 109 in circuit board assembly 106. It should be understood that in other embodiments, through-holes 105, 109 and fasteners 101 may be omitted as described below.

[0020] In an embodiment, circuit board assembly 106 can be a 3D printed layer. In such an embodiment, it should be understood that the 3D printed layer of circuit board assembly 106 reduces the overall thermal resistance. In an embodiment, circuit board assembly 106 can be laminated to cooling plate 102. However, other additive manufacturing processes for attaching circuit board assembly 106 to cooling plate 102 are envisioned and are within the scope of the present disclosure. Additionally, as described in more detail herein, via connections or vias can be made using laser drilling between various components of circuit board assembly 106 and power electronics device 140 (FIG. 4). That is, the vias are drilled through circuit board assembly 106 to the top surface of each conductive layer and power electronics device 140. As described in more detail herein, the vias are then filled with copper by an electroplating method to establish an electrical connection between the components. Circuit board assembly 106 is generally shown in FIGS. 1 and 2, although the individual layers and various steps of the assembly are shown in FIGS. 7 - 12.

[0021] Referring now to FIGS. 3-12, the individual steps of manufacturing the power electronics assembly 100 are shown. As shown in FIG. 3, a first electrical insulation layer 180 is deposited on a first surface 107 of the cooling plate 102 so as to reduce the thermal resistance between the circuit board assembly 106 (FIG. 1) and the cooling plate 102. The first electrical insulation layer 180 can generally be any layer that provides electrical insulation, such as a ceramic or the like. In an embodiment, the first electrical insulation layer 180 includes an insulated metal substrate (IMS) dielectric film. The IMS dielectric film can be a solid film layer. In other embodiments, the first electrical insulation layer 180 can be a thermal grease layer. Note that the first electrical insulation layer 180 may not have dedicated vias.

[0022] Referring now to FIGS. 4 and 5, there are shown, respectively, an exploded bottom perspective view and an assembled cross-sectional view of an exemplary substrate 121. The substrate 121 includes a plurality of stacked layers. In particular, the substrate 121 shown in FIGS. 4 and 5 includes a metal layer 122 and a graphite layer 124 incorporated within the metal layer 122. The metal layer 122 includes an inner surface 125 and an outer surface 128 opposite the inner surface 125. In an embodiment, the metal layer 122 includes a first metal layer and a second metal layer, and the graphite layer 124 is positioned between the first metal layer and the second metal layer. The metal layer 122 includes a recess 127 disposed within the outer surface 128 of the metal layer 122. The recess 127 is sized to receive a power electronics device 140. As will be described in more detail below, the metal layer 122 provides an electrically conductive surface to which electrodes at the bottom surface of the power electronics device 140 are connected (e.g., directly and / or via electrical connection vias). It should be understood that the various layers of the substrate 121 shown in FIGS. 4 and 5 are merely exemplary. That is, in some embodiments, for example, the substrate 121 may include a plurality of graphite layers and / or other layers disposed between metal layers. The substrate 121 is an inverted substrate 121 as described in more detail herein such that when disposed on the cold plate 102, the power electronics device 140 faces in a direction that is the direction of the cold plate 102 (i.e., the -z direction of the coordinate axes shown in the drawings) and not the opposite direction (i.e., the +z direction of the coordinate axes).

[0023] Note that the substrate 121 in the embodiments of FIGS. 4 and 5 includes a graphite layer 124 incorporated within the metal layer 122 so as to provide a substrate 121 that is symmetric along the z-axis of the coordinate axes shown in FIGS. 4 and 5. The symmetry of the substrate 121 balances the forces on the substrate 121 during the high-temperature bonding process. Since the metal layer 122 and the graphite layer 124 have different coefficients of thermal expansion, it may be desirable to have a symmetric substrate stack to balance the thermally induced stresses during the bonding process.

[0024] The metal layer 122 can be made of any suitable metal or alloy. As non-limiting examples, copper and aluminum can be used as the metal layer 122. The metal layer 122 of the substrate 121 has a recess 127 formed within its outer surface 128. The recess 127 can be formed, for example, by chemical etching. The recess 127 has a size and shape to receive the power electronics device 140. The outer surface 128 can generally be the second major surface or face of the metal layer 122 on the opposite side of the inner surface 125 (configured as the first major surface or face of the metal layer 122). That is, the metal layer 122 can be a planar layer, whereby the inner surface 125 faces the graphite layer 124 and the opposite outer surface 128 faces the power electronics device 140 and the circuit board assembly 106 (FIG. 1).

[0025] The graphite layer 124 shown in the embodiment of FIG. 5 is provided to facilitate both heat dissipation across the substrate 121 and heat dissipation towards the cooling plate 102 (see, e.g., FIG. 12). The crystal structure of graphite provides high thermal conductivity to the graphite and is useful for conducting the heat flux towards the cooling plate 102. However, graphite does not have an isothermal profile. Rather, graphite has a non-isothermal profile, having high conductivity along two axes and low thermal conductivity along a third axis. To account for the non-isothermal profile of graphite, the substrate 121 is designed to be a rectangular shape such that the length dimension of the substrate 121 is greater than the width dimension of the substrate 121. Referring to FIG. 5, the graphite layer 124 has high thermal conductivity along the x-axis and z-axis of the coordinate axes shown in FIG. 5. Accordingly, the substrate 121 is designed such that the dimension along the x-axis of the substrate 121 is greater than the dimension along the y-axis of the substrate 121. The heat flux moves along the x-axis and z-axis. As described in more detail below, the heat flux moves along the x-axis towards the cooling plate 102 by the substrate 121. The heat flux also moves along the z-axis towards the cooling plate 102.

[0026] Referring back to FIG. 4, an exploded view of a power electronics device assembly 146 including a substrate 121 and a power electronics device 140 is shown. FIG. 4 shows the power electronics device 140 and a bonding layer 143 with respect to a recess 127 in the substrate 121. For example, the bonding layer 143 can be a solder layer. As another example, the bonding layer 143 can be a transient liquid phase bonding layer 143. The power electronics device 140 includes a plurality of large electrodes 141 and a plurality of small electrodes 142 on an outward-facing surface. The large electrodes 141 can be power supply electrodes, while the small electrodes 142 can be signal electrodes. It should be noted that although not visible in FIG. 4, the power electronics device 140 further includes one or more electrodes on the opposite inward-facing surface. One or more electrodes on the inward-facing surface of the power electronics device 140 are electrically connected to the metal layer 122 by disposing the power electronics device 140 within the recess 127. Thus, the electrical connection to the electrodes on the inward-facing surface of the power electronics device 140 can be made by the metal layer 122.

[0027] As described above, the substrate 121 is a mounting substrate to which the power electronics device 140 is bonded. The substrate 121 provides an electrically conductive surface area for making connections to the electrodes on the inward-facing surface of the power electronics device 140. The substrate 121 further provides a heat dissipation function and electrical insulation.

[0028] Referring now to FIG. 6, a bottom perspective view of the laminate panel 200 is shown to include one or more power electronics device assemblies 146 surrounded by a laminate material 202. The laminate panel 200 is provided on a first electrical insulation layer 180 opposite the cooling plate 102 (FIG. 3). In an embodiment, the laminate material 202 includes FR-4, although alternative materials fall within the scope of the present disclosure. As shown, a total of six power electronics device assemblies 146 are provided and joined to the cooling plate 102 in two rows of three each via the first electrical insulation layer 180 and the laminate material 202. However, it should be understood that any number of power electronics device assemblies 146 may be utilized depending on the application.

[0029] Referring now to FIGS. 7-11, the individual steps of forming the circuit board assembly 106 are shown. Specifically, referring to FIG. 7, a cross-sectional view of the laminate panel 200 is shown to include an upper conductive layer 206 and a lower conductive layer 208 defining a core layer 204. The upper conductive layer 206 is provided on the upper surface 200a of the laminate panel 200, and the lower conductive layer 208 is provided on the lower surface 200b opposite the laminate panel 200. The upper conductive layer 206 has an upper surface 206a and a lower surface 206b opposite the upper surface 206a of the upper conductive layer 206. Similarly, the lower conductive layer 208 has an upper surface 208a and a lower surface 208b opposite the upper surface 208a of the lower core conductive layer 208. As shown in FIG. 7 and described herein, holes are formed in the core layer 204, and the power electronics device assemblies 146 are inserted into the respective holes. Thus, the power electronics devices 140 are exposed through the lower conductive layer 208.

[0030] Referring now to FIG. 8, a second electrical insulating layer 210 is provided on an upper surface 206a of the upper conductive layer 206, and a third electrical insulating layer 212 is provided on a lower surface 208b of the lower conductive layer 208. The second electrical insulating layer 210 has an upper surface 210a and a lower surface 210b on a side opposite to the upper surface 210a of the second electrical insulating layer 210. Similarly, the third electrical insulating layer 212 has an upper surface 212a and a lower surface 212b on a side opposite to the upper surface 212a of the third electrical insulating layer 212. As shown, the laminate panel 200 is provided between the second electrical insulating layer 210 and the third electrical insulating layer 212. It should be understood that the second electrical insulating layer 210 and the third electrical insulating layer 212 may include the same material as the first electrical insulating layer 180 (FIG. 3). Still referring to FIG. 8, a first electrically conductive logic layer 216 is provided on the upper surface 210a of the second electrical insulating layer 210, and a first electrically conductive power layer 218 is provided on the lower surface 212b of the third electrical insulating layer 212. In an embodiment, the first electrically conductive logic layer 216 and the first electrically conductive power layer 218 are copper layers. The first electrically conductive logic layer 216 has an upper surface 216a and a lower surface 216b on a side opposite to the upper surface 216a of the first electrically conductive logic layer 216. Similarly, the first electrically conductive power layer 218 has an upper surface 218a and a lower surface 218b on a side opposite to the upper surface 218a of the first electrically conductive power layer 218.

[0031] Referring to FIG. 9, vias 112 (both electrical conduction vias and thermal vias) are formed to extend between any combination of the power electronics device 140 of the power electronics device assembly 146, the first electrically conductive logic layer 216, and the first electrically conductive power layer 218. For example, via 112 is shown as extending between the first electrically conductive logic layer 216 and the first electrically conductive power layer 218. Further, via 112 is shown as extending between the first electrically conductive power layer 218 and the bottom surface 140b of the power electronics device 140 so as to electrically connect the first electrically conductive logic layer 216 and the first electrically conductive power layer 218 to the bottom surface 140b of the power electronics device 140. Further, via 112 is shown as extending between the first electrically conductive power layer 218 and the bottom surface 121b of the substrate 121 so as to electrically connect the first electrically conductive logic layer 216 and the first electrically conductive power layer 218 to the top surface 140a of the power electronics device 140. Via 112 can be formed by any suitable method such as laser drilling, for example. It should be understood that the scope of the present disclosure is not limited to the specific configuration of via 112 shown in FIG. 9, and other configurations are envisioned based on the specific needs of the circuit board assembly 106.

[0032] Via 112 not only provides a current path for the switching current, but can also provide a drive signal to the power electronics device 140. Note that in some embodiments, a portion of via 112 can be configured as a thermal via that does not carry the drive signal or the switching current. Additionally, the arrangement of the substrate enables flux transfer from the power electronics device 140 to the cooling plate 102 (FIG. 12) through the substrate 121 as described herein. Thus, the heat flux is optimally directed through the substrate 121 towards the cooling plate 102 in a direction away from the power electronics device 140.

[0033] Referring now to FIG. 10, via 112 is filled with copper by electroplating to form an electrical connection between each power electronics device assembly 146, the first electrically conductive logic layer 216, and the first electrically conductive power layer 218. However, it should be understood that via 112 may be filled by any other suitable method other than electroplating.

[0034] Referring now to FIG. 11, the first electrically conductive logic layer 216 and the first electrically conductive power layer 218 are etched in a specified pattern to conduct current. When the first electrically conductive logic layer 216 and the first electrically conductive power layer 218 are etched, the steps described above with respect to FIGS. 8-10 are repeated, and as a result, a fourth electrical insulation layer 220 is provided on the upper surface 216a of the first electrically conductive logic layer 216, and a fifth electrical insulation layer 222 is provided on the lower surface 218b of the first electrically conductive power layer 218.

[0035] Subsequently, the second electrically conductive logic layer 224 is provided on the upper surface 220a of the fourth electrically insulating layer 220 on the side opposite to the first electrically conductive logic layer 216, and the second electrically conductive power layer 226 is provided on the lower surface 222b of the fifth electrically insulating layer 222 on the side opposite to the first electrically conductive power layer 218. Accordingly, the first electrically conductive logic layer 216 and the second electrically conductive logic layer 224 are provided on the upper side of the power electronics device assembly 146, and the first electrically conductive power layer 218 and the second electrically conductive power layer 226 are provided on the lower side of the power electronics device assembly 146 on the side opposite to the upper side. In other words, the power electronics device assembly 146 separates the first electrically conductive logic layer 216 and the second electrically conductive logic layer 224 from the first electrically conductive power layer 218 and the second electrically conductive power layer 226. Accordingly, it should be understood that each electrically conductive logic layer 216, 224 is on one side of the power electronics device assembly 146, and each electrically conductive power layer 218, 226 is on the opposite side of the power electronics device assembly 146. Further, the electrically conductive logic layers 216, 224 are not adjacent to any of the electrically conductive power layers 218, 226, and vice versa.

[0036] Subsequently, additional vias 112 are formed through the second electrically conductive logic layer 224 to the first electrically conductive logic layer 216, and further, the additional vias 112 are formed through the second electrically conductive power layer 226 to the first electrically conductive power layer 218. Then, similar to what has been described herein with respect to FIG. 10, the vias 112 are filled with copper by electroplating so as to form electrical connections between the first electrically conductive logic layer 216 and the second electrically conductive logic layer 224, and between the first electrically conductive power layer 218 and the second electrically conductive power layer 226. However, it should be understood that the vias 112 can be filled by any other suitable method other than electroplating.

[0037] Still referring to FIG. 11, the second electrically conductive logic layer 224 and the second electrically conductive power layer 226 are also etched into a specified pattern that conducts current. It should be understood that within a high temperature and high pressure chamber, the second electrically conductive logic layer 224 may be laminated to the first electrically conductive logic layer 216, and the second electrically conductive power layer 226 may be laminated to the first electrically conductive power layer 218. During this lamination step, the material from the second electrical insulation layer 210 and the fourth electrical insulation layer 220 fills the gaps defined by the etching of the first electrically conductive logic layer 216 and the second electrically conductive logic layer 224. Similarly, the material from the third electrical insulation layer 212 and the fifth electrical insulation layer 222 fills the gaps defined by the etching of the first electrically conductive power layer 218 and the second electrically conductive power layer 226.

[0038] It should be understood that the circuit board assembly 106 may include any number of electrical insulation layers and electrical conductive layers other than those shown herein. However, in an embodiment, the circuit board assembly 106 includes the same number of electrically conductive logic layers as the number of electrically conductive power layers. Additionally, each of the electrically conductive logic layers is provided on one side of the power electronics device assembly 146, and each of the electrically conductive power layers is provided on the opposite side of the power electronics device assembly 146. In such a case, the steps described herein with respect to FIGS. 8 - 11 may be repeated with each additional layer laminated to the previous layer.

[0039] Referring now to FIG. 12, a cross-sectional view of the power electronics assembly 100 is shown including a circuit board assembly 106 mounted on a cooling plate 102 via a first electrical insulating layer 180. It should be understood that the electrically conductive logic layers are not provided between the laminate panel 200 and the cooling plate 102. Instead, only the electrically conductive power layers 218, 226 are provided between the laminate panel 200 and the cooling plate 102, and the electrically conductive logic layers 216, 224 are disposed on the opposite side of the laminate panel 200. Further, since each of the electrically conductive power layers 218, 226 is provided between the laminate panel 200 and the cooling plate 102, the electrically conductive power layers 218, 226 are not provided on the side of the laminate panel 200 opposite to the cooling plate 102. Thus, each of the electrically conductive logic layers 216, 224 is separated from each of the electrically conductive power layers 218, 226 by the laminate panel 200.

[0040] The advantage of separating the electrically conductive logic layers 216, 224 from the electrically conductive power layers 218, 226 is that the total number of layers of the circuit board assembly 106 can be reduced without increasing the total footprint of the circuit board assembly 106. Further, this reduces the overall thermal resistance between the power electronics device 140 and the cooling plate 102 since the electrically conductive power layers 218, 226 provide a lower thermal resistance as compared to the electrically conductive logic layers 216, 224. This also provides an improvement in cooling performance for the circuit board assembly 106. Further, having the electrically conductive power layers 218, 226 provided on the same side of the laminate panel 200 reduces the loop inductance, and thus reduces the losses and increases the efficiency with respect to the circuit board assembly 106.

[0041] As shown, cooling fluid (shown as movement arrow 135) from a storage section (not shown) flows into fluid chamber 115 through fluid inlet 132, and exits fluid chamber 115 as warmed cooling fluid through fluid outlet 134. The cooling fluid flows through, for example, a heat exchanger (not shown), has heat removed from the cooling fluid 135, and then is returned to the storage section. Although not shown, an array of fins may be provided in fluid chamber 115 to provide additional surface area for heat transfer to the cooling fluid 135.

[0042] Still referring to FIG. 12, one or more surface mount electronics 214 may be implemented on a second electrically conductive logic layer 224. As described herein, the surface mount electronics 214 may include, for example, transistors, resistors, capacitors, and the like. Thus, it should be understood that the circuit board assembly 106 includes at least a laminate panel 200 including a plurality of power electronics device assemblies 146, as well as a first electrically conductive logic layer 216, a second electrically conductive logic layer 224, a first electrically conductive power layer 218, a second electrically conductive power layer 226, and surface mount electronics 214.

[0043] It should be understood from the above that a power electronics assembly and a method of manufacturing a power electronics assembly are defined herein. Specifically, the power electronics assembly disclosed herein includes a circuit board assembly including a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, and a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive logic layers. The laminate panel includes a substrate and a power electronics device assembly including a power electronics device. The substrate includes a graphite layer and a metal layer covering the graphite layer. A recess is formed on the outer surface of the metal layer. The power electronics device is joined within the recess on the outer surface of the substrate. Each electrically conductive logic layer is provided on a first surface of the laminate panel, and each electrically conductive power layer is provided on a second surface of the laminate panel opposite the first surface of the laminate panel.

[0044] Note that the terms "substantially" and "about" may be used herein to represent the degree of inherent uncertainty that may arise from any quantitative comparison, value, measurement, or other representation. These terms may also be used herein to represent the degree to which a quantitative representation may vary from the stated reference without causing a change in the basic function of the subject matter in question.

[0045] Although specific embodiments are described and depicted herein, it is to be understood that various other changes and modifications may be made without departing from the scope of the claimed subject matter. Further, although various aspects of the claimed subject matter are described herein, such aspects need not be utilized in combination. Accordingly, the appended claims are intended to encompass all such changes and modifications that fall within the scope of the claimed subject matter.

[0046] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments described herein without departing from the scope of the claimed subject matter. Accordingly, this specification is intended to cover such modifications and variations as fall within the scope of the appended claims and their equivalents.

[0047] [Example 1] A power electronics assembly, wherein the power electronics assembly comprises a circuit board assembly, and the circuit board assembly comprises a plurality of electrically conductive logic layers, a plurality of electrically conductive power layers, a laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers, and, the laminate panel comprises a power electronics device assembly, and the power electronics device assembly comprises a substrate, wherein a graphite layer, a metal layer covering the graphite layer, the metal layer having a recess formed in an outer surface thereof, a substrate comprising: a power electronics device joined within the recess in the outer surface of the substrate, and comprising: each electrical conductive logic layer is provided on a first surface of the laminate panel, and each electrical conductive power layer is provided on a second surface of the laminate panel opposite the first surface of the laminate panel, a power electronics assembly. [Example 2] The laminate panel is a laminate material, and a plurality of power electronics device assemblies incorporated within the laminate material, the power electronics assembly according to Example 1. [Example 3] The laminate material includes FR-4, the power electronics assembly according to Example 2. [Example 4] The circuit board assembly further includes a plurality of vias that extend through the plurality of electrical conductive logic layers and the plurality of electrical conductive power layers to thermally connect the power electronics device to the plurality of electrical conductive logic layers and the plurality of electrical conductive power layers, the power electronics assembly according to Example 1. [Example 5] The substrate has a length greater than the width of the substrate, the power electronics assembly according to Example 1. [Example 6] further comprising a cooling plate, the circuit board assembly being joined to a surface of the cooling plate by a first electrical insulating layer, the power electronics assembly according to Example 1. [Example 7] The power electronics device of the power electronics device assembly faces the direction of the cooling plate, the power electronics assembly according to Example 6. [Example 8] Each of the plurality of electrically conductive power layers is provided between the laminate panel and the cooling plate, the power electronics assembly according to Example 6. [Example 9] The electrically conductive logic layer is not provided between the power electronics device assembly and the cooling plate, the power electronics assembly according to Example 6. [Example 10] The electrically conductive power layer is not provided on the side opposite to the cooling plate in the power electronics device assembly, the power electronics assembly according to Example 6. [Example 11] A power electronics assembly, wherein the power electronics assembly A circuit board assembly, wherein the circuit board assembly A plurality of electrically conductive logic layers, A plurality of electrically conductive power layers, A laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers, and, the laminate panel Comprises a power electronics device assembly, the power electronics device assembly Is a substrate, A graphite layer, A metal layer covering the graphite layer, the metal layer having a recess formed on the outer surface thereof, and, a substrate, A power electronics device joined in the recess on the outer surface of the substrate, a plurality of vias thermally connecting each of the power electronics devices to the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers, a power electronics device, and, a circuit board assembly, A cooling plate, the circuit board assembly being mounted on the surface of the cooling plate, a cooling plate, and, Each electrically conductive logic layer is provided on the first surface of the laminate panel, and each electrically conductive power layer is provided on the second surface of the laminate panel on the side opposite to the first surface of the laminate panel, a power electronics assembly. [Example 12] The laminate panel includes a laminate material, A plurality of power electronics device assemblies are incorporated in the laminate material, the power electronics assembly according to Example 11. [Example 13] The power electronics device of the power electronics device assembly faces the direction of the cooling plate, the power electronics assembly according to Example 11. [Example 14] Each of the plurality of electrically conductive power layers is provided between the laminate panel and the cooling plate, the power electronics assembly according to Example 11. [Example 15] The electrically conductive logic layer is not provided between the power electronics device assembly and the cooling plate, the power electronics assembly according to Example 11. [Example 16] The electrically conductive power layer is not provided on the side opposite to the cooling plate in the power electronics device assembly, the power electronics assembly according to Example 11. [Example 17] Providing a first electrical insulation layer on the first surface of the cooling plate, Providing a circuit board assembly on the first electrical insulation layer on the side opposite to the cooling plate, A method including: the circuit board assembly includes A plurality of electrically conductive logic layers, A plurality of electrically conductive power layers, A laminate panel provided between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers, Comprising: the laminate panel includes A power electronics device assembly, wherein the power electronics device assembly comprises a substrate, a graphite layer, a metal layer covering the graphite layer, the metal layer having a recess formed in an outer surface thereof, and a substrate; a power electronics device joined within the recess in the outer surface of the substrate; and a method, wherein each electrically conductive logic layer is provided on a first surface of the laminate panel, and each electrically conductive power layer is provided on a second surface of the laminate panel opposite to the first surface of the laminate panel. [Example 18] The method according to Example 17, wherein the power electronics device of the power electronics device assembly faces the direction of the cooling plate. [Example 19] The method according to Example 17, wherein the electrically conductive logic layer is not provided between the power electronics device assembly and the cooling plate. [Example 20] The power electronics assembly according to Example 17, wherein the electrically conductive power layer is not provided on a side opposite to the cooling plate in the power electronics device assembly.

Claims

1. 1. A power electronics assembly, comprising: a circuit board assembly, the circuit board assembly comprising: a plurality of electrically conductive logic layers; a plurality of electrically conductive power planes; a laminate panel disposed between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers; The laminate panel comprises: a power electronics device assembly, the power electronics device assembly comprising: A substrate, A graphite layer; a metal layer covering the graphite layer, the metal layer having a recess formed on an outer surface of the metal layer; A substrate comprising: a power electronic device bonded within the recess on the outer surface of the substrate; Equipped with each electrically conductive logic layer is disposed on a first side of the laminate panel and each electrically conductive power layer is disposed on a second side of the laminate panel opposite the first side of the laminate panel.

2. The laminate panel comprises: A laminate material; a plurality of power electronic device assemblies embedded within the laminate material; The power electronics assembly of claim 1 , comprising:

3. The power electronics assembly of claim 2 , wherein the laminate material comprises FR-4.

4. 10. The power electronics assembly of claim 1 , wherein the circuit board assembly further comprises a plurality of vias extending through the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers to thermally couple the power electronics device to the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers.

5. The power electronics assembly of claim 1 , wherein the substrate has a length that is greater than a width of the substrate.

6. 10. The power electronics assembly of claim 1, further comprising a cold plate, said circuit board assembly being bonded to a surface of said cold plate by a first electrically insulating layer.

7. The power electronics assembly of claim 6 , wherein the power electronics device of the power electronics device assembly faces toward the cold plate.

8. The power electronics assembly of claim 6 , wherein each of said plurality of electrically conductive power planes is disposed between said laminate panel and said cold plate.

9. The power electronics assembly of claim 6 , wherein no electrically conductive logic layer is disposed between said power electronics device assembly and said cold plate.

10. 7. The power electronics assembly of claim 6, wherein an electrically conductive power plane is not provided on an opposite side of the power electronics device assembly from the cold plate.

11. 1. A power electronics assembly, comprising:

1. A circuit board assembly, comprising: a plurality of electrically conductive logic layers; a plurality of electrically conductive power planes; a laminate panel disposed between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers; The laminate panel comprises: a power electronics device assembly, the power electronics device assembly comprising: A substrate, A graphite layer; a metal layer covering the graphite layer, the metal layer having a recess formed on an outer surface of the metal layer; A substrate comprising: power electronics devices bonded within the recesses on the outer surface of the substrate, a plurality of vias thermally connecting each of the power electronics devices to the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers; a circuit board assembly comprising: a cooling plate, the circuit board assembly being mounted to a surface of the cooling plate; Equipped with each electrically conductive logic layer is disposed on a first side of the laminate panel and each electrically conductive power layer is disposed on a second side of the laminate panel opposite the first side of the laminate panel.

12. the laminate panel comprises a laminate material; The power electronics assembly of claim 11 , wherein a plurality of power electronic device assemblies are embedded within the laminate material.

13. providing a first electrically insulating layer on a first surface of the cooling plate; providing a circuit board assembly on the first electrically insulating layer opposite the cold plate; The circuit board assembly includes: a plurality of electrically conductive logic layers; a plurality of electrically conductive power planes; a laminate panel disposed between the plurality of electrically conductive logic layers and the plurality of electrically conductive power layers; The laminate panel comprises: a power electronics device assembly, the power electronics device assembly comprising: A substrate, A graphite layer; a metal layer covering the graphite layer, the metal layer having a recess formed on an outer surface of the metal layer; A substrate comprising: a power electronic device bonded within the recess on the outer surface of the substrate; Equipped with each electrically conductive logic layer is disposed on a first side of the laminate panel and each electrically conductive power layer is disposed on a second side of the laminate panel opposite the first side of the laminate panel.

14. The method of claim 13 , wherein the power electronics devices of the power electronics device assembly face toward the cold plate.

15. The method of claim 13 , wherein an electrically conductive logic layer is not disposed between the power electronics device assembly and the cold plate.

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