CTLE Using a Low-Power Inverter

Abstract

An electronic device is provided that includes a continuous-time linear equalizer (CTLE). In one example, the CTLE includes a first inverter (402), a second inverter (404) having an input for receiving an input signal (IN), a capacitor (408) coupled between the input of the first inverter (402) and the input of the second inverter (404), a resistor (410) coupled between a common-mode voltage (VCM) and the input of the first inverter, a third inverter (406) having an output for providing an output signal (Out), and a node (416) having the output of the first inverter (404), the output of the second inverter (402), the input of the third inverter (406), and the output of the third inverter.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to electronic circuits, and more particularly, to a continuous-time linear equalizer (CTLE) using a low-power inverter.

Background Art

[0002] A continuous-time linear equalizer (CTLE) is a core analog building block of a wired receiver front-end for signal equalization. Various CTLE architectures have been studied to optimize power, area, and performance. Conventional CTLE circuits use current-mode logic (CML) circuits. In recent years, in CTLE design, circuits using inverters have attracted attention because they have a smaller die area compared to designs using CML. However, the power and performance of designs using inverters depend on the topology, the number and size of the inverters, and their linearity. It is desirable to provide a design using a low-power inverter for CTLE.

Summary of the Invention

[0003] Techniques are described for providing an electronic device including a continuous-time linear equalizer (CTLE) and a CTLE using a low-power inverter. In one example, an electronic device configured as a continuous-time linear equalizer (CTLE) includes a first inverter, a second inverter having an input for receiving an input signal, a capacitor coupled between the input of the first inverter and the input of the second inverter, a resistor coupled between a common-mode voltage and the input of the first inverter, a third inverter having an output for supplying an output signal, and nodes having the output of the first inverter, the output of the second inverter, the input of the third inverter, and the output of the third inverter.

[0004] In another example, an electronic device configured as a receiver includes a front-end circuit having a continuous-time linear equalizer (CTLE) and a digital back-end circuit coupled to the front-end. The CTLE includes a first inverter, a second inverter having an input for receiving an input signal, a capacitor coupled between the input of the first inverter and the input of the second inverter, a resistor coupled between the common-mode voltage and the input of the first inverter, a third inverter having an output for supplying an output signal, and a node having the output of the first inverter, the output of the second inverter, the input of the third inverter, and the output of the third inverter.

[0005] In another example, an electronic device configured as a continuous-time linear equalizer (CTLE) includes a first inverter, a second inverter having an input for receiving an input signal, a capacitor coupled between the input of the first inverter and the input of the second inverter, a first resistor coupled between the common-mode voltage and the input of the first inverter, a third inverter, and a node including the output of the first inverter, the output of the second inverter, and the output of the third inverter, the node being an output node for supplying an output signal, and a second resistor coupled between the input of the third inverter and the node.

[0006] These and other aspects can be understood with reference to the following detailed description.

[0007] To enable a more detailed understanding of the features described above, the content briefly summarized above will be described more specifically with reference to implementation examples, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only general implementation examples and should not be regarded as limiting the scope thereof.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 12A

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Figure 12C

Mode for Carrying Out the Invention

[0009] For ease of understanding, the same reference numerals are used to designate the same elements common to the figures, as far as possible. It is considered that the elements in one example can be beneficially incorporated into other examples.

[0010] Hereinafter, various features will be described with reference to the drawings. Note that the drawings are not necessarily drawn to scale, and elements having the same structure or function are denoted by the same reference numerals throughout the drawings. Note that the drawings are only intended to facilitate the description of the features. The drawings are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated examples need not include all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or explicitly described as such.

[0011] FIG. 1 is a block diagram showing an electronic device configured as a receiver 100 according to an example. The receiver 100 includes a front-end circuit 102 and a digital back-end circuit 104. The front-end circuit 102 includes a continuous-time linear equalizer (CTLE) 106 among other components (for example, an automatic gain control circuit, a filter, an additional CTLE that may or may not be the same as the CTLE 106). The digital back-end circuit 104 includes various circuits for processing an analog signal output by the front-end circuit 102 (for example, a sampler, an analog-to-digital converter (ADC), a decision feedback equalizer (DFE) circuit, a clock and data recovery circuit, etc.). The CTLE 106 receives an input signal and operates as a high-pass filter for compensating for the low-pass characteristics of a transmission medium that supplies the input signal. Both the maximum amplitude and position of the frequency response of the CTLE 106 are adjustable by a control circuit within the front-end circuit 102 and / or the digital back-end circuit 104. An example of the CTLE 106 will be described below.

[0012] FIG. 2 is a schematic diagram showing a conventional CTLE 200. Such a circuit is described in "A 56 Gb / s 6 mW 300 um" by Zheng, Kevin et al. 2It is described in "Inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS" (2018 IEEE Custom Integrated Circuits Conference (CICC)). CTLE200 includes inverters 202, 204, 208, 210 and capacitor 206. The inputs of inverters 202 and 204 are connected to receive an input signal (IN). The output of inverter 202 is connected to node X. The output of inverter 204 is connected to node Y. Capacitor 206 is connected between nodes X and Y. Both the input and output of inverter 208 are connected to node X. Both the input and output of inverter 210 are connected to node Y. The output of inverter 210 supplies an output signal (OUT).

[0013] Inverter 204 has a transconductance gm1, inverter 202 has a transconductance gm2, and inverters 208, 210 have a transconductance gm- L and capacitor 206 has a capacitance C HF are assumed. CTLE200 is a CTLE using an inverter with an additive topology. Peaking is achieved by adding gm2 to the high-frequency signal path through capacitor 206 (resulting in an "additive" topology). The low-frequency gain (G1), high-frequency gain (G2), and peaking are defined by the following equations. G1 = gm1 / gm L G2=(gm1 + gm2) / (2*gm L ) Peaking (dB)=20*log[(gm1 + gm2) / 2*gm1]

[0014] The boundary between low frequency and high frequency is determined by C HF and gm L .

[0015] FIG. 3 is a schematic diagram showing a CTLE 300 according to the prior art. The CTLE in FIG. 3 uses a subtractive topology as described, for example, in "An Inverter-based Analog Front End for a 56 Gb / s PAM4 Wireline Transceiver in 16 nm CMOS" by Zheng, Kevin et al. (2018 IEEE VLSI Circuits Symposium). The CTLE 300 includes inverters 302, 304, 306, 308, 310 and a capacitor 312. The inputs of inverters 302 and 308 are connected to receive an input signal (IN). The output of inverter 302 is connected to the input of inverter 304, the output of inverter 304, and the input of inverter 306 (referred to as node 314). The output of inverter 306 is connected to the output of inverter 308, the input of inverter 310, and the output of inverter 310 (referred to as node 316). Node 316 supplies an output signal (OUT).

[0016] Inverter 302 has a transconductance gm A and inverter 304 has a transconductance gm B -, inverter 306 has a transconductance gm2, inverter 308 has a transconductance gm1, and inverter 310 has a transconductance gm L are assumed to have. G1, G2, and peaking of the CTLE 300 are defined by the following equations. G1=(gm1 / gm L )-(gm A / gm B )*(gm2 / gm L ) G2=gm1 / gm L Peaking (dB)=20*log[(gm B *gm1) / (gm B *gm1-gm A *gm2)]

[0017] The boundary between the low frequency and the high frequency is C HF and gm BIt is determined by

[0018] CTLE design using an inverter is attractive in terms of area consumption, but its power consumption is a serious design issue. The more aggressive equalization is required, the more power is consumed by the CTLE. Another design problem with the inverter-based CTLE is linearity, which affects the signal-to-noise and distortion ratio (SNDR). When explaining the power consumption estimation, assuming G1 = 0 dB and G2 = 6 dB, 6 dB of peaking can be obtained.

[0019] Consider the additive topology shown in Figure 2. In this case, the following holds. G1 = gm1 / gm L = 1 (0 dB) G2 = (gm1 + gm-- -2 ) / (2*gm L- ) = 2 (6 dB) gm1 = gm L gm2 = 3*gm L Total gm = gm1 + gm2 + 2*gm L = gm- L + 3*gm L + 2*gm L = 6*gm L

[0020] Therefore, in this example, the transconductance of inverter 202 is 3*gm L and the transconductance of inverter 204 is gm L The total device drain parasitic capacitance is approximately 6*Cdd, and the total device gate parasitic capacitance is approximately 2*Cgg. Here, Cdd and Cgg are the drain and gate capacitances of an inverter with a transconductance of gm- L respectively. The additive topology of Figure 2 has a linearity problem due to the common-mode mismatch between node X and node Y. The DC bias conditions at nodes X and Y are the capacitances C HF and two different gms LIt is not the same for the inverter. More specifically, if all devices are exactly the same, the bias conditions of the inverter will actually be the same. However, when the input swing enters the image, there is non-linearity. In this topology, to achieve 6 dB peaking, the top path requires a gain of 3x(gm2 / gm L = 3). In this case, with a large input swing, the top path may saturate. As a result, the inverter will have a significantly different signal bias compared to the bottom path.

[0021] In the subtractive topology of Figure 3, assuming again G1 = 0 dB and G2 = 6 dB, 6 dB peaking can be obtained. In this case, the following holds. (1) G1 = (gm1 / gm L ) - (gm A / gm B ) * (gm2 / gm L ) = 1 (0 dB) (2) G2 = gm1 / gm L = 2 (6 dB) -> gm1 = 2 * gm L (3) From (1), gm1 - (gm A / gm B ) * gm2 = gm L (2) and (3) give gm2 = (gm B / gm A ) * gm L- And the total gm = gm1 + gm2 + gm L = 2 * gm L + (gm B / gm A ) * gm L + gm L = 3 * gm L + (gm B- / gm A ) * gm L gm A = gm B When, the total gm is 4 * gm L-

[0022] To obtain a fair comparison with the additive topology of FIG. 2, for the gain bandwidth product, the gm of the subtractive topology of FIG. 3 L needs to be doubled (e.g., 2*gm L ). Therefore, the transconductance of inverter 306 is 2*gm L , the transconductance of inverter 308 is 4*gm L , and the transconductance of inverter 310 is 2*gm L . Assuming gm A = gm B , the total gm is 8*gm L . The total device drain parasitic capacitance at OUT is approximately 8*Cdd, and the total device gate parasitic capacitance at OUT is approximately 2*Cgg. Here, Cdd and Cgg are the drain and gate parasitic capacitances of an inverter having a transconductance of gm L , respectively.

[0023] Comparing the additive topology of FIG. 2 with the subtractive topology of FIG. 3, the subtractive topology improves linearity because the outputs of inverter 308 and inverter 306 are connected. In particular, by connecting the outputs of inverter 306 and inverter 308, since the large signal bias conditions are very similar, the problems in the additive topology of FIG. 2 are eliminated. However, the subtractive topology of FIG. 3 exhibits higher power consumption and more device parasitic capacitance and has the same gain bandwidth product as the additive topology of FIG. 2.

[0024] Figure 4 is a schematic diagram showing an example of CTLE106. CTLE106 includes inverters 402, 404, 406, a capacitor 408, and a resistor 410. CTLE106 can be connected to a VCM generator 450. An example of the VCM generator 450 will be described below with reference to FIG. 10. Those skilled in the art will understand that other types of common-mode voltage generators can be used. Node 412 is connected to the input of inverter 402. Node 414 is connected to the input of inverter 404. Capacitor 408 is connected between node 412 and node 414. Resistor 410 is connected between voltage VCM and node 412. Node 414 receives an input signal (IN). The output of inverter 402 is connected to the output of inverter 404, the input of inverter 406, and the output of inverter 406 (referred to as node 416). Node 416 supplies an output signal (OUT). Resistor 410 has a resistance R HF and capacitor 408 has a capacitance C HF . Inverter 404 has a transconductance gm1, inverter 402 has a transconductance gm2, and inverter 406 has a transconductance gm L .

[0025] The CTLE106 shown in FIG. 4 adopts an additive topology. In contrast to the CTLE200 in FIG. 2, capacitor 408 is arranged at the inputs of inverter 402 and inverter 404. Also, the CTLE106 in FIG. 4 omits one of the gm L inverters (for example, inverter 208). Voltage VCM is the input common-mode voltage generated internally by the front-end circuit 102. An example of the generation of VCM will be described below.

[0026] G1 and G2 of CTLE106 are defined by the following equations. G1 = gm1 / gm L G2=(gm1 + gm2) / gm L Peaking (dB)=20*log[(gm1 + gm2) / gm1]

[0027] At low frequencies, the input signal is blocked by capacitor 408. At high frequencies, the input signal passes through capacitor 408. Therefore, CTLE106 has an additive topology. The transfer function of CTLE106 is (gm1 / gm L )*(1+(gm2 / gm1)*(sR HF C HF / (1+sR HF C- HF ))), where s is the complex frequency parameter.

[0028] Figure 5 is a graph 500 of the transfer function of CTLE106 in Figure 4. In graph 500, the vertical axis represents the gain (dB), and the horizontal axis represents the frequency (log scale). Curve 502 represents the transfer function of CTLE106 having a gain equal to 20*log(G2) between frequency F2 and frequency F3. Between frequency 0 and frequency F1, the gain is 20*log(G1). Therefore, the obtained peaking is 20*log(G2 / G1) in dB units. After frequency F3, the gain decreases.

[0029] Assuming G1 = 0dB and G2 = 6dB, a peaking of 6dB occurs. In this case, the following holds. G1 = gm1 / gm L = 1 (0dB) -> gm1 = gm L G2 = (gm1 + gm2) / gm L = 2 (6dB) -> gm2 = gm L Total gm = gm1 + gm2 + gm L = 3*gm L

[0030] To obtain a fair comparison with CTLE200 in Figure 2, with respect to the gain-bandwidth product, the gm of CTLE106 L needs to be doubled (for example, 2*gm L ). In such a case, the transconductance of inverter 402 is 2*gm Land the transconductance of the inverter 404 is 2*gm L and the transconductance of the inverter 406 is 2*gm L The total device drain parasitic capacitance at OUT is approximately 6*Cdd, and the total device gate parasitic capacitance at OUT is approximately 2*Cgg. Here, Cdd and Cgg are the drain and gate parasitic capacitances of an inverter having a transconductance of gm L respectively. Compared with the additive topology of FIG. 2, the additive topology of FIG. 4 exhibits the same power consumption and device parasitic capacitance, but does not exhibit a linearity problem because the output of the inverter 402 and the output of the inverter 404 are connected to each other.

[0031] Table 1 below summarizes the comparison between the CTLE200 of FIG. 2 and the CTLE106 of FIG. 4. TIFF0007697956000001.tif50170

[0032] As shown in Table 1, the topology of the CTLE106 of FIG. 4 shows less power consumption and no linearity problem than the subtractive topology as seen in the additive topology of FIG. 2.

[0033] FIG. 6 is a schematic diagram showing a CTLE600 according to another example. The CTLE600 can be used as an alternative version of the above CTLE106. The CTLE600 exhibits multiple peakings at low and high frequencies. By adding another inverter, resistor, and capacitor compared to the CTLE106 of FIG. 4, additional peakings are implemented.

[0034] In particular, CTLE600 includes inverters 602, 604, 606, 608, resistors 610, 612, and capacitors 614, 616. Node 618 is connected to the input of inverter 602. Node 620 is connected to the input of inverter 604. Node 622 is connected to the input of inverter 606. Capacitor 614 is connected between node 618 and node 620. Capacitor 616 is connected between node 620 and node 622. Resistor 610 is connected between node 618 and voltage VCM. Resistor 612 is connected between node 622 and voltage VCM. Node 624 includes the outputs of inverters 602, 604, 606, the input and output of inverter 608. Node 624 supplies the output signal (OUT). Node 620 receives the input signal (IN). Resistors 610 and 612 each have a resistance of R HF and a resistance of R LF respectively. Capacitors 614 and 616 each have a capacitance of C- HF and a capacitance of C LF respectively. Inverters 604, 602, 606, 608 each have a transconductance of gm1, gm2, gm3, gm L respectively.

[0035] FIG. 7 is a graph 700 of the transfer function of CTLE600 of FIG. 6. In graph 700, the vertical axis represents gain (dB) and the horizontal axis represents frequency (log scale). Curve 702 represents the transfer function of CTLE600 and has an intermediate gain equal to 20*log(G1) between frequency FL2 and frequency FH1, and a high gain equal to 20*log(G2) between frequency FH2 and frequency F3. Between frequency 0 and frequency FL1, the low gain is equal to 20*log(G0). Therefore, the obtained peakings are respectively peaking H and peaking LFor this, it is 20 * log(G2 / G1) and 20 * log(G2 / G0) in dB. After frequency F3, the gain decreases. CTLE600 can be extended to have additional peaks by adding an inverter leg (using corresponding capacitors and resistors) between the input and the output.

[0036] Figure 8 is a schematic diagram showing CTLE800 according to another example. CTLE800 can be used as an alternative version of the above CTLE106. CTLE800 includes inverters 802, 804, 806, a capacitor 808, and resistors 810, 818. Node 812 is connected to the input of inverter 802. Node 814 is connected to the input of inverter 804. Capacitor 808 is connected between node 812 and node 814. Resistor 810 is connected between voltage VCM and node 812. Node 814 receives the input signal (IN). The output of inverter 802 is connected to the outputs of inverter 804 and inverter 806 (referred to as node 816). Node 816 supplies the output signal (OUT). Resistor 818 is connected between node 816 and the input of inverter 806. Resistor 810 has a resistance R HF and capacitor 808 has a capacitance C HF and inverter 804 has a transconductance gm1, inverter 802 has a transconductance gm2, inverter 806 has a transconductance gm L and resistor 818 has a resistance R A CTLE800 is similar to CTLE106 in Figure 4 but employs bandwidth expansion using an active inductor formed by inverter 806 and resistor 818.

[0037] FIG. 9 is a schematic diagram showing a CTLE900 according to another example. CTLE900 includes inverters 902, 904, 906, a capacitor 908, resistors 910, and an inductor 918. Node 912 is connected to the input of inverter 902. Node 914 is connected to the input of inverter 904. Capacitor 908 is connected between node 912 and node 914. Resistor 910 is connected between voltage VCM and node 912. Node 914 receives an input signal (IN). The output of inverter 902 is connected to the output of inverter 904, the input of inverter 906, and the output of inverter 906 (referred to as node 916). Inductor 918 is connected to node 916 and supplies an output signal (OUT). Resistor 910 has a resistance R HF and capacitor 908 has a capacitance C HF and inverter 904 has a transconductance gm1, inverter 902 has a transconductance gm2, inverter 906 has a transconductance gm L and inductor 918 has an inductance L. CTLE900 is similar to CTLE106 in FIG. 4 but employs bandwidth expansion using a passive inductor 918.

[0038] In yet another example, the various components of CTLE106, 600, 800, 900 may be variable and may be programmable for equalization goals and applications. In the case of CTLE106, it includes resistor 410, capacitor 408, inverters 402, 404, 406 (i.e., the inverters may have adjustable transconductance). In the case of CTLE600, it includes resistors 610, 612, capacitors 614, 616, and inverters 602, 604, 606, 608. In the case of CTLE800, it includes resistors 810, 818, capacitor 808, and inverters 802, 804, 806. In the case of CTLE900, it includes resistor 910, capacitor 908, inductor 918, and inverters 902, 904, 906.

[0039] FIG. 10 is a schematic diagram showing a VCM generator 1000 for a CTLE circuit according to an example. The VCM generator 1000 includes an inverter 1002 having an input connected to an output, and supplies a voltage VCM. The VCM generator 1000 is implemented using a diode using an inverter. The inverter 1002 must be a replica of the inverters 402, 404, 406 from the perspective of the layout form and bias conditions (e.g., current density).

[0040] FIG. 11 is a schematic diagram showing a CTLE 1100 according to another example. The CTLE 1100 generates a common-mode voltage VCM from a pseudo-differential output. The CTLE 1100 includes inverters 1102, 1104, 1106, 1122, 1124, 1126. The CTLE 1100 further includes resistors 1110, 1130, 1137, 1138. The CTLE 1100 further includes capacitors 1108 and 1128.

[0041] Node 1112 is connected to the input of inverter 1102. Node 1114 is connected to the input of inverter 1104. Capacitor 1108 is connected between node 1112 and node 1114. Resistor 1110 is connected between node 1114 and node 1140 that supplies VCM. Node 1112 receives an input signal (INP). The output of inverter 1102 is connected to the output of inverter 1104, the input of inverter 1106, and the output of inverter 1106 (referred to as node 1116). Node 1116 supplies an output signal (OUTN). Resistor 1110 has a resistance R HF and capacitor 1108 has a capacitance C HF and inverter 1102 has a transconductance gm1, inverter 1104 has a transconductance gm2, and inverter 1106 has a transconductance gm L having.

[0042] Node 1132 is connected to the input of inverter 1122. Node 1134 is connected to the input of inverter 1124. Capacitor 1128 is connected between node 1132 and node 1134. Resistor 1130 is connected between node 1132 and node 1140 that supplies VCM. Node 1134 receives an input signal (INN). The output of inverter 1122 is connected to the output of inverter 1124, the input of inverter 1126, and the output of inverter 1126 (referred to as node 1136). Node 1136 supplies an output signal (OUTP). Resistor 1130 has a resistance R HF and capacitor 1128 has a capacitance C HF and inverter 1124 has a transconductance gm1, inverter 1122 has a transconductance gm2, and inverter 1126 has a transconductance gm L .

[0043] Resistor 1137 is connected between node 1116 and node 1140. Resistor 1138 is connected between node 1136 and node 1140. Node 1140 supplies a voltage VCM. In this pseudo-differential case, VCM is generated via self-biasing, thereby eliminating the power consumption associated with having a replica diode as a VCM generator.

[0044] FIG. 12A is a block diagram showing a programmable device 54 according to an example. The programmable device 54 includes a plurality of programmable integrated circuits (ICs) 1, such as programmable ICs 1A, 1B, 1C, 1D. In one example, the programmable ICs 1 are each IC dies disposed on an interposer 60. The programmable ICs 1 each include a super logic region (SLR) 53 of the programmable device 54, such as SLR 53A, 53B, 53C, 53D. The programmable ICs 1 are interconnected via conductors on the interposer 60 (referred to as super long lines (SLLs) 52).

[0045] FIG. 12B is a block diagram showing a programmable IC1 according to an example. When using the programmable IC1, one of the programmable devices or programmable ICs can be implemented in the programmable device 54. The programmable IC1 includes a programmable logic (PL) 3 (also called a programmable fabric), a configuration logic 25, and a configuration memory 26. The programmable IC1 can be connected to external circuits such as a non-volatile memory 27, a DRAM 28, and other circuits 29. The PL3 includes logic cells 30, a support circuit 31, and a programmable interconnect 32. The logic cells 30 include circuits configurable to implement a general logic function of a plurality of inputs. The support circuit 31 includes dedicated circuits such as transceivers, input / output blocks, digital signal processors, and memories. The logic cells and the support circuit 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cells 30, setting parameters of the support circuit 31, and programming the programmable interconnect 32 is stored in the configuration memory 26 by the configuration logic 25. The configuration logic 25 can obtain configuration data from the non-volatile memory 27 or any other source (e.g., the DRAM 28, or other circuits 29). The programmable IC1 may include a processing system (PS) 2. The PS2 may include a microprocessor, a memory, a support circuit, an IO circuit, etc. The programmable IC1 may include a network on chip (NOC) 55 and a data processing engine (DPE) array 56. The NOC55 is configured to provide communication between subsystems of the programmable IC1, such as between the PS2, the PL3, and the DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. In one example, the programmable IC1 may include one or more examples of the CTLE106, including any implementation example described herein.

[0046] FIG. 12C shows an implementation of a field programmable gate array (FPGA) of a programmable IC1 including PL3. The PL3 shown in FIG. 12C can be used in an example of any programmable device described herein. PL3 includes a number of different programmable tiles including configurable logic blocks ("CLB") 33, random access memory blocks ("BRAM") 34, input / output blocks ("IOB") 36, configuration logic and clock logic ("CONFIG / CLOCKS") 42, digital signal processing blocks ("DSP") 35, special input / output blocks ("I / O") 41 (e.g., configuration ports and clock ports), digital clock managers, analog-to-digital converters, system monitoring logic, and other programmable logic 39. In one example, the programmable IC1 may include one or more examples of CTLE106, including any implementation example described herein.

[0047] In some PLs, each programmable tile may include at least one programmable interconnect element ("INT") 43 having connections to the input and output terminals 48 of the programmable logic elements within the same tile, as shown by the example included in the upper part of FIG. 6D. Each programmable interconnect element 43 may further include connections to the interconnect segments 49 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 43 may also include connections to the interconnect segments 50 of the general-purpose routing resources between logic blocks (not shown). The general-purpose routing resources may include a routing channel between a logic block (not shown) having tracks of interconnect segments (e.g., interconnect segment 50) and a switch block (not shown) for connecting the interconnect segments. The interconnect segments of the general-purpose routing resources (e.g., interconnect segment 50) may span one or more logic blocks. The programmable interconnect element 43, together with the general-purpose routing resources, implements a programmable interconnect structure ("programmable interconnect") for the illustrated PL.

[0048] In an implementation example, the CLB33 may include a configurable logic element (CLE) 44 that can be programmed to implement user logic in addition to one programmable interconnect element (INT) 43. The BRAM34 may include a BRAM logic element (BRL) 45 in addition to one or more programmable interconnect elements. Usually, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as five CLBs, but other numbers (e.g., 4) can also be used. The DSP tile 35 may include a DSP logic element (DSPL) 46 in addition to an appropriate number of programmable interconnect elements. The IOB36 may include two examples of input / output logic elements (IOL) 47 in addition to, for example, an example of the programmable interconnect element 43. As will be apparent to those skilled in the art, the actual I / O pads connected to, for example, the I / O logic element 47 are typically not limited to the area of the input / output logic element 47.

[0049] In the illustrated example, the horizontal region near the center of the die (shown in FIG. 3D) is used for configuration, clock, and other control logic. The vertical columns 51 extending from this horizontal region or column are used to distribute clock and configuration signals across the width of the PL.

[0050] The PL utilizing the architecture shown in FIG. 12C may include additional logic blocks that disrupt the regular cylindrical structure that makes up most of the PL. The additional logic blocks may be programmable blocks and / or dedicated logic.

[0051] Note that FIG. 12C is intended to show only an exemplary PL architecture. For example, the number of logic blocks in a row, the relative width of a row, the number and order of rows, the type of logic blocks included in a row, the relative size of the logic blocks, and the interconnect / logic implementation included at the top of FIG. 12C are merely exemplary. For example, in an actual PL, in order to facilitate an efficient implementation of user logic, wherever a CLB appears, there are usually multiple adjacent CLB rows, but the number of adjacent CLB rows varies depending on the overall size of the PL.

[0052] The foregoing is directed to specific examples, but other and further examples can be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. An electronic device, comprising a continuous-time linear equalizer (CTLE), wherein the CTLE comprises: a first inverter having an input connected to a first node; a second inverter having an input connected to a second node, wherein the input of the second inverter is configured to receive a low-frequency component of an input signal and a high-frequency component of the input signal via the second node; a capacitor connected between the first node and the second node, wherein the capacitor is configured to block the low-frequency component and pass the high-frequency component to the first node; a first resistor connected between a common-mode voltage and the first node; a third inverter having an output for supplying an output signal; and a third node having the output of the first inverter, the output of the second inverter, the input of the third inverter, and the output of the third inverter. An electronic device comprising the above.

2. A front-end circuit having the CTLE according to Claim 1; and a digital back-end circuit connected to the front-end circuit. The electronic device according to Claim 1, comprising the above.

3. The electronic device according to Claim 1 or 2, further comprising a common-mode voltage generator connected to the first resistor for supplying a common-mode voltage. The electronic device according to Claim 1 or 2, further comprising the above.

4. The common-mode voltage generator comprises: a fourth inverter having an input and an output, wherein the input and the output of the fourth inverter are connected to supply the common-mode voltage. The electronic device according to Claim 3, comprising the above.

5. The electronic device according to Claim 4, wherein the fourth inverter is a replica of each of the first inverter, the second inverter, and the third inverter.

6. a fourth inverter having an output connected to the third node; an additional capacitor connected between the input of the second inverter and the input of the fourth inverter; and an additional resistor connected between the common-mode voltage and the input of the fourth inverter. The electronic device according to Claim 1 or 2, further comprising the above.

7. The electronic device according to Claim 1 or 2, further comprising an inductor connected between the third node and the output signal. The electronic device according to Claim 1 or 2, further comprising the above.

8. The capacitor includes a first capacitor, and the CTLE comprises: a fourth inverter; A fifth inverter having an input connected to receive an additional input signal, wherein the input signal and the additional input signal include a differential signal pair, the fifth inverter; A second capacitor connected between the input of the fifth inverter and the input of the fourth inverter; A second resistor connected between the input of the fourth inverter and the common mode voltage; A sixth inverter having an output for supplying an additional output signal, wherein the output signal and the additional output signal include a differential signal pair, the sixth inverter; A fourth node including the output of the fourth inverter, the output of the fifth inverter, the input of the sixth inverter, and the output of the sixth inverter; A fifth node for supplying the common mode voltage; A third resistor connected between the third node and the fifth node; A fourth resistor connected between the fourth node and the fifth node The electronic device according to claim 1 or 2, further comprising.

9. An electronic device, Comprising a continuous-time linear equalizer (CTLE), the CTLE comprising: A first inverter having an input connected to a first node; A second inverter having an input connected to a second node, wherein the input of the second inverter is configured to receive a low-frequency component and a high-frequency component of an input signal via the second node; A capacitor connected to the first node and the second node, the capacitor being configured to block the low-frequency component and pass the high-frequency component to the first node; A first resistor connected between the common mode voltage and the first node; A third inverter; A third node including the output of the first inverter, the output of the second inverter, and the output of the third inverter, the third node supplying an output signal; A second resistor connected between the input of the third inverter and the third node An electronic device comprising.

10. A common mode voltage generator connected to the first resistor for supplying the common mode voltage The electronic device according to claim 9, further comprising.

11. The common mode voltage generator is: A fourth inverter having an input and an output, wherein the input and the output of the fourth inverter are connected to supply the common mode voltage, the fourth inverter The electronic device according to claim 10, comprising

12. The electronic device according to claim 11, wherein the fourth inverter is a replica of each of the first inverter, the second inverter, and the third inverter.

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