Integrated device, semiconductor device, and method of manufacturing an integrated device

Abstract

An integrated device, a semiconductor device, and a method for manufacturing the integrated device are provided, which improve the integration density of the capacitors of the integrated device. The integrated device in the embodiment of the present application includes: disposing a first dielectric layer on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer forming a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer forming a second capacitor; and the first metal layer is connected to the second metal layer via a first conductor structure, and the first capacitor and the second capacitor are connected in parallel.

Description

Technical Field

[0001] This application relates to microelectronics technology, and in particular, to integrated devices, semiconductor devices, and methods of manufacturing integrated devices.

Background Art

[0002] Gallium nitride (GaN) power devices have great potential in the field of power conversion due to their small on-resistance and fast turn-on speed of the gallium nitride power devices. However, the spike voltage (10V) that the gate of the device can withstand is smaller than that of conventional silicon devices, and the threshold voltage is relatively small (between 1.0V and 2.5V). Therefore, in the high-speed turn-on process of the device, vibrations are likely to occur in the drive waveform of the gate of the device due to parasitic inductance on the substrate. As a result, the gate of the device is damaged by overvoltage, or the device is accidentally turned on. To solve this problem, a gate drive circuit and a single die can be monolithically integrated on the platform of the gallium nitride device.

[0003] Currently, on a single-die process platform, usually, the metal layers available in the process flow are used to form the electrode plates of the capacitor (such as the field plate layer or the gate metal layer, etc.), and the integration of the capacitor is limited by the chip area.

[0004] Since the thickness of the dielectric layer usually occupies a large area of the chip region, there are limitations in the integration of the capacitor.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present application provide an integrated device, a semiconductor device, and a method of manufacturing an integrated device for improving the integration density of capacitors of the integrated device.

Means for Solving the Problems

[0006] In a first aspect of the present application, there is provided an integrated device having a first metal layer, a first dielectric layer disposed on the first metal layer, a second dielectric layer disposed on the first dielectric layer, a gate metal layer disposed between the first dielectric layer and the second dielectric layer, and a second metal layer disposed on the second dielectric layer. The first metal layer, the first dielectric layer, and the gate metal layer form a first capacitor. The second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor. The first metal layer is connected to the second metal layer via a first conductor structure, and the first capacitor and the second capacitor are connected in parallel.

[0007] In the first aspect, the gate metal layer, the first dielectric layer, and the first metal layer form a first capacitor, and the gate metal layer, the second dielectric layer, and the second metal layer form a second capacitor, that is, two capacitors are formed simultaneously within one integrated device. Also, the first metal layer is connected to the second metal layer via a first conductor structure, and the first capacitor and the second capacitor are connected in parallel. Therefore, the capacitance in the integrated device increases, that is, the integration density of the capacitors in the integrated device is improved.

[0008] In an imaginable embodiment, the gate metal layer and the first metal layer have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities.

[0009] In a possible embodiment, the integrated device further has a third metal layer, a P-type conductive layer disposed below the first metal layer, and a gallium aluminum nitride layer disposed below the P-type conductive layer, and a two-dimensional electron gas is included below the gallium aluminum nitride layer. The first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor. The third metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacts the two-dimensional electron gas. The third metal layer is connected to the gate metal layer through a second conductor structure, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel.

[0010] In the foregoing embodiment, the two-dimensional electron gas is disposed below the gallium aluminum nitride layer, and when the voltage between the third metal layer and the gate metal layer falls within a preset range, the two-dimensional electron gas is generated. The first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor, that is, three capacitors are simultaneously formed on the integrated device. Also, the third metal layer is connected to the gate metal layer through a second conductor structure, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel. Therefore, the integration density of the capacitors of the integrated device can be further improved.

[0011] In a possible embodiment, the third metal layer and the first metal layer have opposite polarities.

[0012] In a possible embodiment, the gallium aluminum nitride layer is disposed on the aluminum nitride layer, and the two-dimensional electron gas is disposed below the aluminum nitride layer.

[0013] In the foregoing possible embodiment, the two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, and as a result, the electron concentration of the two-dimensional electron gas can be increased.

[0014] In a possible embodiment, the P-type conductive layer includes P-type gallium nitride or P-type gallium aluminum nitride.

[0015] In a possible embodiment, the first metal layer includes titanium nitride or tungsten.

[0016] In a possible embodiment, the materials of the first conductor structure and the second conductor structure include copper or aluminum.

[0017] In a second aspect of the present application, there is provided an integrated device including a gallium aluminum nitride layer, a first dielectric layer disposed on the gallium aluminum nitride layer, a second dielectric layer disposed on the first dielectric layer, a gate metal layer disposed between the first dielectric layer and the second dielectric layer, and a second metal layer disposed on the second dielectric layer. A two-dimensional electron gas is formed under the gallium aluminum nitride layer. The two-dimensional electron gas, the first dielectric layer, and the gate metal layer form a first capacitor. The second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor. The second metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacts the two-dimensional electron gas, and the first capacitor and the second capacitor are connected in parallel.

[0018] In the second aspect, the two-dimensional electron gas is disposed under the gallium aluminum nitride layer, and when the voltage between the second metal layer and the gate metal layer falls within a preset range, the two-dimensional electron gas is generated. The gate metal layer, the first dielectric layer, and the two-dimensional electron gas form a first capacitor, and the gate metal layer, the second dielectric layer, and the second metal layer form a second capacitor, that is, two capacitors are simultaneously formed on the integrated device. Also, the two-dimensional electron gas is connected to the second metal layer, and the first capacitor and the second capacitor are connected in parallel. Therefore, the integration density of the capacitors of the integrated device is improved.

[0019] In a possible embodiment, the second metal layer and the gate metal layer have opposite polarities.

[0020] In a possible embodiment, the first dielectric layer includes p-type gallium nitride or p-type aluminum gallium nitride, the gate metal layer penetrates the first dielectric layer, and the gate metal layer is formed on the p-type gallium nitride or p-type aluminum gallium nitride.

[0021] In a possible embodiment, the aluminum gallium nitride layer is disposed on the aluminum nitride layer, and the two-dimensional electron gas is disposed under the aluminum nitride layer.

[0022] In a possible embodiment, the material of the conductor structure includes copper or aluminum.

[0023] In a third aspect of the present application, there is provided a semiconductor device having an integrated device according to any one of the first aspects, or an integrated device provided by any method of the first aspect, and a semiconductor formed on the integrated device.

[0024] In a fourth aspect of the present application, there is provided a semiconductor device having an integrated device according to any one of the second aspects, or an integrated device provided by any method of the second aspect, and a semiconductor formed on the integrated device.

[0025] In a fifth aspect of the present application, there is provided a method for manufacturing an integrated device, including the steps of forming a first dielectric layer on a first metal layer, forming a gate metal layer on the first dielectric layer, forming a second dielectric layer on the gate metal layer, and forming a second metal layer on the second dielectric layer. The first metal layer, the first dielectric layer, and the gate metal layer form a first capacitor. The second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor. The first metal layer is connected to the second metal layer through a first conductor structure, and the first capacitor and the second capacitor are connected in parallel.

[0026] In a possible embodiment, the method further includes that the gate metal layer and the first metal layer have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities.

[0027] In a possible implementation, the method further includes forming a P-type conductive layer on the gallium aluminum nitride layer, and forming the first metal layer on the P-type conductive layer, wherein a two-dimensional electron gas is formed on the lower side of the gallium aluminum nitride layer, and the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor; forming a third metal layer on the second dielectric layer, wherein the third metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacts the two-dimensional electron gas; and connecting the third metal layer to the gate metal layer through a second conductor structure, wherein the first capacitor, the second capacitor, and the third capacitor are connected in parallel.

[0028] In a possible embodiment, the third metal layer and the first metal layer have opposite polarities.

[0029] In a possible embodiment, the gallium aluminum nitride layer is formed on the aluminum nitride layer, and the two-dimensional electron gas is disposed on the lower side of the aluminum nitride layer.

[0030] In a possible embodiment, the P-type conductive layer includes P-type gallium nitride or P-type gallium aluminum nitride.

[0031] In a possible embodiment, the first metal layer includes titanium nitride or tungsten.

[0032] In a possible embodiment, the materials of the first conductor structure and the second conductor structure include copper or aluminum.

[0033] In a sixth aspect of the present application, there is provided a method for manufacturing an integrated device, comprising the steps of forming a first dielectric layer on a gallium aluminum nitride layer, forming a gate metal layer on the first dielectric layer, forming a second dielectric layer on the gate metal layer, and forming a second metal layer on the second dielectric layer, wherein a two-dimensional electron gas is formed on the lower side of the gallium aluminum nitride layer. The two-dimensional electron gas, the first dielectric layer, and the gate metal layer form a first capacitor. The second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor. The second metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacts the two-dimensional electron gas, and the first capacitor and the second capacitor are connected in parallel.

[0034] In a possible embodiment, the second metal layer and the gate metal layer have opposite polarities.

[0035] In a possible embodiment, the first dielectric layer includes p-type gallium nitride or p-type gallium aluminum nitride, the gate metal layer passes through the first dielectric layer, and the gate metal layer is formed on the p-type gallium nitride or p-type gallium aluminum nitride.

[0036] In a possible embodiment, the gallium aluminum nitride layer is formed on an aluminum nitride layer, and the two-dimensional electron gas is disposed on the lower side of the aluminum nitride layer.

[0037] In a seventh aspect of the present application, there is provided a drive circuit, comprising a gate driver and an integrated device according to any one of the embodiments of the first and second aspects, or an integrated device obtained by using the method for manufacturing an integrated device according to any one of the embodiments of the fifth and sixth aspects, wherein the gate driver supplies current to the gate of the integrated device.

[0038] In the eighth aspect of the present application, an electronic device is provided. The electronic device has an integrated device described in any one of the embodiments of the first aspect and the second aspect, or an integrated device obtained by using the method described in any one of the embodiments of the fifth aspect and the sixth aspect.

Brief Description of the Drawings

[0039]

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Embodiments for Carrying out the Invention

[0040] Embodiments of the present application provide an integrated device, a semiconductor device, and a method for manufacturing an integrated device to improve the integration density of capacitors in the integrated device.

[0041] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is obvious that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments of the present application. As technology develops and new scenarios emerge, those skilled in the art can understand that the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0042] In the specification, claims, and accompanying drawings of the present application, terms such as "first", "second", etc. are intended to distinguish similar objects and do not necessarily indicate a specific order or arrangement. Data represented in such a way are interchangeable in appropriate situations, and it should be understood that the embodiments described in the present application may be implemented in an order other than the order shown or described in the present application. Furthermore, the terms "include" and "have", and any other variations, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a list of steps or units is not necessarily limited to the explicitly listed steps or units, and may include other steps or units not explicitly listed or specific to such a process, method, product, or device.

[0043] In the embodiments of the present application, "upward" and "downward" are described based on the process flow of the power device. When a "substrate" is used as the bottom surface, the direction away from the "substrate" along the vertical path is "upward", and the direction in which no other layers are arranged on the "substrate" along the vertical path is "downward".

[0044] For example, the related expression "A is arranged on B" merely indicates that A is spatially arranged above B, and the connection relationship between A and B is not limited. For example, when A is arranged on B, A may be in direct contact with B, or A may not be in direct contact with B. In this case, C may be included between A and B, and C may or may not completely separate A from B.

[0045] Hereinafter, some important terms in the embodiments of the present application will be described.

[0046] Gallium nitride (GaN): Gallium nitride (GaN) is a semiconductor having a wide bandgap and belongs to semiconductors with a wide bandgap. Gallium nitride is an excellent material for microwave power transistors and a new semiconductor material for developing microelectronic and optoelectronic devices. Gallium nitride has a wide direct bandgap, strong atomic bonds, high thermal conductivity, good chemical stability (hardly corroded by acids), and strong radiation resistance.

[0047] Two-dimensional electron gas (two-dimensional electron gas, 2DEG): The two-dimensional electron gas represents a phenomenon in which the electron gas can move freely in the two-dimensional direction but is restricted in the three-dimensional direction. The two-dimensional electron gas is arranged between the aluminum gallium nitride layer and the gallium nitride layer in a gallium nitride device platform. The two-dimensional electron gas can also be referred to as channel electrons. The two-dimensional electron gas is the basis for the operation of many field-effect devices (such as MOSFETs and HEMTs).

[0048] A metal-insulator-metal (MIM) capacitor (also referred to as an on-board capacitor) can provide the least interference to transistors and can offer good linearity and symmetry. Therefore, metal-insulator-metal (MIM) capacitors are widely used, especially in the fields of mixed signals and radio frequencies.

[0049] The integrated device in the embodiments of the present application may be applied to any scenario where the integration density of capacitors is increased. In the embodiments of the present application, a gallium nitride device is used as an example. FIG. 1 is an architecture diagram of power amplification according to an embodiment of the present application. The architecture diagram has an input module 11, a power amplifier 12, and an output module 13. The power amplifier 12 may amplify the output power of the input module 11 and then output the output power to the output module 13. The power grid voltage varies greatly in countries around the world. For example, the AC voltage in Country A is 220V and is relatively stable. The power grid voltage in Country B varies greatly in the range of 90VAC to 350VAC. To operate in a wide input voltage range, a large capacitance (low voltage) of the input filter capacitor and a high breakdown voltage rating (high voltage) of the input filter capacitor are required. To support a higher breakdown voltage, the capacitor manufacturer needs to increase the size of the capacitor, and as a result, the volume of the capacitor increases significantly. Gallium nitride (GaN) devices may be used to increase the switching frequency and reduce the size of the transformer. Specifically, the power amplifier 12 is a gallium nitride device, and the GaN device is a semiconductor device with a large bandwidth, a high amplifier gain, a high energy efficiency, and a small size. Due to the wide bandgap and high thermal conductivity of the GaN device, it can operate at temperatures exceeding 200°C and bear a higher energy density compared to other power amplifiers. Therefore, the GaN device has higher reliability. Due to the wide bandgap and excellent insulation of the GaN device, the electric field is affected, resulting in a reduction in the on-resistance of the device. This helps to improve the overall energy efficiency of the device. Due to the high-speed electron saturation and high carrier mobility of the GaN device, the device can operate at high speed.

[0050] Currently, in a single-die process platform, usually, the metal layers available in the process flow are used, and usually, the electrode plates of capacitors (such as the field plate layer and the gate metal layer) are formed. Therefore, the integration of capacitors is restricted by the thickness of the dielectric layer. However, the dielectric layer usually occupies most of the chip structure, and the integration of capacitors is restricted by the chip area.

[0051] To solve the above problems, embodiments of the present application provide an integrated device. The structure of the integrated device will be described below.

[0052] FIG. 2 is a schematic diagram of the structure of an integrated device according to an embodiment of the present application. The integrated device includes a semiconductor substrate 21, a gallium nitride (GaN) layer 22, an aluminum gallium nitride (AlGaN) layer 23, a P-type conductive layer 24, a first metal layer 25, a first dielectric layer 26, a gate metal layer 27, a second dielectric layer 28, and a second metal layer 29.

[0053] The semiconductor substrate 21 may be composed of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon on insulator (SOI) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a quartz (SiO2) substrate, or a diamond (C) substrate.

[0054] The gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably an undoped gallium nitride layer (when the gallium nitride layer 22 is a doped gallium nitride layer, magnesium Mg is used as a dopant).

[0055] The aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22, and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.

[0056] The P-type conductive layer 24 is disposed on the aluminum gallium nitride layer 23. The P-type conductive layer 24 is disposed in the active region of the aluminum gallium nitride layer 23. The P-type conductive layer 24 may be P-type gallium nitride or P-type aluminum gallium nitride. For example, the P-type conductive layer 24 is P-type gallium nitride. The P-type gallium nitride may be a beryllium-doped gallium nitride layer, a zinc-doped gallium nitride layer, or a magnesium-doped gallium nitride layer.

[0057] The first metal layer 25 is disposed on the P-type conductive layer 24. The first metal layer may preferably be composed of titanium nitride (TiN) or tungsten (W). Titanium nitride is a transition metal nitride, including a mixed system of ionic bond, metallic bond, and covalent bond, having high strength, high hardness, high temperature resistance, corrosion resistance to acids and alkalis, wear resistance, good electrical conductivity, and good thermal conductivity, and is an excellent material for ohmic contact metal.

[0058] The first dielectric layer 26 is disposed on the first metal layer 25. The first dielectric layer 26 covers the first metal layer 25, the P-type conductive layer 24, and the aluminum gallium nitride layer 23.

[0059] The gate metal layer 27 is disposed on the first dielectric layer 26. The second dielectric layer 28 is disposed on the gate metal layer 27. The second metal layer 29 is disposed on the second dielectric layer 28.

[0060] The first dielectric layer 26 separates the gate metal layer 27 from the first metal layer 25. The first metal layer 25 and the gate metal layer 27 have opposite polarities, and the gate metal layer 27, the first dielectric layer 26, and the first metal layer 25 form a first capacitor (MIM). The second dielectric layer 28 separates the gate metal layer 27 from the second metal layer 29. The second metal layer 29 and the gate metal layer 27 have opposite polarities, and the gate metal layer 27, the second dielectric layer 28, and the second metal layer 29 form a second capacitor (MIM). When the first metal layer 25 is connected to the second metal layer 29 via a first conductor structure (not shown), the first terminal of the first capacitor is interconnected with the first terminal of the second capacitor, and the second terminal of the first capacitor is interconnected with the second terminal of the second capacitor. That is, the first capacitor and the second capacitor are connected in parallel. In this case, the equivalent circuit diagram of the integrated device is shown in FIG. 3, and the dashed line in the circuit diagram indicates that the polarities are the same. Alternatively, the first capacitor and the second capacitor may be connected in parallel by another connection method, or the first capacitor and the second capacitor may be connected in series by another connection method. This is not limited to the present application. In this embodiment of the present application, the gate metal layer may be a positive electrode layer, and the second metal layer may be a negative electrode layer.

[0061] Specifically, with regard to the first conductor structure, FIG. 4 is referred to. The first metal layer 25 is connected to the metal M1 through the conductor D1 in the etching hole of the dielectric layer on the first metal layer 25. The second metal layer 29 is connected to the metal M1 through the conductor D2 in the etching hole of the dielectric layer on the second metal layer 29. The two pieces of the metal M1 belong to the same metal piece (not shown).

[0062] In this embodiment of the present application, the first dielectric layer separates the gate metal layer from the titanium nitride layer, the second dielectric layer separates the gate metal layer from the second metal layer, the first metal layer is connected to the second metal layer through the first conductor structure, and the first capacitor and the second capacitor are connected in parallel. This increases the capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, enables the integrated device to operate at high voltages, and at the same time enables it to have a high capacitance density.

[0063] To achieve a higher capacitance density for integrated devices that do not require a limited voltage range, the present application provides another schematic diagram of the structure of the integrated device shown in FIG. 5. The integrated device includes a semiconductor substrate 21, a gallium nitride (GaN) layer 22, an aluminum gallium nitride (AlGaN) layer 23, a P-type conductive layer 24, a first metal layer 25, a first dielectric layer 26, a gate metal layer 27, a second dielectric layer 28, and a second metal layer 29.

[0064] The semiconductor substrate 21 may be composed of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon on insulator (SOI) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a quartz (SiO2) substrate, or a diamond (C) substrate.

[0065] The gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably an undoped gallium nitride layer (when the gallium nitride layer 22 is a doped gallium nitride layer, magnesium Mg is used as a dopant).

[0066] The aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22, and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.

[0067] The P-type conductive layer 24 is disposed on the aluminum gallium nitride layer 23. The P-type conductive layer 24 is disposed in the active region of the aluminum gallium nitride layer 23. The P-type conductive layer 24 may be P-type gallium nitride or P-type aluminum gallium nitride. For example, the P-type conductive layer 24 is P-type gallium nitride. The P-type gallium nitride may be a beryllium-doped gallium nitride layer, a zinc-doped gallium nitride layer, or a magnesium-doped gallium nitride layer.

[0068] The first metal layer 25 is disposed on the P-type conductive layer 24. The first metal layer may preferably be composed of titanium nitride (TiN) or tungsten (W). Titanium nitride is a transition metal nitride, including a mixed system of ionic bonds, metallic bonds, and covalent bonds, having high strength, high hardness, high high-temperature resistance, corrosion resistance to acids and alkalis, wear resistance, good electrical conductivity, and good thermal conductivity, and is an excellent material for ohmic contact metals.

[0069] The first dielectric layer 26 is disposed on the first metal layer 25. The first dielectric layer 26 covers the first metal layer 25, the P-type conductive layer 24, and the aluminum gallium nitride layer 23.

[0070] The gate metal layer 27 is disposed on the first dielectric layer 26. The second dielectric layer 28 is disposed on the gate metal layer 27. The second metal layer 29 is disposed on the second dielectric layer 28.

[0071] The integrated device further includes a third metal layer 210. The third metal layer 210 further penetrates through the first dielectric layer 26, the second dielectric layer 28, and the aluminum gallium nitride layer 23 and is connected to the gallium nitride layer 22.

[0072] The first dielectric layer 26 separates the gate metal layer 27 from the first metal layer 25. The first metal layer 25 and the gate metal layer 27 have opposite polarities, and the gate metal layer 27, the first dielectric layer 26, and the first metal layer 25 form a first capacitor (MIM). The second dielectric layer 28 separates the gate metal layer 27 from the second metal layer 29. The second metal layer 29 and the gate metal layer 27 have opposite polarities, and the gate metal layer 27, the second dielectric layer 28, and the second metal layer 29 form a second capacitor (MIM). The first metal layer 25, the P-type conductive layer 24, and the two-dimensional electron gas 211 form a third capacitor (CJ). When the voltage between the gate metal layer 27 and the third metal layer 210 falls within a preset range, a two-dimensional electron gas 211 is generated, and the voltage range of use of the junction capacitor is from 5V to 7V. The third metal layer 210 is in contact with the two-dimensional electron gas, and the third metal layer 210 and the first metal layer 25 have opposite polarities.

[0073] If necessary, an aluminum nitride layer is further included between the gallium nitride layer and the aluminum gallium nitride layer. The two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, and as a result, the electron concentration of the two-dimensional electron gas can be increased. When the first metal layer 25 is connected to the second metal layer 29 via a first conductor structure (not shown), and the third metal layer 210 is connected to the gate metal layer 27 via a second conductor structure (not shown), the first conductor structure and the second conductor structure may be copper or aluminum. The first terminals of the first capacitor, the first capacitor of the second capacitor, and the first capacitor of the third capacitor are connected to each other, and the second terminals of the first capacitor, the second capacitor of the second capacitor, and the second capacitor of the third capacitor are connected to each other. That is, the first capacitor, the second capacitor, and the third capacitor are connected in parallel. For the equivalent circuit diagram of the integrated device, reference is made to FIG. 6.

[0074] Regarding the first conductor and the second conductor, the relevant description of the first conductor in FIG. 4 is referred to. The first metal layer 25 and the second metal layer 29 are separately connected to the metal M1, and the third metal layer 210 and the gate metal layer 27 are separately connected to the metal M2.

[0075] In this embodiment of the present application, the two-dimensional electron gas corresponding to the first metal layer, the P-type conductive layer, and the third metal layer forms a third capacitor. The third metal layer is connected to the gate metal layer via the second conductor structure, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel. This increases the capacitor capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, and further improves the capacitor integration density of the integrated device.

[0076] FIG. 7 is another schematic diagram of the structure of an integrated device according to an embodiment of the present application. The integrated device includes a semiconductor substrate 21, a gallium nitride (GaN) layer 22, an aluminum gallium nitride (AlGaN) layer 23, a first dielectric layer 26, a gate metal layer 27, a second dielectric layer 28, and a second metal layer 29.

[0077] The semiconductor substrate 21 may be composed of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon on insulator (SOI) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a quartz (SiO2) substrate, or a diamond (C) substrate.

[0078] The gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably an undoped gallium nitride layer (when the gallium nitride layer 22 is a doped gallium nitride layer, magnesium Mg is used as a dopant).

[0079] The aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22, and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.

[0080] The first dielectric layer 26 is disposed on the aluminum gallium nitride layer 23. The first dielectric layer 26 may have a fourth metal layer 261. The fourth metal layer 261 is P-type gallium nitride or P-type aluminum gallium nitride. The fourth metal layer 261 is disposed in the active region of the aluminum gallium nitride layer 23. For example, the fourth metal layer 261 is P-type gallium nitride. P-type gallium nitride may be a beryllium (Be)-doped gallium nitride layer, a zinc (Zn)-doped gallium nitride layer, or a magnesium (Mg)-doped gallium nitride layer. If necessary, the fourth metal layer may further have titanium nitride or tungsten, and the titanium nitride or tungsten completely separates the P-type gallium nitride from the gate metal layer 27.

[0081] The gate metal layer 27 is disposed on the first dielectric layer 26. The second dielectric layer 28 is disposed on the gate metal layer 27. The second metal layer 29 is disposed on the second dielectric layer 28. In this case, the fourth metal layer 261 is exposed by etching the first dielectric layer 26, and the gate metal layer 27 is formed in the etching holes formed by etching.

[0082] The first dielectric layer 26 may separate the gate metal layer 27 from the aluminum gallium nitride layer 23, and the two-dimensional electron gas 211 below the aluminum gallium nitride layer 23 is connected to the second metal layer 29. The first dielectric layer has a fourth metal layer 261, and the fourth metal layer 261 may be p-type gallium nitride or p-type aluminum gallium nitride. The second metal layer 29 and the gate metal layer 27 have opposite polarities. Therefore, the first capacitor including the gate metal layer 27, the first dielectric layer 26, and the two-dimensional electron gas 211 is a junction capacitor (CJ). The second dielectric layer 28 separates the gate metal layer 27 from the second metal layer 29. The second metal layer 29 and the gate metal layer 27 have opposite polarities, and the gate metal layer 27, the second dielectric layer 28, and the second metal layer 29 form a second capacitor (MIM). When the voltage between the gate metal layer 27 and the second metal layer 29 is within a preset range, a two-dimensional electron gas 211 is generated, and the voltage usage range of the junction capacitor is from 5V to 7V.

[0083] If necessary, further, an aluminum nitride layer is included between the gallium nitride layer and the aluminum gallium nitride layer, and the two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, so that the electron concentration of the two-dimensional electron gas can be increased. The second metal layer penetrates through the second dielectric layer 28, the first dielectric layer 26, and the aluminum gallium nitride layer 23 and contacts the two-dimensional electron gas 211. In this case, the first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the first capacitor is connected to the second terminal of the second capacitor. That is, the first capacitor and the second capacitor are connected in parallel. Regarding the equivalent circuit diagram of the integrated device, FIG. 8 is referred to. Alternatively, the first capacitor and the second capacitor may be connected in parallel by another connection method, or the first capacitor and the second capacitor may be connected in series by another connection method. This is not limited in this specification.

[0084] In this embodiment of the present application, the gate metal layer may be the positive electrode layer, and the second metal layer may be the negative electrode layer. In this embodiment of the present application, the gate metal layer, the first dielectric layer, and the two-dimensional electron gas form the first capacitor, and the gate metal layer, the second dielectric layer, and the second metal layer form the second capacitor. The two-dimensional electron gas is connected to the second metal layer, and as a result, the first capacitor and the second capacitor are connected in parallel. This increases the capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, and improves the integration density of the capacitors of the integrated device.

[0085] When the capacitor shown in FIG. 2 is a capacitor having a high capacitor density that can be used at high voltages, the embodiment of the present application further provides another schematic diagram of the structure of the integrated device shown in FIG. 9. The integrated device has a semiconductor substrate 21, a gallium nitride layer 22, an aluminum gallium nitride layer 23, a first dielectric layer 26, a gate metal layer 27, a second dielectric layer 28, and a second metal layer 29.

[0086] The semiconductor substrate 21 may be composed of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon-on-insulator (SOI) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a quartz (SiO2) substrate, or a diamond (C) substrate.

[0087] The gallium nitride layer 22 is disposed on the semiconductor substrate 21, and the gallium nitride layer 22 is preferably an undoped gallium nitride layer (when the gallium nitride layer 22 is a doped gallium nitride layer, magnesium Mg is used as a dopant).

[0088] The aluminum gallium nitride layer 23 is disposed on the gallium nitride layer 22, and the aluminum gallium nitride layer 23 is preferably an undoped aluminum gallium nitride layer.

[0089] The first dielectric layer 26 is disposed on the aluminum gallium nitride layer 23, the gate metal layer 27 is disposed on the first dielectric layer 26, the second dielectric layer 28 is disposed on the gate metal layer 27, and the second metal layer 29 is disposed on the second dielectric layer 28.

[0090] The first dielectric layer 26 may separate the gate metal layer 27 from the aluminum gallium nitride layer 23. In this embodiment of the present application, the first dielectric layer 26 may use a common dielectric material. The two-dimensional electron gas 211 below the aluminum gallium nitride layer 23 is connected to the second metal layer 29. The second metal layer 29 and the gate metal layer 27 have opposite polarities. The first capacitor including the gate metal layer 27, the first dielectric layer 26, and the two-dimensional electron gas 211 is an interboard capacitor (MIM). The second dielectric layer 28 separates the gate metal layer 27 from the second metal layer 29. The second metal layer 29 and the gate metal layer 27 have opposite polarities. The gate metal layer 27, the second dielectric layer 28, and the second metal layer 29 form a second capacitor (MIM). When the voltage between the gate metal layer 27 and the second metal layer 29 is within a preset range, a two-dimensional electron gas 211 is generated, and the voltage usage range of the junction capacitor is from 5V to 7V.

[0091] If necessary, an aluminum nitride layer is further included between the gallium nitride layer and the aluminum gallium nitride layer. The two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, and as a result, the electron concentration of the two-dimensional electron gas can be increased. The second metal layer penetrates through the second dielectric layer 28, the first dielectric layer 26, and the aluminum gallium nitride layer 23 and contacts the two-dimensional electron gas 211. In this case, the first terminal of the first capacitor is connected to the two terminals of the second capacitor. That is, the first capacitor and the second capacitor are connected in parallel. For the equivalent circuit diagram of the integrated device, reference is made to FIG. 10. Alternatively, the first capacitor and the second capacitor may be connected in parallel by another connection method, or the first capacitor and the second capacitor may be connected in series by another connection method. This is not limited to this specification. In this embodiment of the present application, the gate metal layer may be a positive electrode layer, and the second metal layer may be a negative electrode layer.

[0092] In this embodiment of the present application, the gate metal layer, the first dielectric layer, and the two-dimensional electron gas form the first capacitor, the gate metal layer, the second dielectric layer, and the second metal layer form the second capacitor, the two-dimensional electron gas has the same potential as the second metal layer, the first capacitor and the second capacitor are connected in parallel, and there is no junction capacitor. This makes it possible to increase the capacitance of the integrated device, improve the breakdown voltage characteristics of the integrated device, improve the integration density of the capacitors of the integrated device, and operate the integrated device at a high voltage.

[0093] In this embodiment of the present application, the amount of capacitors in the integrated device is not limited to two or three or more capacitors. For example, the integrated device may further include one fourth dielectric layer and one fourth metal layer. In this case, the integrated device can integrate another capacitor. Alternatively, the gallium nitride layer and the aluminum gallium nitride layer may be divided into two parts, and the two-dimensional electron gas is provided by different cathodes. That is, the integrated device may further include another junction capacitor or an interboard capacitor. Specifically, whether another junction or interboard capacitor is connected in parallel or in series within the integrated device is determined based on the specifications. Then, the two terminals of another junction or interboard capacitor may be connected to the integrated device through a conductor structure. This is not limited in this specification.

[0094] FIG. 11 is an embodiment of a method for manufacturing an integrated device according to an embodiment of the present application.

[0095] At 1101, a semiconductor substrate is provided.

[0096] In this embodiment of the present application, the semiconductor substrate may be composed of a silicon (Si) substrate, a sapphire (Al2O3) substrate, a silicon-on-insulator (SOI) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a quartz (SiO2) substrate, or a diamond (C) substrate.

[0097] At 1102, a gallium nitride layer is formed on the semiconductor substrate.

[0098] In this embodiment of the present application, a gallium nitride epitaxial wafer grows on the semiconductor substrate and functions as a buffer layer. The gallium nitride layer is preferably an undoped gallium nitride layer (when the gallium nitride layer is a doped gallium nitride layer, magnesium Mg is used as a dopant).

[0099] In 1103, an aluminum gallium nitride layer is formed on the gallium nitride layer.

[0100] In this embodiment of the present application, the thickness of the aluminum gallium nitride layer may be from 25 nm to 35 nm. In a specific formation method of the aluminum gallium nitride layer, it may be grown on the gallium nitride layer at a temperature of about 1100°C, and the aluminum gallium nitride layer is preferably an undoped aluminum gallium nitride layer.

[0101] In 1104, A P-type conductive layer is formed on the aluminum gallium nitride layer.

[0102] In this embodiment of the present application, the P-type conductive layer is formed in the active region of the aluminum gallium nitride layer. Using the P-type conductive layer, negative electrons are discharged in the surface state on the aluminum gallium nitride layer, and the dangling bonds on the aluminum gallium nitride layer are neutralized. The P-type conductive layer may be P-type gallium nitride or P-type aluminum gallium nitride.

[0103] The active region of the aluminum gallium nitride layer is a region formed between the gate electrode, source electrode, drain electrode, and / or electrodes.

[0104] In one embodiment, the regions other than the active region are coated with photoresist, the P-type conductive layer is formed in the active region, and then the photoresist outside the active region and the P-type conductive layer are removed. In another embodiment, the P-type conductive layer is formed on the aluminum gallium nitride layer, one layer of photoresist is formed in the active region, and then the P-type conductive layer outside the active region is removed, and finally the photoresist is removed. The specific forming method may be selected according to the actual specifications. Details are not described again here.

[0105] In 1105, a first metal layer is formed on the P-type conductive layer.

[0106] In this embodiment of the present application, the first metal layer covers only the P-type conductive layer, and the first metal layer is titanium nitride or tungsten, and good conductivity may be provided. Titanium nitride is a transition metal nitride, including a mixed system of ionic bond, metallic bond, and covalent bond, having high strength, high hardness, high high-temperature resistance, corrosion resistance to acids and alkalis, wear resistance, good conductivity, and good thermal conductivity, and is an excellent material for ohmic contact metal.

[0107] At 1106, a first dielectric layer is formed on the first metal layer.

[0108] In this embodiment of the present application, the first dielectric layer is formed on the first metal layer, the first dielectric layer covers both the P-type conductive layer and the aluminum gallium nitride layer, and the first dielectric layer is used to separate the layers from each other and maintain the insulation between the layers.

[0109] At 1107, a gate metal layer is formed on the first dielectric layer.

[0110] In this embodiment of the present application, one layer of photoresist is coated on the first dielectric layer, at the same position as the active region of the aluminum gallium nitride layer, the photoresist on the uncovered region is left, the gate metal layer is formed on the uncovered region, and then the photoresist outside the active region and the gate metal layer are removed. Alternatively, the gate metal layer may be formed in another embodiment in step 1101. Here, the details will not be described again.

[0111] The gate metal layer and the first metal layer have opposite polarities, and the gate metal layer and the first metal layer separated by the first dielectric layer form a first capacitor. In this case, the first capacitor is an inter-board capacitor.

[0112] At 1108, a second dielectric layer is formed on the gate metal layer.

[0113] In this embodiment of the present application, the second dielectric layer is formed on the gate metal layer, and the second dielectric layer covers the first dielectric layer.

[0114] At 1109, a second metal layer is formed on the second dielectric layer.

[0115] In this embodiment of the present application, the second metal layer is formed directly on the second dielectric layer, the second metal layer and the gate metal layer have opposite polarities, and the gate metal layer and the second metal layer separated by the second dielectric layer form a second capacitor. The second capacitor is an interboard capacitor.

[0116] At 1110, a first metal layer is connected to the second metal layer through a first conductor structure.

[0117] In this embodiment of the present application, the first metal layer is connected to the second metal layer through a first conductor structure, the first terminal of the first capacitor is interconnected with the first terminal of the second capacitor, and the second terminal of the first capacitor is interconnected with the second terminal of the second capacitor. That is, the first capacitor and the second capacitor are connected in parallel. Thereby, the integrated device can have a high voltage range and a high capacitor density.

[0118] If necessary, the material of the first conductor structure may be copper, aluminum, or the like.

[0119] In this embodiment of the present application, the first dielectric layer separates the gate metal layer from the titanium nitride layer, the second dielectric layer separates the gate metal layer from the second metal layer, the first metal layer is connected to the second metal layer through a first conductor structure, and the first capacitor and the second capacitor are connected in parallel. This increases the capacitor capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, enables the integrated device to operate at a high voltage, and at the same time enables it to have a high capacitor density.

[0120] FIG. 12 shows another embodiment of a method for manufacturing an integrated device according to an embodiment of the present application.

[0121] At 1201, a semiconductor substrate is provided.

[0122] At 1202, a gallium nitride layer is formed on the semiconductor substrate.

[0123] At 1203, an aluminum gallium nitride layer is formed on the gallium nitride layer.

[0124] At 1204, a P-type conductive layer is formed on the aluminum gallium nitride layer.

[0125] At 1205, a first metal layer is formed on the P-type conductive layer.

[0126] At 1206, a first dielectric layer is formed on the first metal layer.

[0127] At 1207, a gate metal layer is formed on the first dielectric layer.

[0128] At 1208, a second dielectric layer is formed on the gate metal layer.

[0129] At 1209, a second metal layer is formed on the second dielectric layer.

[0130] At 1210, the first metal layer is connected to the second metal layer through a first conductor structure.

[0131] In this embodiment of the present application, for steps 1201 to 1210, the related descriptions of steps 1101 to 1110 in the method shown in FIG. 11 are referred to. Here, the details will not be described again.

[0132] At 1211, a third metal layer is formed on the aluminum gallium nitride layer.

[0133] In this embodiment of the present application, the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the P-type conductive layer region may be etched until the gallium nitride layer is exposed and an etching hole is obtained. Next, a third metal layer may be formed in the etching hole. The third metal layer and the first metal layer have opposite polarities. When the voltage between the gate metal layer and the third metal layer falls within a preset range, a two-dimensional electron gas is generated under the aluminum gallium nitride layer. In this case, the third metal layer is combined with the two-dimensional electron gas. That is, the two-dimensional electron gas and the first metal layer have opposite polarities.

[0134] If necessary, further, an aluminum nitride layer may be provided between the aluminum gallium nitride layer and the gallium nitride layer on the gallium nitride device platform. In this case, the two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, and the electron concentration of the two-dimensional electron gas can be increased.

[0135] In 1212, the third metal layer is connected to the gate metal layer through the second conductor structure.

[0136] In this embodiment of the present application, the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor. Since the P-type conductive layer includes P-type gallium nitride or P-type aluminum gallium nitride, the third capacitor is a junction capacitor. The third metal layer may be connected to the gate metal layer through the second conductor structure. The first capacitor, the second capacitor, and the third capacitor are connected in parallel, and an integrated device with a higher capacitor density can be obtained. The materials of the first conductor structure and the second conductor structure may be copper or aluminum.

[0137] In this embodiment of the present application, the two-dimensional electron gas corresponding to the first metal layer, the P-type conductive layer, and the third metal layer forms a third capacitor, and the third metal layer is connected to the gate metal layer via the second conductor structure. As a result, the first capacitor, the second capacitor, and the third capacitor are connected in parallel. This increases the capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, and further improves the integration density of the capacitors of the integrated device.

[0138] FIG. 13 is another embodiment of a method for manufacturing an integrated device according to an embodiment of the present application.

[0139] At 1301, a semiconductor substrate is provided.

[0140] At 1302, a gallium nitride layer is formed on the semiconductor substrate.

[0141] At 1303, an aluminum gallium nitride layer is formed on the gallium nitride layer.

[0142] In this embodiment of the present application, for steps 1301 to 1303, the related descriptions of steps 1101 to 1103 in the method shown in FIG. 11 are referred to. Here, the details will not be described again.

[0143] At 1304, a first dielectric layer is formed on the aluminum gallium nitride layer.

[0144] In this embodiment of the present application, the first dielectric layer is formed on the aluminum gallium nitride layer, and the first dielectric layer may include P-type gallium nitride or P-type aluminum gallium nitride.

[0145] At 1305, the first dielectric layer is etched to expose P-type gallium nitride or P-type aluminum gallium nitride.

[0146] In this embodiment of the present application, the first dielectric layer is etched until P-type gallium nitride or P-type aluminum gallium nitride in the first dielectric layer is exposed. Specifically, when titanium nitride is further disposed on P-type gallium nitride or P-type aluminum gallium nitride, it is necessary to etch the first dielectric layer until the titanium nitride is exposed.

[0147] At 1306, a gate metal layer is formed on P-type gallium nitride or P-type aluminum gallium nitride.

[0148] In this embodiment of the present application, the gate metal layer is formed in the etching hole obtained by etching the first dielectric layer, and the gate metal layer is connected to P-type gallium nitride or P-type aluminum gallium nitride. Further, when titanium nitride is disposed on P-type gallium nitride or P-type aluminum gallium nitride, the gate metal layer is connected to the titanium nitride.

[0149] At 1307, a second dielectric layer is formed on the gate metal layer. In this embodiment of the present application, the second dielectric layer covers both the first dielectric layer and the gate metal layer.

[0150] At 1308, a second metal layer is formed on the second dielectric layer.

[0151] In this embodiment of the present application, the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the gate metal layer region may be etched to obtain an etching hole, and the gallium nitride layer is exposed at the bottom end of the etching hole. Next, a second metal layer is formed on the etching hole and the second dielectric layer, and the second metal layer and the gate metal layer have opposite polarities. In this case, the gate metal layer and the second metal layer separated by the second dielectric layer form a first capacitor, and the first capacitor is an inter-board capacitor. When the voltage between the gate metal layer and the second metal layer falls within a preset range, a two-dimensional electron gas is generated under the aluminum nitride layer, the two-dimensional electron gas is connected to the second metal layer, and the gate metal layer, the first dielectric layer, and the two-dimensional electron gas mutually form a third capacitor (junction capacitor). The second metal layer has the same potential as the two-dimensional electron gas. Therefore, the two terminals of the first capacitor and the second capacitor are connected to each other, that is, the first capacitor and the second capacitor are connected in parallel.

[0152] If necessary, further, an aluminum nitride layer may be provided between the aluminum gallium nitride layer and the gallium nitride layer on the gallium nitride device platform. In this case, the two-dimensional electron gas is disposed between the aluminum nitride layer and the gallium nitride layer, and as a result, the electron concentration of the two-dimensional electron gas can be increased.

[0153] In this embodiment of the present application, the gate metal layer may be a positive electrode layer, and the second metal layer may be a negative electrode layer. In this embodiment of the present application, the gate metal layer, the first dielectric layer, and the two-dimensional electron gas form a first capacitor, the gate metal layer, the second dielectric layer, and the second metal layer form a second capacitor, the two-dimensional electron gas is connected to the second metal layer, and as a result, the first capacitor and the second capacitor are connected in parallel. This increases the capacitance of the integrated device, improves the breakdown voltage characteristics of the integrated device, and improves the integration density of the capacitors of the integrated device.

[0154] FIG. 14 shows another embodiment of a method for manufacturing an integrated device according to an embodiment of the present application.

[0155] At 1401, a semiconductor substrate is provided.

[0156] At 1402, a gallium nitride layer is formed on the semiconductor substrate.

[0157] At 1403, an aluminum gallium nitride layer is formed on the gallium nitride layer.

[0158] In this embodiment of the present application, for steps 1401 to 1403, the related descriptions of steps 1101 to 1103 in the method shown in FIG. 11 are referred to. Here, the details will not be described again.

[0159] At 1404, a first dielectric layer is formed on the aluminum gallium nitride layer.

[0160] In this embodiment of the present application, the first dielectric layer covers the aluminum gallium nitride layer, the material of the first dielectric layer is a dielectric structure in an interboard capacitor, different layers are separated using the first dielectric layer, and the layers are insulated from each other.

[0161] At 1405, a gate metal layer is formed on the first dielectric layer.

[0162] In this embodiment of the present application, during implementation, the gate metal layer is formed directly on the first dielectric layer, the photoresist is coated on the gate metal layer portion on the active region of the aluminum gallium nitride layer, the gate metal layer not covered by the photoresist is removed, and then the photoresist is removed.

[0163] In another embodiment, the first dielectric layer is coated with a photoresist except for the portion above the active region of the aluminum gallium nitride layer. A gate metal layer is formed at the position of the first dielectric layer above the active region of the aluminum gallium nitride layer. Then, the gate metal layer and the photoresist outside the active region are removed.

[0164] At 1406, a second dielectric layer is formed on the gate metal layer.

[0165] In this embodiment of the present application, the second dielectric layer is formed directly on the gate metal layer, and the second dielectric layer covers both the gate metal layer and the first dielectric layer.

[0166] At 1407, a second metal layer is formed on the second dielectric layer.

[0167] In this embodiment of the present application, the first dielectric layer, the second dielectric layer, and the aluminum gallium nitride layer outside the gate metal layer region may be etched to obtain an etching hole, and the gallium nitride layer is exposed at the bottom end of the etching hole. Next, a second metal layer is formed on the etching hole and the second dielectric layer, and the second metal layer and the gate metal layer may have opposite polarities. In this case, the gate metal layer and the second metal layer separated by the second dielectric layer form a first capacitor, and the first capacitor is an interboard capacitor. When the voltage between the gate metal layer and the second metal layer falls within a preset range, a two-dimensional electron gas is generated under the aluminum gallium nitride layer, the second metal layer is connected to the two-dimensional electron gas phase, and the gate metal layer, the first dielectric layer, and the two-dimensional electron gas combine to form a third capacitor. When the first dielectric layer does not contain P-type gallium nitride or P-type aluminum gallium nitride, the third capacitor is an interboard capacitor.

[0168] The second metal layer has the same potential as the two-dimensional electron gas. Therefore, the two terminals of the first capacitor and the second capacitor are connected to each other, that is, the first capacitor and the second capacitor are connected in parallel.

[0169] If necessary, further, an aluminum gallium nitride layer may be provided between the aluminum gallium nitride layer and the gallium nitride layer on the gallium nitride device platform. In this case, the two-dimensional electron gas is disposed between the aluminum gallium nitride layer and the gallium nitride layer, and the electron concentration of the two-dimensional electron gas can be increased.

[0170] In this embodiment of the present application, the gate metal layer, the first dielectric layer, and the two-dimensional electron gas form the first capacitor, the gate metal layer, the second dielectric layer, and the second metal layer form the second capacitor, and the two-dimensional electron gas has the same potential as the second metal layer. Therefore, the first capacitor and the second capacitor are connected in parallel, and there is no junction capacitor. This increases the capacitance of the integrated device, improves the breakdown voltage performance of the integrated device, improves the integration density of the capacitors of the integrated device, and enables the integrated device to operate at a high voltage.

[0171] FIG. 15 is a possible schematic diagram of the structure of a drive circuit 150 according to an embodiment of the present application. The drive circuit 150 includes a gate driver 1501 and an integrated device 1502. The gate driver device 1501 may include a plurality of current sources, and one or more of the plurality of current sources may supply current to the gate metal layer in the integrated device 1502 and change the voltage of the gate metal layer. The integrated device 1502 may be any of the integrated devices in FIGS. 2, 5, 7, and 9.

[0172] FIG. 16 is a possible schematic diagram of the structure of an electronic device 160 according to an embodiment of the present application. The electronic device may be an adapter or a server. For example, the electronic device is an adapter. The adapter may include the drive circuit 150 shown in FIG. 15, that is, it may include the gate driver 1501 and the integrated device 1502. The integrated device 1502 may be any of the integrated devices in FIGS. 2, 5, 7, and 9.

[0173] Finally, it should be noted that the foregoing embodiments are merely intended to illustrate the technical solutions of the present invention and do not limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that it is possible to modify the technical solutions described in the foregoing embodiments or perform equivalent substitutions for some or all of the technical features without departing from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated device, comprising: a first metal layer; a first dielectric layer disposed on the first metal layer; a second dielectric layer disposed on the first dielectric layer; a gate metal layer disposed between the first dielectric layer and the second dielectric layer; a second metal layer disposed on the second dielectric layer; wherein the first metal layer, the first dielectric layer, and the gate metal layer form a first capacitor; the second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor; the first metal layer is connected to the second metal layer via a first conductor structure, and the first capacitor and the second capacitor are connected in parallel; the integrated device further comprises: a third metal layer; a P-type conductive layer disposed below the first metal layer; a gallium aluminum nitride layer disposed below the P-type conductive layer, wherein a two-dimensional electron gas is formed below the gallium aluminum nitride layer; wherein the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor; the third metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacts the two-dimensional electron gas; the third metal layer is connected to the gate metal layer via a second conductor structure, and the first capacitor, the second capacitor, and the third capacitor are connected in parallel.

2. The integrated device according to claim 1, wherein the gate metal layer and the first metal layer have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities.

3. The integrated device according to claim 1, wherein the third metal layer and the first metal layer have opposite polarities.

4. The integrated device according to claim 1, wherein the gallium aluminum nitride layer is disposed on a gallium nitride layer, and the two-dimensional electron gas is disposed between the gallium aluminum nitride layer and the gallium nitride layer.

5. The integrated device according to any one of claims 1 to 4, wherein the P-type conductive layer comprises P-type gallium nitride or P-type gallium aluminum nitride.

6. The integrated device according to any one of claims 1 to 5, wherein the first metal layer comprises titanium nitride or tungsten.

7. The integrated device according to any one of claims 1 to 6, wherein the materials of the first conductor structure and the second conductor structure include copper or aluminum.

8. An integrated device, comprising: a gallium aluminum nitride layer; a first dielectric layer disposed on the gallium aluminum nitride layer; a second dielectric layer disposed on the first dielectric layer; a gate metal layer disposed between the first dielectric layer and the second dielectric layer; a second metal layer disposed on the second dielectric layer; and having a two-dimensional electron gas is formed below the gallium aluminum nitride layer; the two-dimensional electron gas, the first dielectric layer, and the gate metal layer form a first capacitor; the second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor; the second metal layer penetrates through the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer, contacts the two-dimensional electron gas, and the first capacitor and the second capacitor are connected in parallel.

9. The integrated device according to claim 8, wherein the second metal layer and the gate metal layer have opposite polarities.

10. The first dielectric layer covers a layer including P-type gallium nitride or P-type gallium aluminum nitride, The gate metal layer penetrates through the first dielectric layer and is formed on the layer including P-type gallium nitride or P-type gallium aluminum nitride. The integrated device according to any one of claims 8 and 9.

11. The gallium aluminum nitride layer is disposed on a gallium nitride layer, and the two-dimensional electron gas is disposed between the gallium aluminum nitride layer and the gallium nitride layer. The integrated device according to any one of claims 8 and 9.

12. A semiconductor device having the integrated device according to any one of claims 1 to 11 and a semiconductor formed on the integrated device.

13. A method for manufacturing an integrated device, comprising: forming a first dielectric layer on a first metal layer; forming a gate metal layer on the first dielectric layer; forming a second dielectric layer on the gate metal layer; forming a second metal layer on the second dielectric layer; and having the first metal layer, the first dielectric layer, and the gate metal layer form a first capacitor; The second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor, the first metal layer is connected to the second metal layer via a first conductor structure, and the first capacitor and the second capacitor are connected in parallel, furthermore, forming a P-type conductive layer on the gallium aluminum nitride layer, forming the first metal layer on the P-type conductive layer, a two-dimensional electron gas is formed on the lower side of the gallium aluminum nitride layer, the first metal layer, the P-type conductive layer, and the two-dimensional electron gas form a third capacitor, forming a third metal layer on the second dielectric layer, the third metal layer penetrating the second dielectric layer, the first dielectric layer, and the gallium aluminum nitride layer and contacting the two-dimensional electron gas, connecting the third metal layer to the gate metal layer via a second conductor structure, the first capacitor, the second capacitor, and the third capacitor being connected in parallel, A method for manufacturing an integrated device having the above steps.

14. The method for manufacturing an integrated device according to claim 13, wherein the gate metal layer and the first metal layer have opposite polarities, and the second metal layer and the gate metal layer have opposite polarities.

15. The method for manufacturing an integrated device according to claim 13, wherein the third metal layer and the first metal layer have opposite polarities.

16. The method for manufacturing an integrated device according to claim 13, wherein the gallium aluminum nitride layer is formed on a gallium nitride layer, and the two-dimensional electron gas is disposed between the gallium aluminum nitride layer and the gallium nitride layer.

17. The method for manufacturing an integrated device according to any one of claims 14 to 16, wherein the P-type conductive layer includes P-type gallium nitride or P-type gallium aluminum nitride.

18. The method for manufacturing an integrated device according to any one of claims 13 to 16, wherein the first metal layer includes titanium nitride or tungsten.

19. The method for manufacturing an integrated device according to any one of claims 14 to 16, wherein the materials of the first conductor structure and the second conductor structure include copper or aluminum.

20. A method for manufacturing an integrated device, Forming a first dielectric layer on an aluminum gallium nitride layer; Forming a gate metal layer on the first dielectric layer; Forming a second dielectric layer on the gate metal layer; Forming a second metal layer on the second dielectric layer; having; a two-dimensional electron gas is formed on the lower side of the aluminum gallium nitride layer, and the two-dimensional electron gas, the first dielectric layer, and the gate metal layer form a first capacitor; the second metal layer, the second dielectric layer, and the gate metal layer form a second capacitor; the second metal layer penetrates through the second dielectric layer, the first dielectric layer, and the aluminum gallium nitride layer and is in contact with the two-dimensional electron gas, and the first capacitor and the second capacitor are connected in parallel, a method for manufacturing an integrated device.

21. The method for manufacturing an integrated device according to claim 20, wherein the second metal layer and the gate metal layer have opposite polarities.

22. The first dielectric layer covers a layer containing P-type gallium nitride or P-type aluminum gallium nitride, the gate metal layer penetrates through the first dielectric layer and is formed on the layer containing P-type gallium nitride or P-type aluminum gallium nitride, the method for manufacturing an integrated device according to claim 20.

23. The aluminum gallium nitride layer is formed on a gallium nitride layer, and the two-dimensional electron gas is disposed between the aluminum gallium nitride layer and the gallium nitride layer, the method for manufacturing an integrated device according to any one of claims 20 to 22.

24. A drive circuit, a gate driver, an integrated device according to any one of claims 1 to 11, or an integrated device obtained by using the method for manufacturing an integrated device according to any one of claims 13 to 23, having; the gate driver is configured to supply current to the integrated device, a drive circuit.

25. An electronic device, an integrated device according to any one of claims 1 to 11, or an integrated device obtained by using the method for manufacturing an integrated device according to any one of claims 13 to 23 having, an electronic device.

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