Random number generator

Abstract

To provide a random number generator that can generate high-quality random numbers with low power consumption and is highly resistant to a noise injection attack.SOLUTION: A random number generator according to one aspect of the present invention comprises: an inverter circuit that includes a feedback inverter unit as a source of randomness, and a digital conversion circuit that generates random numbers based on the randomness generated by the feedback inverter unit, the feedback inverter unit including one input and one output, and that is configured such that a potential of the output is an inverted amplification of a potential of the input; and a feedback circuit including one or more resistance feedback paths that feedback the output of the inverter circuit to the input. A conductance of at least one of the resistance feedback paths is smaller than a mutual conductance of the inverter circuit in an equilibrium state where the potentials of the input and the output of the inverter circuit are statically equal to each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a random number generator.

Background Art

[0002] With the development of IoT (Internet of Things), the security requirements for things are increasing. To meet this requirement, for example, a method of using random numbers for passwords and encryption keys has been put into practical use. However, in the so-called pseudo-random numbers generated based on an algorithm, if the seed is leaked, the random number value can be easily reproduced. Even if the seed is not leaked, there is also a possibility that the random number value can be reproduced by using the developed AI technology and quantum computers nowadays.

[0003] For this reason, a random number generator that utilizes the dynamic randomness based on physical phenomena such as thermal noise has been proposed. Random numbers that employ such physical phenomena are unpredictable and highly random, and are called true random numbers as opposed to the above-described pseudo-random numbers.

[0004] As random number generators that generate true random numbers, those that utilize the frequency fluctuation of a ring oscillator (see, for example, Japanese Patent Application Laid-Open No. 2010-117846) and those that utilize the metastable state of a latch circuit (see, for example, International Publication No. 2011 / 117929) are known.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] Conventional random number generators using ring oscillators can obtain relatively stable and high-quality random numbers, that is, random numbers in which 0 and 1 are generated with almost equal probabilities. However, the circuit scale is large, and the power consumption for obtaining a 1-bit random number tends to be large. In addition, when it is subjected to a so-called noise injection attack in which a disturbance wave having a frequency close to the oscillation frequency of the ring oscillator is superimposed, the oscillation frequency is locked to that frequency, and there is a vulnerability that the randomness decreases.

[0007] Conventional random number generators using latch circuits have a small basic circuit scale and low power consumption. However, due to the nature of the circuit variation characteristics, the generation probability of either 0 or 1 tends to be large, and it tends to be a biased random number. Although this bias can be eliminated by corrections such as feedback control or by preparing a large number of latch circuits and taking their exclusive OR, it offsets the original advantage of using latch circuits, which is low power consumption.

[0008] The present invention has been made based on the above circumstances, and an object thereof is to provide a random number generator that can generate high-quality random numbers with low power consumption and has high resistance to noise injection attacks.

Means for Solving the Problems

[0009] A random number generator according to an aspect of the present invention includes a feedback inverter unit that serves as a source of randomness, and a digital conversion circuit that generates a random number based on the randomness generated from the feedback inverter unit. The feedback inverter unit includes an inverter circuit having one input and one output, and configured such that the potential of the output is an inverted amplification of the potential of the input, and a feedback circuit having one or a plurality of resistive feedback paths that feedback the output of the inverter circuit to the input. The conductance of at least one of the resistive feedback paths is smaller than the mutual conductance of the inverter circuit in an equilibrium state where the potentials of the input and the output of the inverter circuit are statically equal.

[0010] When the random number generator makes the conductance of the resistive feedback path of the feedback inverter section acting as an amplifier smaller than the mutual conductance of the inverter circuit, it causes, for example, oscillation or damped oscillation using the voltage of thermal noise superimposed on the feedback inverter section as a seed, and a noise voltage with a large amplitude can be obtained. This noise voltage causes the states where the input is larger and smaller than the output to occur relatively randomly and without bias around the equilibrium state where the potentials of the input and output of the inverter circuit of the feedback inverter section are statically equal, so it becomes a high-quality randomness source. Also, in this random number generator, since the digital conversion circuit generates random numbers based on this noise voltage with a large amplitude, it is possible to generate high-quality random numbers with a small circuit scale, that is, low power consumption. Furthermore, in this random number generator, since a noise voltage with a large amplitude can be obtained with a relatively small number of cycles, it is difficult to be locked even when subjected to a noise injection attack, and it has high resistance to noise injection attacks.

[0011] The feedback circuit may preferably include a plurality of resistive feedback paths with different conductances and a control unit that selects one resistive feedback path from the plurality of resistive feedback paths. By providing a plurality of resistive feedback paths with different conductances in the feedback circuit and using the plurality of resistive feedback paths in this way, the autocorrelation when obtaining random numbers continuously can be reduced. Also, the resistance to noise injection attacks can be enhanced.

[0012] One of the resistive feedback paths may preferably have a plurality of resistive elements, and at least one of the plurality of resistive elements is commonly used with the resistive elements of the other resistive feedback paths. By providing resistive elements commonly used in a plurality of resistive feedback paths in this way, it becomes possible to reduce the area of the feedback circuit and further reduce the power consumption.

[0013] The above resistance feedback path in 1 has a plurality of resistive elements connected in series, and among the plurality of resistive elements, the conductances of two or more resistive elements may be smaller than the mutual conductance of the inverter circuit. When using resistive elements connected in series in this way, due to the effects of parasitic capacitance elements and the like between the series connections, the phase change of the oscillation wave becomes large, and it becomes easy to generate oscillation with the voltage of thermal noise as a seed. Since the seeds are random, oscillation waves with randomly varying phases can be generated each time oscillation occurs. Also, since the circuit area of the resistive elements can be kept relatively small and the amplitude of the oscillation wave is large, the scale of the digital conversion circuit can be reduced and the power consumption can be further reduced.

[0014] When including a pair of the above feedback inverter units and setting the pair of feedback inverter units as a first feedback inverter unit and a second feedback inverter unit, the digital conversion circuit may include a first selection circuit that selects the presence or absence of a connection via a feedback circuit between the output and input of the inverter circuits of the first feedback inverter unit and the second feedback inverter unit, and a second selection circuit that selects the presence or absence of a connection between the output of the inverter circuit of the first feedback inverter unit and the input of the inverter circuit of the second feedback inverter unit and between the output of the inverter circuit of the second feedback inverter unit and the input of the inverter circuit of the first feedback inverter unit. By configuring the random number generator as described above, it is possible to suppress the occurrence of bias in the random numbers generated due to variations in the element characteristics constituting the digital conversion circuit.

[0015] The inverter circuit includes MOS transistors, the resistive elements of the resistive feedback path are composed of MOS transistors, and it is preferable that the combined value of the gate width ratio to the gate length of the MOS transistors constituting the resistance of at least one of the resistive feedback paths is smaller than the combined value of the MOS transistors included in the inverter circuit. In this way, by using MOS transistors for the inverter circuit and the resistive elements of the resistive feedback path and setting the combined value of the gate width ratio to the gate length to the above relationship, it is possible to easily implement it in an integrated circuit while maintaining the quality of the generated random numbers. Also, in a circuit that is proportionally scaled down in response to the miniaturization of transistor manufacturing technology, the above relationship is maintained, so with a relatively simple design, it is possible to easily benefit from the miniaturization in manufacturing cost, power consumption, and speed.

[0016] Here, the "inverter circuit in which the potential of the output is an inverted amplification of the potential of the input" means an inverter circuit in which the differential coefficient of the output potential change with respect to the input potential change is 0 or less, and the differential coefficient at the input potential where the potentials of the input and output are statically equal is less than -1, that is, an inverter circuit in which the absolute value of the differential coefficient is greater than 1 and there is an amplification effect.

[0017] In this specification, the "one resistive feedback path" of the feedback circuit refers to the entire circuit network formed by circuit elements arranged between the output and the input of the inverter circuit when forming a feedback circuit that feeds back the output of the inverter circuit to the input, and through which the feedback current flowing from the output to the input flows. In particular, it is not necessary that all of the resistive circuit elements constituting the path are connected in series. Therefore, the "conductance of the resistive feedback path" refers to the combined conductance of the entire circuit network connected between the output and the input of the inverter circuit when the resistive feedback path is composed of a plurality of circuit elements. Also, even when some or all of the constituting circuit elements are common, if the form of the circuit network is different, it shall be classified as a different resistive feedback path.

[0018] The "composite value of the gate width ratio to the gate length of the MOS transistor" refers to, for all MOS transistors constituting the target inverter circuit or a single resistive feedback path, obtaining the ratio (W / L) of the gate width W to the gate length L of each individual MOS transistor. For MOS transistor portions connected in parallel, the sum of the above W / L (in the case where the target MOS transistors are synthesized, the synthesis ratio; the same applies hereinafter) is used as the synthesis ratio, and for MOS transistor portions connected in series, the reciprocal of the sum of the reciprocals of the above W / L is used as the synthesis ratio. It refers to one composite value obtained by repeatedly performing this synthesis for all MOS transistors of the circuit (or circuit network) targeted for synthesis.

Advantages of the Invention

[0019] The random number generator of the present invention can generate high-quality random numbers with low power consumption and has high resistance to noise injection attacks.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

DETAILED DESCRIPTION OF THE INVENTION

[0021] [First Embodiment] Hereinafter, a random number generator according to a first embodiment of the present invention will be described with reference to the drawings as appropriate.

[0022] The random number generator 1 shown in FIG. 1 includes a feedback inverter section 10 serving as a source of randomness, and a digital conversion circuit 20 that generates a random number based on the randomness generated from the feedback inverter section 10.

[0023] <Feedback Inverter Section> The feedback inverter section 10 has an inverter circuit 10a and a feedback circuit 10b.

[0024] (Inverter Circuit) The inverter circuit 10a has one input Vin and one output Vout, and is configured such that the potential of the output Vout is an inverting amplification of the potential of the input Vin (hereinafter, the input Vin and the output Vout may be simply referred to as "Vin" and "Vout", respectively).

[0025] The inverter circuit 10a includes MOS transistors. That is, the inverter circuit 10a includes a MOS transistor P that is a PMOS INV and a MOS transistor N that is an NMOS INV (hereinafter, for example, the MOS transistor P INV may be simply referred to as "P INV ". The same applies to other MOS transistors. P indicates a PMOS, and N indicates an NMOS). Specifically, as shown in FIG. 1, P INV and N INV are connected with their respective drains as connection points, and P INVThe source of [element] is connected to the power supply VDD (hereinafter, also simply referred to as "VDD"), and the source of N INV is grounded. Also, the source of P INV and N INV is connected to Vin at the gate, and Vout is connected to the drains (the above connection points) of P INV and N INV .

[0026] (Feedback circuit) The feedback circuit 10b feeds back the output Vout of the inverter circuit 10a to the input Vin, and includes two resistive feedback paths 11 with different conductances (a high-resistance feedback path 11a and a low-resistance feedback path 11b), and a control unit 12 that selects one resistive feedback path 11 from the two resistive feedback paths 11. The resistive elements of the resistive feedback path 11 are composed of MOS transistors.

[0027] As shown in FIG. 1, the high-resistance feedback path 11a is composed of a transmission gate TG1 (hereinafter, also simply referred to as "TG1") fixed in the ON state, which is a resistive element. Specifically, TG1 is composed of a PMOS transistor P TG1 and an NMOS transistor N TG1 , and their sources and drains are connected to each other. TG1 is arranged between Vin and Vout of the inverter circuit 10a (the above source is connected to Vin, and the above drain is connected to Vout), and the gate of P TG1 is grounded, and the gate of N TG1 is connected to VDD. That is, both P TG1 and N TG1 are fixed in the ON state.

[0028] On the one hand, the low-resistance feedback path 11b is composed of the above-mentioned TG1 and the transmission gate TG2. That is, the low-resistance feedback path 11b has two resistive elements (TG1 and TG2), and one of the plurality of resistive elements, TG1, is commonly used with the resistive element (TG1) of the high-resistance feedback path 11a, which is another resistive feedback path 11. By providing a resistive element that is commonly used in a plurality of resistive feedback paths 11 in this way, it becomes possible to reduce the area of the feedback circuit 10b, and the power consumption can be further reduced.

[0029] TG2 is arranged between Vin and Vout of the inverter circuit 10a, and the TG1 gate of P is connected to the external input terminal F of the control unit 12 described later, and the TG1 gate of N is connected to the inverted signal of the external input terminal F.

[0030] Here, since the high-resistance feedback path 11a is composed of only TG1 and the low-resistance feedback path 11b is composed of a circuit network formed by the parallel connection of TG1 and TG2, the resistance value of the high-resistance feedback path 11a is higher than that of the low-resistance feedback path 11b. In terms of conductance, which is the reciprocal of the resistance value, the conductance of the high-resistance feedback path 11a is smaller than that of the low-resistance feedback path 11b.

[0031] As shown in FIG. 1, the control unit 12 has an external input terminal F for determining the resistive feedback path 11 to be selected, and an inverter element INV1 whose input is connected to this external input terminal F and which outputs the inverted signal of the external input terminal F.

[0032] INV1 can be realized by, for example, a CMOS inverter. The output of INV1 is connected to the TG1 gate of N that constitutes TG2. Also, the external input terminal F is TG1 also connected to the TG1Since the logical value 0 (ground potential), which is the inverted signal, is transmitted to the gate of , TG2 is turned off, and the high-resistance feedback path 11a composed only of TG1 is selected. Conversely, when the external input terminal F is set to the logical value 0, TG2 is turned on, and the low-resistance feedback path 11b composed of TG1 and TG2 is selected.

[0033] (Operation of the feedback inverter section) Here, the operation of the feedback inverter section 10 will be described. FIG. 2 shows an equivalent circuit of the feedback inverter section 10 in a state where the resistive feedback path 11 of is selected. In FIG. 2, C1 and C2 (the capacitance values are represented by C1 and C2 respectively) are parasitic capacitances, or parasitic capacitances and capacitive elements added thereto. For example, C1 includes the drain capacitance of P INV as a parasitic capacitance, the drain capacitance of N INV as a parasitic capacitance, the gate capacitance of N3, etc., and C2 includes the gate capacitance of P INV as a parasitic capacitance, the gate capacitance of N INV as a parasitic capacitance, the gate capacitance of N2. G1 represents the mutual conductance of the inverter circuit 10a (hereinafter, also simply referred to as "the mutual conductance of the inverter circuit") in an equilibrium state where the potentials of the input Vin and the output Vout of the inverter circuit 10a are statically equal. With the potential of the output Vout in the above equilibrium state being Veq, using the input Vin and the output current Iout, the following formula 1 is satisfied. G2 is the equivalent conductance of the selected resistive feedback path of . Iout = -(Vin - Veq) × G1 ···1

[0034] Considering the transient response when the potential of the output Vout fluctuates from Veq due to thermal noise or the like in the circuit of FIG. 2, when the time constant C2 / G2 of the feedback circuit 10b is smaller than a certain critical value, as shown in FIG. 3, ΔVout = Vout - Veq shows a monotonic decay behavior of monotonically decaying to 0. On the other hand, when the above time constant C2 / G2 is made larger than the above critical value, as shown in FIG. 4, ΔVout shows a damped oscillation behavior of approaching 0 in amplitude while oscillating.

[0035] Here, the capacitance values of the parasitic capacitance elements shown in FIG. 2 generally satisfy C1≈C2. In this case, the above critical value becomes C1 / G1≈C2 / G1. That is, when the conductance G2 of the resistive feedback path 11 is larger than the mutual conductance G1 of the inverter circuit 10a, the time constant C2 / G2 becomes smaller than the above critical value and monotonically decays. On the other hand, when the conductance G2 of the resistive feedback path 11 becomes smaller than the mutual conductance G1 of the inverter circuit 10a, the time constant C2 / G2 becomes larger than the above critical value and decaying oscillation occurs.

[0036] Thermal noise is always generated and has a wide frequency component and random amplitude and phase. Under the conditions of decaying oscillation, components with frequencies close to the decaying waveform reinforce each other, and a large noise voltage can be obtained by the accumulation of a large number of past noise voltages as ΔVout. FIG. 5 shows the noise simulation results under the monotonic decay condition of G1<G2 (left side of the graph) and the decaying oscillation condition of G2<G1 (right side of the graph). During decaying oscillation, the amplitude of the voltage of Vout (upper side of the graph, voltage axis on the left side) is larger than that during monotonic decay, and a specific frequency component can be recognized, but it is not a periodic waveform like a sine wave, and both the amplitude and phase are random. At this time, the voltage of Vin (lower side of the graph, voltage axis on the right side) also has a random amplitude and phase centered on Veq (0.33V in FIG. 5) like Vout, and it is also different for each cycle.

[0037] In the random number generator 1, the conductance of the high-resistance feedback path 11a is configured to be smaller than the mutual conductance of the inverter circuit 10a, and the conductance of the low-resistance feedback path 11b is configured to be larger than the mutual conductance of the inverter circuit 10a. That is, in the random number generator 1, at least one resistive feedback path 11 satisfies the configuration that its conductance is smaller than the mutual conductance of the inverter circuit 10a. When the high-resistance feedback path 11a is selected, decaying oscillation occurs, and when the low-resistance feedback path 11b is selected, monotonic decay occurs.

[0038] The upper limit of the ratio of the conductance of the high-resistance feedback path 11a to the mutual conductance of the inverter circuit 10a is 1, more preferably 0.9, even more preferably 0.5, and particularly preferably 0.1. By setting the conductance ratio to be equal to or less than the upper limit, a large noise voltage can be easily obtained. Also, as described above, usually C1≒C2, but by setting the conductance ratio to be 0.9 or less, when the difference between C1 and C2 is 2 times or less, and by setting the conductance ratio to be 0.5 or less, when the difference between C1 and C2 is 5 times or less, decay oscillation can be generated, so that the random number generator 1 can operate stably. Note that "the difference between C1 and C2 is N times or less" means that either C1 / C2≦N or C2 / C1≦N holds.

[0039] On the other hand, the lower limit of the conductance ratio is not particularly limited and may be 0, which is the theoretical limit value, but 0.01 is preferable. If the conductance ratio is less than the lower limit, the time required for feedback and the time for amplitude increase associated therewith become long, the throughput (the number of random numbers obtained per unit time) becomes small, and the power consumption per random number bit may increase.

[0040] As described above, in the random number generator 1, the resistive element of the resistive feedback path 11 is composed of MOS transistors. Among the resistive feedback paths 11, it is preferable that the combined value of the gate width ratio to the gate length of the MOS transistors constituting the high-resistance feedback path 11a having a conductance smaller than the mutual conductance of the inverter circuit 10a is smaller than the combined value of the MOS transistors included in the inverter circuit 10a. Specifically, in the high-resistance feedback path 11a, since the two MOS transistors constituting TG1 are connected in parallel, the combined value X1 is represented by the following formula 2. On the other hand, in the inverter circuit 10a, since the two MOS transistors are connected in parallel with respect to VDD and ground, the combined value X2 is represented by the following formula 3, and it is preferable that X1<X2. Note that the subscripts in formulas 2 and 3 represent the corresponding MOS transistors in FIG. 1.

Number

[0041] In this way, by using MOS transistors for the inverter circuit 10a and the resistive elements of the resistive feedback path 11 and setting the composite value of the gate width ratio with respect to the gate length to the above relationship, it is possible to easily implement it in an integrated circuit while maintaining the quality of the generated random numbers. Also, in a circuit that is proportionally scaled down in response to the miniaturization of transistor manufacturing technology, the above relationship is maintained, so it is possible to easily benefit from miniaturization in terms of manufacturing cost, power consumption, and speed with a relatively simple design.

[0042] <Digital conversion circuit> The digital conversion circuit 20 takes both the input Vin and the output Vout of the inverter circuit 10a as inputs and outputs logic according to the potentials of the input Vin and the output Vout of the inverter circuit 10a.

[0043] The digital conversion circuit 20 shown in FIG. 1 is a so-called strong-arm latch and has a latch circuit 21. The latch circuit 21 includes a first CMOS inverter 21a and a second CMOS inverter 21b and is configured to be able to hold data with opposite polarities to each other. Specifically, the output Q of the first CMOS inverter 21a is connected to the input of the second CMOS inverter 21b, and the output QB of the second CMOS inverter 21b is connected to the input of the second CMOS inverter 21b. With this configuration, the latch circuit 21 is stable with the output Q and the output QB being inverted with respect to each other, and the data is held.

[0044] The digital conversion circuit 20 further includes four PMOS transistors P1, P2, P3, and P4, three NMOS transistors N1, N2, and N3, and an external input terminal SE. P1 is between the output Q of the first CMOS inverter 21a and the power supply VDD, P2 is between the source of the NMOS transistor Na constituting the first CMOS inverter 21a and the power supply VDD, P3 is between the output QB of the second CMOS inverter 21b and the power supply VDD, and P4 is between the source of the NMOS transistor Nb constituting the second CMOS inverter 21b and the power supply VDD, respectively. Also, the gates of P1 to P4 are connected to the external input terminal SE. The source of N1 is grounded, and the drain is connected to the sources of N2 and N3. The drain of N2 is connected to the source of Na of the first CMOS inverter 21a, and the drain of N3 is connected to the source of Nb of the second CMOS inverter 21b, respectively. Further, the gate of N1 is connected to the external input terminal SE, the gate of N2 is connected to the input Vin of the inverter circuit 10a of the feedback inverter section 10, and the gate of N3 is connected to the output Vout of the inverter circuit 10a of the feedback inverter section 10, respectively.

[0045] Regarding the operation of the digital conversion circuit 20, first, by setting SE to a logical value 0 (ground potential), N1 is turned off and P1 to P4 are turned on. At this time, regardless of the ON / OFF of the PMOS transistor Pa constituting the first CMOS inverter 21a and the PMOS transistor Pb constituting the second CMOS inverter 21b, all internal nodes of the latch circuit 21 are precharged to the power supply potential VDD.

[0046] Next, when the feedback circuit 10b is in the damped oscillation state, that is, when the high-resistance feedback path 11a is selected, if SE is set to the logical value 1 (power supply potential), N1 becomes ON and P1 to P4 become OFF, and the latching operation of the latch circuit 21 starts. Specifically, the potential of the pre-charged internal node decreases. Here, the rate of decrease in the potentials of the outputs Q and QB depends on the on-resistances of N2 and N3 respectively. For example, when Vin > Vout, since the on-resistance of N2 becomes smaller, the potential of Q decreases faster, and the latch circuit stabilizes at Q = 0 and QB = 1, and the data is latched. Conversely, when Vin < Vout, it stabilizes at Q = 1 and QB = 0, and the data is latched.

[0047] As described above, since both Vin and Vout of the inverter circuit 10a vary randomly around Veq, the states of Vin > Vout and Vin < Vout occur randomly and with equal probability. Therefore, when the variations of the transistors constituting the latch circuit 21 are sufficiently small, a true random number with equal probabilities of 0.5 for the latch circuit 21 to take 0 and 1 can be obtained.

[0048] On the other hand, when the variations of the transistors constituting the latch circuit 21 cannot be ignored, a bias that makes it easier for either 0 or 1 to occur may arise. Here, the variations of the transistors are on the order of several tens of mV in terms of potential. On the other hand, the thermal noise itself is typically on the order of several mV, and by itself, the variations of the transistors cannot be ignored. However, in this random number generator 1, by utilizing damped oscillation, the amplitude of the thermal noise is amplified and utilized, so the influence of the variations of the transistors is reduced, and the randomness can be improved.

[0049] Note that the response speed of the digital conversion circuit 20 (the time required from when SE changes from 0 to 1 until the latch circuit 21 acquires a random number value) is preferably shorter than the period of the damped oscillation. Thereby, stable and high-quality random numbers can be obtained.

[0050] <Usage method of the said random number generator> When the random number generator 1 can select a low-resistance feedback path 11b that causes monotonic attenuation in addition to the high-resistance feedback path 11a that causes damped oscillation. The advantages of using both and the method of using them will be described below.

[0051] When obtaining random numbers continuously with the random number generator 1, 0 and 1 will be repeatedly input to SE. When this repetition interval is short, the next random number may be obtained in a state where the influence of the past damped oscillation that contributed to the previous random number acquisition remains. In this case, autocorrelation may occur between the previous random number value and the current one, and the randomness may decrease. This autocorrelation can be avoided by making the period of obtaining random numbers sufficiently larger than the period of damped oscillation, but the throughput of random number generation also decreases.

[0052] When the low-resistance feedback path 11b is used in combination, it is possible to reduce autocorrelation while suppressing a decrease in the throughput of random number generation. Specifically, as shown in FIG. 6, the external input terminals F and SE are controlled. When F = 1 in FIG. 6, the high-resistance feedback path 11a is selected and damped oscillation occurs. On the other hand, when F = 0, the low-resistance feedback path 11b is selected and monotonic attenuation occurs. The acquisition of random numbers (SE = 0 → 1) is performed when F = 1, that is, when the high-resistance feedback path 11a is selected. However, before the next random number is acquired, the low-resistance feedback path 11b is selected (F = 0) to provide a period of monotonic attenuation. By providing a period of monotonic attenuation, the thermal noise that was damped oscillating immediately before converges to Veq quickly, so the influence on the acquisition of the next random number can be reduced.

[0053] In this way, by providing a plurality of resistive feedback paths 11 with different conductances in the feedback circuit 10b and using the plurality of resistive feedback paths 11, the autocorrelation when obtaining random numbers continuously can be reduced. In addition, the resistance to noise injection attacks can be enhanced. Furthermore, by providing a period of monotonic attenuation, the magnitude of the through-current that always flows through the inverter circuit 10a can be reduced, so the power consumption can also be reduced.

[0054] <Advantages> When the random number generator 1 reduces the conductance of the resistive feedback path 11 of the feedback inverter section 10 that acts as an amplifier below the mutual conductance of the inverter circuit 10a, it attenuates and oscillates using the voltage of the thermal noise superimposed on the feedback inverter section 10 as a seed, and a noise voltage with a large amplitude can be obtained. This noise voltage causes states where the input Vin is larger and smaller than the output Vout to occur relatively randomly and without bias around the equilibrium state where the potentials of the input and output of the inverter circuit 10a of the feedback inverter section 10 are statically equal, so it becomes a high-quality noise source. Also, in the random number generator 1, based on this noise voltage with a large amplitude, the digital conversion circuit 20 generates random numbers, so high-quality random numbers can be generated with a small circuit scale, that is, low power consumption. Furthermore, in the random number generator 1, the voltage of the thermal noise can be attenuated and oscillated with a relatively small number of cycles to obtain a noise voltage with a large amplitude, so it is difficult to be locked even when subjected to a noise injection attack, and it has high resistance to noise injection attacks.

[0055] [Second Embodiment] The random number generator 2 shown in FIG. 7 includes a feedback inverter section 14 that serves as a noise source, and a digital conversion circuit 20 that generates random numbers based on the noise generated from the feedback inverter section 14. Among these, since the digital conversion circuit 20 can be configured in the same manner as the digital conversion circuit 20 of the first embodiment, the same reference numerals are given and the detailed description is omitted.

[0056] The feedback inverter section 14 has an inverter circuit 10a having one input Vin and one output Vout and configured such that the potential of the output Vout is an inverting amplification of the potential of the input Vin, and a feedback circuit 14b. Among these, since the inverter circuit 10a is the same as the inverter circuit 10a of the first embodiment, the same reference numerals are given and the detailed description is omitted.

[0057] The feedback circuit 14b has three resistive feedback paths 15 that feedback the output Vout of the inverter circuit 10a to the input Vin, and a control section 16 that selects one resistive feedback path 15 from the three resistive feedback paths 15.

[0058] As shown in FIG. 7, the control unit 16 includes two external input terminals F1 and F2 for determining the resistive feedback path 15 to be selected, and two inverter elements INV2 and INV3 whose inputs are respectively connected to these external input terminals F1 and F2 and which output inverted signals of the external input terminals F1 and F2.

[0059] In the random number generator 2, as the resistive feedback path 15, in addition to the monotonic attenuation feedback path 15a that causes monotonic attenuation and the damped oscillation feedback path 15b that causes damped oscillation, it has an oscillation feedback path 15c. Among these, the conductances of the damped oscillation feedback path 15b and the oscillation feedback path 15c are smaller than the mutual conductance of the inverter circuit 10a. That is, the conductance of at least one resistive feedback path 15 is smaller than the mutual conductance of the inverter circuit 10a in the equilibrium state where the potentials of the input Vin and the output Vout of the inverter circuit 10a are statically equal. Hereinafter, the oscillation feedback path 15c will be described. Note that the resistive elements of the resistive feedback path 15 are composed of MOS transistors.

[0060] (Oscillation feedback path) As shown in FIG. 7, the oscillation feedback path 15c is constituted by a series connection of two transmission gates TG3 and TG4. The configuration of the transmission gate is as described in the first embodiment. TG3 and TG4 of the oscillation feedback path 15c are fixed in the ON state and are commonly used with the resistive elements of the other resistive feedback paths 15, namely the monotonic attenuation feedback path 15a and the damped oscillation feedback path 15b. The conductance of this oscillation feedback path 15c is smaller than the mutual conductance of the inverter circuit 10a. Also, the conductances of TG3 and TG4 that constitute the series connection are each smaller than the mutual conductance of the inverter circuit 10a. That is, in the random number generator 2, one resistive feedback path 15 (oscillation feedback path 15c) has a plurality of resistive elements connected in series, and among the plurality of resistive elements, the conductances of two or more resistive elements are configured to be smaller than the mutual conductance of the inverter circuit 10a.

[0061] In the random number generator 1 according to the first embodiment, the resistive element has one stage. In contrast, in the random number generator 2, the resistive element has two stages, and the RC circuit with the parasitic capacitance has a two-stage configuration. In such an RC circuit with two or more stages, by appropriately controlling the values of each RC, the phase change in feedback becomes larger compared to the case of a one-stage RC circuit configuration, and as shown in FIG. 8, oscillation can be achieved. At this time, the amplitude of Vout during oscillation can be amplified to about half of the power supply voltage.

[0062] It is preferable that the combined value of the gate width ratio to the gate length of the MOS transistor constituting the oscillation feedback path 15c having a smaller conductance than the mutual conductance of the inverter circuit 10a is smaller than the combined value of the MOS transistors included in the inverter circuit 10a. Specifically, for the combined value X3 of the oscillation feedback path 15c represented by the following formula 4 and the combined value X4 of the inverter circuit 10a represented by the following formula 5, it is preferable that X3 < X4. Also, the combined values X5 and X6 of the two resistive elements TG3 and TG4 constituting the oscillation feedback path 15c are represented by the following formula 6 and the following formula 7, and it is more preferable that X5 < X4 and X6 < X4. Note that the subscripts in formulas 4 to 7 represent the corresponding MOS transistors in FIG. 7. [Number]

[0063] The logical values of the external input terminals F1 and F2 when the oscillation feedback path 15c is selected are both 1.

[0064] (Attenuated oscillation feedback path) The attenuation oscillation feedback path 15b includes a transmission gate TG5 in addition to the transmission gates TG3 and TG4 that constitute the oscillation feedback path 15c. TG5 is connected in parallel to TG4, which is located on the downstream side when viewed from the output Vout of the inverter circuit 10a, among the two serially connected transmission gates TG3 and TG4. Also, the gate of TG5 is controlled by the external input terminal F2. TG5 turns on when the external input terminal F2 is at a logical value of 0. That is, the logical values of the external input terminals F1 and F2 when the attenuation oscillation feedback path 15b is selected are F1 = 1 and F2 = 0.

[0065] Since TG5 is connected in parallel to TG4, the conductance of the entire circuit network of the attenuation oscillation feedback path 15b becomes larger than the conductance of the oscillation feedback path 15c. As a result, when the attenuation oscillation feedback path 15b is selected, it is configured not to satisfy the oscillation conditions. On the other hand, the conductance of the attenuation oscillation feedback path 15b with TG3 as the main conductance component is configured to be smaller than the mutual conductance of the inverter circuit 10a. Therefore, when the attenuation oscillation feedback path 15b is selected, attenuation oscillation occurs. At this time, the combined value of the gate width ratio to the gate length of the MOS transistors constituting the attenuation oscillation feedback path 15b is smaller than X4 represented by the above formula 5 and larger than X3 represented by the above formula 4.

[0066] (Monotonic attenuation feedback path) The monotonic attenuation feedback path 15a includes at least a transmission TG6 in addition to the transmission gates TG3 and TG4 that constitute the attenuation oscillation feedback path 15b. TG6 is connected in parallel to the serially connected TG3 and TG4. Also, the gate of TG6 is controlled by the external input terminal F1. Note that TG6 turns on when the external input terminal F1 is at a logical value of 0. On the other hand, as long as the conductance of the entire circuit network is larger than the mutual conductance of the inverter circuit 10a, TG5 may be in the ON state or the OFF state. That is, either a logical value of 0 or 1 is selected for F2.

[0067] Since TG6 is connected in parallel to the serially connected TG3 and TG4, the conductance of the entire circuit network of the monotonic attenuation feedback path 15a becomes even larger than the conductance of the attenuation oscillation feedback path 15b. As a result, when the monotonic attenuation feedback path 15a is selected, its conductance is configured to be larger than the mutual conductance of the inverter circuit 10a, and the thermal noise is monotonically attenuated.

[0068] <Method of using the random number generator> The random number generator 2 can select one resistive feedback path 15 from the three resistive feedback paths 15 of the monotonic attenuation feedback path 15a, the attenuation oscillation feedback path 15b, and the oscillation feedback path 15c. The advantages of using the three and its usage method will be described below.

[0069] Since the random number generator 2 has an oscillation feedback path 15c that generates oscillation, the initial minute amplitude of the thermal noise can be taken out as a large amplitude. Therefore, the bias of the random number due to the variation of the transistors in the digital conversion circuit 20 can be further suppressed. However, when directly switching from the monotonic attenuation feedback path 15a to the oscillation feedback path 15c to suppress the autocorrelation as in the random number generator 1 of the first embodiment, in the oscillation feedback path 15c, a single-shot noise with a high degree of identity generated at the time of switching grows as a seed, so that the waveforms are the same every time and the phases tend to be aligned. For this reason, the generated random number is likely to be biased to 0 or 1, and there is a possibility that a high-quality random number cannot be obtained.

[0070] In the random number generator 2, this problem can be solved by using the damped oscillation feedback path 15b. That is, in the random number generator 2, first, the monotonic damping feedback path 15a is selected to perform monotonic damping. This selection serves to quickly return Vin and Vout of the inverter circuit 10a, which had a large amplitude in the previous cycle, to Veq. Next, the damped oscillation feedback path 15b is selected to generate damped oscillation. Thereby, the amplitudes of Vin and Vout can be increased. When the amplitude increases due to damped oscillation, the oscillation feedback path is switched to 15c. Then, the amplitude further increases and oscillation occurs. Finally, with the external input terminal SE having a logical value of 1, a random number value is obtained according to the magnitude relationship between Vin and Vout at that moment. At this time, the seed that is growing into oscillation is the noise generated by damped oscillation, so the phase changes randomly each time. Also, since the amplitude grows significantly due to oscillation, compared to the case of using the damped oscillation feedback path 15b, the influence of the variation of the MOS transistors in the digital conversion circuit 20 is reduced, so it is possible to more easily obtain random numbers in which 0 and 1 occur with almost equal probabilities. After obtaining the random number value, by selecting the monotonic damping feedback path 15a again and repeating the above procedure, high-quality random numbers can be continuously obtained.

[0071] Note that in the random number generator 2, the case of switching and using the three resistive feedback paths 15 has been described. However, for example, by controlling the waveform of the signal input to the external input terminal F1 so that the transition from 0V to VDD or from VDD to 0V changes slowly over time, it is also possible to shift from monotonic damping to damped oscillation and then to oscillation. In the case of performing such control, the external input terminals F2, INV3, and TG5 can be omitted. Also, on the premise that only TG6 is in the ON state in addition to TG3 and TG4, monotonic damping will occur.

[0072] Alternatively, in a configuration where the external input terminals F2, INV3, and TG5 are omitted, TG6 may be provided so that damped oscillation occurs when the logical value of F1 is 1. Even if the random number generator 2 makes a transition from damped oscillation (logical value 0 of F1) to oscillation (logical value 1 of F1) without using monotonic damping, it exhibits the same effect.

[0073] <Advantages>

[0074]

[0075] [Third Embodiment]

[0076] <Feedback Inverter Section> The first feedback inverter section 17 includes a first inverter circuit 17a having one input Vin1 and one output Vout1, configured such that the potential of the output Vout1 is an inverting amplification of the potential of the input Vin, and a first feedback circuit 17b having two resistive feedback paths for feeding back the output Vout1 of the first inverter circuit 17a to the input Vin1. Also, in the first feedback inverter section 17, the conductance of at least one of the resistive feedback paths is smaller than the mutual conductance of the first inverter circuit 17a in an equilibrium state where the potentials of the input Vin and the output Vout of the first inverter circuit 17a are statically equal.

[0077] The second feedback inverter section 18 includes a second inverter circuit 18a having one input Vin2 and one output Vout2, configured such that the potential of the output Vout2 is an inverting amplification of the potential of the input Vin2, and a second feedback circuit 18b having two resistive feedback paths for feeding back the output Vout2 of the second inverter circuit 18a to the input Vin2. Also, in the second feedback inverter section 18, the conductance of at least one of the resistive feedback paths is smaller than the mutual conductance of the second inverter circuit 18a in an equilibrium state where the potentials of the input Vin2 and the output Vout2 of the second inverter circuit 18a are statically equal.

[0078] The first inverter circuit 17a and the second inverter circuit 18a can be configured in the same manner as the inverter circuit 10a of the first embodiment, and thus detailed description thereof is omitted. Note that the first inverter circuit 17a and the second inverter circuit 18a preferably have the same configuration.

[0079] The first feedback circuit 17b and the second feedback circuit 18b can adopt, for example, the feedback circuit 10b of the first embodiment, the feedback circuit 14b of the second embodiment, or other configurations. The first feedback circuit 17b and the second feedback circuit 18b are preferably of the same configuration. Here, a case where both the first feedback circuit 17b and the second feedback circuit 18b are configured in the same manner as the feedback circuit 10b of the first embodiment will be taken as an example for description, but the configurations of the first feedback circuit 17b and the second feedback circuit 18b are not limited to the configuration of the feedback circuit 10b of the first embodiment.

[0080] <Digital conversion circuit> The digital conversion circuit 30 includes a first selection circuit 31 that selects whether there is a connection via a feedback circuit between the output and the input of the inverter circuits of the first feedback inverter section 17 and the second feedback inverter section 18, and between the output Vout1 of the inverter circuit of the first feedback inverter section 17 and the input Vin2 of the inverter circuit of the second feedback inverter section 18, and between the output Vout2 of the inverter circuit of the second feedback inverter section 18 and the input Vin1 of the inverter circuit of the first feedback inverter section 17. And a second selection circuit 32 for selecting the presence or absence of the connection.

[0081] Specifically, as shown in FIG. 9, the first selection circuit 31 includes two transmission gates TG11, TG12, an inverter element INV4, and an external input terminal SE1. TG11 is disposed between the output Vout1 of the first inverter circuit 17a of the first feedback inverter section 17 and the first feedback circuit 17b, and TG12 is disposed between the output Vout2 of the second inverter circuit 18a of the second feedback inverter section 18 and the second feedback circuit 18b. The gates of the PMOS transistors included in TG11 and TG12 are connected to the external input terminal SE1, and the gates of the NMOS transistors included in TG11 and TG12 are connected to the external input terminal SE1 and further connected to INV4 that generates an inverted signal thereof.

[0082] With this configuration, in the first selection circuit 31, when SE1 is set to logical value 0, TG11 and TG12 are in the ON state, and the output and input of the inverter circuits of the first feedback inverter section 17 and the second feedback inverter section 18 are connected via a feedback circuit, and a feedback inverter is configured in each of the first feedback inverter section 17 and the second feedback inverter section 18. On the other hand, when SE1 is set to logical value 1, TG11 and TG12 are in the OFF state, and the connection between the output and input of the inverter circuits of the first feedback inverter section 17 and the second feedback inverter section 18 is disconnected.

[0083] As shown in FIG. 9, the second selection circuit 32 includes two transmission gates TG21, TG22, an inverter element INV5, and an external input terminal SE2. TG21 is disposed between the output Vout1 of the inverter circuit of the first feedback inverter section 17 and the input Vin2 of the inverter circuit of the second feedback inverter section 18, and TG22 is disposed between the output Vout2 of the inverter circuit of the second feedback inverter section 18 and the input Vin1 of the inverter circuit of the first feedback inverter section 17. The gates of the PMOS transistors included in TG21 and TG22 are connected to the external input terminal SE2, and the gates of the NMOS transistors included in TG21 and TG22 are connected to INV5 which is connected to the external input terminal SE2 to generate an inverted signal thereof.

[0084] With this configuration, in the second selection circuit 32, when SE2 is set to logical value 0, TG21 and TG22 are in the ON state, and the connection is made between the output Vout1 of the inverter circuit of the first feedback inverter section 17 and the input Vin2 of the inverter circuit of the second feedback inverter section 18 and between the output Vout2 of the inverter circuit of the second feedback inverter section 18 and the input Vin1 of the inverter circuit of the first feedback inverter section 17, forming a latch circuit. On the other hand, when SE2 is set to logical value 1, TG21 and TG22 are in the OFF state, and the above-mentioned connection is disconnected.

[0085] <Method of using the random number generator> In the random number generator 3, initially, the logical values are set as SE1 = 0 and SE2 = 1, and feedback inverter circuits are configured in the first feedback inverter section 17 and the second feedback inverter section 18. Here, by setting the logical values of the external input terminals F of both the first feedback inverter section 17 and the second feedback inverter section 18 from 0 to 1, the first feedback inverter section 17 and the second feedback inverter section 18 perform damped oscillation.

[0086] When SE1 = 1 while the first feedback inverter section 17 and the second feedback inverter section 18 are in a state of damped oscillation, the feedback is cut off, and the voltages of the input Vin1 and Vin2 with the noise voltage superimposed at that moment are held in their respective C2s. This noise voltage is amplified by the first inverter circuit 17a and the second inverter circuit 18a respectively.

[0087] Next, when SE2 = 0, a latch circuit is configured by the first inverter circuit 17a and the second inverter circuit 18a. At this time, the value held by the latch circuit depends on the noise voltage held in the C2s of the first inverter circuit 17a and the second inverter circuit 18a, so it becomes a random value each time.

[0088] <Advantages> As described in the first embodiment, when the variations in the transistors constituting the latch circuit cannot be ignored, a bias may occur where either 0 or 1 is likely to occur in the obtained random number. In the random number generator 3, since the inverter circuit constituting the latch circuit also constitutes the feedback inverter circuit, the influence of this variation can be offset. Therefore, by configuring the random number generator 3 as described above, it is possible to suppress the occurrence of a bias in the random number generated due to variations in the element characteristics of the digital conversion circuit 30.

[0089] [Other Embodiments] The above embodiments do not limit the configuration of the present invention. Therefore, based on the description in this specification and common technical knowledge, it is possible to omit, replace, or add the constituent elements of each part of the above embodiments, and all of them should be interpreted as belonging to the scope of the present invention.

[0090] In the above embodiment, the case where the inverter circuit includes MOS transistors and the resistive elements of the resistive feedback path are composed of MOS transistors has been described. However, part or all of the inverter circuit and the resistive elements of the resistive feedback path may be composed of elements other than MOS transistors. For example, the resistive elements of the resistive feedback path can also be composed of well resistors, polysilicon resistors, chip resistors, etc.

[0091] In the above embodiment, the case where the feedback circuit has a plurality of resistive feedback paths has been described. However, a random number generator having one resistive feedback path is also within the scope of the present invention. A random number generator having one resistive feedback path also exhibits the same effect. In this case, the conductance of the above one resistive feedback path is smaller than the mutual conductance of the inverter circuit. Also, in this configuration, the control unit of the feedback circuit can be omitted.

[0092] In the above embodiment, the case where the digital conversion circuit inputs both the input and output of the inverter circuit has been described. However, it is also possible to input either one of the input and output of the inverter circuit. Also, the digital conversion circuit is not limited to the configuration of the above embodiment, and any circuit that can extract the logical value at an arbitrary timing from the feedback inverter section that is the source of the randomness is acceptable.

[0093] In the above third embodiment, a method of selecting the presence or absence of connection between the output of the inverter circuit of each feedback inverter section and the feedback circuit by a transmission gate as the first selection circuit has been described. However, by controlling all the resistive feedback paths in the feedback circuit to be non-connected, the presence or absence of connection via the feedback circuit between the output and input of the inverter circuit may be selected. For example, in the case of using the feedback circuit 14b shown in FIG. 7, if TG3 and TG6 are turned off, all the resistive feedback paths in the feedback circuit can be made non-connected. In this case, the transmission gates (TG11, TG12 in FIG. 9) of the first selection circuit can be omitted.

[0094] In the above embodiment, the case where an oscillating or damped oscillation occurs in a resistive feedback path having a smaller conductance than the mutual conductance of the inverter circuit has been described. However, it is not essential for an oscillating or damped oscillation to occur in a resistive feedback path having a smaller conductance than the mutual conductance of the inverter circuit. Even if damped oscillation does not occur, by making the conductance of the resistive feedback path smaller than the mutual conductance of the inverter circuit, the amplitude of the noise voltage can be increased, and thus the same effect as that of the above embodiment can be obtained.

Industrial Applicability

[0095] As described above, the random number generator of the present invention can generate high-quality random numbers with low power consumption and has high resistance to noise injection attacks.

Explanation of Signs

[0096] 1, 2, 3 Random number generator 10, 14 Feedback inverter section 10a Inverter circuit 10b, 14b Feedback circuit 11 Resistive feedback path 11a High-resistance feedback path 11b Low-resistance feedback path 12, 16 Control section 15 Resistive feedback path 15a Monotonically decaying feedback path 15b Damped oscillation feedback path 15c Oscillation feedback path 17 First feedback inverter section 17a First inverter circuit 17b First feedback circuit 18 Second feedback inverter section 18a Second inverter circuit 18b Second feedback circuit 20 Digital conversion circuit 21 Latch circuit 21a First CMOS inverter 21b Second CMOS inverter 30 Digital conversion circuit 31 First selection circuit 32nd selection circuit Inputs: Vin, Vin1, Vin2 Outputs: Vout, Vout1, Vout2 Power supply: VDD External input terminals: F, F1, F2, SE, SE1, SE2 P INV , N INV MOS transistors Transmission gates: TG1, TG2, TG3, TG4, TG5, TG6 Transmission gates: TG11, TG12, TG21, TG22 P TG1 , P TG2 , P TG3 , P TG4 , P TG5 , P TG6 MOS transistors N TG1 , N TG2 , N TG3 , N TG4 , N TG5 , N TG6 MOS transistors Inverter elements: INV1, INV2, INV3, INV4, INV5 Capacitance elements: C1, C2, C3 Equivalent resistances: G1, G2 MOS transistors: Pa, Pb, Na, Nb Output of the first CMOS inverter: Q Output of the second CMOS inverter: QB MOS transistors: P1, P2, P3, P4 MOS transistors: N1, N2, N3

Claims

1. A feedback inverter section that is a source of noise, and a digital conversion circuit that generates a random number based on the noise generated from the feedback inverter section are provided, wherein the feedback inverter section has one input and one output, and is configured such that the potential of the output is an inverting amplification of the potential of the input, an inverter circuit, and a feedback circuit having one or more resistive feedback paths that feedback the output of the inverter circuit to the input are provided, the conductance of at least one of the resistive feedback paths is smaller than the mutual conductance of the inverter circuit in an equilibrium state where the potentials of the input and the output of the inverter circuit are statically equal, and a random number generator that obtains a random number by selecting a resistive feedback path having a conductance smaller than the mutual conductance of the inverter circuit.

2. The feedback circuit of the random number generator according to claim 1, wherein the feedback circuit has a plurality of resistive feedback paths having different conductances, and a control section that selects one resistive feedback path from the plurality of resistive feedback paths.

3. The random number generator according to claim 2, wherein one of the resistive feedback paths has a plurality of resistive elements, and at least one of the plurality of resistive elements is commonly used with a resistive element of another one of the resistive feedback paths.

4. The random number generator according to claim 1, claim 2, or claim 3, wherein one of the resistive feedback paths has a plurality of resistive elements connected in series, and the conductances of two or more of the plurality of resistive elements are smaller than the mutual conductance of the inverter circuit.

5. The random number generator according to any one of claims 1 to 4, further comprising a pair of the feedback inverter sections, wherein when the pair of feedback inverter sections are a first feedback inverter section and a second feedback inverter section, the digital conversion circuit has a first selection circuit that selects the presence or absence of a connection via a feedback circuit between the output and the input of the inverter circuits of the first feedback inverter section and the second feedback inverter section, and a second selection circuit that selects the presence or absence of a connection between the output of the inverter circuit of the first feedback inverter section and the input of the inverter circuit of the second feedback inverter section and between the output of the inverter circuit of the second feedback inverter section and the input of the inverter circuit of the first feedback inverter section.

6. The inverter circuit includes MOS transistors, The resistive element of the resistive feedback path is composed of MOS transistors, The random number generator according to any one of claims 1 to 5, wherein a composite value of a gate width ratio with respect to a gate length of a MOS transistor constituting a resistance of at least one of the resistive feedback paths is smaller than the composite value of the MOS transistors included in the inverter circuit.

Images