Module and Method for Manufacturing the Same

Abstract

The present invention provides a module in which a plurality of different types of chips are inexpensively integrated, and a method for manufacturing said module. A module 1 configured by stacking a plurality of dies, the module 1 comprising: a package substrate 10; a main die 11 positioned such that a circuit surface thereof faces a main surface of the package substrate 10; at least one intermediate die 12 positioned between the package substrate 10 and the main die 11, such that a circuit surface of the at least one intermediate die 12 faces the circuit surface of the main die 11; a sub-die 13 provided in parallel in a direction intersecting the thickness direction of the main die 11 and positioned such that a circuit surface of the sub-die 13 faces the circuit surface of the at least one intermediate die 12; and connection portions 14 for electrically connecting the package substrate 10 and the regions on the circuit surface of the main die 11 and the circuit surface of the sub-die 13 that do not overlap the intermediate dies 12, at least one of the intermediate dies 12 being positioned spanning across the main die 11 and the sub-die 13 such that the circuit surface of said intermediate die faces an end portion of the circuit surface of the main die 11 and an end portion of the circuit surface of the sub-die 13.

Description

Technical Field

[0001] The present invention relates to a module and a method for manufacturing the same.

Background Art

[0002] Conventionally, volatile memories (RAMs) such as DRAM (Dynamic Random Access Memory) are known as storage devices. For DRAM, there is a demand for increased capacity to withstand the high performance of arithmetic units (hereinafter referred to as logic chips or logic chips) and the increase in data volume. Therefore, miniaturization of the memory (memory cell array, memory chip) and increased capacity by planar addition of cells have been attempted. On the other hand, due to vulnerability to noise due to miniaturization and an increase in chip area, this type of capacity increase has reached its limit.

[0003] Therefore, recently, technologies have been developed to realize increased capacity by stacking a plurality of planar memories in three dimensions (3D). In addition, with the increase in data volume, the speed of data communication between chips (logic chips and memory chips) has been increased (see, for example, Patent Documents 1 to 3).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor module of Patent Document 1, a recess is formed on the upper part of the intermediate substrate, and a plug penetrating the intermediate substrate is formed. Then, a large chip is arranged on one surface side of the intermediate substrate, and a package substrate is arranged on the other surface side. Also, a small chip is arranged at the position of the recess. The large chip is electrically connected to the package substrate using the plug and is also electrically connected to the small chip. However, since an intermediate substrate having a plug is used, the cost is high.

[0006] In the semiconductor module of Patent Document 2, a seed layer is formed on the substrate, and low pillars are formed on the region excluding the resist. Further, in the second photolithography process, additional pillars are added on some of the low pillars to form high pillars. Then, the seed layer is removed, and two chips are stacked and connected to the pillars. However, since pillars with different heights are formed on the substrate, two photolithography processes are required, and the cost is high.

[0007] In the semiconductor module of Patent Document 3, one die is arranged at the portion where the solder resist of the package substrate is removed, and the other die is arranged so as to overlap the one die. The other die is connected to the package substrate and the one die. Since the other die is connected in the same process as the package substrate and the one die, it is necessary to improve the height accuracy, and the cost is high. Also, when height variations occur, the yield is considered to be low.

[0008] The present invention has been made in view of the above problems, and an object thereof is to provide a module in which a plurality of different types of chips are integrated at low cost and a manufacturing method thereof.

Means for Solving the Problems

[0009] The present invention relates to a module formed by stacking a plurality of dies, the module comprising: a package substrate; a main die arranged with its circuit surface facing a main surface of the package substrate; at least one intermediate die arranged between the package substrate and the main die and arranged with its circuit surface facing the circuit surface of the main die; a sub-die arranged with its circuit surface facing the circuit surface of at least one of the intermediate die and juxtaposed in a direction intersecting the thickness direction of the main die; and a connection portion electrically connecting between an area of ​​the circuit surface of the main die and an area of ​​the circuit surface of the sub-die that does not overlap with the intermediate die and the package substrate, wherein at least one of the intermediate dies is arranged straddling an end of the circuit surface of the main die and an end of the circuit surface of the sub-die with its circuit surface facing the end of the circuit surface of the main die.

[0010] Preferably, the module further comprises a stress relief layer disposed between the at least one intermediate die and the package substrate, for relieving stress between the package substrate and the at least one intermediate die.

[0011] The connection portion preferably has a multi-layer connection structure.

[0012] In addition, any one of the main die, the intermediate die, and the sub-die is preferably a stacked memory.

[0013] It is also preferable that the circuit surface of the main die is provided with a power supply circuit for increasing or decreasing the voltage of the power supplied to the intermediate die, in an area adjacent to the connection area of ​​the intermediate die.

[0014] It is also preferable that the main die and the sub die are supplied with power from each other via the intermediate die that straddles both of them.

[0015] In addition, the sub-die is preferably a power supply plate that supplies power to the intermediate die disposed across the main die and the sub-die.

[0016] The present invention also relates to a module manufacturing method in which a plurality of dies are stacked, the method including: a connection portion arranging step of arranging a connection portion for establishing an electrical connection on a circuit surface of a main die; an intermediate die arranging step of arranging a plurality of intermediate dies on the circuit surface of the main die with their circuit surfaces facing each other; a package substrate arranging step of facing one surface of a package substrate having a relaxation layer arranged at a position overlapping at least one of the intermediate dies to the main die and the intermediate dies, and bringing the relaxation layer into contact with at least one of the intermediate dies; and a sub-die arranging step of arranging a sub-die with its circuit surface facing the circuit surface of at least one of the intermediate dies and the one surface of the package substrate. The intermediate die arranging step relates to a module manufacturing method in which an end portion of at least one of the intermediate dies is arranged so as to protrude in a direction intersecting the thickness direction from an end portion of the main die.

[0017] Preferably, the connection portion arranging step includes a main-side connection portion arranging step of arranging one connection terminal on the circuit surface of the main die, and a substrate-side connection terminal arranging step of arranging the other connection terminal on one surface of the package substrate.

[0018] Preferably, the intermediate die arranged across the main die and the sub-die is a memory die that relays communication between the main die and the sub-die, and preferably includes an interface circuit, a control arbitration circuit, a memory control circuit, and a memory array.

[0019] Preferably, the intermediate die arranged across the main die and the sub-die is a stacked memory in which a logic die and a memory die are stacked.

[0020] Preferably, the main die and the sub-die are arranged in a one-dimensional direction or a two-dimensional direction in a plan view via the intermediate die arranged across the main die and the sub-die.

Advantages of the Invention

[0021] According to the present invention, it is possible to provide a module in which a plurality of different types of chips are integrated at low cost and a method for manufacturing the same.

Brief Description of the Drawings

[0022]

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Embodiments for Carrying Out the Invention

[0023] Hereinafter, the module 1 according to each embodiment of the present invention and its manufacturing method will be described with reference to FIGS. 1 to 17 be referred to and explained. First, the outline of the module 1 according to each embodiment will be described.

[0024] The module 1 according to each embodiment is a module 1 in which a plurality of different types of chips (dies) are integrated. Thereby, a module 1 in which a plurality of chips are arranged on one package substrate 10 can be provided. Since the plurality of chips have different sizes and thicknesses respectively, it is necessary to arrange them on the package substrate 10 in consideration of this size and thickness. In particular, it is necessary to configure a circuit for electrically connecting a plurality of chips, and it is preferable to adopt a configuration with lower cost and higher yield. In the following embodiments, an attempt is made to provide a module 1 with low cost and high yield.

[0025] [First Embodiment] Next, the module 1 according to the first embodiment of the present invention and its manufacturing method will be described with reference to FIGS. 1 to 7. The module 1 according to the first embodiment is a module 1 configured by stacking a plurality of dies. As shown in FIG. 1, the module 1 includes a package substrate 10, a main die 11, a plurality of intermediate dies 12, a sub die 13, a connection portion 14, a relaxation layer 15, an underfill layer 16, and heat dissipation fins 17.

[0026] The package substrate 10 is, for example, an organic substrate. The package substrate 10 is a plate-like body having a rectangular shape in plan view. The package substrate 10 has a circuit (not shown) inside. On the surface 10b opposite to the one surface 10a of the package substrate 10, a solder ball 101 for electrically connecting to a main substrate (not shown) is arranged.

[0027] The main die 11 is a processor such as an MPU, for example. The main die 11 is a plate-like body having a rectangular shape in plan view. The main die 11 is configured to have an area smaller than that of the package substrate 10 in plan view. The main die 11 has a circuit surface 11a on one surface. The main die 11 is arranged such that the circuit surface 11a faces the main surface 10a of the package substrate 10.

[0028] At least one intermediate die 12 is provided. Preferably, a plurality of intermediate dies 12 are provided. The intermediate die 12 includes, for example, a stacked DRAM, an IF-IP, a stacked SRAM, a power module VRM, a coprocessor, and the like. The intermediate die 12 is a plate-like body having a rectangular shape in plan view. The intermediate die 12 is arranged between the package substrate 10 and the main die 11, and the circuit surface 12a of the intermediate die 12 faces the circuit surface 11a of the main die 11. The intermediate die 12 is electrically connected to the main die 11 using microbumps 121 or the like.

[0029] The sub-die 13 is, for example, a power plate. The sub-die 13 is a plate-like body having a rectangular shape in plan view. The sub-die 13 is arranged such that its circuit surface 13a faces the circuit surface 12a of at least one intermediate die 12. Also, the sub-dies 13 are arranged side by side in a direction intersecting the thickness direction of the main die 11. In the present embodiment, the sub-die 13 is electrically connected to the circuit surface 12a of at least one intermediate die 12 using solder balls or the like. Also, a solder ball 131 is arranged on the circuit surface 13a of the sub-die 13 as an example of the connection portion 14.

[0030] According to the above main die 11, intermediate die 12, and sub-die 13, at least one of the intermediate dies 12 is arranged to straddle with its circuit surface 12a facing the end of the circuit surface 11a of the main die 11 and the end of the circuit surface 13a of the sub-die 13. In this embodiment, as an example, the intermediate die 12 which is a stacked memory (stacked DRAM) is arranged with its circuit surface 12a facing the circuit surfaces 11a and 13a of both the end of the main die 11 and the end of the sub-die 13. Also, this intermediate die 12 is electrically connected to both the main die 11 and the sub-die 13. And in this embodiment, this intermediate die 12 is connected to the main die 11 using, for example, a Cu pillar 141 with a protruding part solder-coated as a part of the connection part 14.

[0031] The connection part 14 is composed of, for example, a conductive material. The connection part 14 electrically connects the region that does not overlap with the intermediate die 12 between the circuit surface of the main die 11 and the circuit surface of the sub-die 13 and the package substrate 10. The connection part 14 is composed of, for example, a multilayer connection structure. Specifically, the connection part 14 is composed of, for example, a Cu pillar 141 arranged on the circuit surface of the main die 11 and a Cu core ball 142 arranged on one surface 10a of the package substrate 10.

[0032] The relaxation layer 15 is, for example, a die Ta attach material. The relaxation layer 15 is arranged between at least one intermediate die 12 and the package substrate 10 to relax the stress between the package substrate 10 and at least one intermediate die 12. In this embodiment, the relaxation layer 15 is arranged between a stacked DRAM which is one of the intermediate dies 12 and the package substrate 10. In this embodiment, a material with high thermal conductivity may be used for the relaxation layer 15.

[0033] The underfill layer 16 is, for example, an epoxy layer. The underfill layer 16 is disposed between the package substrate 10 and the main die 11. Also, the underfill layer 16 is disposed between the package substrate 10 and the sub-die 13. Also, the underfill layer 16 is disposed between the main die 11 and the intermediate die 12. Also, the underfill layer 16 is disposed between the sub-die 13 and the intermediate die 12.

[0034] The heat sink fins 17 are made of, for example, a metal material. The heat sink fins 17 are configured to have an area larger than that of the main die 11 and the sub-die 13 in a plan view. The heat sink fins 17 are disposed, for example, on the exposed surface opposite to the circuit surfaces of the main die 11 and the sub-die 13 via the TIM 171.

[0035] According to the above module 1, power is supplied from the package substrate 10 to the main die 11 and the sub-die 13 via the connection portion 14. The intermediate die 12 connected to the main die 11 receives power supply from the main die 11. Also, the intermediate die 12 connected to the sub-die 13 receives power supply from the sub-die 13. The intermediate die 12 connected to the main die 11 and the sub-die 13 receives power supply from both of them. Thereby, the plurality of dies can operate.

[0036] Next, a method for manufacturing the module 1 according to the present embodiment will be described. The method for manufacturing the module 1 includes a main die placement step, a connection portion placement step, an intermediate die placement step, a relaxation layer placement step, a package substrate placement step, a sub-die placement step, a solder ball placement step, and a heat sink fin placement step.

[0037] In the main die placement step, as shown in FIGS. 2 and 3, the main die 11 is placed on the placement jig 100. The main die 11 is placed on the placement jig 100 having a pedestal portion 110 that protrudes in a convex shape at a position for placing the intermediate die 12 that straddles the end portions. The main die 11 is placed at a position on the placement jig 100 that does not overlap with the pedestal portion 110.

[0038] In the connection part arrangement step, a connection part 14 for establishing an electrical connection is arranged on the circuit surface 11a of the main die 11. In the connection part arrangement step, the connection part 14 is appropriately arranged in a region of the circuit surface 11a of the main die 11 where the intermediate die 12 is not arranged. Also, in the connection part arrangement step, the connection part 14 is arranged in a region that Intermediate die 12 overlaps with the part arranged across the main die 11. In the present embodiment, the connection part arrangement step includes a main-side connection part arrangement step of arranging one connection terminal on the circuit surface 11a of the main die 11 and a substrate-side connection terminal arrangement step of arranging the other connection terminal on one surface 10a of the package substrate 10. Specifically, the connection part arrangement step includes a main-side connection step of arranging a Cu pillar 141 on the circuit surface 11a of the main die 11 and a step of arranging a Cu core ball 142 on one surface 10a of the package substrate 10. Also, the connection part arrangement step includes a substrate-side connection step of arranging a Cu pillar 141 on the circuit surface 13a of the sub-die 13.

[0039] In the intermediate die arrangement step, a plurality of intermediate dies 12 are arranged on the circuit surface 11a of the main die 11 with their own circuit surfaces 12a facing each other. Intermediate In the die arrangement step, for example, an IF-IP, a stacked SRAM, a coprocessor, a VRM, and a stacked DRAM are arranged. In the intermediate die arrangement step, at least one end of the intermediate die 12 is arranged to protrude in a direction intersecting the thickness direction from the end of the main die 11. In the present embodiment, in the intermediate die arrangement step, the stacked DRAM is arranged to protrude in a direction intersecting the thickness direction from the end of the main die 11.

[0040] In the relaxation layer arrangement step, as shown in FIG. 4, a relaxation layer 15 is arranged on one surface 10a of the package substrate 10. In the relaxation layer arrangement step, the relaxation layer 15 is arranged according to the position of the intermediate die 12 arranged across the main die 11 and the sub-die 13 on one surface 10a of the package substrate 10.

[0041] In the package substrate placement step, one surface 10a of the package substrate 10, on which a relaxation layer 15 for stress relaxation is disposed at a position overlapping at least one intermediate die 12, faces the main die 11 and the intermediate die 12. Also, in the package substrate placement step, the relaxation layer 15 is brought into contact with at least one intermediate die 12. Then, in the package substrate placement step, the position of the Cu core ball 142 disposed on one surface 10a of the package substrate 10 is aligned with and connected to the Cu pillar 141 disposed on the circuit surface 11a of the main die 11. In the package substrate placement step, after the connection, the placement jig 100 is removed.

[0042] In the sub-die placement step, as shown in FIG. 5, the sub-die 13 is disposed with its circuit surface 13a facing the circuit surface 12a of at least one intermediate die 12 and the one surface 10a of the package substrate 10. In the sub-die placement step, for example, the circuit surface 13a of the sub-die 13 faces the circuit surface 12a of the intermediate die 12 that protrudes in a direction intersecting the thickness direction from the main die 11. In the sub-die placement step, the solder ball 131 disposed on the region of the circuit surface 13a overlapping the intermediate die 12 is connected to the circuit surface 12a of the intermediate die 12. Also, in the sub-die placement step, the solder ball 131 disposed on the region of the circuit surface 13a that does not overlap the intermediate die 12 is connected to the Cu core ball 142 disposed on the one surface 10a of the package substrate 10. Note that a Cu pillar 141 may be used instead of the solder ball 131. Also, in the sub-die placement step, an underfill layer 16 (e.g., an epoxy resin) is filled between the main die 11 and the sub-die 13 and the package substrate 10.

[0043] In the solder ball placement step, as shown in FIG. 6, the solder ball 101 is disposed on the other surface 10b of the package substrate 10. In the solder ball placement step, the solder ball 101 is disposed at a position for electrical connection to the main substrate.

[0044] In the heat dissipation fin arrangement step, as shown in FIG. 7, heat dissipation fins 17 are arranged on the exposed surfaces 11b and 13b opposite to the circuit surfaces of the main die 11 and the sub-die 13. In the heat dissipation fin arrangement step, the heat dissipation fins 17 are arranged via the TIM 171.

[0045] According to the module 1 and its manufacturing method according to the first embodiment as described above, the following effects can be obtained. (1) A module 1 composed of a plurality of dies stacked, including a package substrate 10, a main die 11 arranged with its circuit surface facing the main surface of the package substrate 10, a plurality of intermediate dies 12 arranged between the package substrate 10 and the main die 11 with their circuit surfaces facing the circuit surface of the main die 11, a sub-die 13 arranged with its circuit surface facing the circuit surface of at least one intermediate die 12 and arranged in parallel in a direction intersecting the thickness direction of the main die 11, and a connection portion 14 that electrically connects the region between the package substrate 10 and the region that does not overlap with the intermediate die 12 among the circuit surfaces of the main die 11 and the sub-die 13. At least one of the intermediate dies 12 is arranged to straddle the end of the circuit surface of the main die 11 and the end of the circuit surface of the sub-die 13 with its circuit surface facing them. Thereby, compared with the case of providing a substrate between the package substrate 10, the main die 11, and the sub-die 13, low cost can be realized.

[0046] (2) The module 1 further includes a relaxation layer 15 arranged between at least one intermediate die 12 and the package substrate 10 to relax the stress between the package substrate 10 and at least one intermediate die 12. Thereby, when using an intermediate die 12 with a certain thickness that is likely to contact the package substrate 10, the stress generated in the intermediate die 12 can be relaxed using the relaxation layer 15. Also, when using a plurality of intermediate dies 12 with a certain thickness that are likely to contact the package substrate 10, the variation in the thickness of the intermediate dies 12 can be absorbed, so high yield can be realized.

[0047] (3) The sub-die 13 is a power supply plate that supplies power to the intermediate die 12 disposed across the main die 11 and the sub-die 13. Thereby, power can be efficiently supplied to the main die 11 and the intermediate die 12.

[0048] (4) A method for manufacturing a module 1 formed by stacking a plurality of dies, including a connection part arranging step of arranging a connection part 14 for establishing an electrical connection on the circuit surface of the main die 11, an intermediate die arranging step of arranging a plurality of intermediate dies 12 with their circuit surfaces facing each other on the circuit surface of the main die 11, a package substrate arranging step of facing one surface of the package substrate 10 provided with a relaxation layer 15 for relaxing stress at a position overlapping at least one intermediate die 12 to the main die 11 and the intermediate die 12 and bringing the relaxation layer 15 into contact with at least one intermediate die 12, and a sub-die arranging step of arranging the sub-die 13 with its circuit surface facing the circuit surface of at least one intermediate die 12 and one surface of the package substrate 10. The intermediate die arranging step arranges at least one end portion of the intermediate die 12 to protrude in a direction intersecting the thickness direction from the end portion of the main die 11. Thereby, since the package can be formed only by overlapping the package substrate 10, the main die 11, and the sub-die 13, low cost can be achieved. Further, by providing the relaxation layer 15, the stress generated in the intermediate die 12 can be relaxed when using an intermediate die 12 having a certain thickness that is likely to contact the package substrate 10. Further, when using a plurality of intermediate dies 12 having a certain thickness that are likely to contact the package substrate 10, the variation in the thickness of the intermediate die 12 can be absorbed to achieve a high yield.

[0049] (5) The connection part arranging step includes a main-side connection part arranging step of arranging one connection terminal on the circuit surface of the main die 11 and a substrate-side connection terminal arranging step of arranging the other connection terminal on one surface of the package substrate 10. By configuring the connection terminals in two parts and connecting them, a high connection part 14 can be realized while absorbing the variation in height to achieve a high yield.

[0050] [Second Embodiment] Next, the module 1 and its manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. 8 to 10. In the second embodiment, the same components are denoted by the same reference numerals, and the description will be simplified or omitted. In the module 1 and its manufacturing method according to the second embodiment, as shown in FIG. 8, it is different from the first embodiment in that a base plate 18 is disposed between the main die 11 and the sub-die 13 and the heat dissipation fins 17. The base plate 18 is, for example, a metal plate or the like. Further, in the module 1 and its manufacturing method according to the second embodiment, as shown in FIG. 9, it is different from the first embodiment in that the base plate 18 is used instead of the mounting jig 100. Further, in the module 1 and its manufacturing method according to the second embodiment, it is different from the first embodiment in that the sub-die 13 is disposed on the base plate 18 together with the main die 11. Further, in the module 1 and its manufacturing method according to the second embodiment, as shown in FIG. 10, the main die 11, the sub-die 13, and the intermediate die 12 are inverted up and down from the state shown in FIG. 9 in which they are disposed on the base plate 18, and are aligned and disposed on the package substrate 10 on which the Cu core balls 142 and the relaxation layer 15 are disposed. Thereby, since the main die 11, the sub-die 13, and the intermediate die 12 can be formed into the module 1 while being disposed on the base plate 18, the handling property during manufacturing can be improved.

[0051] [Third Embodiment] Next, the module 1 and its manufacturing method according to the third embodiment of the present invention will be described with reference to FIG. 11. In the third embodiment, the same components are denoted by the same reference numerals, and the description will be simplified or omitted. In the module 1 and its manufacturing method according to the third embodiment, it is different from the first and second embodiments in that the intermediate die 12 disposed across the main die 11 and the sub-die 13 is connected to the main die 11 by bump-less bonding. The intermediate die 12 disposed across the main die 11 and the sub-die 13 communicates with the main die 11 using hybrid bonding or non-contact communication means ( Magnetic field coupled communication (TCI), or Electric field coupled communication, etc.). (6) In the module 1 and its manufacturing method according to the third embodiment, when the intermediate die 12 arranged across the main die 11 and the sub-die 13 communicates with the main die 11 with a high bandwidth, for example, like a stacked DRAM, the hybrid bonding can be arranged with a higher density than the Cu pillar 141, so a higher bandwidth can be realized. Also, if non-contact communication means is used, the Cu pillar 141 becomes unnecessary, so the yield can be increased and the cost can be reduced.

[0052] [Fourth Embodiment] Next, the module 1 and its manufacturing method according to the fourth embodiment of the present invention will be described with reference to FIGS. 12 to 14. In the fourth embodiment, the same components are denoted by the same reference numerals, and the description will be simplified or omitted. The module 1 and its manufacturing method according to the fourth embodiment are different from the first to third embodiments in that, as shown in FIG. 12, they include two main dies 11 and two sub-dies 13. Also, the module 1 and its manufacturing method according to the fourth embodiment are different from the first to third embodiments in that one intermediate die 12 is arranged so as to straddle the main die 11. Further, in the module 1 and its manufacturing method according to the fourth embodiment, as shown in FIG. 13, in the main die arrangement step, the two main dies 11 are arranged with respect to the mounting jig 100 having two pedestal portions 110, which is different from the first to third embodiments. Thereby, the module 1 in which the sub-die 13 and the intermediate die 12 are arranged with respect to two or more main dies 11 can be manufactured. Note that, as shown in FIG. 14, when there is sufficient margin between the reverse side of the circuit surface 12a of the intermediate die 12 arranged so as to straddle the two main dies 11 and one surface 10a of the package substrate 10, the relaxation layer 15 may not be used.

[0053] [Fifth Embodiment] Next, the module 1 and its manufacturing method according to the fifth embodiment of the present invention will be described with reference to FIG. 15. In the fifth embodiment, the same components are denoted by the same reference numerals, and the description will be simplified or omitted. In the module 1 and its manufacturing method according to the fifth embodiment, the circuit surface 11a of the main die 11 is different from the first to fourth embodiments in that a power supply circuit 111 for boosting or bucking and stabilizing the voltage of the power supplied to the intermediate die 12 is provided in a region adjacent to the connection region of the intermediate die 12. The power supply circuit 111 boosts or buckles and stabilizes the power that decreases or increases at the connection position with the intermediate die 12. The power supply circuit 111 measures, for example, the voltage value of the power supplied to the intermediate die 12, and performs boosting or bucking based on the difference between the measured voltage value and a predetermined voltage value. The power supply circuit 111 performs boosting or bucking, for example, so as to reduce the difference in the voltage value with the largest difference among the power supplied to the intermediate die 12. It is also conceivable that the intermediate die 12 is a power supply module DRM that supplies power.

[0054] (7) The circuit surface 11a of the main die 11 is provided with a power supply circuit 111 for boosting or bucking the voltage of the power supplied to the intermediate die 12 in a region adjacent to the connection region of the intermediate die 12. Thereby, the operation of the intermediate die 12 can be stabilized.

[0055] [Sixth Embodiment] Next, the module 1 and its manufacturing method according to the sixth embodiment of the present invention will be described with reference to FIG. 16. In the sixth embodiment, the same components are denoted by the same reference numerals, and the description is simplified or omitted. In the module 1 and its manufacturing method according to the sixth embodiment, in the fourth and fifth embodiments, a part of the connection portion 14 between the two main dies 11 is used as the connection portion 14 for power supply, and the connection portion 14 for power supply to one main die 11 and the connection portion 14 for power supply to the other main die 11 are provided for each main die 11, which is different from the fourth and fifth embodiments. The intermediate die 12 (for example, a bridge chip) arranged across the two main dies 11 is different from the fourth and fifth embodiments in that it relays the power supply between the two main dies 11. Thereby, since power can be supplied to the ends of the two main dies 11 from a main die 11 different from itself, the wiring resistance can be reduced.

[0056] As described above, the preferred embodiments of the module of the present invention and its manufacturing method have been described. However, the present invention is not limited to the above-described embodiments and can be appropriately modified.

[0057] For example, in the fourth embodiment, the intermediate die 12 disposed across the two main dies 11 may be a memory die that relays communication between the two main dies 11. The memory die preferably includes, for example, as shown in FIG. 17, a plurality of interface circuits 201 with the main die 11, a control arbitration circuit 202, and a memory 203 (memory control circuit and memory array). Also, there may be a path for accessing the memory 203 (memory control circuit and memory array) from the plurality of interface circuits 201, and there may be a path for the interface circuits 201 to directly transmit and receive data without going through the memory 203 (memory control circuit and memory array). Further, based on the control information input from the interface circuit 201, the control arbitration circuit 202 preferably arbitrates the reading and writing of data from the plurality of interface circuits 201 to the memory 203 (memory control circuit and memory array) and controls the communication between the interface circuits 201.

[0058] Also, in the fourth embodiment, the intermediate die 12 disposed across the two main dies 11 may be a stacked memory in which a logic die and a memory die are stacked.

[0059] Also, the plurality of main dies 11 are preferably arranged in a one-dimensional direction or a two-dimensional direction in plan view via the intermediate die 12 disposed across the two main dies 11.

[0060] According to such a configuration, various methods can be adopted for access from the interface circuit 201 to its own memory 203 (memory control circuit and memory array) or communication with other interface circuits 201. For example, in a memory space common to all memory arrays existing in a plurality of intermediate dies 12, an address may be assigned to each memory array. When access to a memory array other than the self - confident memory array is detected, access information of the address and control signal may be forwarded to the interface circuit 201 existing in all other intermediate dies 12 arranged in module 1.

[0061] Also, when data transmission and reception are in packet form, a dedicated address may be assigned to each memory array existing in all intermediate dies 12. The addresses of the memory arrays connected to the front of the interface circuit 201 may be stored in their respective intermediate dies 12. During communication, the target memory array is specified by the packet header. The intermediate die 12 that receives the packet preferably determines access to its own memory array or data transmission and reception to the intermediate die 12 for forwarding. At this time, control information regarding memory access such as the address of the memory array to be accessed and read / write may be embedded in the payload part.

[0062] Furthermore, it may be a modified distributed memory system in which only a plurality of adjacent main dies 11 share the memory arrays existing in the intermediate die 12 commonly connected to them. In such a configuration, the memory arrays existing in the intermediate die 12 may be used as buffer memories or FIFOs connecting between the main dies 11.

[0063] For example, in the fourth embodiment, the main die 11 and the intermediate die 12 protruding in a direction intersecting the thickness direction from the main die 11 may be connected by bump - less bonding, similar to the third embodiment.

[0064] Also, in the above - mentioned embodiment, although the package substrate 10 is arranged with respect to the main die 11 arranged on the mounting jig 100, it is not limited thereto. Conversely, the main die 11 arranged on the mounting jig 100 may be arranged with respect to the package substrate 10.

[0065] Also, in the above embodiment, the intermediate die 12 was described as a stacked memory (stacked DRAM), but it is not limited thereto. Any one of the main die 11, the intermediate die 12, and the sub-die 13 may be a stacked memory.

Explanation of Reference Numerals

[0066] 1 Module 10 Package Substrate 11 Main Die 12 Intermediate Die 13 Sub-Die 14 Connection Portion 15 Relaxation Layer 16 Underfill Layer 17 Heat Dissipation Fin 18 Base Plate 100 Mounting Fixture 101 Solder Ball 110 Pedestal Portion 111 Power Circuit 121 Microbump 131 Solder Ball 141 Cu Pillar 142 Cu Core Ball

Claims

1. A module formed by stacking multiple dies, A package substrate; a main die arranged with a circuit surface facing a main surface of the package substrate; two intermediate dies disposed between the package substrate and the main die, the intermediate dies being disposed with their circuit surfaces facing the circuit surfaces of the main die; a sub-die arranged with its circuit surface facing a circuit surface of one of the intermediate dies and arranged in parallel in a direction intersecting a thickness direction of the main die; a connection portion that electrically connects a region of a circuit surface of the main die and a circuit surface of the sub die that does not overlap with the intermediate die to the package substrate; Equipped with The other intermediate die is disposed with its entire circuit surface facing the circuit surface of the main die; the intermediate die is disposed across an end of the circuit surface of the main die and an end of the circuit surface of the sub die with its circuit surface facing the end of the circuit surface of the main die; A module in which the circuit surface of the main die is provided with a power supply circuit in an area adjacent to the connection area of ​​the intermediate die, the power supply circuit increasing or decreasing the voltage of the power supplied to the intermediate die.

2. The module of claim 1 , wherein any one of the main die, the intermediate die, and the sub-die is a stacked memory.

3. The module according to claim 1 or 2, wherein the sub-die is a power supply plate that supplies power to the main die and the one of the intermediate dies arranged across the sub-die.

4. The module according to claim 1 , wherein the one of the intermediate dies arranged across the main die and the sub die is a bridge that relays communication between the main die and the sub die.

5. 4. The module according to claim 1, wherein the one of the intermediate dies arranged across the main die and the sub die is a stacked memory in which a logic die and a memory die are stacked.

6. A module formed by stacking multiple dies, A package substrate; Two main dies are arranged on a main surface of the package substrate with circuit surfaces facing each other; first to third intermediate dies disposed between the package substrate and the main die, each intermediate dies being disposed with its circuit surface facing a circuit surface of the main die; a connection portion electrically connecting a region of a circuit surface of the main die that does not overlap with the intermediate die to the package substrate; Equipped with the second and third intermediate dies are arranged with their entire circuit surfaces facing the respective circuit surfaces of the main die; the first intermediate die is disposed across an end of a circuit surface of one of the main dies and an end of a circuit surface of the other of the main dies with its circuit surface facing the end of the circuit surface of the other of the main dies; A module in which the circuit surface of the main die is provided with a power supply circuit in an area adjacent to the connection area of ​​the intermediate die, the power supply circuit increasing or decreasing the voltage of the power supplied to the intermediate die.

7. fourth and fifth intermediate dies disposed between the package substrate and the main die, with their circuit surfaces facing a circuit surface of the main die; Two sub dies are arranged with their circuit surfaces facing each other on the circuit surfaces of the fourth and fifth intermediate dies, and are arranged side by side in a direction intersecting the thickness direction of each of the main dies; Further equipped with the fourth intermediate die is disposed across an end of a circuit surface of the one of the main dies and an end of a circuit surface of one of the sub dies with its circuit surface facing the end of the circuit surface of the one of the sub dies; The module described in claim 6, wherein the fifth intermediate die is arranged across an end of a circuit surface of the other main die and an end of a circuit surface of the other of the sub-dies with its circuit surface facing the end of the circuit surface of the other of the sub-dies.

8. The module according to claim 6 or 7, wherein the first intermediate die arranged across the one main die and the other main die is a bridge that relays communication between the one main die and the other main die.

9. The fourth intermediate die arranged across the one main die and the one sub die is a bridge that relays communication between the one main die and the one sub die, The module described in claim 7 , wherein the fifth intermediate die arranged across the other main die and the other sub-die is a bridge that relays communication between the other main die and the other sub-die.

10. 10. The module of claim 7 or 9, wherein the main die is a processor and the sub-dies are stacked memories.

11. The module according to claim 1 , wherein the connection portion is a multi-layer connection structure.

12. The module according to any one of claims 1 to 5, wherein the main die and the sub-die are arranged in a one-dimensional direction or a two-dimensional direction in a plan view via the one intermediate die arranged across the main die and the sub-die.

13. The module according to any one of claims 7, 9, and 10, wherein the main die and the sub-die are arranged in a one-dimensional direction or a two-dimensional direction in a plan view via at least one of the first intermediate die arranged across the main dies or the fourth and fifth intermediate dies arranged across the main die and the sub-die, respectively.

14. The module according to claim 12 or 13, wherein the sub-die is a stacked memory, and memory arrays of a plurality of the stacked memories are assigned addresses in a common memory space.

15. A method for manufacturing a module formed by stacking a plurality of dies, a main die arranging step of arranging the main die on a mounting jig having a pedestal portion protruding convexly at a position where an intermediate die arranged across an end portion of the main die is to be arranged; a connection portion arranging step of arranging a connection portion for establishing an electrical connection on a circuit surface of the main die; an intermediate die arranging step of arranging a plurality of the intermediate dies on the circuit surface of the main die with their own circuit surfaces facing each other; a package substrate arranging step of arranging one surface of a package substrate to face the main die and the intermediate die; a sub-die arranging step of arranging a sub-die with its own circuit surface facing the circuit surface of at least one of the intermediate dies and one surface of the package substrate; comprising The intermediate die arranging step is a method for manufacturing a module, in which an end portion of at least one of the intermediate dies is arranged to protrude in a direction intersecting the thickness direction from an end portion of the main die.

16. The connection portion arranging step a main side connection portion arranging step of arranging one connection terminal on a circuit surface of the main die; a substrate side connection terminal arranging step of arranging the other connection terminal on one surface of the package substrate; The method for manufacturing a module according to claim 15, comprising.

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