Image forming apparatus

Abstract

To provide an image formation apparatus which forms an electrostatic latent image by emitting light to the surface of a photoreceptor by an exposure head and can correct a light amount when forming a pixel.SOLUTION: In an image formation apparatus, an exposure head 6 comprises: light-emitting element array chips 40a, 40b which are arranged at the same position in a rotation axial direction of a photoreceptor drum 1 and at different positions in a rotation direction of the photoreceptor drum 1; a rod lens array 23a which are fixed to a housing 24 at a position facing the light-emitting element array chip 40a and forms an image with the light emitted from a light emission part 50 of the light-emitting element array chip 40a on the photoreceptor drum 1; and a rod lens array 23b which is fixed to the housing 24 at the position facing the light-emitting element array chip 40b and forms an image with the light emitted from the light emission part 50 of the light-emitting element array chip 40b on the photoreceptor drum 1. The light emission part 50 of the light-emitting element array chip 40a and the light emission part 50 of the light-emitting element array chip 40b perform multiple exposure.SELECTED DRAWING: Figure 16

Description

Technical Field

[0001] The present invention relates to an image forming apparatus such as an electrophotographic copying machine or an electrophotographic printer that forms an image on a sheet using an electrophotographic method.

Background Art

[0002] When forming an image with an electrophotographic image forming apparatus, first, an electrostatic latent image is formed on the surface of a photoreceptor by irradiating the surface of the photoreceptor with light corresponding to image data. Then, toner is attached to the electrostatic latent image on the surface of the photoreceptor by a developing device to form a toner image, the toner image is transferred to a sheet, and the toner image transferred to the sheet is heated by a fixing device and fixed to the sheet to form an image.

[0003] Here, in Patent Document 1, as an apparatus for irradiating a photoreceptor with light to form an electrostatic latent image, an image forming apparatus is described that includes a light emitting unit using an organic EL or the like and an exposure head having a lens that forms the light irradiated from this light emitting unit on the surface of the photoreceptor. By using such an exposure head, compared with a configuration of a laser scanning method in which laser light is deflected and scanned by a rotating polygon mirror to form an electrostatic latent image, the number of components can be reduced, and the size reduction and manufacturing cost reduction of the image forming apparatus can be achieved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The light quantity of one light emitting unit using an LED, an organic EL, etc. included in the exposure head cannot be said to be sufficiently high. Therefore, in the exposure process, it is desirable that deterioration of image quality can be suppressed by compensating for the light quantity when forming pixels.

[0006] Therefore, an object of the present invention is to provide an image forming apparatus capable of compensating for the amount of light when forming pixels in an image forming apparatus that forms an electrostatic latent image by irradiating the surface of a photoreceptor with light from an exposure head.

Means for Solving the Problems

[0007] A typical configuration of an image forming apparatus according to the present invention for achieving the above object is an image forming apparatus that forms an electrostatic latent image by irradiating the surface of a rotating photoreceptor with light, and forms an image by attaching toner to the electrostatic latent image. In the image forming apparatus, an exposure head that forms the electrostatic latent image by irradiating the surface of the photoreceptor with light includes a housing, a circuit board fixed to the housing, a silicon substrate mounted on the circuit board, a plurality of light emitting portions that emit light, a first electrode layer including a plurality of electrodes arranged in the rotation axis direction of the photoreceptor and separated and arranged on the silicon substrate, a light emitting layer laminated on the first electrode layer and emitting light when a voltage is applied, and a second electrode layer arranged on the side opposite to the side where the first electrode layer is arranged with respect to the light emitting layer and through which light can pass. A first light emitting chip and a second light emitting chip each including a plurality of light emitting portions, the first light emitting chip and the second light emitting chip arranged at different positions in the rotation direction of the photoreceptor, a first lens fixed to the housing at a position facing the first light emitting chip and imaging the light emitted from the plurality of light emitting portions included in the first light emitting chip on the photoreceptor, and a second lens configured separately from the first lens and fixed to the housing at a position facing the second light emitting chip and imaging the light emitted from the plurality of light emitting portions included in the second light emitting chip on the photoreceptor. The exposure head has, and each of the first light emitting chip and the second light emitting chip includes a drive circuit built in the silicon substrate and driving each of the plurality of light emitting portions. and a control unit that controls application of voltages to each of the plurality of electrodes of the first light-emitting chip and the plurality of electrodes of the second light-emitting chip based on image data so that the light-emitting layer of the first light-emitting chip and the light-emitting layer of the second light-emitting chip emit light respectively, the control unit being capable of controlling application of voltages to each of the plurality of electrodes of the first light-emitting chip and the plurality of electrodes of the second light-emitting chip so that the first light-emitting chip and the second light-emitting chip irradiate light at the same position on the photoreceptor by applying voltages to the plurality of electrodes of the first light-emitting chip and the plurality of electrodes of the second light-emitting chip Furthermore, at least a part of the plurality of electrodes overlaps with the drive circuit when viewed along a direction perpendicular to the surface of the silicon substrate. This is a feature.

Effects of the Invention

[0008] According to the present invention, in an image forming apparatus that forms an electrostatic latent image by irradiating light onto the surface of a photoreceptor with an exposure head, it is possible to compensate for the amount of light when forming pixels.

Brief Description of the Drawings

[0009]

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Embodiment for Carrying Out the Invention

[0010] <Image forming apparatus> Hereinafter, the overall configuration of the image forming apparatus A according to the present invention will be described with reference to the drawings together with the operation during image formation. Note that the dimensions, materials, shapes, relative arrangements, etc. of the constituent parts described below are not intended to limit the scope of the present invention only to those, unless otherwise specifically described.

[0011] The image forming apparatus A is a full-color image forming apparatus that forms an image by transferring four colors of toner, yellow Y, magenta M, cyan C, and black K, onto a sheet. In the following description, although suffixes Y, M, C, and K are attached to the members using the above-mentioned respective color toners, the configurations and operations of the respective members are substantially the same except that the colors of the toners used are different. Therefore, the suffixes are appropriately omitted unless distinction is required.

[0012] FIG. 1 is a schematic cross-sectional view of the image forming apparatus A. As shown in FIG. 1, the image forming apparatus A has an image forming unit for forming an image. The image forming unit includes a photosensitive drum 1 (1Y, 1M, 1C, 10K) as a photoreceptor, a charging device 2 (2Y, 2M, 2C, 2K), an exposure head 6 (6Y, 6M, 6C, 6K), a developing device 4 (4Y, 4M, 4C, 4K), and a transfer device 5 (5Y, 5M, 5C, 5K).

[0013] Next, the image forming operation by the image forming apparatus A will be described. When forming an image, first, a sheet S stored in the sheet cassette 99a or the sheet cassette 99b is sent to the registration roller 96 by the pickup rollers 91a, 91b, the feed rollers 92a, 92b, and the conveyance rollers 93a to 93c. Thereafter, the sheet S is fed onto the conveyance belt 11 by the registration roller 96 at a predetermined timing.

[0014] On one hand, in the image forming unit, first, the surface of the photosensitive drum 1Y is charged by the charging device 2Y. Next, according to the image data read by the image reading unit 90 or the image data transmitted from an external device (not shown), the exposure head 6Y irradiates light onto the surface of the photosensitive drum 10Y to form an electrostatic latent image on the surface of the photosensitive drum 10Y. Then, yellow toner is attached to the electrostatic latent image formed on the surface of the photosensitive drum 1Y by the developing device 4Y to form a yellow toner image on the surface of the photosensitive drum 1Y. The toner image formed on the surface of the photosensitive drum 1Y is transferred to the sheet S being conveyed by the conveying belt 11 by applying a transfer bias to the transfer device 5Y.

[0015] By the same process, the photosensitive drums 1M, 1C, and 1K are also irradiated with light from the exposure heads 6M, 6C, and 6K to form electrostatic latent images, and magenta, cyan, and black toner images are formed by the developing devices 4M, 4C, and 4K. Then, by applying a transfer bias to the transfer devices 5M, 5C, and 5K, these toner images are superposed and transferred onto the yellow toner image on the sheet S. Thereby, a full-color toner image corresponding to the image data is formed on the surface of the sheet S.

[0016] Thereafter, the sheet S carrying the toner image is conveyed to the fixing device 94 by the conveying belt 97, and heating and pressing processes are performed in the fixing device 94. Thereby, the toner image on the sheet S is fixed to the sheet S. Thereafter, the sheet S with the fixed toner image is discharged to the discharge tray 95 by the discharge roller 98.

[0017] <Exposure head> Next, the configuration of the exposure head 6 will be described.

[0018] Fig. 2(a) is a perspective view of the photosensitive drum 1 and the exposure head 6. Fig. 2(b) is a cross-sectional view of the photosensitive drum 1 and the exposure head 6. Figs. 3(a) and 3(b) are views showing the mounting surfaces on one side and the other side of the printed circuit board 22 provided in the exposure head 6. Fig. 3(c) is an enlarged view of the region V shown in Fig. 3(b).

[0019] As shown in FIG. 2, the exposure head 6 is fixed by a fixing member (not shown) at a position facing the surface of the photosensitive drum 1. The exposure head 6 includes a light-emitting element array chip 40 that emits light, and a printed circuit board 22 (first circuit board) on which the light-emitting element array chip 40 is mounted. The exposure head 6 also includes a rod lens array 23 that forms an image (condenses light) of the light emitted from the light-emitting element array chip 40 on the photosensitive drum 1, and a housing 24 to which the rod lens array 23 and the printed circuit board 22 are fixed.

[0020] A connector 21 is mounted on the surface of the printed circuit board 22 opposite to the mounting surface of the light-emitting element array chip 40. The connector 21 is provided for transmitting the control signal of the light-emitting element array chip 40 transmitted from the image controller unit 70 (FIG. 8) and connecting the power supply line. The light-emitting element array chip 40 is driven via the connector 21.

[0021] As shown in FIG. 3, a plurality of light-emitting element array chips 40 are mounted on the printed circuit board 22 in a staggered four-row arrangement. Here, the light-emitting element array chip 40a (first light-emitting chip) and the light-emitting element array chip 40b (second light-emitting chip) are arranged at the same position in the direction of the arrow X, which is the rotation axis direction of the photosensitive drum 1, and at different positions in the rotation direction (arrow Y direction) of the photosensitive drum 1. Although the light-emitting element array chips 40a and 40b are illustrated and described here, the other light-emitting element array chips 40 have the same arrangement. Note that the positions of the light-emitting element array chips 40a and 40b in the direction of the arrow X and the direction of the arrow Y may deviate within the tolerance range.

[0022] In each light-emitting element array chip 40, a plurality of light-emitting portions 50 are arranged at a resolution pitch of 1200 dpi (about 21.16 μm) in the longitudinal direction (arrow X direction). In each light-emitting element array chip 40, a plurality of light-emitting portions 50 are arranged at a predetermined pitch in the short-side direction (arrow Y direction). That is, in each light-emitting element array chip 40, the light-emitting portions 50 are two-dimensionally arranged in the arrow X direction and the arrow Y direction.

[0023] In this embodiment, the arrow X direction, which is the longitudinal direction of the light-emitting element array chip 40, is the rotation axis direction of the photosensitive drum 1 and also the main scanning direction. Further, the arrow Y direction, which is the short side direction of the light-emitting element array chip 40, is the rotation direction of the photosensitive drum 1 and also the sub-scanning direction. Also, the arrow Z direction is the stacking direction in which the layers of the light-emitting portion 50 of the layer structure described later overlap. Note that the longitudinal direction of the light-emitting element array chip 40 may be inclined by about ±1° with respect to the rotation axis direction of the photosensitive drum 1. Also, the short side direction of the light-emitting element array chip 40 may be inclined by about ±1° with respect to the rotation direction of the photosensitive drum 1.

[0024] <Light-emitting element array chip> Next, the configuration of the light-emitting element array chip 40 will be described.

[0025] FIG. 4 is a schematic view of the light-emitting element array chip 40. FIG. 5 is a cross-sectional view of the light-emitting element array chip 40 cut along the M-M cross-section shown in FIG. 4.

[0026] As shown in FIG. 4, the light-emitting element array chip 40 includes a light-emitting substrate 42 (second circuit substrate) having a circuit portion 46 for controlling the light-emitting portion 50, a light-emitting region 44 in which a plurality of light-emitting portions 50 are regularly arranged on the light-emitting substrate 42, and wire bonding pads 48. The light-emitting substrate 42 is mounted on the printed circuit board 22. Input and output of signals between the outside of the light-emitting element array chip 40 and the circuit portion 46 and power supply to the circuit portion 46 are performed through the wire bonding pads 48. Note that the circuit portion 46 can use a circuit including an analog drive circuit, a digital control circuit, or both.

[0027] As shown in FIG. 5, the light-emitting portion 50 is composed of a light-emitting substrate 42, a plurality of lower electrodes 54 two-dimensionally arranged at regular intervals in the arrow X direction and the arrow Y direction on the light-emitting substrate 42, a light-emitting layer 56, and an upper electrode 58.

[0028] The lower electrode 54 (the first electrode layer having a plurality of electrodes) is a plurality of electrodes formed in a layered and separated manner on the light-emitting substrate 42, and is an electrode provided corresponding to each pixel. The upper electrode 58 (the second electrode layer) is laminated on the light-emitting layer 56 at a position opposite to the side where the lower electrode 54 with respect to the light-emitting layer 56 is disposed. The upper electrode 58 is an electrode capable of transmitting (transmittable) light having the emission wavelength of the light-emitting layer 56.

[0029] The circuit unit 46 controls the potential of the selected lower electrode 54 based on a control signal generated according to the image data, and generates a potential difference between the selected lower electrode 54 and the upper electrode 58. When a potential difference occurs between the upper electrode 58, which is the anode, and the lower electrode 54, which is the cathode, electrons flow from the cathode into the light-emitting layer 56, and holes flow from the anode into the light-emitting layer 56. The light-emitting layer 56 emits light when electrons and holes recombine in the light-emitting layer 56.

[0030] The light directed toward the upper electrode 58 when the light-emitting layer 56 emits light is transmitted through the upper electrode 58 and emitted. Also, the light directed from the light-emitting layer 56 toward the lower electrode 54 is reflected from the lower electrode 54 toward the upper electrode 58, and the reflected light is also transmitted through the upper electrode 58 and emitted. In this way, the light-emitting unit 50 emits light. Although there is a time difference in the emission timing between the light directly emitted from the light-emitting layer 56 toward the upper electrode 58 and the light reflected from the lower electrode 54 and emitted from the upper electrode 58, since the thickness of the layer of the light-emitting unit 50 is extremely thin, it can be regarded as being almost simultaneous.

[0031] In this embodiment, the light-emitting substrate 42 is a silicon substrate. The upper electrode 58 is preferably transparent to the light-emitting wavelength of the light-emitting layer 56. For example, by using a transparent electrode such as indium tin oxide (ITO), the aperture ratio becomes substantially 100%, and the light emitted by the light-emitting layer 56 is directly emitted through the upper electrode 58. In this embodiment, the upper electrode 58 is an anode provided in common for each of the lower electrodes 54. However, it may be configured to be provided individually for each of the lower electrodes 54, or one upper electrode 58 may be provided for each of the plurality of lower electrodes 54. When a transparent electrode is used as the upper electrode 58, it is not necessarily entirely a transparent electrode. Only the light-emitting aperture may be a transparent electrode, and the wiring outside the aperture may be an electrode other than the transparent electrode such as a metal wire.

[0032] Also, an organic EL film, an inorganic EL layer, or the like is used for the light-emitting layer 56. When an organic EL film (organic light-emitting layer) is used as the light-emitting layer 56, the light-emitting layer 56 may be a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer as required. The light-emitting layer 56 may be continuously formed in the arrow X direction or may be divided into the same size as the lower electrode 54. Also, each of the lower electrodes 54 may be divided into a plurality of groups, and one light-emitting layer 56 may be laminated on the upper part of the lower electrodes 54 belonging to each group.

[0033] When a light-emitting material that is vulnerable to moisture, such as an organic EL layer or an inorganic EL layer, is used for the light-emitting layer 56, it is desirable to seal it to prevent moisture from entering the light-emitting region 44. As a sealing method, for example, a single film or a laminated sealing film of a thin film such as silicon oxide, silicon nitride, or aluminum oxide is formed. As a method for forming the sealing film, a method with excellent covering performance for structures such as steps is preferable, and for example, an atomic layer deposition method (ALD method) can be used. Note that the material, configuration, formation method, etc. of the sealing film are just examples and are not limited to the examples described above. Appropriate ones may be selected as appropriate.

[0034] Also, the lower electrode 54 is preferably made of a metal having a high reflectance with respect to the emission wavelength of the light-emitting layer 56. For example, Ag, Al, or an alloy of Ag and Al is used. Further, the lower electrode 54 is formed using Si integrated circuit processing technology together with the formation of the circuit portion 46, and is directly connected to the driving portion of the circuit portion 46. By forming the lower electrode 54 using Si integrated circuit processing technology in this way, since the process rule is about 0.2 μm and the accuracy is high, the lower electrode 54 can be arranged with high density and high accuracy. Furthermore, since the lower electrode 54 can be arranged with high density, almost all of the light-emitting region 44 can be made to emit light, and the utilization efficiency of the light-emitting region 44 can be increased. Note that the organic material of the light-emitting layer 56 is filled between the respective lower electrodes 54, and each lower electrode 54 is partitioned by the organic material.

[0035] Also, when the voltage applied across both ends of the light-emitting portion 50 becomes a predetermined value or more, a current starts to flow, and thereafter the value of the current increases almost proportionally to the value of the voltage. There is variation in the voltage at which the current starts to flow in each light-emitting portion 50. Therefore, at the stage before the product is shipped from the factory, the light-emitting portions 50 of the light-emitting element array chip 40 are caused to emit light individually and sequentially, and the current flowing through the light-emitting portion 50 is adjusted so that the light collected through the rod lens array 23 has a predetermined light amount. Note that the exposure head 6 performs focus adjustment for adjusting the distance between the light-emitting element array chip 40 and the rod lens array 23 in addition to the above-described light amount adjustment at the stage before the product is shipped from the factory.

[0036] FIG. 6(a) is a schematic diagram for explaining the configuration of each light-emitting portion 50 of the light-emitting element array chips 40a and 40b shown in FIG. 3(b). Here, although the light-emitting element array chips 40a and 40b are illustrated and described, the configuration of each light-emitting portion 50 of the light-emitting element array chip 40 arranged at the same position in the arrow X direction and at different positions in the arrow Y direction is also the same.

[0037] As shown in Fig. 6(a), the light-emitting part 50 of the light-emitting element array chip 40a is circular with a diameter of 60 μm, and eight light-emitting parts 50 are arranged side by side within a range of length L1 (480 μm in this embodiment) in the direction of arrow Y. Also, the light-emitting part 50a1 and the light-emitting part 50e1 are at the same position in the direction of arrow X and at different positions in the direction of arrow Y. The same applies to the light-emitting part 50b1 and the light-emitting part 50f1, the light-emitting part 50c1 and the light-emitting part 50g1, and the light-emitting part 50d1 and the light-emitting part 50h1. That is, the light-emitting element array chip 40a is provided with a plurality of sets of light-emitting parts 50 that are at the same position in the direction of arrow X and at different positions in the direction of arrow Y. Also, two adjacent light-emitting parts 50 in the direction of arrow Y are arranged such that their positions in the direction of arrow X are shifted by a distance L2 each. In this embodiment, the distance L2 is set to 21.16 μm (1200 dpi).

[0038] Since the light-emitting element array chip 40b uses the same components as the light-emitting element array chip 40a, the configuration (shape, arrangement) of its light-emitting part 50 is also the same as that of the light-emitting part 50 of the light-emitting element array chip 40a. Also, as described above, the light-emitting element array chip 40a and the light-emitting element array chip 40b are arranged at the same position in the direction of arrow X and at different positions in the direction of arrow Y. Therefore, in the direction of arrow X, two light-emitting parts 50 of the light-emitting element array chip 40a and two light-emitting parts 50 of the light-emitting element array chip 40b are arranged at the same position.

[0039] For example, the light-emitting parts 50a1, 50e1 of the light-emitting element array chip 40a and the light-emitting parts 50a2, 50e2 of the light-emitting element array chip 40b are at the same position in the direction of arrow X and at different positions in the direction of arrow Y. The same applies to the light-emitting parts 50b1, 50b2, 50f1, 50f2, the light-emitting parts 50c1, 50c2, 50g1, 50g2, and the light-emitting parts 50d1, 50d2, 50h1, 50h2.

[0040] Consider a case where the light emitting units 50a1, 50e1, 50a2, and 50e2 are arranged in this order from the upstream side to the downstream side in the rotation direction of the photosensitive drum 1. In this case, after the light emitting unit 50a1 emits light during the exposure process, the light emitting unit 50e1 emits light after a predetermined time, so that the same position on the photosensitive drum 1 is exposed by the light emitted from the light emitting units 50a1 and 50e1. In other words, one pixel is formed on the photosensitive drum 1 by the light emitted from the light emitting units 50a1 and 50e1. Irradiating the same position on the photosensitive drum 1 with light from a plurality of such light emitting units 50 is hereinafter referred to as multiple exposure. Similarly, multiple exposure can be performed by the light emitting unit 50a2 emitting light after a predetermined time from when the light emitting unit 50e1 emits light, and the light emitting unit 50e2 emitting light after that predetermined time.

[0041] Here, let the delay time of the light emission timing of the light emitting unit 50 during multiple exposure be Δt, the rotation speed of the photosensitive drum 1 be v, and the distance in the arrow Y direction of the light emitting unit 50 performing multiple exposure be L3 (Fig. 6). In this case, the delay time Δt is calculated from Δt = L3 / v. In the present embodiment, the distance L3 is 240 μm and the rotation speed v of the photosensitive drum 1 is 600 mm / s. Therefore, the delay time Δt of the light emission timing between the light emitting unit 50a2 and the light emitting unit 50e2 is 0.4 ms.

[0042] As described above, the image controller unit 70 (Fig. 8) controls the light emission timing of the light emitting unit 50 to perform the multiple exposure described above. As a result, since one pixel can be formed by a plurality of light emitting units 50 performing multiple exposure, even when the light amount of one of the light emitting units 50 is small, the light amount when forming one pixel can be compensated. Therefore, it is possible to suppress a shortage of the light amount for forming an electrostatic latent image during the exposure process, and it is possible to suppress deterioration of the image quality.

[0043] If the distance in the arrow Y direction of the light-emitting units 50 located at the same position in the arrow X direction is too large, the following problems may occur. That is, although the longitudinal direction of the printed circuit board 22 and the rotation axis direction of the photosensitive drum 1 are parallel in design, a deviation occurs due to tolerances and assembly errors. Due to the influence of this deviation, a deviation occurs in the relative positions of the light-emitting units 50a1, 50e1, 50a2, and 50e2 that are designed to be located at the same position in the arrow X direction. This deviation becomes larger as the distance in the arrow Y direction between the light-emitting units 50 arranged at the same position in the arrow X direction is larger. Hereinafter, consider the deviation in the arrow X direction between the light-emitting unit 50a1 and the light-emitting unit 50e2, which have the largest distance in the arrow Y direction.

[0044] FIG. 6(b) is a schematic diagram showing the positional relationship between the light-emitting unit 50a1 and the light-emitting unit 50e2 when the above-described deviation occurs. As shown in FIG. 6(b), when the distance in the arrow X direction between the light-emitting unit 50a1 and the light-emitting unit 50e2 is dX and the distance in the arrow Y direction is dY, dY = dX / tanθ. tanθ is calculated as tanθ = (0.1×2) / 340 when the assembly error between the printed circuit board 22 and the photosensitive drum 1 is ±0.1 mm and the length of the printed circuit board 22 in the arrow X direction is 340 mm.

[0045] When the deviation of the light imaging position on the photosensitive drum 1 exceeds 5 μm, the deviation is likely to be visually recognized on the image output to the sheet S. Therefore, in order to make the distance dX 5 μm or less, substituting dX = 5 μm and tanθ = (0.1×2) / 340 into the formula dY ≦ dX / tanθ, we get dY ≦ 8.5 mm. Therefore, by making the distance dY 8.5 mm or less, the deviation of the light imaging position on the photosensitive drum 1 can be suppressed to 5 μm or less, and the deviation is less likely to be visually recognized in the image on the sheet S.

[0046] Also, the distance L4 in the arrow Y direction between the light emitting part 50a1 and the light emitting part 50a2, that is, the pitch in the arrow Y direction between the light emitting element array chip 40a and the light emitting element array chip 40b, is calculated by dY - L3. As described above, the distance L3 is 240 μm. Therefore, in order to make it difficult to visually recognize the deviation on the image output to the sheet S, from the calculation result of substituting L3 = 240 μm and dY = 8.5 mm into the formula L4 ≦ dY - L3, the distance L4 is preferably 8.26 mm or less.

[0047] In the present invention, the shape of the light emitting part 50 is not limited to a circle, and as long as the light of the exposure area size corresponding to the output resolution of the image forming apparatus A is emitted and the image quality of the output image is at a level that satisfies the design specifications of the image forming apparatus A, it may be a polygon with four or more sides, an ellipse, or the like. Since the amount of light of the organic light emitting material is less than that of an LED, as shown in FIG. 7, by making the light emitting part 50 square and reducing the distance between adjacent light emitting parts 50, it is possible to secure a light emitting area for obtaining an amount of light sufficient to change the potential of the photosensitive drum 1.

[0048] In the present embodiment, although the configuration in which the light emitting parts 50 are two-dimensionally arranged in the arrow X direction and the arrow Y direction in one light emitting element array chip 40 has been described, it is sufficient that at least a plurality of light emitting parts 50 are arranged in the arrow X direction. Even in this case, if the configuration is such that multiple exposure is performed by each of the light emitting parts 50 of the light emitting element array chips 40 located at the same position in the arrow X direction, the amount of light for the exposure process can be increased as compared with the configuration in which the exposure process is performed by one light emitting part 50.

[0049] <System Configuration of Exposure Head> Next, the configuration of the exposure head 6 and the image controller unit 70 (control unit) that controls the exposure head 6 will be described. The image controller unit 70 is provided on the main body side of the image forming apparatus A. Although the control performed when processing one piece of image data (monochromatic) will be described below, when performing an image forming operation, the same processing for the four pieces of image data corresponding to yellow, magenta, cyan, and black is performed in parallel.

[0050] FIG. 8 is a block diagram showing the system configuration of the image controller unit 70 and the exposure head 6. As shown in FIG. 8, the image controller unit 70 includes an image data generation unit 71, a chip data conversion unit 72, a CPU 73, and a synchronization signal generation unit 74. The image controller unit 70 performs processing of image data, processing of image formation timing, and transmission of control signals for controlling the exposure head 6 by these parts.

[0051] The image data generation unit 71 receives the image data of the document read by the image reading unit 90 or the image data transferred from an external device via a network. The image data generation unit 71 performs dithering processing on the input image data at the resolution instructed by the CPU 73, and generates image data for outputting an image.

[0052] The synchronization signal generation unit 74 generates a line synchronization signal representing the division of each line of the image data. The CPU 73 instructs the synchronization signal generation unit 74 of the time interval of the signal period with the period in which the surface of the photosensitive drum 1 moves by a pixel size of 1200 dpi in the rotation direction as one line period with respect to the preset rotation speed of the photosensitive drum 1. For example, when the photosensitive drum 1 rotates at 200 mm / s, the time interval is instructed with one line period being 105.8 μs.

[0053] The chip data conversion unit 72 divides the image data for one line into each light emitting element array chip 40 in synchronization with the line synchronization signal generated by the synchronization signal generation unit 74 and input via the line synchronization signal line 78. Then, the chip data conversion unit 72 transmits the image data for one line to each light emitting element array chip 40 together with the chip select signal representing the valid range of the clock signal and the image data via the chip select signal line 75, the clock signal line 76, and the image data signal line 77.

[0054] The head information storage unit 171 provided in the exposure head 6 is connected to the CPU 73 via the communication signal line 79. The head information storage unit 171 stores, as head information, the light emission amount and mounting position information of each light emitting element array chip 40. Further, the light emitting element array chip 40 causes the light emitting unit 50 to emit light based on the set values of the above signals input from the image controller unit 70. Further, the light emitting element array chip 40 generates a chip select signal used by other light emitting element array chips 40 connected via the chip select signal line 75.

[0055] <System configuration of the light emitting element array chip> Next, the system configuration of the light emitting element array chip 40 will be described.

[0056] FIG. 9 is a block diagram showing the system configuration of the light emitting element array chip 40. As shown in FIG. 9, the circuit unit 46 of the light emitting element array chip 40 is composed of a digital unit 80 and an analog unit 86. The analog unit 86 generates a signal for driving the light emitting unit 50 based on the pulse signal generated by the digital unit 80, as will be described later.

[0057] The digital unit 80 includes a communication IF unit 81, a register unit 82, a chip select signal generation unit 83, an image data storage unit 84, and a pulse signal generation unit 85. The digital unit 80 generates a pulse signal for causing the light emitting unit 50 to emit light based on the set value, chip select signal, image data signal, and line synchronization signal preset by the communication signal in synchronization with the clock signal by these parts, and transmits it to the analog unit 86.

[0058] The chip select signal generation unit 83 delays the input chip select signal and generates a chip select signal used by other light emitting element array chips 40 connected via the chip select signal line 75.

[0059] The register unit 82 stores exposure timing information used by the image data storage unit 84, width information and phase information (delay information) of the pulse signal generated by the pulse signal generation unit 85, setting information of the drive current set by the analog unit 86, and the like. The communication IF unit 81 controls writing and reading of set values for the register unit 82 based on the communication signal input from the CPU 73.

[0060] The image data storage unit 84 holds the image data while the input chip select signal is valid, and outputs the image data to the pulse signal generation unit 85 in synchronization with the line synchronization signal. The pulse signal generation unit 85 generates a pulse signal that controls the timing to turn on the light emitting unit 50 based on the width information and phase information of the pulse signal set in the register unit 82 according to the image data input from the image data storage unit 84, and outputs it to the analog unit 86.

[0061] <Image data storage unit> Next, the operation of the image data storage unit 84 will be described. In the following description, although the chip select signal cs and the line synchronization signal lsync are negative logic signals, they may be positive logic signals.

[0062] FIG. 10 is a circuit configuration diagram of the image data storage unit 84. As shown in FIG. 10, the clock gate circuit 30 outputs the logical product of the inverted signal of the chip select signal cs and the clock signal clk, and outputs the clock signal s_clk to the flip-flop circuit 31 only when the chip select signal cs is valid. The flip-flop circuit 31 uses the image data signal data input to the image data storage unit 84 as the main input, and the same number as the number of light emitting units 50 provided in the longitudinal direction of the light emitting element array chip 40 are connected in series.

[0063] The flip-flop circuit 31 operates with the clock signal s_clk sent from the clock gate circuit 30. The flip-flop circuit 32 takes the output of the flip-flop circuit 31 as input and operates with the line synchronization signal lsync. The output of the flip-flop circuit 32 is output to the pulse signal generation unit 85 and the flip-flop circuit 33 as image data buf_data_0_000 to buf_data_0_747. The flip-flop circuit 33 takes the output of the flip-flop circuit 32 as input and operates with the multi-timing signal lshift_0. The output of the flip-flop circuit 33 is output to the pulse signal generation unit 85 as image data buf_data_1_000 to buf_data_1_xxx.

[0064] The multi-timing signal generation unit 34 generates the multi-exposure timing signal lshift_0 based on the line synchronization signal lsync, the clock signal clk, and the multi-timing setting signal lshift_start. In this embodiment, the multi-timing setting signal lshift_start generates lshift_0 by delaying the line synchronization signal lsync by the lshift_start setting value in cycles. For example, when lshift_start is set to 1, the multi-timing signal lshift_0 is a signal obtained by delaying the line synchronization signal lsync by one cycle with the clock signal clk.

[0065] FIG. 11 is a timing chart showing the operation in the main scanning direction in the image data storage unit 84. The meanings of the symbols shown in FIG. 11 are the same as those of the symbols shown in FIG. 10. As shown in FIG. 11, between the times T0 and T1 when cs = 0 is captured at the rising edge of clk, the image data is shifted in order such as data → dly_data_000 → dly_data_001. cs = 0 is input as many times as the number of light emitting units 50 in the main scanning direction of the clock signal. As a result, the image data for one line is held in dly_data_000 to dly_data_xxx.

[0066] After time T1, since cs = 1, the shift operation is not performed and the data is held. When lsync = 0 is captured at the rising edge of clk at time T2, one line of image data, such as dly_data_000 → buf_data_0_000 → dly_data_001 → buf_data_0_001, is output to the pulse signal generation unit 85 as buf_data_0_000~buf_data_0_xxx all at once.

[0067] Figure 12 is a timing chart showing the operation in the sub-scanning direction in the image data storage unit 84. The meanings of the symbols shown in Figure 12 are the same as those shown in Figure 10. Hereinafter, using Figure 12, the output buf_data_0_000 of the flip-flop circuit 32 and the output buf_data_1_000 of the flip-flop circuit 33 shown in Figure 10 will be described as representatives. And although the description will be omitted hereinafter, the same applies to all of buf_data_0_001~buf_data_0_xxx and buf_data_1_001~buf_data_1_xxx.

[0068] As shown in Figure 12, when lsync = 0 is input to the flip-flop circuit 32 at time T0, the value of dly_data_000 is output to buf_data_0_000. At time T1, when lshift_0 = 0 is input to the flip-flop circuit 33, the value of buf_data_0_000 is output to the pulse signal generation unit 85 as buf_data_1_000.

[0069] In this way, the data output to the pulse signal generation unit 85 as buf_data_0_000 when lsync = 0 is output to the pulse signal generation unit 85 again as buf_data_1_000 at the timing of the next lshift_0 = 0. Multiple exposure is realized by connecting buf_data_0_000 to the light emitting unit 50 that performs exposure first on the photosensitive drum 1 and buf_data_1_000 to the light emitting unit 50 that performs exposure later.

[0070] In the present embodiment, a flip-flop circuit has been exemplified and described as a configuration for holding the data of the light-emitting unit 50. However, the present invention is not limited to this. That is, for example, a memory circuit such as a RAM may be used to hold the data of the light-emitting unit 50. However, it is preferable to adopt a configuration in which the flip-flop circuit runs in parallel with the light-emitting unit 50 as in the present embodiment. Thereby, a simple circuit with a small wiring area can be formed.

[0071] <Analog section> Next, the configuration of the analog section 86 will be described. In the following description, although two driving units 61 for driving two light-emitting units 50 will be described, all the light-emitting units 50 are driven in the same manner.

[0072] FIG. 13 is a block diagram showing the configuration of the analog section 86. As shown in FIG. 13, the analog section 86 includes a driving unit 61 for driving the light-emitting unit 50, a DAC 62 (digital-to-analog converter), and a driving unit selection section 67.

[0073] The DAC 62 supplies an analog voltage for determining a driving current to the driving unit 61 via the signal line 63 based on the data set in the register section 82. The pulse signal generated by the pulse signal generation section 85 is input to the driving unit 61 via the signal line 66. In this way, an analog voltage for determining a driving current and a pulse signal are input to the driving unit 61. Then, based on these signals, the driving unit 61 controls the driving current and the light-emitting time of the light-emitting unit 50 by a driving circuit described later.

[0074] The drive unit selection unit 67 supplies a drive unit select signal for selecting the drive unit 61 to the two drive units 61 via the signal lines 64 and 65 based on the data set in the register unit 82. Here, the drive unit select signal is generated such that only the signal connected to the selected drive unit 61 becomes Hi. For example, when the upper drive unit 61 shown in FIG. 13 is selected, Hi is supplied only to the signal line 64, and Low is supplied to the signal line 65. The two drive units 61 have an analog voltage for determining the drive current set from the DAC 62 at the timing when the drive unit select signal becomes Hi. In this way, the CPU 73 sequentially selects the drive units 61 via the register unit 82 and sets the analog voltages of all the drive units 61 using one DAC 62 by setting the analog voltage of the selected drive unit 61.

[0075] Next, the configuration of the drive unit 61 will be described. FIG. 14 is a circuit diagram of the drive unit 61. As shown in FIG. 14, the drive unit 61 includes MOSFETs 112 to 115, a capacitor 116, and an inverter 117.

[0076] The MOSFET 112 supplies a drive current to the light emitting unit 50 according to the value of the gate voltage, and controls the current so that the drive current is turned off (extinguished) when the gate voltage is at the Low level. The signal line 63 is connected to the gate of the MOSFET 114. The MOSFET 114 transfers the voltage charged in the capacitor 116 to the MOSFET 112 when the PWM signal input via the signal line 63 is Hi.

[0077] The MOSFET 115 has the drive unit select signal transmitted from the drive unit selection unit 67 via the signal line 64 connected to its gate. The MOSFET 115 turns on when the input drive unit select signal is Hi, and charges the capacitor 116 with the analog voltage output from the DAC 62 and transmitted via the signal line 63. In this embodiment, the DAC 62 sets the analog voltage in the capacitor 116 at the timing before image formation, and keeps the voltage level by turning off the MOSFET 115 during the image formation operation.

[0078] By the above operation, the MOSFET 112 supplies a drive current to the light-emitting unit 50 according to the set analog voltage and the PWM signal. Also, when the input capacitance of the light-emitting unit 50 is large and the response speed during the off state is slow, the MOSFET 113 can increase the response speed during the off state. A signal obtained by logically inverting the PWM signal by the inverter 117 is input to the gate of the MOSFET 1103. When the PWM signal is Low, the gate of the MOSFET 113 becomes Hi, and the charge stored in the input capacitance of the light-emitting unit 50 is forcibly discharged.

[0079] <Rod lens array> Next, the configuration of the rod lens array 23 will be described.

[0080] In the present embodiment, as described above, the two light-emitting element array chips 40 are arranged at the same position in the arrow X direction and at different positions in the arrow Y direction. When the light emitted from the light-emitting units 50 provided in such two light-emitting element array chips 40 is imaged on the photosensitive drum 1 by one rod lens array 23, the following problems may occur.

[0081] FIG. 15(a) is a graph showing the relationship between the distance in the arrow Y direction between the center of the rod lens array 23 and the light-emitting unit 50 and the deviation amount of the imaging position of the light emitted from the light-emitting unit 50 and imaged on the photosensitive drum 1 by the rod lens array 23 with respect to the ideal position. FIG. 15(b) is a graph showing the relationship between the distance in the arrow Y direction between the center of the rod lens array 23 and the light-emitting unit 50 and the amount of light of the light emitted from the light-emitting unit 50 and imaged on the photosensitive drum 1 by the rod lens array 23.

[0082] As shown in FIG. 15, when the light emitting portion 50 is located at a position away from the center of the rod lens array 23, the deviation amount of the imaging position of light on the photosensitive drum 1 with respect to the ideal position increases, and the amount of light imaging on the photosensitive drum 1 also decreases. That is, when the light of the light emitting portions 50 of the two light emitting element array chips 40 described above is imaged on the photosensitive drum 1 using one rod lens array 23, problems such as deviation of the imaging position and decrease in the amount of light on the photosensitive drum 1 may occur. Further, as a problem on the rod lens array 23 side, when the diameter of the rod lens array 23 is increased, in addition to the depth of focus becoming shallow and the focus being easily shifted, the lens aberration becomes large and the shape of the converged spot deteriorates, and the image quality is likely to decrease.

[0083] Therefore, as shown in FIG. 16, a rod lens array 23a (first lens) fixed to the housing 24 is provided at a position facing the light emitting element array chip 40a. Further, at a position facing the light emitting element array chip 40b, a rod lens array 23b (second lens) which is separately formed from the rod lens array 23a and fixed to the housing 24 is provided. The rod lens array 23a images the light emitted from the light emitting portion 50 of the light emitting element array chip 40a on the surface of the photosensitive drum 1. The rod lens array 23b images the light emitted from the light emitting portion 50 of the light emitting element array chip 40b on the surface of the photosensitive drum 1.

[0084] In the present embodiment, as the rod lens array 23a, a selfoc (registered trademark) lens having a diameter D of 270 μm is two-dimensionally arranged in the arrow X direction and the arrow Y direction, and a selfoc lens array integrally formed thereof is used. The configuration of the rod lens array 23b is the same as that of the rod lens array 23a.

[0085] In this way, two rod lens arrays 23a and 23b are arranged at positions facing the two light-emitting element array chips 40a and 40b, respectively. As a result, the distance in the arrow Y direction between the light-emitting part 50 included in the light-emitting element array chip 40a and the rod lens array 23a becomes shorter, and the distance in the arrow Y direction between the light-emitting part 50 included in the light-emitting element array chip 40b and the rod lens array 23b becomes shorter. Therefore, it is possible to suppress displacement of the imaging position, reduction in light quantity, defocusing of the rod lens arrays 23a and 23b, and deterioration of the spot shape of the light emitted from the light-emitting parts 50 included in the light-emitting element array chips 40a and 40b on the photosensitive drum 1.

[0086] In addition, when the distance in the arrow Y direction between the two light-emitting element array chips 40a and 40b arranged at the same position in the arrow X direction and at different positions in the arrow Y direction is too short, the following problems may occur. That is, the light emitted from the light-emitting part 50 of the light-emitting element array chip 40a may enter the rod lens array 23b, and there is a risk that exposure processing is performed at an unintended position on the photosensitive drum 1 and the image quality deteriorates. Similarly, the light emitted from the light-emitting part 50 of the light-emitting element array chip 40b may enter the rod lens array 23a, and there is a risk that exposure processing is performed at an unintended position on the photosensitive drum 1 and the image quality deteriorates.

[0087] Here, as shown in FIG. 15(b), when the distance in the arrow Y direction between the center of the rod lens array 23 and the light-emitting part 50 is separated by about 700 μm or more, the light quantity of the light imaged on the photosensitive drum 1 becomes zero. Therefore, the light-emitting element array chips 40a and 40b and the rod lens arrays 23a and 23b are arranged so that the distance in the arrow Y direction between the light-emitting part 50 of the light-emitting element array chip 40a and the center of the rod lens array 23b and the distance in the arrow Y direction between the light-emitting part 50 of the light-emitting element array chip 40b and the center of the rod lens array 23a are about 700 μm or more. Thereby, it is possible to suppress that exposure processing is performed at an unintended position on the photosensitive drum 1 and the image quality deteriorates.

[0088] In addition, in the present embodiment, a configuration has been described in which two light-emitting element array chips 40 are provided at the same position in the arrow X direction and at different positions in the arrow Y direction, and rod lens arrays 23 are arranged at positions facing these light-emitting element array chips 40 respectively. However, the number of sets of the light-emitting element array chips 40 and the rod lens arrays 23 is not limited to two as long as it is plural. That is, for example, as shown in FIG. 17, a configuration may be adopted in which multiple exposures are performed with three sets of the light-emitting element array chips 40 and the rod lens arrays 23.

Explanation of Reference Numerals

[0089] 1…Photosensitive drum (photoconductor) 6…Exposure head 22…Printed circuit board (first circuit board) 23a…Rod lens array (first lens) 23b…Rod lens array (second lens) 24…Housing 40a…Light-emitting element array chip (first light-emitting chip) 40b…Light-emitting element array chip (second light-emitting chip) 42…Light-emitting substrate (second circuit board) 50…Light-emitting unit 54…Lower electrode (first electrode layer including a plurality of electrodes) 56…Light-emitting layer 58…Upper electrode (second electrode layer) 70…Image controller unit (control unit) A…Image forming apparatus

Claims

1. In an image forming apparatus that irradiates the surface of a rotating photoreceptor with light to form an electrostatic latent image and attaches toner to the electrostatic latent image to form an image, an exposure head that irradiates the surface of the photoreceptor with light to form the electrostatic latent image, a housing, a circuit board fixed to the housing, a silicon substrate mounted on the circuit board, a plurality of light emitting portions that emit light, a plurality of electrodes arranged in the rotation axis direction of the photoreceptor, and a first electrode layer including a plurality of electrodes separately arranged on the silicon substrate, a light emitting layer laminated on the first electrode layer and emitting light when a voltage is applied, and a second electrode layer arranged on the side opposite to the side where the first electrode layer is arranged with respect to the light emitting layer and through which light can pass, and a plurality of light emitting portions, and a first light emitting chip and a second light emitting chip each including the plurality of light emitting portions, the first light emitting chip and the second light emitting chip arranged at different positions in the rotation direction of the photoreceptor, a first lens fixed to the housing at a position facing the first light emitting chip and imaging the light emitted from the plurality of light emitting portions included in the first light emitting chip onto the photoreceptor, a second lens configured separately from the first lens, fixed to the housing at a position facing the second light emitting chip, and imaging the light emitted from the plurality of light emitting portions included in the second light emitting chip onto the photoreceptor, an exposure head having the above, each of the first light emitting chip and the second light emitting chip includes a drive circuit built in the silicon substrate and driving each of the plurality of light emitting portions, a control unit that controls the application of voltage to each of the plurality of electrodes of the first light emitting chip and the plurality of electrodes of the second light emitting chip based on image data so that the light emitting layer of the first light emitting chip and the light emitting layer of the second light emitting chip each emit light, and the control unit is capable of controlling the application of voltage to each of the plurality of electrodes of the first light emitting chip and the plurality of electrodes of the second light emitting chip so that the first light emitting chip and the second light emitting chip irradiate the same position on the photoreceptor with light, further comprising, when viewed along the direction perpendicular to the surface of the silicon substrate, at least a part of the plurality of electrodes overlaps with the drive circuit, The image forming apparatus is characterized by the above.

2. The image forming apparatus is, A first light-emitting chip group including a plurality of light-emitting chips arranged along the rotation axis direction, each of which includes the silicon substrate and the plurality of light-emitting portions, and including the first light-emitting chip, A second light-emitting chip group including a plurality of light-emitting chips arranged along the rotation axis direction and at a position different from that of the first light-emitting chip group in the rotation direction, each of which includes the silicon substrate and the plurality of light-emitting portions, and including the second light-emitting chip, The image forming apparatus according to claim 1, further comprising the same.

3. The image forming apparatus is A first lens array provided corresponding to the first light-emitting chip group and provided along the rotation axis direction, including the first lens array including the first lens, A second lens array provided corresponding to the second light-emitting chip group and provided along the rotation axis direction, including the second lens array including the second lens, The image forming apparatus according to claim 2, further comprising the same.

4. The light-emitting layer of the first light-emitting chip and the light-emitting layer of the second light-emitting chip are organic light-emitting layers, and the image forming apparatus according to claim 1 is characterized in that.

Images