Semiconductor device

Abstract

To provide a semiconductor device capable of extending an output voltage range by simple constitution.SOLUTION: In a semiconductor device constituted as a multichip type so that high voltage is applied especially to a lead terminal, a voltage detection circuit 200A has a multichip structure divided into a first chip 10 for reducing (dropping) the voltage of a directly applied high voltage signal and a second chip 20 for processing a voltage-reduced or voltage-dropped signal through the first chip 10. By adding a resistance element 2d and a resistance element 2e to the first chip 10 and connecting one-ends of both the resistance elements to GND, voltage to be inputted to an operational amplifier of the second chip 20 is reduced and an output voltage range can be extended.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a multi-chip type semiconductor device, and particularly to a semiconductor device to which a high voltage is applied to lead terminals.

Background Art

[0002] In hybrid vehicles and electric vehicles, a vehicle drive battery is configured to output a predetermined drive voltage, and it is necessary to constantly monitor the output voltage of the battery. For example, the output voltage of a vehicle drive battery in a hybrid vehicle is about 200V, and this is further boosted and used at around 500V. Therefore, a voltage monitoring circuit is required to monitor abnormal voltages. In recent years, a high voltage monitoring circuit for monitoring abnormal voltages exceeding 1000V has been demanded.

[0003] FIG. 5 shows an example of a motor drive device including a voltage detection circuit. The motor drive device 100 boosts a DC voltage (for example, 200V) output from a high voltage battery B insulated from the vehicle body by a boost converter 101 (for example, boosts it to 600V), and converts the boosted voltage into a three-phase AC voltage for motor drive by an inverter circuit 103 via a smoothing capacitor 102 and supplies it to a vehicle drive motor M. This type of motor drive device is described in, for example, Patent Document 1.

[0004] In this type of motor drive device, in order to monitor the boosted voltage, a voltage detection circuit 200 is provided, the voltages of a node b1 connected to the positive side of the battery B and a node b2 connected to the negative side of the battery B are detected, and based on the detection result, a control signal is output from a control circuit (not shown) to the boost converter 101 and the inverter circuit 103 to control motor drive.

[0005] The voltage detection circuit 200 for detecting a high voltage can be composed of an operational amplifier and a resistive element. FIG. 6 shows an example of configuring the voltage detection circuit 200 shown in FIG. 5 with an operational amplifier and a resistive element. The voltage detection circuit 200 shown in FIG. 6 has a resistive element 202a having a sufficiently large resistance value as an element for reducing the high voltage on the positive side of the battery B, and the terminal B1 is connected to the node b1 connected to the positive electrode side of the battery B shown in FIG. 5. The other end of the resistive element 202a is connected to the non-inverting input terminal of the operational amplifier 201 and also connected to one end of the resistive element 202b. This resistive element 202b is an element for applying the reduced voltage to the non-inverting input terminal of the operational amplifier 201, and has a smaller resistance value than the resistive element 202a having a large resistance value.

[0006] On the other hand, a resistive element 202c having a sufficiently large resistance value is an element for reducing the high voltage on the negative side of the battery B, and the terminal B2 is connected to the node b2 connected to the negative electrode side of the battery B shown in FIG. 5. The other end of the resistive element 202c is connected to the inverting input terminal of the operational amplifier 201.

[0007] The resistive element 202d is a resistive element (feedback resistor) for determining the amplification gain of the operational amplifier 201. One end of the resistive element 202d is connected to the inverting input terminal of the operational amplifier 201, and the other end is connected to the output terminal OUT of the operational amplifier 201. The detection signal output from the voltage detection circuit 200 is input to a control circuit (not shown), and a control signal for controlling the operations of the boost converter 101 and the inverter circuit 103 is output from the control circuit to control the driving of the motor M.

[0008] In this type of semiconductor device, the negative power supply terminal of the operational amplifier 201 is connected to the ground potential GND, and the positive power supply terminal is connected to the positive power supply voltage V+ with reference to the ground potential GND. Also, in order to offset the two input terminals of the operational amplifier 201 to the positive side with reference to the ground potential GND, the other end of the resistive element 202b connected to the non-inverting input terminal of the operational amplifier 201 is connected to the positive reference voltage VREF. By connecting in this way, it becomes unnecessary to prepare both a positive power supply for supplying a positive voltage and a negative power supply for supplying a negative voltage.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] By the way, in the semiconductor device shown in FIG. 6, the non-inverting input terminal of the operational amplifier 201 is connected to the resistor element 202b connected to the reference voltage VREF, and the potentials of the non-inverting input terminal and the inverting input terminal of the operational amplifier 201 become almost equal to the reference voltage VREF. In such a state, when the reference voltage VREF approaches the positive power supply voltage V+ of the operational amplifier 201 and the operational amplifier 201 does not have an input full-swing function, the operation stops. Specifically, when the positive power supply voltage V+ = 5.0 V and the reference voltage VREF is applied in the range of 0 V to 5 V, the output voltage obtained when the operational amplifier 201 operates normally is about 0 V to 4.4 V. In order to widen the output voltage range, the positive power supply voltage V+ may be set high, but power supplies (reference voltage and power supply voltage) with different voltage values are required. Also, if the operational amplifier 201 is changed to an operational amplifier having an input full-swing function, generally the cost increases. In view of such an actual situation, an object of the present invention is to provide a semiconductor device capable of widening the output voltage range with a simple configuration.

Means for Solving the Problems

[0011] In order to achieve the above object, the invention according to claim 1 of the present application is a semiconductor device in which a first chip having a function of reducing the input voltage and a second chip having a function of signal-processing the output signal of the first chip are mounted on a die pad, wire connections are made between the chip electrodes and between each chip electrode and a lead terminal for external extraction, and the device is sealed with a sealing resin. The lead terminal is Composed of a plurality of lead terminals,Comprising a first lead row and a second lead row arranged opposite to each other with the die pad therebetween; the first chip having a resistor element as a main component and including first to sixth resistor elements; the second chip having an operational amplifier as a main component; the lead terminals of the first lead row being composed of two lead terminals, one lead terminal of the first lead row being one of two resistor chip electrodes formed on one side of the first lead row side on the rectangular first chip, which is connected to a resistor chip electrode connected to one end of a series resistor row of the first resistor element and the second resistor element, the other lead terminal of the first lead row being the other resistor chip electrode of the two resistor chip electrodes, which is connected to a resistor chip electrode connected to one end of the third resistor element, and among the other resistor chip electrodes arranged on the other side opposite to the one side with respect to the two resistor chip electrodes, a resistor chip electrode connected to the connection point of the first resistor element and the second resistor element that outputs the divided voltage of the series resistor row and a resistor chip electrode connected to one end of the fourth resistor element are arranged on one side of the first chip side formed on the rectangular second chip and connected to the non-inverting input terminal of the operational amplifier First Connected to the operational amplifier chip electrode, and among the operational amplifier chip electrodes arranged on one side of the first chip side, a resistor chip electrode connected to the other end of the third resistor element and a resistor chip electrode connected to one end of the fifth resistor element are connected to the inverting input terminal of the operational amplifier Second Connected to the lead terminal of the second lead row is a resistor chip electrode connected to the other end of the series resistor row to which the reference voltage is connected, and connected to the lead terminal of the second lead row are a resistor chip electrode connected to the other end of the fourth resistor element connected to the ground potential and a resistor chip electrode connected to the other end of the fifth resistor element, and among the operational amplifier chip electrodes arranged on one side of the first chip side formed on the second chip, a resistor chip electrode connected to the output terminal of the operational amplifier Third Operational amplifier chip electrode and the SecondConnect resistance chip electrodes, each connected to both ends of the sixth resistance element, to the operational amplifier chip electrodes, and the First and second The operational amplifier chip electrodes other than the operational amplifier chip electrodes are connected to the lead terminals of the second lead row, and the voltage applied to the lead terminals of the first lead row is reduced by the resistance element formed on the first chip, and is output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip, and the output signal processed by the second chip is output from the lead terminals of the second lead row. The two lead terminals of the first lead row are sized to withstand the voltage applied to the lead terminals Separation and are arranged. At least the sealing resin is filled between the two lead terminals of the first lead row.

[0012] The invention according to claim 2 of the present application is the semiconductor device according to claim 1, characterized in that auxiliary wiring is arranged on the surface of the first chip on the side of the second chip, and the output terminal of the operational amplifier and the lead terminal of the second lead row are connected via the auxiliary wiring.

[0013] The invention according to claim 3 of the present application is the semiconductor device according to any one of claims 1 or 2, characterized in that any lead terminal of the second lead row and the resistance chip electrode or the operational amplifier chip electrode are connected via a relay chip mounted on the die pad.

[0014] The invention according to claim 4 of the present application is the semiconductor device according to any one of claims 1 or 2, characterized in that any lead terminal of the second lead row and the resistance chip electrode or the operational amplifier chip electrode are connected via a relay chip provided with an ESD protection element mounted on the die pad.

Effect of the Invention

[0015] The semiconductor device of the present invention can perform voltage monitoring or voltage measurement under conditions where a high voltage is applied, and can widen the range of the output voltage.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0017] The semiconductor device according to the present invention is a semiconductor device capable of applying a high voltage of about 1000V. Therefore, in the present invention, it has a multi-chip structure divided into a first chip that steps down (reduces the voltage) the directly applied high voltage signal, and a second chip that processes the signal stepped down (reduced in voltage) via the first chip. In particular, in the present invention, in order to widen the output voltage range of the operational amplifier formed on the second chip, a resistor element is arranged on the first chip and connected to the operational amplifier and also connected to a predetermined potential. Hereinafter, embodiments of the present invention will be described in detail.

Examples

[0018] Regarding the embodiments of the present invention, a voltage detection circuit for detecting a high voltage exceeding 1000V will be taken as an example for explanation. FIG. 1 is an explanatory diagram of the semiconductor device of the present invention and is a block diagram of the voltage detection circuit 200A.

[0019] As shown in FIG. 1, the resistor elements 2a and 2b (voltage dividing resistor series) connected in series are elements that divide the high voltage on the negative side of the battery. Terminal B1 is connected to the negative electrode of the battery, and the other end is connected to the reference voltage (VREF). The connection point of the resistor element 2a and the resistor element 2b is connected to the non-inverting input terminal of the operational amplifier 1. Here, since the first chip 10 on which the resistor element is formed and the second chip 20 on which the operational amplifier is formed are each composed of a separate chip, the connection point of the resistor elements 2a and 2b and the non-inverting input terminal of the operational amplifier 1a are connected by a wire 3.

[0020] On the other hand, the resistor element 2c is an element for reducing the high voltage on the positive side of the battery, and the terminal B2 is connected to the positive electrode of the battery. The other end of the resistor element 2c is connected to the inverting input terminal of the operational amplifier 1. The resistor element 2c and the inverting input terminal of the operational amplifier 1 are connected by a wire 3.

[0021] The resistor element 2f is a feedback resistor for determining the amplification gain of the operational amplifier 1. One end of the resistor element 2f is connected to the inverting input terminal of the operational amplifier 1, and the other end is connected to the output terminal of the operational amplifier 1 by a wire 3, respectively. The output terminal OUT of the operational amplifier 1 outputs an output signal obtained by reducing the differential voltage between the positive and negative electrodes of the battery connected between the terminal B1 and the terminal B2. This terminal OUT is connected to a control circuit (not shown), and a control signal for controlling the operations of the boost converter 101 and the inverter circuit 103 shown in FIG. 5 is output from the control circuit to control the driving of the motor M.

[0022] The circuit configuration described above is almost the same as the configuration of the voltage detection circuit 200 shown in FIG. 6. By the way, in the voltage detection circuit shown in FIG. 6, as will be described later, the potential VX of the node VX connected to the non-inverting input terminal of the operational amplifier 201 can be expressed as follows. Here, in the voltage detection circuit 200 shown in FIG. 6, assuming that the input voltage of the terminal B1 is VN, the resistance value of the resistor element 202a is 36 MΩ, and the resistance value of the resistor element 202b is 100 kΩ, the node VX is

Equation

[0023] That is, in the voltage detection circuit 200 shown in FIG. 6, due to the virtual short circuit of the operational amplifier 201, the potentials of the non-inverting input terminal and the inverting input terminal become VREF. Therefore, when the positive power supply voltage V+ of the operational amplifier 201 approaches 5V and the reference voltage VREF approaches 5V, no current is supplied from the bias current source of the operational amplifier 201 to the input differential pair, and the operational amplifier 201 cannot operate normally and stops operating. Therefore, when the reference voltage VREF is applied in the range of 0 to 5V, the output voltage VOUT becomes about 0 to 4.4V, and the output voltage range becomes narrow.

[0024] Therefore, in this embodiment, as shown in FIG. 1, one end of the resistance element 2d is connected to the non-inverting input terminal of the operational amplifier 1. Also, in order to match the impedances between the non-inverting input terminal of the operational amplifier 1 to which the resistance element 2d is connected and the inverting input terminal of the operational amplifier 1, one end of the resistance element 2e is connected to the inverting input terminal. The other ends of the resistance element 2d and the resistance element 2e are connected to the ground potential GND.

[0025] In the voltage detection circuit 200A connected in this way, the potential of the node VY connected to the non-inverting input terminal of the operational amplifier 1 becomes the potential divided by the resistance element 2b and the resistance element 2e.

[0026] In the voltage detection circuit 200A shown in FIG. 1, assuming that the input voltage of the lead terminal B1 is VN, the resistance value of the resistance element 2a is 36 MΩ, and the resistance values of the resistance element 2b and the resistance element 2d are 100 kΩ, the voltage VY of the node XY is

Equation

[0027] That is, due to the virtual short circuit of the operational amplifier, the potentials of the non-inverting input terminal and the inverting input terminal become VREF / 2. Therefore, even if the positive power supply voltage V+ of the operational amplifier 1 without the input full-swing function is 5V and the reference voltage VREF is 5V, current is supplied from the bias current source of the operational amplifier 1 without the input full-swing function to the input differential pair, and the operational amplifier 1 will operate normally. That is, when the reference voltage VREF is applied in the range of 0 to 5V, the output voltage VOUT can follow 0 to 5V, and the output voltage range will not become narrow.

[0028] FIG. 2 is an explanatory diagram of the semiconductor device of this embodiment. In order to form the voltage detection circuit 200A described in FIG. 1 using the first chip 10 composed of resistance elements and the second chip 20 composed of an operational amplifier, it schematically shows the connection state when mounted on a lead frame.

[0029] As shown in FIG. 2, the first chip 10 on which resistance elements are formed and the second chip 20 on which an operational amplifier is formed are mounted on the die pad 4. This lead frame has two lead terminals L1 and L2 (corresponding to the first lead row) on the left side of the drawing, and seven lead terminals L4 to L10 and the suspension leads L3 and L11 of the die pad 4 (corresponding to the second lead row) on the right side of the drawing.

[0030] The lead terminal L1 is connected to the node b1 that is connected to the positive electrode side of the battery, and the lead terminal L2 is connected to the node b2 that is connected to the negative electrode side of the battery. The series circuit of the resistance element 2a and the resistance element 2b has one end connected to the lead terminal L1 and the other end connected to the lead terminal L10. The lead terminal L10 is connected to a predetermined reference potential VREF. The connection point of the resistance element 2a and the resistance element 2b is connected to the non-inverting input terminal of the operational amplifier 1 formed on the second chip 20 using the wire 3. Similarly, one end of the resistance element 2c is connected to the lead terminal L2 and the other end is connected to the inverting input terminal of the operational amplifier 1.

[0031] The output terminal of the operational amplifier 1 formed on the second chip 20 is connected by a wire 3 to one end of a resistor element 2f formed on the first chip 10. The other end of this resistor element 2f is connected to the other end of the resistor element 2c and is connected to the inverting input terminal of the operational amplifier 1 formed on the second chip using the wire 3, whereby the resistor element 2f serves as the feedback resistor of the operational amplifier 1.

[0032] Furthermore, the resistor element 2b and the resistor element 2d are connected in series, and the connection point of the resistor element 2b and the resistor element 2d is connected to the non-inverting input terminal of the operational amplifier 1 formed on the second chip 20 using the wire 3. The other end of the resistor element 2d is connected to the lead terminal L9. Also, the resistor element 2c and the resistor element 2e are connected in series, and the connection point of the resistor element 2c and the resistor element 2e is connected to the inverting input terminal of the operational amplifier 1 formed on the second chip 20 using the wire 3. The other end of the resistor element 2e is connected to the lead terminal L9. The ground potential is connected to the lead terminal L9. Note that FIG. 2 shows an example in which the resistor elements 2d and 2e and the lead terminal L9 are connected via a relay chip 30 on which an auxiliary wiring 5 is formed. Of course, it is also possible to connect directly without using the relay chip 30, but when the connection to the lead terminal L10 connected to the reference potential VREF and the connection to the lead terminal L9 connected to the ground potential GND are close to each other, it is preferable to pass through the relay chip 30 to form the wire 3 short and prevent mutual contact.

[0033] On the second chip 20, a power supply terminal of the operational amplifier 1 is formed. The positive power supply terminal V+ is connected to the lead terminal L5, and the negative power supply terminal V- is connected to the lead terminal L9 via the relay chip 30. A positive voltage V+ is connected to the lead terminal L5, and the ground potential GND is connected to the lead terminal L9, and a power supply voltage is supplied from each terminal.

[0034] Although the output terminal of the operational amplifier 1 can be directly connected to L4 which serves as the output terminal by wire 3, in order to avoid contact between the power supply terminal V+ of the operational amplifier 1 and wire 3 connecting the lead terminal L5, it can be connected to the lead terminal L4 by wire 3 via the auxiliary wiring 5 separately formed on the first chip 10. The connection between the auxiliary wiring 5 and the lead terminal L4 may be through the relay chip 30.

[0035] Furthermore, in order to ensure a predetermined creepage distance, the lead terminals L1 and L2 to which a higher voltage is applied are arranged at a predetermined distance apart according to the voltage applied to each lead terminal. In this embodiment, since the voltage applied to the first lead row is greater than the voltage applied to the second lead row, the interval between the lead terminals L1 and L2 in the first lead row is set wider than the interval between the lead terminals in the second lead row.

[0036] Also, the lead terminal L1 is arranged not only to maintain a creepage distance from the lead terminal L2 but also at a position separated by a predetermined dimension from the other lead terminals L4 to L10. Similarly, the lead terminal L2 is arranged at a position separated by a predetermined dimension from the other lead terminals L4 to L10. Similarly, in order to maintain the creepage distance, the suspension leads L3 and L11 of the die pad 5 are also arranged on the right side of the drawing (the second lead row side) as shown in FIG. 2.

[0037] The first chip 10 etc. mounted on the die pad 4 are encapsulated with a sealing resin. In order to prevent discharge between the lead terminals L1 and L2 exposed to the outside from the resin-encapsulated semiconductor device, a resin layer 6 corresponding to the thickness of the lead terminals is filled between the lead terminals. The formation of this resin layer 6 is performed simultaneously with the resin encapsulation of the semiconductor device body, and thus shows the case where the resin layer 6 is also formed between the lead terminals on the second lead row side as shown in FIG. 2.

[0038] When a higher voltage is applied, the die pad 4 may be encapsulated with resin so as not to be exposed from the semiconductor device body.

[0039] The semiconductor device shown in FIG. 2 may be used to realize a structure without using the auxiliary wiring 5, although the lead terminals L6 to L8 are not connected. Of course, it is also possible to use a semiconductor device excluding these unconnected lead terminals.

[0040] The relationship between the input voltage and the output voltage of the semiconductor device of this embodiment is shown in FIG. 3. The example shown in FIG. 3 shows the simulation results of the voltage output from the output terminal (lead terminal L4) of the operational amplifier 1 when a predetermined voltage is input between nodes B1 and B2 (between lead terminals L1 and L2) when 4V is input as the reference voltage VREF (thin line) and when 5V is input (thick line). The resistance values of the resistance elements 2a and 2c are 36 MΩ, and the resistance values of the resistance elements 2b, 2d, 2e, and 2f are 116 kΩ.

[0041] As shown in FIG. 3, it can be seen that even when the positive power supply voltage of the operational amplifier is 5V and the reference voltage VREF is 5V, the output voltage becomes 5V. Thus, it was confirmed that in the present invention, it is possible to widen the output voltage range without increasing the positive power supply voltage.

[0042] Therefore, according to the present invention, it is preferable that the output voltage range can be widened without preparing power supplies having different voltage values for the reference voltage and the reference voltage of the operational amplifier.

Embodiment

[0043] Next, a second embodiment of the semiconductor device of the present invention will be described. FIG. 4 is an explanatory diagram of the second embodiment of the present invention. The connection method between the semiconductor device of the first embodiment described in FIG. 2 and the lead terminals of the first chip 10 and the second lead row is different. For example, the first chip 10 and the lead terminal L4 of the second lead row are connected via a relay chip 30 provided with the auxiliary wiring 5.

[0044] In addition, in order to protect the internal circuit of the semiconductor device from surge voltages such as static electricity, the relay chip 30 is provided with an ESD protection element 7. It is easy to form an ESD protection element simultaneously with the formation of the operational amplifier 1 on the second chip 20. However, since a high voltage is applied to the first chip 10, a thick insulating film is formed on the surface, making it difficult to form an ESD protection element. Therefore, the ESD protection element 7 is arranged on the relay chip 30. Specifically, in a general semiconductor device, the oxide film formed on the surface is about 0.7 μm, whereas in the semiconductor device of the present invention to which a high voltage exceeding 1000 V is applied, it is necessary to form an oxide film with a thickness of 5 μm or more. Therefore, if an ESD protection element is formed on the semiconductor substrate under the oxide film, it is necessary to remove the thick oxide film to expose the ESD protection element.

[0045] Therefore, the ESD protection element 7 is formed on the relay chip 30. Such a relay chip 30 can be formed by the manufacturing process of a general semiconductor device. Therefore, the oxide film formed on its surface does not need to be thick, which is suitable for forming the ESD protection element 7. In the semiconductor device having the structure shown in FIG. 4, even when a surge voltage is applied to the lead terminal L10 of the second lead row, the ESD protection element 7 can prevent the destruction of the resistance element of the first chip 10.

[0046] Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the resistance values of the resistance element 2b and the resistance element 2d do not necessarily have to match, and they may be set within the range where the operational amplifier 1 operates normally.

Explanation of Reference Numerals

[0047] 1: Operational amplifier, 2a - 2f: Resistance elements, 3: Wire, 4: Die pad, 5: Auxiliary wiring, 6: Resin layer, 7: ESD protection element, 10: First chip, 20: Second chip, 30: Relay chip, 100: Motor drive device, 101: Boost converter, 102: Smoothing capacitor, 103: Inverter circuit, 200: Voltage detection circuit

Claims

1. In a semiconductor device in which a first chip having a function of reducing an input voltage and a second chip having a function of signal - processing an output signal of the first chip are mounted on a die pad, wire - connected between each chip electrode and between each chip electrode and a lead terminal for external extraction, and sealed with a sealing resin, the lead terminals are composed of a plurality of lead terminals, and constitute a first lead row and a second lead row which are arranged opposite to each other with the die pad interposed therebetween; the first chip has a resistor element as a main component and includes first to sixth resistor elements; the second chip has an operational amplifier as a main component; the lead terminals of the first lead row are composed of two lead terminals. One lead terminal of the first lead row is connected to one of two resistor chip electrodes formed on one side of the first lead row side on the rectangular first chip, which is a resistor chip electrode connected to one end of a series resistor column of the first resistor element and the second resistor element. The other lead terminal of the first lead row is connected to the other resistor chip electrode of the two resistor chip electrodes, which is a resistor chip electrode connected to one end of the third resistor element. Among the other resistor chip electrodes arranged on the other side opposite to the one side from the two resistor chip electrodes, the resistor chip electrode connected to the connection point of the first resistor element and the second resistor element that outputs the divided voltage of the series resistor column and the resistor chip electrode connected to one end of the fourth resistor element are connected to a first operational - amplifier chip electrode arranged on one side of the first - chip side formed on the rectangular second chip, which is connected to the non - inverting input terminal of the operational amplifier. The resistor chip electrode connected to the other end of the third resistor element and the resistor chip electrode connected to one end of the fifth resistor element are connected to a second operational - amplifier chip electrode arranged on one side of the first - chip side, which is connected to the inverting input terminal of the operational amplifier. The resistor chip electrode connected to the other end of the series resistor column to which the reference voltage is connected is connected to the lead terminal of the second lead row. The resistor chip electrode connected to the other end of the fourth resistor element connected to the ground potential and the resistor chip electrode connected to the other end of the fifth resistor element are connected to the lead terminal of the second lead row. Of the operational amplifier chip electrodes arranged on one side on the first chip side formed on the second chip, resistance chip electrodes connected to both ends of the sixth resistor element are respectively connected between the third operational amplifier chip electrode connected to the output terminal of the operational amplifier and the second operational amplifier chip electrode, and the operational amplifier chip electrodes other than the first and second operational amplifier chip electrodes are connected to the lead terminals of the second lead row. The voltage applied to the lead terminals of the first lead row is stepped down by a resistor element formed on the first chip and output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip, and the output signal processed by the second chip is output from the lead terminals of the second lead row. The two lead terminals of the first lead row are arranged apart from each other by a dimension that can withstand the voltage applied to the lead terminals. A semiconductor device characterized in that the sealing resin is filled at least between two lead terminals of the first lead row.

2. In the semiconductor device according to claim 1, Auxiliary wiring is arranged on the surface on the second chip side of the first chip. A semiconductor device characterized in that the output terminal of the operational amplifier and the lead terminal of the second lead row are connected via the auxiliary wiring.

3. In the semiconductor device according to any one of claims 1 and 2, A semiconductor device characterized in that any lead terminal of the second lead row and the resistance chip electrode or the operational amplifier chip electrode are connected via a relay chip mounted on the die pad.

4. In the semiconductor device according to any one of claims 1 and 2, A semiconductor device characterized in that any lead terminal of the second lead row and the resistance chip electrode or the operational amplifier chip electrode are connected via a relay chip provided with an ESD protection element mounted on the die pad.

Images