Non-volatile memory

Abstract

To provide a nonvolatile memory capable of appropriately recording temperature in writing.SOLUTION: According to an embodiment, a control circuit of a nonvolatile memory executes a first program operation and executes a second program operation after the first program operation. The first program operation is an operation for setting a threshold value voltage for each of a plurality of second memory cells to a first section corresponding to write data among a plurality of first sections and setting a threshold value voltage for each of a plurality of third memory cells to a second section among the plurality of first sections. The second program operation is an operation for setting a threshold value voltage for each of the plurality of second memory cells to a third section corresponding to the write data among a plurality of third sections and setting a threshold value voltage for each of the plurality of third memory cells to a fourth section corresponding to temperature information among two fourth sections from the plurality of third sections.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] This embodiment relates to a non-volatile memory.

Background Art

[0002] The operating characteristics of non-volatile memories such as NAND flash memories may vary depending on the operating temperature. Also, recording the temperature during writing in a non-volatile memory can be used for failure analysis. Therefore, it is desirable to appropriately record the temperature during writing in a non-volatile memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a non-volatile memory that can appropriately record the temperature during writing.

Means for Solving the Problems

[0005] According to one embodiment, the non-volatile memory includes a first plurality of memory cells, a temperature sensor, an interface, and a control circuit. Gates of each of the first plurality of memory cells are connected to word lines. The interface is configured to receive write data. The control circuit is configured to execute a first program operation and, after the first program operation, execute a second program operation. In the first program operation, the control circuit sets the threshold voltage of each of a second plurality of memory cells among the first plurality of memory cells to a first section corresponding to the write data among a plurality of first sections by applying a programming voltage to the word lines, and sets the threshold voltage of each of a third plurality of memory cells different from the second plurality of memory cells among the first plurality of memory cells to a second section among the plurality of first sections. In the second program operation, the control circuit sets the threshold voltage of each of the second plurality of memory cells to a third section corresponding to the write data among a plurality of third sections provided in a range wider than the plurality of first sections by applying a further programming voltage to the word lines, and sets the threshold voltage of each of the third plurality of memory cells to a fourth section corresponding to first temperature information detected by the temperature sensor among two fourth sections set on the same or higher voltage side as the second section among the plurality of third sections.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] The non-volatile memory according to the embodiment stores data non-volatilely, but has a characteristic that the reliability of the storage depends on the operating temperature. For example, in a non-volatile memory, the detection voltage Vsense that minimizes the number of error bits varies depending on the temperature during the write operation and the temperature during the read operation.

[0008] Here, the technology compared with the embodiment will be described. The technology compared with the embodiment is referred to as a comparative example. According to the comparative example, in a non-volatile memory, temperature correction is not performed, or the detection voltage Vsense is corrected using the temperature detected by a temperature sensor during read.

[0009] When using the temperature during read, there may be cases where the detection voltage Vsense cannot be properly corrected. For example, when the temperature during data write and the temperature during read are significantly different, that is, when there is a temperature crossover, the detection voltage Vsense obtained based on the temperature during read deviates from the appropriate detection voltage Vsense, that is, the detection voltage Vsense that minimizes the number of error bits. In such cases, the number of error bits in the memory system of the comparative example may increase.

[0010] In the comparative example, the temperature information during write is managed and recorded by a memory controller provided outside the non-volatile memory. For example, the non-volatile memory detects the temperature in response to a temperature status acquisition command from the memory controller. The non-volatile memory returns the detected temperature information to the memory controller. The temperature information is written as metadata to the memory cell array of the non-volatile memory in response to a command from the memory controller. In this case, there is a time lag between the time when the temperature is detected and the time when the data is written. Therefore, even if correction is performed using the temperature detected during read and the temperature information in the metadata, it is difficult to accurately correct the temperature crossover.

[0011] In addition, the temperature managed by the memory controller is information represented in units larger than the unit of data writing (for example, block units). Therefore, when the memory controller refers to the temperature of the metadata for each unit of data writing, the temperature may deviate significantly from the temperature at the time of writing. From this perspective as well, even if temperature intersection correction is performed using the temperature detected at the time of read and the temperature information in the metadata, it is difficult to accurately perform the temperature intersection correction.

[0012] Also, recording the usage temperature of the non-volatile memory is important as information for failure analysis. In the comparative example, temperature information representing units larger than the unit of data writing is recorded. Therefore, during failure analysis, when the memory controller refers to the temperature information for each unit of data writing, the exact temperature at the time of writing cannot be known.

[0013] Therefore, in the present embodiment, in the non-volatile memory, when writing data to the memory cell array, the control circuit writes the temperature information detected by the built-in temperature sensor to the redundant storage area in the memory cell array. As a result, the temperature information at the time of data writing is properly recorded and managed.

[0014] Hereinafter, the non-volatile memory according to the embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited by these embodiments.

[0015] (First Embodiment) FIG. 1 is a schematic diagram showing an example of the configuration of a memory system 1 including a memory chip 10 according to the first embodiment.

[0016] The memory system 1 is communicably connected to the host 100 and functions as an external storage device for the host 100. The memory system 1 may be a memory card or the like, or may be an SSD (Solid State Drive) or the like. The host 100 may be, for example, an information processing device such as a personal computer, a server, a storage box, etc., or a mobile terminal such as a mobile phone, an imaging device, a tablet computer, or a smartphone, or a game device, or an in-vehicle terminal such as a car navigation system.

[0017] The memory system 1 includes a memory controller 2 and a memory bank 3. The memory controller 2 includes a host interface 21, a memory interface 22, a control unit 23, and an ECC (Error Checking and Correction) unit 24. The memory bank 3 includes a plurality of memory chips 10-1 to 10-n. Each of the plurality of memory chips 10-1 to 10-n (n is an arbitrary integer of 2 or more) is referred to as a memory chip 10. Note that the memory chip 10 is an example of the non-volatile memory of the embodiment.

[0018] The memory controller 2 is a semiconductor integrated circuit configured as, for example, a SoC (System-on-a-Chip). Some or all of the operations of each component of the memory controller 2 described below may be realized by the CPU (Central Processing Unit) executing firmware, or may be realized by hardware.

[0019] In the memory controller 2, the memory interface 22 is connected to the memory bank 3 via the memory bus 5, and the host interface 21 is connected to the host 100 via the host bus 6. The control unit 23 controls the write process to the memory bank 3 according to the host write command received from the host 100 via the host interface 21. Also, the control unit 23 controls the read process from the memory bank 3 according to the host read command received from the host 100 via the host interface 21. As the standard compliant with the host bus 6, for example, any standard such as SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe (Registered Trademark) (Peripheral Component Interconnect express) (including NVM express (Registered Trademark)) can be adopted.

[0020] The memory bus 5 transmits and receives signals according to the memory interface 22. When the memory interface 22 is a so-called NAND interface, specific examples of this signal may include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal I / O, and the like.

[0021] The signal CEn is a signal for enabling the memory chip 10. The signal CLE is a signal for notifying the memory chip 10 that the input signal I / O to the memory chip 10 is a command. The signal ALE is a signal for notifying the memory chip 10 that the input signal I / O to the memory chip 10 is an address. The signal WEn is a signal for causing the memory chip 10 to capture the input signal I / O. The signal REn is a signal for reading the output signal I / O from the memory chip 10. The Ready-Busy signal RBn is a signal indicating whether the memory chip 10 is in a ready state (a state in which it can receive a command from the memory controller 2) or a busy state (a state in which it cannot receive a command from the memory controller 2). The input / output signal I / O is, for example, an 8-bit signal. The input / output signal I / O is the entity of data transmitted and received between the memory chip 10 and the memory controller 2, and is a command, an address, write data (data to be written), read data (read data), and the like.

[0022] The ECC unit 24 performs encoding and decoding of data for error detection and error correction in the read data. Specifically, the ECC unit 24 encodes the data (write data) written to the memory bank 3. Also, the ECC unit 24 decodes the data (read data) read from the memory bank 3. The ECC unit 24 performs error detection and error correction in the read data by decoding. If the error correction fails, the ECC unit 24 notifies the control unit 23 of the failure of the error correction. Any algorithm using an RS (Reed-Solomon) code, a BCH (Bose-Chaudhuri-Hocquenghem) code, a low-density parity-check (LDPC) code, or the like can be applied to the encoding and decoding algorithms by the ECC unit 24.

[0023] For example, during the write process, under the control of the control unit 23, the ECC unit 24 receives user data to be written to the memory bank 3 via a write command, generates parity based on the user data, attaches the parity to the user data to obtain write data. In the memory bank 3, the write data including parity is written as encoded data.

[0024] During the read process, under the control of the control unit 23, the ECC unit 24 receives read data read from the memory bank 3 via a read command, and extracts parity from the read data. The ECC unit 24 generates a syndrome based on the parity, and determines whether there is an error bit in the user data. When the user data contains an error bit, the ECC unit 24 identifies the position of the error bit. The number of correctable error bits of the ECC unit 24 is determined by, for example, the number of bits of the parity. When the number of error bits contained in the user data is equal to or less than the number of correctable error bits, the ECC unit 24 corrects the error bit and notifies the control unit 23 of the success of the correction. When the number of error bits contained in the user data exceeds the number of correctable error bits, the ECC unit 24 notifies the control unit 23 of the failure of the correction as uncorrectable.

[0025] The memory chip 10 constituting the memory bank 3 is a memory that stores data non-volatilely, for example, a NAND type flash memory (hereinafter also referred to as a NAND device). In the following description, the case where a NAND device is used as the memory chip 10 is exemplified, but it is also possible to use a storage medium other than a NAND device such as a three-dimensional structure flash memory, ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory) for the memory bank 3.

[0026] Each memory chip 10 has a memory cell array 11, a temperature sensor 12, an I / O interface 13, a data buffer 14, and a control circuit 15. The control circuit 15 has a sequencer 16, a row module 17, and a column module 18.

[0027] The row module 17 has a row decoder and a driver circuit. The row decoder selects a block to be accessed and further selects a row in the selected block. The driver circuit supplies a voltage to the selected block via the row decoder.

[0028] The column module 18 includes a sense amplifier and a data latch composed of a plurality of latch circuits. In the program operation, the column module 18 writes the write data supplied to the data latch from the memory controller 2 via the I / O interface 13 and the data buffer 14 to the memory cell array 11. Also, in the read operation, the column module 18 senses the data written in the memory cell array 11 and performs necessary operations. Then, the column module 18 outputs the obtained read data to the memory controller 2 via the data latch, the data buffer 14, and the I / O interface 13.

[0029] Note that in this specification, the program operation is a series of operations for writing data to the memory cell array 11 in the memory chip 10. The read operation is a series of operations for reading data from the memory cell array 11 in the memory chip 10. The erase operation is an operation for erasing data in the memory cell array 11 in the memory chip 10.

[0030] The temperature sensor 12 is arranged around the memory cell array 11 in the memory chip 10, detects the temperature around the memory cell array 11, and generates a signal TEMP indicating the detected temperature.

[0031] The memory cell array 11 has a plurality of memory cell transistors MT. Each memory cell transistor MT is associated with a row and a column. The memory cell array 11 stores data instructed by a write command from the memory controller 2.

[0032] FIG. 2 is a schematic diagram showing an example of the configuration of the memory cell array 11 of the first embodiment.

[0033] The memory cell array 11 includes a plurality of blocks 30. Data written to one block 30 is erased in a batch. Each block 30 includes a plurality of memory cell groups MCG. For each block, program operations and read operations are executed in units of the memory cell group MCG.

[0034] FIG. 3 is a schematic diagram showing an example of the circuit configuration of the block 30 of the first embodiment. Each block has a common circuit configuration.

[0035] The block 30 has a plurality of string units SU0 to SU3. The plurality of string units SU0 to SU3 correspond to a plurality of selection gate lines SGDL0 to SGDL3 and share a selection gate line SGSL. Each of the string units SU0 to SU3 functions as a driving unit in the block 30. Each of the string units SU0 to SU3 can be driven by its corresponding selection gate line and the selection gate line SGSL among the plurality of selection gate lines SGDL0 to SGDL3. Also, each of the string units SU0 to SU3 includes a plurality of memory strings MST.

[0036] Each memory string MST includes, for example, 64 memory cell transistors MT (MT0 to MT63) and selection transistors SDT and SST. The memory cell transistor MT has a control gate and a charge storage film, and holds data non-volatilely. And the 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of the selection transistor SDT and the drain of the selection transistor SST. Note that the number of memory cell transistors MT in the memory string MST is not limited to 64.

[0037] The plurality of word lines WL0 to WL63 commonly connect the control gates of the memory cell transistors MT among the respective memory strings MST in each string unit SU in the block 30. That is, the control gates of the memory cell transistors MT in the same row in each string unit SU in the block 30 are connected to the same word line WL. That is, the string unit SU of the block 30 includes a plurality of memory cell groups MCG corresponding to the plurality of word lines WL, and each memory cell group MCG includes (p + 1) memory cell transistors MT connected to the same word line WL.

[0038] A program operation and a read operation are performed for each memory cell group MCG. And the data obtained by collecting 1-bit data written to the memory cell MT for each memory cell group MCG is treated as a page.

[0039] Hereinafter, the memory cell transistor MT is simply referred to as a memory cell MT.

[0040] In the program operation, the threshold voltage of the memory cell MT is set in a section corresponding to the data. More specifically, the range in which the threshold voltage of the memory cell MT can take is 2 to which different data of N bits (where N is an integer of 1 or more) are associated. NIt is divided into N a number of sections, and in the program operation, by injecting charge into the charge storage layer of the memory cell MT, the threshold voltage of the memory cell MT becomes 2

[0041] In the read operation, one or more voltages corresponding to the boundaries of adjacent sections are sequentially applied as the detection voltage Vsense, thereby identifying the section including the threshold voltage of the memory cell MT. Then, the data corresponding to the identified section is acquired as the data stored in the memory cell MT.

[0042] The memory cell MT can store data with one or more bits. The method of storing 1-bit data in the memory cell MT is called SLC (Single Level Cell). The method of storing 2-bit data in the memory cell MT is called MLC (Multi Level Cell). The method of storing 3-bit data in the memory cell MT is called TLC (Triple Level Cell). The method of storing 4-bit data in the memory cell MT is called QLC (Quad-Level Cell). The method of storing 5-bit data in the memory cell MT is called PLC (Penta-Level Cell).

[0043] In the embodiment, any method can be applied as long as the method stores data with 2 or more bits in the memory cell MT. Hereinafter, as an example, the case where the TLC method is applied will be described.

[0044] FIG. 4 is a diagram showing an example of a plurality of distributions of the threshold voltage of the memory cell MT formed when the write operation is executed in the TLC mode in the memory chip 10 of the first embodiment.

[0045] In the case of TLC, eight sections R0 to R7 associated with different 3-bit data are provided.

[0046] For example, on the lowest voltage side, an interval R0 up to voltage Va1 is provided. On the higher voltage side than interval R0, there are provided an interval R1 from voltage Va1 to voltage Vc2, an interval R2 from voltage Va2 to voltage Va3, an interval R3 from voltage Va3 to voltage Vc4, an interval R4 from voltage Va4 to voltage Va5, an interval R5 from voltage Va5 to voltage Vc6, an interval R6 from voltage Va6 to voltage Va7, and an interval R7 starting from voltage Va7.

[0047] In the program operation, the threshold voltage of each memory cell MT is set within the interval corresponding to the data. As a result, the threshold voltages of a plurality of memory cells MT form a lobe-shaped distribution for each interval. The interval RX may be denoted as state SX. X is an integer of 2 or more, and in the example shown in FIG. 4, it is an integer from 0 to 7.

[0048] In the erase operation, the threshold voltage of the memory cell MT is set to a state lower than voltage Vc1, that is, S0. That is, state S0 is also regarded as the state where the data has been erased. By the program operation executed after the erase operation, the threshold voltage of the memory cell MT is set to any one of states S0 to S7. Note that setting the threshold voltage of the memory cell MT to state S0 is synonymous with the memory cell MT being maintained in state S0 without the threshold voltage of the memory cell MT being increased.

[0049] In the read operation, by setting the voltage corresponding to the boundary of adjacent intervals R as the detection voltage Vsense, it is determined which interval RX (in other words, state SX) the threshold voltage of the memory cell MT is included in. For example, the voltages Va1, Va2, Va3, Va4, Va5, Va6, and Va7 shown in FIG. 4 are used as the detection voltage Vsense.

[0050] According to the TLC method, 3-bit data is stored in each memory cell MT. Among the 3 bits, the LSB (Least Significant Bit) is the lower bit, the MSB (Most Significant Bit) is the upper bit, and the bit between the LSB and the MSB is called the middle bit. Also, the data obtained by collecting the data of the lower bits among the 3-bit data for the number of memory cell groups MCG is called the lower page. The data obtained by collecting the data of the upper bits among the 3-bit data for the number of memory cell groups MCG is called the upper page. The data obtained by collecting the data of the middle bits among the 3-bit data for the number of memory cell groups MCG is called the middle page.

[0051] As described above, data is associated with each section RX (in other words, each state SX) in which the threshold voltage can be set. The correspondence between the section RX and the data is called data coding.

[0052] FIG. 5 is a diagram showing an example of the data coding of the first embodiment. In this specification, when data is denoted as “abc”, “a” indicates the value of the lower bit, “b” indicates the value of the middle bit, and “c” indicates the value of the upper bit.

[0053] According to the example of the data coding shown in FIG. 5, the data “111” is associated with the section R0, the data “011” is associated with the section R1, the data “001” is associated with the section R2, the data “000” is associated with the section R3, the data “010” is associated with the section R4, the data “110” is associated with the section R5, the data “100” is associated with the section R6, and the data “101” is associated with the section R7.

[0054] Note that the above data coding is an example. The data coding can be arbitrarily changed.

[0055] The threshold voltage of the memory cell MT can vary due to various factors including cell - to - cell interference. Therefore, a part on the high - voltage side or a part on the low - voltage side of the lobe - shaped distribution formed in each section RX may protrude into an adjacent section RX.

[0056] When a part of the lobe - shaped distribution formed in a certain section RX protrudes into an adjacent section RX, in a read operation, incorrect data, that is, an error, is read from the memory cells MT included in the part that protrudes into the adjacent section RX of the distribution. The incorrect data is sent to the memory controller 2 and corrected by the ECC unit 24 provided in the memory controller 2.

[0057] However, there is a limit to the number of error bits that can be corrected by the ECC unit 24. Therefore, it is desirable that the threshold voltage of each memory cell MT be set so as not to protrude from the target section RX as much as possible during the program operation.

[0058] In order to make the threshold voltage of each memory cell MT not protrude from the target section R as much as possible, the memory chip 10 is configured to be able to execute a multi - stage program operation. The multi - stage program operation is a program operation that is executed in multiple stages. In the first embodiment, as an example of the multi - stage program operation, the memory chip 10 executes a foggy fine program operation.

[0059] In the foggy fine program operation, data of all bits (for example, 3 bits in the case of the TLC method) are roughly written to the first memory cell MT. That is, the threshold voltage of the first memory cell MT is roughly set according to the data of all bits. Then, data of all bits are roughly written to the second memory cell MT adjacent to the first memory cell MT. In other words, data of all bits are roughly written to the second memory cell MT connected to the word line WL adjacent to the word line WL to which the first memory cell MT is connected. Then, data of all bits are precisely rewritten to the first memory cell MT. That is, for each memory cell MT, a first-stage program operation in which data of all bits are roughly written and a second-stage program operation in which data of all bits are precisely rewritten are executed.

[0060] By the second-stage program operation of the foggy fine program operation, the threshold voltage of each memory cell MT can be precisely set. By using the foggy fine program operation, the amount of change in the threshold voltage of each memory cell can be reduced. Thereby, the cell-to-cell interference received by each memory cell MT from adjacent memory cells MT can be suppressed, and the variation in the threshold voltage due to cell-to-cell interference can be suppressed. That is, it is possible to suppress the threshold voltage of each memory cell MT from exceeding the target section RX due to cell-to-cell interference.

[0061] FIG. 6 is a schematic diagram for explaining the change in the distribution of the threshold voltage by the foggy fine program operation executed by the memory chip 10 of the first embodiment. FIG. 6 shows three graphs showing the change in the distribution of the threshold voltage of the memory cells MT constituting one memory cell group MCG. In each graph, the horizontal axis indicates voltage, and the vertical axis indicates the number of memory cells MT.

[0062] After the erase operation in block 30, the threshold voltages of all memory cells MT are in state S0. In particular, when the program operation has not yet started after the erase operation, a lobe-shaped distribution that spreads widely in a range lower than voltage Vc1 is formed as shown in the uppermost graph of FIG. 6.

[0063] For the memory cell group MCG in the state after the erase operation, the first-stage program operation is executed. The first-stage program operation in the foggy fine program operation is referred to as the foggy program operation.

[0064] In the foggy program operation, the threshold voltage of each memory cell MT is roughly set so as to be as close as possible to the target section RX among the eight sections R0 to R7.

[0065] More specifically, a section R0' that is approximately equal to section R0, a section R1' obtained by shifting section R1 slightly to the lower voltage side, a section R2' obtained by shifting section R2 slightly to the lower voltage side, a section R3' obtained by shifting section R3 slightly to the lower voltage side, a section R4' obtained by shifting section R4 slightly to the lower voltage side, a section R5' obtained by shifting section R5 slightly to the lower voltage side, a section R6' obtained by shifting section R6 slightly to the lower voltage side, and a section R7' obtained by shifting section R7 slightly to the lower voltage side are provided.

[0066] Specifically, in the example shown in FIG. 6, the interval R0' is set as the interval up to the voltage Va1, the interval R1' is set as the interval from the voltage Vb1 (where Vb1 < Va1) to the voltage Vb2 (where Vb2 < Va2), the interval R2' is set as the interval from the voltage Vb2 to the voltage Vb3 (where Vb3 < Va3), the interval R3' is set as the interval from the voltage Vb3 to the voltage Vb4 (where Vb4 < Va4), the interval R4' is set as the interval from the voltage Vb4 to the voltage Vb5 (where Vb5 < Va5), the interval R5' is set as the interval from the voltage Vb5 to the voltage Vb6 (where Vb6 < Va6), the interval R6' is set as the interval from the voltage Vb6 to the voltage Vb7 (where Vb7 < Va7), and the interval R7' is set as the interval from the voltage Vb7. And since the intervals R1' to R7' are set slightly lower in voltage than the intervals R1 to R7, the range R11 where the intervals R1' to R7' are set is narrower than the range R10 where the intervals R1 to R7 are set.

[0067] In the foggy program operation, the threshold voltage of the memory cell MT whose finally set interval is the interval RX is set to the interval RX'. Thus, the threshold voltage of each memory cell MT is set to belong to any one of the intervals R0' to R7'. Note that the interval finally set by the program operation of the second stage (the fine program operation in this example) may be referred to as the final target interval. Also, an interval set in the program operation of the first stage (the foggy program operation in this example), such as the interval RX', may be referred to as an intermediate target interval.

[0068] The threshold voltage of the memory cell MT is increased by applying a pulsed program voltage (also referred to as a program pulse) to the gate of the memory cell MT via the word line WL. In the foggy program operation, the amount of shift of the threshold voltage of the memory cell MT per application of the program pulse is set such that it is larger than the amount of shift of the threshold voltage of the memory cell MT per application of the program pulse in the fine program operation described later. Thus, the peak, pulse width, or both of one program pulse are set. Therefore, in the foggy program operation, it is possible to largely shift the threshold voltage in a short period. However, since the amount of shift of the threshold voltage of the memory cell MT per application of the program pulse is large, the threshold voltage may not fall within the intermediate target range.

[0069] Also, even when the threshold voltage of the specified memory cell MT is set within the intermediate target range by the foggy program operation, the threshold voltage of the specified memory cell MT may vary outside the intermediate target range due to cell - to - cell interference with the memory cells MT adjacent to the specified memory cell MT. Therefore, as shown in the graph in the middle of FIG. 6, after the foggy program operation, each of the eight lobe - shaped distributions corresponding to the intervals R0’ to R7’ may protrude from the boundary of the corresponding interval.

[0070] Hereinafter, the interval RX’ may be denoted as the state SX’.

[0071] For the memory cell MT in which the interval R0 is the final target interval, in the foggy program operation, the threshold voltage is not actually increased. Therefore, the threshold voltage of the memory cell MT in which the interval R0 is the final target interval is maintained in the state S0 in the foggy program operation. That is, in the example shown in FIG. 6, the state S0’ is equal to the state S0.

[0072] After the foggy program operation, the program operation of the second stage is executed. The program operation of the second stage in the foggy fine program operation is referred to as the fine program operation.

[0073] In the fine program operation, the threshold voltage of each memory cell MT is set to the final target interval RX. In the fine program operation, the amplitude, application period, or both of a single program pulse are set so that the amount of change in the threshold voltage per application of the program pulse is smaller than the amount of change in the threshold voltage per application in the foggy program operation.

[0074] In the fine program operation, since the amount of change in the threshold voltage per application of the program pulse is smaller than the amount of change in the threshold voltage per application in the foggy program operation, it is possible to narrow the shape of each distribution. That is, from within the interval RX corresponding to each distribution, precise setting can be performed so that the threshold voltage of the memory cell MT does not protrude as much as possible.

[0075] Also, by performing the foggy program operation before the fine program operation, the threshold voltage of each memory cell MT becomes closer to the final target interval RX than the threshold voltage of the memory cell MT in the state after the erase operation. For this reason, the amount of change in the threshold voltage of each memory cell MT in the fine program operation is suppressed. Therefore, in the fine program operation, cell - to - cell interference can be reduced.

[0076] Also, in the fine program operation, the amount of change in the threshold voltage of the memory cell MT per application of the program pulse is small. For this reason, when changing the threshold voltage of the memory cell MT only by the fine program operation, it takes a relatively long time. However, since the total amount of change in the threshold voltage of each memory cell MT in the fine program operation is suppressed by previously executing the foggy program operation, an increase in the time required for the completion of the fine program operation is suppressed.

[0077] As described above, writing to the memory cell array 11 is performed in units of memory cell groups MCG. In the first embodiment, each time the memory chip 10 writes data to a memory cell group MCG, it writes temperature information TEMP to some of the plurality of memory cells MT included in the memory cell group MCG to be written.

[0078] FIG. 7 is a schematic diagram showing an example of the write position of temperature information TEMP in the memory cell group MCG of the first embodiment.

[0079] The memory cell group MCG constitutes a storage area ARmcg. And some of the plurality of memory cells MT in the memory cell group MCG constitute a redundant area ARred, and the other plurality of memory cells MT constitute a user area ARusr to which the data received from the memory controller 2 is written.

[0080] Block 30 includes a plurality of redundant memory cells MT in case of failure. Each memory cell group MCG in block 30 includes more memory cells MT than the required number of memory cells MT. When a failure is found in any of the memory cells MT assigned to the user area ARusr, the function of the failed memory cell MT is replaced by a redundant memory cell MT. In principle, the memory controller 2 cannot write data to the memory cells MT among the plurality of redundant memory cells MT that do not replace the failed memory cell MT. The redundant area ARred is a storage area constituted by a plurality of memory cells MT among the plurality of redundant memory cells MT that do not replace the failed memory cell MT.

[0081] In the user area ARusr, user data for three pages (i.e., the upper page, the middle page, and the lower page), and ECC parity generated from the user data of each page are written. Here, as an example, it is assumed that the user data of each page has a size of 16 kByte, and the ECC parity generated from the user data of each page has a size of 2 kByte. However, the size of each data is not limited to these values.

[0082] In the redundant area ARred, a plurality of temperature storage areas ARtemp are provided. The temperature information TEMP is multiplexed into a plurality, and one of the plurality of temperature information TEMP is written to each of the plurality of temperature storage areas ARtemp. In this example, it is assumed that four temperature storage areas ARtemp are provided in the redundant area ARred, and the temperature information TEMP is multiplexed into four and written.

[0083] Also, in this example, the temperature information TEMP represents a temperature in the range from minus 127 degrees Celsius to 127 degrees Celsius in 8 bits. Note that the bit length of the temperature information TEMP and the representable temperature range are not limited to this.

[0084] In the foggy fine program operation, it is assumed that the same data is written in the foggy program operation and the fine program operation. In the first embodiment, this premise is observed for writing to the user area ARusr, but this premise is not observed for writing the temperature information TEMP to the redundant area ARred.

[0085] In addition, during the program operation, the memory chip 10 can maintain or increase the threshold voltage of the memory cell MT, but cannot decrease it. That is, after increasing the threshold voltage of the memory cell MT during the foggy program operation, it becomes impossible to set a threshold voltage lower than the increased threshold voltage for the memory cell MT during the fine program operation. Therefore, in the first embodiment, the memory controller 2 does not write the temperature information TEMP during the foggy program operation, but writes the temperature information TEMP during the fine program operation.

[0086] Furthermore, in the first embodiment, the memory chip 10 writes 1-bit information per memory cell MT with respect to the temperature information TEMP. One temperature storage area RAtemp is composed of 8 memory cells MT. That is, one temperature storage area RAtemp can store 8-bit information. One temperature information TEMP is 8 bits. Therefore, 4 temperature information TEMP (32 bits) are held using 4 temperature storage areas RAtemp (a total of 32 memory cells MT). Hereinafter, each 1-bit value of the digits constituting the temperature information TEMP is denoted as a temperature bit value TEMP-b.

[0087] FIG. 8 is a schematic diagram for explaining an example of the transition of the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp of the first embodiment. In this figure, the distribution in which the memory cell MT constituting the temperature storage area ARtemp may be included is hatched. In the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature storage area ARtemp is simply denoted as the memory cell MT.

[0088] During the foggy program operation, the threshold voltage of the memory cell MT is set to the lowest voltage side section R0', that is, the state S0', regardless of the temperature bit value TEMP-b written to the memory cell MT. That is, during the foggy program operation, the increase in the threshold voltage for the memory cell MT is not executed. The threshold voltage of the memory cell MT is maintained in the state S0' (that is, the state S0).

[0089] In the subsequent fine program operation, the threshold voltage of the memory cell MT is set to state S0 or state S1 according to the temperature bit value TEMP-b. In one example, when the temperature bit value TEMP-b is "1", the threshold voltage of the memory cell MT is set to state S0. When the temperature bit value TEMP-b is "0", the threshold voltage of the memory cell MT is set to state S1. Note that the correspondence between the temperature bit value TEMP-b and the two states S0 and S1 can be arbitrarily determined by the designer.

[0090] According to the example of the threshold voltage transition shown in FIG. 8, in the fine program operation, the amount of change in the threshold voltage of the memory cell MT is at most the amount from state S0' (i.e., state S0) to state S1, and is much smaller than the range R10 provided with intervals R0 to R7. Therefore, the inter-cell interference acting on the temperature storage area ARtemp is suppressed.

[0091] Also, since the amount of change in the threshold voltage of the memory cell MT in the fine program operation is sufficiently small, the time required for the memory controller 2 to complete the fine program operation on the memory cell MT can be suppressed.

[0092] As described above, 3-bit data is associated with each of the states S0 to S7. Therefore, for the memory cell MT constituting the temperature storage area ARtemp, in order to set its threshold voltage to state S0 or state S1, actually, instead of the temperature bit value TEMP-b, 3-bit data corresponding to state S0 or state S1 is written to the memory cell MT via the column module 18. Specifically, the sequencer 16 generates 3-bit data corresponding to state S0 or state S1 based on the temperature bit value TEMP-b and the data coding shown in FIG. 5. The column module 18 receives the 3-bit data from the sequencer 16 and writes the received 3-bit data to the memory cell MT constituting the temperature storage area ARtemp.

[0093] FIG. 9 is a diagram for explaining 3-bit data generated during the program operation for the temperature memory area ARtemp of the first embodiment. Also in the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory area ARtemp is simply referred to as the memory cell MT.

[0094] In the foggy program operation, the sequencer 16 generates the data "111" regardless of whether the temperature bit value TEMP-b is "0" or "1", and supplies the data "111" to the column module 18. A "1" is written as the lower bit of the memory cell MT, a "1" is written as the middle bit, and a "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0'(S0) regardless of whether the temperature bit value TEMP-b held in the memory cell MT is "0" or "1".

[0095] In the fine program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "011" and supplies the data "011" to the column module 18. A "0" is written as the lower bit of the memory cell MT, a "1" is written as the middle bit, and a "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S1 corresponding to the temperature bit value TEMP-b of "0". When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "111" and supplies the data "111" to the column module 18. A "1" is written as the lower bit of the memory cell MT, a "1" is written as the middle bit, and a "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0 corresponding to the temperature bit value TEMP-b of "1".

[0096] Subsequently, the operation of the memory system 1 of the first embodiment will be described.

[0097] FIG. 10 is a flowchart showing an example of the program operation of the memory chip 10 of the first embodiment.

[0098] The I / O interface 13 receives data for three pages together with a write command from the memory controller 2 (ST101). The data for three pages received from the memory controller 2 is data for the lower page, the middle page, and the upper page. The data for each page is user data with ECC parity. The control circuit 15 (more specifically, the column module 18 within the control circuit 15) executes a foggy program operation in response to the reception of the data for three pages (ST1).

[0099] In the foggy program operation, the sequencer 16 generates the data "111" to be written to each memory cell MT constituting the temperature storage area ARtemp (ST102). Then, the control circuit 15 writes the data for three pages to the user area ARusr by applying a program pulse one or more times to the word line WL connected to the memory cell group MCG of the write destination. That is, the control circuit 15 writes the data "111" to each memory cell MT constituting the temperature storage area ARtemp (ST103). Thereby, the foggy program operation ends.

[0100] Subsequently, the control circuit 15 executes a fine program operation (ST2).

[0101] In the fine program operation, the sequencer 16 acquires temperature information TEMP from the temperature sensor 12 (ST104). The sequencer 16 generates, for each memory cell MT constituting each temperature storage area ARtemp, the data "011" corresponding to the temperature bit value TEMP-b of "0" or "111" corresponding to the temperature bit value TEMP-b of "1" based on the temperature information TEMP (ST105).

[0102] Then, the control circuit 15 writes data for three pages to the user area ARusr by applying the program pulse to the word line WL connected to the memory cell group MCG at the write destination one or more times. That is, the control circuit 15 writes the data “011” or “111” generated in ST105 to each memory cell MT constituting each temperature storage area ARtemp (ST106). Then, the fine programming operation ends, and the programming operation in the memory chip 10 ends.

[0103] In this way, in the programming operation of writing the user data received from the memory controller 2 to the memory cell group MCG, the memory chip 10 autonomously acquires the temperature information TEMP and writes it to the temperature storage area ARtemp.

[0104] The memory chip 10 can output the temperature information TEMP written in the temperature storage area ARtemp in response to a read command from the memory controller 2.

[0105] When the memory controller 2 causes the memory chip 10 to execute a read operation, it uses a read command composed of a sense command and a data out command. The sense command is a command that instructs to transfer data from the memory cell group MCG at the read destination to the data buffer 14 via the data latch. The data out command is a command that instructs to output some or all of the data stored in the data buffer 14 to the memory controller 2 in response to the sense command. The data out command can be used one or more times after the sense command.

[0106] The data out command includes a column address as information specifying the data to be output among the data in the data buffer 14. When acquiring the temperature information TEMP from the memory chip 10, the memory controller 2 designates the address indicating the column where the temperature storage area ARtemp is provided as the column address.

[0107] In the memory cell MT that constitutes the temperature memory area ARtemp, 3-bit data corresponding to the temperature information bit value TEMP-b is written. Therefore, the memory controller 2 acquires 3-bit data for each memory cell MT that constitutes the temperature memory area ARtemp. That is, the memory controller 2 acquires a data group in which 8 sets of 3-bit data are collected for each temperature memory area ARtemp.

[0108] The memory controller 2 acquires four data groups from the four temperature memory areas ARtemp, and acquires the temperature information TEMP based on the four data groups.

[0109] FIG. 11 is a flowchart showing an example of an operation of acquiring the temperature information TEMP from four data groups by the memory controller 2 of the first embodiment.

[0110] The memory controller 2 converts the data "111" included in the four data groups into "1", which is the temperature information bit value TEMP-b corresponding to the data "111" (ST201). Similarly, the memory controller 2 converts the data "011" included in the four data groups into "0", which is the temperature information bit value TEMP-b corresponding to the data "011" (ST202).

[0111] As described above, the threshold voltage of the memory cell MT can vary due to various factors. And the temperature information TEMP is written to the temperature memory area ARtemp without error correction coding. Therefore, 3-bit data different from the written 3-bit data may be read from each memory cell MT that constitutes the temperature memory area ARtemp.

[0112] For example, in a certain case, the threshold voltage fluctuates from state S0 to state S1 or from state S1 to state S0. When the threshold voltage fluctuates in such a pattern, the four data groups may include data written as data "111" but read as data "011", or data written as data "011" but read as data "111". Data that cannot be correctly obtained due to the fluctuation between state S0 and state S1 is corrected by the majority decision process (ST204) described later.

[0113] Also, in another case, the four data groups may include data that does not correspond to either data "111" or data "011", that is, data corresponding to any of states S2 to S7. Based on the distance between the state before the fluctuation and the state after the fluctuation, the probability of fluctuating from state S1 to states S2 to S7 is higher than the probability of fluctuating from state S0 to states S2 to S7. That is, when the four data groups include data corresponding to any of states S2 to S7, the data is likely to have been data "011" corresponding to state S1 at the time of writing. Therefore, when the four data groups include data corresponding to any of states S2 to S7, the memory controller 2 regards the data as data that has changed from data "011". That is, when the four data groups include data that does not correspond to either data "111" or data "011", the memory controller 2 converts the data to "0", which is the temperature information bit value TEMP-b (ST203).

[0114] By ST201 to ST203, the 3-bit data corresponding to state S0 is converted to "1" as the temperature information bit value TEMP-b, and the 3-bit data corresponding to states S1 to S7 is converted to "0" as the temperature information bit value TEMP-b, respectively. Thus, temperature information TEMP is obtained from each of the four data groups. However, each temperature information TEMP may include an error based on the variation between state S0 and state S1. Therefore, the memory controller 2 determines one temperature information TEMP by performing a majority vote for each digit among the four temperature information TEMP obtained by the conversion (ST204).

[0115] Specifically, the memory controller 2 takes a majority vote among the four temperature information TEMP for the i-th bit value from the beginning (where i is an integer from 1 to 8) and determines the i-th bit value. The memory controller 2 determines one temperature information TEMP by performing the above-described majority vote for each digit of the 8-bit bit string.

[0116] After ST204, the operation of obtaining the temperature information TEMP ends.

[0117] In the example shown in FIG. 11, the memory controller 2 obtained 3-bit data per memory cell MT from the memory chip 10 and obtained the temperature information TEMP based on the obtained 3-bit data. The method of obtaining the temperature information TEMP is not limited to this.

[0118] For example, the memory chip 10 may be configured to be capable of performing a read operation in the SLC mode even when a plurality of bits of data are written per memory cell MT. In the read operation in the SLC mode, the memory chip 10 outputs "1" or "0" according to whether the threshold voltage of each memory cell MT is higher or lower than one detection voltage Vsense specified by the memory controller 2. The memory controller 2 can obtain the temperature information TEMP from each of the four temperature storage areas ARtemp by using the read operation in the SLC mode.

[0119] In the read operation in the SLC mode, for example, when the threshold voltage of the memory cell MT is lower than the detection voltage Vsense, the memory chip 10 outputs "1", and when the threshold voltage of the memory cell MT is higher than the detection voltage Vsense, it outputs "0". When the memory chip 10 is configured in this way, the memory controller 2 sets the voltage Va1 (see FIG. 8) as the detection voltage Vsense and instructs the memory chip 10 to perform the read operation in the SLC mode. Thereby, the memory controller 2 obtains "1" from the memory cell MT in the state S0 and "0" from the memory cells MT in the states S1 to S7. That is, the memory controller 2 can directly obtain the temperature information TEMP written according to the correspondence shown in FIG. 9 from each temperature storage area ARtemp. In other words, the memory controller 2 can obtain the temperature information TEMP written according to the correspondence shown in FIG. 9 from each temperature storage area ARtemp without referring to the data coding. After the memory controller 2 obtains the temperature information TEMP from each temperature storage area ARtemp, it executes the process of ST204 shown in FIG. 11, that is, the majority decision process, to obtain the temperature information TEMP with the error caused by the variation between the state S0 and the state S1 removed.

[0120] Thus, when the memory cell MT is set to the state S0 or the state S1 according to the temperature information bit value TEMP-b, the memory controller 2 can obtain the temperature information TEMP by any method as long as it can identify whether the memory cell MT is in the state S0 or in the states S1 to S7.

[0121] Note that in the example described in the first embodiment, the temperature information TEMP is multiplexed into four. The number of the multiplexed temperature information TEMP is not limited to four. For example, the memory chip 10 may be configured to multiplex the temperature information TEMP into an odd number so that the memory controller 2 can surely determine one temperature information TEMP by majority decision for each digit among the multiplexed temperature information TEMP.

[0122] As described above, according to the first embodiment, in the foggy program operation which is the program operation of the first stage, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr in the memory cell group MCG to the section RX' corresponding to the write data among the sections R0' to R7'. Further, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the temperature storage area ARtemp in the memory cell group MCG to the section R0' among the sections R0' to R7' in the foggy program operation. In the fine program operation which is the program operation of the second stage, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr to the section RX corresponding to the write data among the sections R0 to R7. Further, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the temperature storage area ARtemp to the section RX corresponding to the temperature information TEMP among the sections R0 and R1 in the fine program operation.

[0123] Therefore, it is possible to record the temperature in units of data writing, rather than in units larger than the unit of data writing (i.e., the unit of the memory cell group MCG). That is, it is possible to appropriately record the temperature at the time of writing.

[0124] The first embodiment can be variously modified. Some modification examples of the first embodiment will be described below.

[0125] (First modification example of the first embodiment) In the first embodiment, in the fine program operation, the threshold voltage of the memory cell MT is set to the state S0 or the state S1 according to the temperature information bit value TEMP-b. The two states in which the threshold voltage of the memory cell MT can be set according to the temperature information bit value TEMP-b are not limited to the state S0 and the state S1.

[0126] As long as the threshold voltage of the memory cell MT is in the same voltage state as the state after the foggy programming operation or in a state with a higher voltage, the designer can arbitrarily determine two states of the threshold voltage of the memory cell MT that can be set according to the temperature information bit value TEMP-b. However, in order to suppress the interference between cells and suppress the time required for the completion of the fine programming operation as much as possible, it is desirable that the amount of change in the threshold voltage of the memory cell MT due to the fine programming operation is small.

[0127] In the first modification of the first embodiment, as shown in FIG. 12, the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp is set to the state S0 or the state S3 according to the temperature bit value TEMP-b in the fine programming operation.

[0128] According to the example shown in FIG. 12, the amount of change in the threshold voltage of the memory cell MT is at most the amount from the state S0' (in other words, the state S0) to the state S3, and is sufficiently smaller than the range R10 provided with the sections R0 to R7. Therefore, regarding the temperature storage area ARtemp, the interference between cells can be suppressed. Also, the time required for the completion of the fine programming operation can be suppressed.

[0129] FIG. 13 is a diagram for explaining 3-bit data generated during the programming operation for the temperature storage area ARtemp of the first modification of the first embodiment. Also in the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature storage area ARtemp is simply referred to as the memory cell MT.

[0130] In the foggy program operation, the sequencer 16 generates the data "111" regardless of whether the temperature bit value TEMP-b is "0" or "1", and supplies the data "111" to the column module 18, similar to the first embodiment. "1" is written as the lower bit of the memory cell MT, "1" as the middle bit, and "1" as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0’(S0) regardless of whether the temperature bit value TEMP-b held in the memory cell MT is "0" or "1".

[0131] In the fine program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "000" and supplies the data "000" to the column module 18. "0" is written as the lower bit of the memory cell MT, "0" as the middle bit, and "0" as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S3. When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "111" and supplies the data "111" to the column module 18. "1" is written as the lower bit of the memory cell MT, "1" as the middle bit, and "1" as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0.

[0132] When the memory controller 2 acquires the temperature information TEMP, it may read 3-bit data per memory cell MT, similar to the first embodiment, or instruct the memory chip 10 to perform a read operation in the SLC mode. However, in the first modification of the first embodiment, "1", which is the temperature bit value TEMP-b corresponding to the state S0, is acquired from the memory cells MT in the states S0 to S1, and "0", which is the temperature bit value TEMP-b corresponding to the state S3, is acquired from the memory cells MT in the states S2 to S7.

[0133] When the memory controller 2 is configured to read 3-bit data per memory cell MT, the memory controller 2 converts the 3-bit data as follows. That is, the memory controller 2 converts not only the data "111" corresponding to the state S0 but also the data "011" corresponding to the state S1 into the "1" of the temperature bit value TEMP-b. The memory controller 2 converts not only the data "000" corresponding to the state S3 but also the data "001" corresponding to the state S2, the data "010" corresponding to the state S4, the data "110" corresponding to the state S5, the data "100" corresponding to the state S6, and the data "101" corresponding to the state S7 into the "0" of the temperature bit value TEMP-b.

[0134] When the memory controller 2 is configured to acquire the temperature information TEMP by a read operation in the SLC mode, the memory controller 2 sets the voltage Va2 (see FIG. 12) as the detection voltage Vsense and instructs the memory chip 10 to perform a read operation in the SLC mode. Thereby, the memory controller 2 acquires "1" from the memory cell MT whose threshold voltage is in the states S0 to S1 and "0" from the memory cell MT whose threshold voltage is in the states S2 to S7. That is, the memory controller 2 can directly acquire the temperature information TEMP written according to the correspondence shown in FIG. 13 from each temperature storage area ARtemp. In other words, the memory controller 2 can acquire the temperature information TEMP written according to the correspondence shown in FIG. 13 from each temperature storage area ARtemp without referring to the data coding.

[0135] In Modification Example 1 of the first embodiment, the two states S0 and S3 corresponding to the temperature bit value TEMP-b are separated from each other with the two states S1 and S2 in between. When reading the temperature information TEMP, the threshold voltage of the memory cell MT is compared with the voltage (voltage Va1 in the above example) in the middle of the two states S0 and S3, and the temperature bit value TEMP-b is determined based on whether it is higher or lower. Therefore, even if the memory cell MT set to the state S0 or the state S3 according to the temperature bit value TEMP-b fluctuates to an adjacent state, it is possible to obtain the temperature bit value TEMP-b without error. That is, when reading the temperature information TEMP, it is possible to suppress the occurrence of errors.

[0136] Note that in Modification Example 1 of the first embodiment, the two states that can be set according to the temperature information bit value TEMP-b are separated from each other with another two states in between. The correspondence between the temperature information bit value TEMP-b and the state may be set such that the two states that can be set according to the temperature information bit value TEMP-b are separated from each other with three or more other states in between. Also, the correspondence between the temperature information bit value TEMP-b and the state may be set such that the two states that can be set according to the temperature information bit value TEMP-b are separated from each other with another one state in between. As described above, the two states set in the fine program operation can be arbitrarily selected by the designer as long as they are in the same voltage state as the state after the foggy program operation or in a higher voltage state.

[0137] (Second Modification Example of the First Embodiment) The state S0 corresponding to the erased state has characteristics different from those of the other states S1 to S7. Specifically, the distribution of the memory cells MT with the threshold voltage set to the state S0 can spread over a wider range compared to the states S1 to S7 and the like. Therefore, the amount of transition of the threshold voltage from the state S0 to the adjacent state S1 is larger than the amount of transition of the threshold voltage from the other states to the adjacent states.

[0138] In the second modification of the first embodiment, in the fine program operation, in order to minimize the amount of shift in the threshold voltage of the memory cell MT constituting the temperature memory region ARtemp, in the foggy program operation, the threshold voltage of the memory cell MT is set to the state SX' located after the second from the low voltage side among the states S0' to S7'.

[0139] For example, as shown in FIG. 14, the threshold voltage of the memory cell MT constituting the temperature memory region ARtemp is set to the state S1' in the foggy program operation. In the subsequent fine program operation, the threshold voltage of the memory cell MT is set to the state S1 or the state S2 according to the temperature bit value TEMP-b.

[0140] FIG. 15 is a diagram for explaining 3-bit data generated during the program operation for the temperature memory region ARtemp of the second modification of the first embodiment. Also in the explanation of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory region ARtemp is simply referred to as the memory cell MT.

[0141] In the foggy program operation, the sequencer 16 generates the data "011" regardless of whether the temperature bit value TEMP-b is "0" or "1", and supplies the data "011" to the column module 18. "0" is written as the lower bit, "1" as the middle bit, and "1" as the upper bit of the memory cell MT. Therefore, the threshold voltage of the memory cell MT is set to the state S1' regardless of whether the temperature bit value TEMP-b held in the memory cell MT is "0" or "1".

[0142] In the fine program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "001" and supplies the data "001" to the column module 18. As the lower bit of the memory cell MT, "0" is written, as the middle bit, "0" is written, and as the upper bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S2. When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "011" and supplies the data "011" to the column module 18. As the lower bit of the memory cell MT, "0" is written, as the middle bit, "1" is written, and as the upper bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S1.

[0143] When the memory controller 2 acquires the temperature information TEMP, similar to the first embodiment, it may read 3-bit data per memory cell MT, or may instruct the memory chip 10 to perform a read operation in the SLC mode. However, in the second modification of the first embodiment, from the memory cells MT with the threshold voltage in the states S0 to S1, "1" which is the temperature bit value TEMP-b corresponding to the state S1 is acquired, and from the memory cells MT with the threshold voltage in the states S2 to S7, "0" which is the temperature bit value TEMP-b corresponding to the state S2 is acquired.

[0144] Note that in the above example, in the foggy program operation, the threshold voltage of the memory cell MT is set to the state S1'. The state in which the threshold voltage of the memory cell MT is set in the foggy program operation is not limited to the state S1'. The designer can arbitrarily select the threshold voltage of the memory cell MT from the states S2' to S6' in the foggy program operation.

[0145] Also, in the above example, in the fine program operation, the threshold voltage of the memory cell MT was set to the state S1 or the state S2 according to the temperature information bit value TEMP-b. The two states of the threshold voltage of the memory cell MT that can be set according to the temperature information bit value TEMP-b in the fine program operation are not limited to the state S1 and the state S2. In the fine program operation, as long as the state of the voltage is the same as the state in the foggy fine program operation or the state on the higher voltage side, the memory cell MT can be set to any two states. For example, as shown in the first modification of the first embodiment, the two states in which the threshold voltage can be set in the fine program operation may be separated from each other with one or more states sandwiched therebetween.

[0146] In the first embodiment and its modification, the control circuit 15 acquired the temperature information TEMP from the temperature sensor 12 during the fine program operation.

[0147] Therefore, it becomes possible to record the temperature at a time point close to the completion of writing all pages of data for the memory cell group MCG.

[0148] Note that the timing of acquiring the temperature information TEMP is not limited to the fine program operation. For example, the control circuit 15 may acquire the temperature information TEMP during the foggy program operation and write the temperature information TEMP to the temperature storage area ARtemp during the fine program operation.

[0149] (Second Embodiment) In the first embodiment and its modification, in the foggy program operation, the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp was set to a common state regardless of whether the temperature bit value TEMP-b held in the memory cell MT is "0" or "1". In the foggy program operation, the threshold voltage of the memory cell MT may be set to any of the two states according to the temperature bit value TEMP-b.

[0150] For example, as shown in FIG. 16, the threshold voltage of the memory cell MT that constitutes the temperature memory area ARtemp is set to the state S0’ (S0) or the state S2’ according to the temperature bit value TEMP-b in the foggy program operation.

[0151] In the subsequent fine program operation, the threshold voltage of the memory cell MT that constitutes the temperature memory area ARtemp is set to the state S2 or the state S4 according to the temperature bit value TEMP-b.

[0152] The state S2 and the state S4 are located on the higher voltage side than the state S2’ which is the higher voltage state among the two states set in the foggy program operation. Therefore, in the fine program operation, the threshold voltage of the memory cell MT can be set to either the state S2 or the state S4 regardless of the state after the foggy program operation. Therefore, different values of temperature information TEMP can be written during the foggy program operation and during the fine program operation. The memory chip 10 executes the acquisition of the temperature information TEMP from the temperature sensor 12 and the writing of the acquired temperature information TEMP in each of the foggy program operation and the fine program operation.

[0153] FIG. 17 is a diagram for explaining 3-bit data generated during the program operation for the temperature memory area ARtemp of the second embodiment. Also in the description of this figure, unless otherwise specified, the memory cell MT that constitutes the temperature memory area ARtemp is simply referred to as the memory cell MT.

[0154] In the foggy program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "001" and supplies the data "001" to the column module 18. As the lower bit of the memory cell MT, "0" is written, as the middle bit, "0" is written, and as the upper bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S2'. When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "111" and supplies the data "111" to the column module 18. As the lower bit of the memory cell MT, "1" is written, as the middle bit, "1" is written, and as the upper bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S0'(S0).

[0155] In the fine program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "001" and supplies the data "001" to the column module 18. As the lower bit of the memory cell MT, "0" is written, as the middle bit, "0" is written, and as the upper bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S2. When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "010" and supplies the data "010" to the column module 18. As the lower bit of the memory cell MT, "0" is written, as the middle bit, "1" is written, and as the upper bit, "0" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S4.

[0156] FIG. 18 is a flowchart showing an example of the program operation of the memory chip 10 according to the second embodiment.

[0157] When the I / O interface 13 receives three pages of data together with a write command from the memory controller 2 (ST301), the control circuit 15 executes the foggy program operation (ST3).

[0158] In the foggy program operation, the sequencer 16 acquires temperature information TEMP from the temperature sensor 12 (ST302). Then, based on the temperature information TEMP acquired in ST302, the sequencer 16 generates, for each memory cell MT constituting the temperature storage area ARtemp, data "001" corresponding to the temperature bit value TEMP-b of "0" or "111" corresponding to the temperature bit value TEMP-b of "1" (ST303).

[0159] Then, the control circuit 15 writes data for three pages to the user area ARusr by applying a program pulse to the word line WL connected to the memory cell group MCG to be written one or more times. That is, the control circuit 15 writes the data "001" or the data "111" generated in ST303 to each memory cell MT constituting the temperature storage area ARtemp (ST304). Then, the foggy program operation ends.

[0160] After the foggy program operation, the control circuit 15 executes a fine program operation (ST4).

[0161] In the fine program operation, the sequencer 16 acquires temperature information TEMP from the temperature sensor 12 (ST305). Then, based on the temperature information TEMP acquired in ST305, the sequencer 16 generates, for each memory cell MT constituting each temperature storage area ARtemp, data "001" corresponding to the temperature bit value TEMP-b of "0" or data "010" corresponding to the temperature bit value TEMP-b of "1" (ST306).

[0162] Then, the control circuit 15 writes the three - page data received at ST301 to the user area ARusr by applying one or more program pulses to the word line WL connected to the memory cell group MCG to be written, and writes the data "001" or the data "010" generated at ST306 to each memory cell MT constituting each temperature storage area ARtemp (ST307). Then, the fine - programming operation ends, and the programming operation by the memory chip 10 ends.

[0163] The memory controller 2 can acquire the temperature information TEMP written by the fine - programming operation in the same manner as the method described in the first embodiment or its modification.

[0164] Also, the memory controller 2 can acquire the temperature information TEMP written by the fog - programming operation until the fine - programming operation starts. Specifically, the memory controller 2 designates the voltage between the state S0' and the state S2' (for example, the voltage Vb10 in FIG. 16) as the detection voltage Vsense, and instructs the memory chip 10 to perform a read operation in the SLC mode. Thereby, the memory controller 2 can acquire "1", which is the temperature bit value TEMP - b corresponding to the state S0' (S0), from the memory cell MT whose threshold voltage is on the lower - voltage side than the voltage Vb10, and "0", which is the temperature bit value TEMP - b corresponding to the state S2', from the memory cell MT whose threshold voltage is on the higher - voltage side than the voltage Vb10.

[0165] The memory controller 2 acquires four temperature information TEMP from the four temperature storage areas ARtemp, either the temperature information TEMP written by the fog - programming operation or the temperature information TEMP written by the fine - programming operation. Then, the memory controller 2 can determine one temperature information TEMP by performing a majority - decision process (for example, the same process as ST204 in FIG. 11) on the four acquired temperature information TEMP.

[0166] Thus, according to the second embodiment, in the foggy program operation which is the program operation of the first stage, the control circuit 15 acquires the temperature information TEMP from the temperature sensor 12. Then, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr to a state corresponding to the write data among the states S0' to S7'. Further, the control circuit 15 sets the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp to a state corresponding to the temperature information TEMP acquired in the foggy program operation among the two states S0' and S2'.

[0167] Also, in the fine program operation which is the program operation of the second stage, the control circuit 15 acquires the temperature information TEMP from the temperature sensor 12. Then, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr to a state corresponding to the write data among the states S0 to S7. Further, the control circuit 15 sets the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp to a state corresponding to the temperature information TEMP acquired in the fine program operation among the two states S2 and S4.

[0168] Therefore, the memory chip 10 can record the temperature information TEMP during the foggy program operation. The memory controller 2 can acquire the temperature information TEMP during the foggy and fine program operations from the memory chip 10 until the fine program operation starts.

[0169] Therefore, for example, if the memory chip 10 fails between the end of the foggy program operation and the start of the fine program operation, the temperature information TEMP during the foggy program operation can be acquired as the temperature information at the time of failure.

[0170] In the second embodiment, in the foggy program operation, the threshold voltage of the memory cell MT was set to state S0' or S2' according to the temperature information bit value TEMP-b. In the fine program operation, the threshold voltage of the memory cell MT was set to state S2 or S4 according to the temperature information bit value TEMP-b. The two states in which the threshold voltage of the memory cell MT can be set according to the temperature information bit value TEMP-b in the foggy program operation and the fine program operation are not limited to these examples.

[0171] As long as the state on the low voltage side of the two states that can be set in the fine program operation is the same as or higher than the state on the high voltage side of the two states that can be set in the foggy program operation, the designer can arbitrarily select the states that can be set in the foggy program operation and the fine program operation.

[0172] For example, the two states that can be set in the fine program operation may be adjacent to each other, or may be separated from each other with one or more states in between.

[0173] Also, the two states that can be set in the foggy program operation may be selected from among states S1' to S6'.

[0174] (Third Embodiment) As multi-stage program operations, in addition to the foggy fine program operation, a multi-stage program operation using internal data load is known. In the third embodiment, a memory chip 10 capable of a multi-stage program operation using internal data load will be described. The multi-stage program operation using internal data load (IDL) is referred to as the IDL program operation.

[0175] In the program operation of the first stage of the IDL program operation, the memory chip 10 writes data of some bits out of the multiple bits of data that will ultimately be written to the memory cell MT to the memory cell MT. Let the number of bits of data that will ultimately be written to the memory cell MT be denoted as (P + Q) bits, and let the number of bits of data written to the memory cell MT in the program operation of the first stage be denoted as P bits. Both P and Q are integers of 1 or more. That is, in the program operation of the first stage, the threshold voltage of the memory cell MT is set to any one of the 2 P intervals associated with P bits of data respectively.

[0176] In the program operation of the second stage of the IDL program operation, the memory chip 10 reads the already written P bits of data from the memory cell MT. The (P + Q) bits of data obtained by combining the read P bits of data and the Q bits of data received from the memory controller 2 are written to the memory cell MT. The threshold voltage of the memory cell MT is set to any one of the 2 (P+Q) intervals associated with (P + Q) bits of data respectively. Note that the operation of the memory chip 10 reading the already written P bits of data from the memory cell MT is referred to as internal data load.

[0177] The memory chip 10 selects the memory cell MT targeted for the program operation of each stage, for example, in the same way as the foggy fine program operation. That is, the memory chip 10 executes the program operation of the first stage on the first memory cell MT and the second memory cell MT adjacent to the first memory cell MT, and then executes the program operation of the second stage on the first memory cell MT. Thereby, the cell - to - cell interference is suppressed.

[0178] FIG. 19 is a schematic diagram for explaining the change in the distribution of threshold voltages due to the IDL program operation executed by the memory chip 10 of the third embodiment. In the description of this figure, as an example, it is assumed that 2 bits of data out of 3 bits of data written in TLC mode are written in the program operation of the first stage. That is, P is "2" and Q is "1". The program operation of the first stage is expressed as an MLC program operation in the sense of writing 2 bits of data per memory cell MT. Also, the program operation of the second stage is expressed as a fine program operation.

[0179] In the block 30 after the erase operation, as shown in the uppermost graph of FIG. 19, all the memory cells MT are in the state S0.

[0180] The MLC program operation, which is the program operation of the first stage, is executed on the memory cell group MCG in the state after the erase operation.

[0181] In the MLC program operation, the threshold voltage of each memory cell MT is set to belong to any one of the four intervals R0” to R3” to which 2 bits of data are associated. Interval R0” is an interval on the lower voltage side than the voltage Vc1 (where Vc1 ≤ Va1). Interval R1” is an interval from the voltage Vc1 to the voltage Vc2 (where Vc2 ≤ Va3). Interval R2” is an interval from the voltage Vc2 to the voltage Vc3 (where Vc3 ≤ Va5). Interval R3” is an interval on the higher voltage side than the voltage Vc3. Hereinafter, the interval RX” may be denoted as the state SX”.

[0182] By the MLC program operation, a group of memory cells MT in which threshold voltages are set to each of the states S0” to S3” forms a lobe-shaped distribution.

[0183] Here, the MLC program operation is executed so that each distribution is formed in a state where they are as non-overlapping as possible when adjacent to each other. That is, according to the MLC program operation, four mutually separated distributions S0” to S3” are formed.

[0184] In the internal data load, the memory chip 10 performs a read operation on the memory cell MT for which the MLC program operation has been completed, using, for example, voltages Vc1, Vc2, and Vc3 as the detection voltage Vsense. And each distribution is set so as to be as non-overlapping as possible when adjacent to each other. Therefore, the memory chip 10 can acquire 2-bit data with few errors from the memory cell MT.

[0185] In the fine program operation, according to 1-bit data newly received from the memory controller 2, the threshold voltage of each memory cell MT is maintained or slightly increased, so that the threshold voltage of each memory cell MT is set to belong to any one of eight intervals R0 to R7.

[0186] Specifically, the threshold voltage of the memory cell MT in state S0” after the MLC program operation is maintained in state S0” (S0) or set to state S1 according to the newly input 1-bit data. The threshold voltage in state S1” after the MLC program operation is set to state S2 or state S3 according to the newly input 1-bit data. The threshold voltage in state S2” after the MLC program operation is set to state S4 or state S5 according to the newly input 1-bit data. The threshold voltage in state S3” after the MLC program operation is set to state S6 or state S7 according to the newly input 1-bit data.

[0187] FIG. 20 is a diagram showing an example of data coding according to the third embodiment. Note that the data coding shown in this figure indicates that in the MLC program operation, the lower bits and the upper bits are written, and in the fine program operation, the upper bits are newly written. When the data is denoted as "ab" in this specification, "a" indicates the value of the lower bits and "b" indicates the value of the middle bits.

[0188] As shown in FIG. 20, data "11" is associated with the section R0” (state S0”). Data "10" is associated with the section R1” (state S1”). Data "00" is associated with the section R2” (state S2”). Data "01" is associated with the section R3” (state S3”).

[0189] And data "111" is associated with the section R0 (state S0), data "110" is associated with the section R1 (state S1), data "100" is associated with the section R2 (state S1), data "101" is associated with the section R3 (state S3), data "001" is associated with the section R4 (state S4), data "000" is associated with the section R5 (state S5), data "010" is associated with the section R6 (state S6), and data "001" is associated with the section R7 (state S7).

[0190] According to this example of data coding, the value of the lower page and the value of the middle page are set to the same value regardless of the value of the upper bits. Therefore, after writing the lower bits and the middle bits by the MLC program operation, it is possible to add the upper page and write data for three pages in the fine program operation.

[0191] In the third embodiment, the memory chip 10 writes the temperature information TEMP to different pages among the lower page, the middle page, and the upper page during the MLC program operation and during the fine program operation.

[0192] FIG. 21 is a schematic diagram for explaining an example of the transition of the threshold voltage of the memory cell MT constituting the temperature memory region ARtemp of the third embodiment. In this figure, the distribution that may include the memory cell MT constituting the temperature memory region ARtemp is hatched. In the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory region ARtemp is simply referred to as the memory cell MT.

[0193] In the MLC program operation, the threshold voltage of the memory cell MT is set to the state S0” (S0) or the state S1” according to the temperature bit value TEMP-b.

[0194] In the subsequent fine program operation, the threshold voltage of the memory cell MT is set to any one of the states S0 to S3 according to the temperature bit value TEMP-b. The threshold voltage of the memory cell MT set to the state S0” by the MLC program operation is set to the state S0 or the state S1 according to the temperature bit value TEMP-b in the fine program operation. The threshold voltage of the memory cell MT set to the state S1” by the MLC program operation is set to the state S2 or the state S3 according to the temperature bit value TEMP-b in the fine program operation.

[0195] FIG. 22 is a diagram for explaining the data generated during the program operation for the temperature memory region ARtemp of the third embodiment. Also in the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory region ARtemp is simply referred to as the memory cell MT.

[0196] In the MLC program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "11" and supplies the data "11" to the column module 18. As the lower bit of the memory cell MT, "1" is written, and as the middle bit, "1" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S0. When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "10" and supplies the data "10" to the column module 18. As the lower bit of the memory cell MT, "1" is written, and as the middle bit, "0" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S1.

[0197] In the fine program operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates "0" as the data of the upper bit. Then, the control circuit 15 reads the 2-bit data already written to the memory cell MT, that is, the values of the lower bit and the upper bit, by internal data loading. Then, the sequencer 16 supplies 3-bit data, which is a combination of the read lower-bit and upper-bit values and the generated upper-bit value, to the column module 18.

[0198] For example, when the temperature bit value TEMP-b written in the MLC program operation is "0", the data "11" is read by internal data loading. The sequencer 16 supplies the data "110", which is a combination of the read data "11" and the upper bit "0", to the column module 18. As the lower bit of the memory cell MT, "1" is written, as the middle bit, "1" is written, and as the upper bit, "0" is written. Therefore, the threshold voltage of the memory cell MT is set to the state S1.

[0199] When the temperature bit value TEMP-b written during the MLC program operation is "1", the data "10" is read by internal data loading. The sequencer 16 supplies the data "100" obtained by combining the read data "10" and the upper bit "0" to the column module 18. A "1" is written as the lower bit of the memory cell MT, a "0" is written as the middle page bit, and a "0" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S2.

[0200] In the fine program operation, when the temperature bit value TEMP-b is "1", the sequencer 16 generates "1" as the data of the upper bit. Then, the control circuit 15 reads the 2-bit data already written to the memory cell MT, that is, the values of the lower bit and the upper bit, by internal data loading. Then, the sequencer 16 supplies 3-bit data, which is a combination of the read values of the lower bit and the upper bit and the generated value of the upper bit, to the column module 18.

[0201] For example, when the temperature bit value TEMP-b written during the MLC program operation is "0", the data "11" is read by internal data loading. The sequencer 16 supplies the data "111" obtained by combining the read data "11" and the upper bit "1" to the column module 18. A "1" is written as the lower bit of the memory cell MT, a "1" is written as the middle bit, and a "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0.

[0202] When the temperature bit value TEMP-b written during the MLC program operation is "1", the data "10" is read by internal data loading. The sequencer 16 supplies the data "101", which is a combination of the read data "10" and the upper bit "1", to the column module 18. A "1" is written as the lower bit, a "0" as the middle bit, and a "1" as the upper bit of the memory cell MT. Therefore, the threshold voltage of the memory cell MT is set to the state S4.

[0203] That is, according to the example shown in FIG. 22, the temperature information TEMP (more precisely, the numerical information obtained by inverting the temperature information TEMP by bits) during the MLC program operation is written to the middle page, and the temperature information TEMP during the fine program operation is written to the upper page.

[0204] Therefore, the memory controller 2 can acquire the temperature information TEMP during the fine program operation by instructing the memory chip 10 to perform a read operation targeting the upper page. The memory controller 2 can acquire the temperature information TEMP during the MLC program operation by instructing the memory chip 10 to perform a read operation targeting the middle page.

[0205] Note that the page where the temperature information TEMP is written during the MLC program operation does not have to be the middle page. The memory chip 10 may be configured such that the temperature information TEMP is written to the lower page during the MLC program operation.

[0206] FIG. 23 is a flowchart showing an example of the program operation of the memory chip 10 according to the third embodiment.

[0207] The I / O interface 13 receives, from the memory controller 2, data for two pages together with a write command, more precisely, data for the lower page and the middle page (ST401). Then, the control circuit 15 executes the MLC program operation (ST5).

[0208] In the MLC program operation, the sequencer 16 acquires temperature information TEMP from the temperature sensor 12 (ST402). Then, based on the temperature information TEMP acquired by ST402, the sequencer 16 generates, for each memory cell MT constituting each temperature storage area ARtemp, data "11" corresponding to a temperature bit value TEMP-b of "0" or "10" corresponding to a temperature bit value TEMP-b of "1" (ST403).

[0209] Then, the control circuit 15 writes the two-page data received in ST401 to the user area ARusr by applying a program pulse to the word line WL connected to the memory cell group MCG of the write destination one or more times. That is, the control circuit 15 writes the data "11" or the data "10" generated in ST403 to each memory cell MT constituting each temperature storage area ARtemp (ST404). That is, the control circuit 15 writes 2-bit data per memory cell MT to the user area ARusr and the temperature storage area ARtemp. Then, the MLC program operation ends.

[0210] Subsequently, the I / O interface 13 receives one-page data, more precisely, upper page data, from the memory controller 2 (ST405). Then, the control circuit 15 executes the fine program operation (ST6).

[0211] In the fine program operation, the sequencer 16 acquires temperature information TEMP from the temperature sensor 12 (ST406). The control circuit 15 acquires the two-page data written in ST404 from the user area ARusr by internal data loading, and acquires the data "11" or the data "10" written in ST404 from the temperature storage area ARtemp (ST407). That is, the control circuit 15 acquires 2-bit data per memory cell MT from the user area ARusr and the temperature storage area ARtemp.

[0212] Based on the temperature information TEMP acquired by ST406, the sequencer 16 generates, for each memory cell MT constituting each temperature storage area ARtemp, the data “0” corresponding to the temperature bit value TEMP-b of “0” or the “0” corresponding to the temperature bit value TEMP-b of “1” (ST408).

[0213] Then, the control circuit 15 writes the data of three pages, which is a combination of the data of two pages read by ST407 and the data of one page received by ST405 in the user area ARusr, by applying the program pulse to the word line WL connected to the memory cell group MCG of the write destination one or more times (ST409). Further, the control circuit 15 writes the data of three bits, which is a combination of the data of two bits per memory cell MT read by ST407 and the data “0” or “1” generated by ST408, to each memory cell MT constituting each temperature storage area ARtemp (ST409). Then, the fine programming operation ends, and the program operation of the third embodiment ends.

[0214] The memory controller 2 can acquire the temperature information TEMP written during the MLC program operation by instructing the memory chip 10 to perform a read operation targeting the middle page. Also, the memory controller 2 can acquire the temperature information TEMP written during the fine programming operation by instructing the memory chip 10 to perform a read operation targeting the upper page.

[0215] In the above example, it is assumed that P is “2” and Q is “1”. The values of P and Q are not limited to these.

[0216] According to the third embodiment, the I / O interface 13 receives data of P bits per memory cell MT, that is, data for P pages. The I / O interface 13 receives data of Q bits per memory cell MT, that is, data for Q pages, after the data for P pages. When the I / O interface 13 receives the data for P pages, the control circuit 15 executes the program operation of the first stage.

[0217] In the program operation of the first stage, the control circuit 15 acquires temperature information from the temperature sensor 12. Then, the control circuit 15 sets the threshold voltage of each memory cell MT constituting the user area ARusr to a section corresponding to the data for P pages out of 2 P sections. Further, the control circuit 15 sets the threshold voltage of each memory cell MT constituting the temperature storage area ARtemp to a section corresponding to the temperature information TEMP acquired in the program operation of the first stage out of 2 P sections.

[0218] After the program operation of the first stage, when the I / O interface 13 receives the data for Q pages, the control circuit 15 executes the program operation of the second stage.

[0219] In the program operation of the second stage, the control circuit 15 acquires temperature information from the temperature sensor 12. Then, the control circuit 15 acquires data for P pages from the user area ARusr by internal data loading. The control circuit 15 acquires data of 2 bits per memory cell MT corresponding to the temperature information TEMP acquired in the program operation of the first stage from the temperature storage area ARtemp. The control circuit 15 sets the threshold voltage of each memory cell MT constituting the user area ARusr to 2 (P+Q)Of the individual sections, set to a section corresponding to (P + Q) pages of data obtained by combining the data for P pages acquired by internal data loading and the data for Q pages received by the I / O interface 13. That is, the control circuit 15 writes the data for (P + Q) pages to the user area ARusr. The control circuit 15 writes the data for (P + Q) pages to the user area ARusr. Further, the control circuit 15 sets the threshold voltage of each memory cell MT constituting the temperature storage area ARtemp to 2 (P+Q) Of the individual sections, set to a second section corresponding to the combination of the temperature information TEMP acquired by internal data loading and the temperature information TEMP acquired from the temperature sensor 12 during the program operation in the second stage.

[0220] Therefore, it becomes possible to acquire both the temperature information TEMP during the program operation in the first stage and the temperature information TEMP during the program operation in the second stage from the memory cell group MCG in which the program operation in the second stage has been completed.

[0221] (Fourth Embodiment) According to the foggy fine program operation described in the second embodiment, the temperature information TEMP is written both during the foggy program operation and during the fine program operation. However, the temperature information TEMP written during the foggy program operation cannot be acquired after the fine program operation.

[0222] Therefore, in the fourth embodiment, the temperature information TEMP is written to a plurality of different memory cells MT in the memory cell group MCG during the foggy program operation and during the fine program operation. This makes it possible to acquire the temperature information TEMP during the foggy program operation even after the fine program operation has been completed.

[0223] FIG. 24 is a schematic diagram showing an example of the write position of the temperature information TEMP in the redundant area ARred provided in the memory cell group MCG of the fourth embodiment.

[0224] As shown in FIG. 24, in the redundant region ARred, a plurality of pairs of a temperature memory region ARtemp0 in which temperature information TEMP is written during the foggy program operation and a temperature memory region ARtemp1 in which temperature information TEMP is written during the fine program operation are provided. Here, as an example, four pairs of the temperature memory region ARtemp0 and the temperature memory region ARtemp1 are provided. That is, the memory cell group MCG includes 32 memory cells MT in which four temperature information TEMP are written during the foggy program operation and 32 memory cells MT in which four temperature information TEMP are written during the fine program operation.

[0225] FIG. 25 is a schematic diagram for explaining an example of the transition of the threshold voltage of the memory cell MT constituting the temperature memory region ARtemp0 of the fourth embodiment. In this figure, the distribution in which the memory cell MT constituting the temperature memory region ARtemp0 may be included is hatched. In the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory region ARtemp0 is simply referred to as the memory cell MT.

[0226] In the foggy program operation, the threshold voltage of the memory cell MT is set to the state S0’ (S0) or the state S3’ according to the temperature bit value TEMP-b.

[0227] In the fine program operation, the threshold voltage of the memory cell MT is maintained in the state after the foggy program operation.

[0228] FIG. 26 is a schematic diagram for explaining an example of the transition of the threshold voltage of the memory cell MT constituting the temperature memory region ARtemp1 of the fourth embodiment. In this figure, the distribution in which the memory cell MT constituting the temperature memory region ARtemp1 may be included is hatched. In the description of this figure, unless otherwise specified, the memory cell MT constituting the temperature memory region ARtemp1 is simply referred to as the memory cell MT.

[0229] In the foggy program operation, as in the first embodiment, the threshold voltage of the memory cell MT is set to the state S0’ (S0) regardless of the temperature bit value TEMP-b.

[0230] In the fine program operation, the threshold voltage of the memory cell MT is set to the state S0 or the state S1 according to the temperature bit value TEMP-b, as in the first embodiment.

[0231] FIG. 27 is a diagram for explaining 3-bit data generated during the program operation for the temperature storage areas ARtemp0 and ARtemp1 of the fourth embodiment.

[0232] For the temperature storage area ARtemp0, in the foggy program operation, when the temperature bit value TEMP-b is “0”, the sequencer 16 generates the data “000” and supplies the data “000” to the column module 18. “0” is written as the lower bit of the memory cell MT, “0” is written as the middle bit, and “0” is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S3’. When the temperature bit value TEMP-b is “1”, the sequencer 16 generates the data “111” and supplies the data “111” to the column module 18. “1” is written as the lower bit of the memory cell MT, “1” is written as the middle bit, and “1” is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0’ (S0).

[0233] For the temperature storage area ARtemp0, in the fine program operation, regardless of whether the temperature bit value TEMP-b is “0” or “1”, the sequencer 16 generates the data “111” and supplies the data “111” to the column module 18. “1” is written as the lower bit of the memory cell MT, “1” is written as the middle bit, and “1” is written as the upper bit.

[0234] The data "111" corresponds to the state S0, which is the lowest voltage state among the states S0 to S7. However, after the foggy programming operation, the threshold value of the memory cell MT is in the state S0' equal to the state S0 or the state S3' set to a higher voltage side than the state S0. Therefore, in the fine programming operation, the threshold voltage in the state S0' (S0) or the state S3' is not increased and is maintained in the state S0' (S0) or the state S3'.

[0235] For the temperature memory area ARtemp1, in the foggy programming operation, the sequencer 16 generates the data "111" regardless of whether the temperature bit value TEMP-b is "0" or "1", and supplies the data "111" to the column module 18. "1" is written as the lower bit of the memory cell MT, "1" is written as the middle bit, and "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0' (S0).

[0236] For the temperature memory area ARtemp1, in the fine programming operation, when the temperature bit value TEMP-b is "0", the sequencer 16 generates the data "011" and supplies the data "011" to the column module 18. "0" is written as the lower bit of the memory cell MT, "1" is written as the middle bit, and "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S1 corresponding to the temperature bit value TEMP-b of "0". When the temperature bit value TEMP-b is "1", the sequencer 16 generates the data "111" and supplies the data "111" to the column module 18. "1" is written as the lower bit of the memory cell MT, "1" is written as the middle bit, and "1" is written as the upper bit. Therefore, the threshold voltage of the memory cell MT is set to the state S0 corresponding to the temperature bit value TEMP-b of "1".

[0237] According to the fourth embodiment, in the foggy program operation which is the program operation of the first stage, the control circuit 15 acquires temperature information TEMP from the temperature sensor 12. Then, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr to a state corresponding to the write data among the states S0' to S7'. Further, the control circuit 15 sets the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp0 to a state corresponding to the temperature information TEMP acquired in the foggy program operation among the two states S0' and S3'.

[0238] Also, in the fine program operation which is the program operation of the second stage, the control circuit 15 acquires temperature information TEMP from the temperature sensor 12. Then, the control circuit 15 sets the threshold voltage of each of the plurality of memory cells MT constituting the user area ARusr to a state corresponding to the write data among the states S0 to S7. Further, the control circuit 15 sets the threshold voltage of the memory cell MT constituting the temperature storage area ARtemp1 to a state corresponding to the fine program operation temperature information TEMP among the two states S0 and S1.

[0239] Therefore, the memory controller 2 can acquire the temperature information TEMP during the foggy program operation by instructing the memory chip 10 to perform a read operation targeting the temperature storage area ARtemp0. Also, the memory controller 2 can acquire the temperature information TEMP written during the fine program operation by instructing the memory chip 10 to perform a read operation targeting the temperature storage area ARtemp1.

[0240] Note that the two states in which the threshold voltage of the memory cell MT can be set according to the temperature information bit value TEMP-b in the foggy program operation and the fine program operation are not limited to the above-described example.

[0241] For example, for the memory cell MT that constitutes the temperature memory area ARtemp1, in the foggy program operation, the control circuit 15 may set the threshold voltage to a state located second or later from the low voltage side among the states S0’ to S7’, similar to the second modification of the first embodiment.

[0242] Also, in the fine program operation, the control circuit 15 may set the threshold voltage of the memory cell MT that constitutes the temperature memory area ARtemp1 to either of two states separated by one or more states in between. Further, the control circuit 15 may set the threshold voltage of the memory cell MT that constitutes the temperature memory area ARtemp1 to either of two states separated from each other by sandwiching another two states in between, similar to the first modification of the first embodiment.

[0243] As long as the state of the memory cell MT that constitutes the temperature memory area ARtemp1 after the fine program operation is the same voltage state as or a higher voltage state than the state of the memory cell MT after the foggy program operation, the designer can arbitrarily determine the two states in which the threshold voltage of the memory cell MT can be set in the fine program operation.

[0244] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0245] 1 Memory system, 2 Memory controller, 3 Memory bank, 5 Memory bus, 6 Host bus, 10 Memory chip, 11 Memory cell array, 12 Temperature sensor, 14 Data buffer, 15 Control circuit, 16 Sequencer, 17 Row module, 18 Column module, 21 Host interface, 22 Memory interface, 23 Control unit, 24 ECC unit, 30 Block, 100 Host.

Claims

1. A first plurality of memory cells each gate of which is connected to a word line; A temperature sensor; An interface configured to receive light data; By applying a programming voltage to the word line, setting the threshold voltage of each of a second plurality of memory cells among the first plurality of memory cells to a first interval corresponding to the light data among a plurality of first intervals, and setting the threshold voltage of each of a third plurality of memory cells different from the second plurality of memory cells among the first plurality of memory cells to a second interval among the plurality of first intervals, and executing a first programming operation; After the first programming operation, by further applying a programming voltage to the word line, setting the threshold voltage of each of the second plurality of memory cells to a third interval corresponding to the light data among a plurality of third intervals provided in a range wider than the plurality of first intervals, and setting the threshold voltage of each of the third plurality of memory cells to a fourth interval corresponding to first temperature information detected by the temperature sensor among two fourth intervals set to the same or higher voltage side as the second interval among the plurality of third intervals, and executing a second programming operation; A control circuit configured as such; A non-volatile memory comprising the same.

2. The control circuit is configured to acquire the first temperature information from the temperature sensor in the second programming operation. The non-volatile memory according to Claim 1.

3. The control circuit In the first programming operation, acquires second temperature information from the temperature sensor, and sets the threshold voltage of each of the third plurality of memory cells to a fifth interval corresponding to the second temperature information among two fifth intervals corresponding to the second interval respectively; In the second programming operation, acquires the first temperature information from the temperature sensor. Configured as such. The non-volatile memory according to Claim 1.

4. The second interval is the first interval located second and later from the low voltage side among the plurality of first intervals. The non-volatile memory according to any one of Claims 1 to 3.

5. The two fourth intervals are spaced apart from each other with two or more third intervals among the plurality of third intervals therebetween. The non-volatile memory according to any one of Claims 1 to 4.

6. A first plurality of memory cells each having a gate connected to a word line, A temperature sensor, An interface configured to receive P (P is an integer of 1 or more) bits of first write data per memory cell and to receive Q (Q is an integer of 1 or more) bits of second write data per memory cell after the first write data, When the interface receives the first light data, first temperature information is obtained from the temperature sensor, and by applying a programming voltage to the word line, the threshold voltage of each of the second plurality of memory cells among the first plurality of memory cells is set to 2 Ｐ to a first section corresponding to the first light data among the two first sections, and the threshold voltage of each of the third plurality of memory cells different from the second plurality of memory cells among the first plurality of memory cells is set to the 2 Ｐ to a first section corresponding to the first temperature information among the two first sections, and execute a first programming operation When the interface receives the second light data, obtain second temperature information from the temperature sensor, read the first light data and the first temperature information from the first plurality of memory cells, and further apply a programming voltage to the word line, thereby setting the threshold voltage of each of the second plurality of memory cells to 2 （Ｐ＋Ｑ） set to a second interval corresponding to a combination of the first light data and the second light data among two second intervals, and set the threshold voltage of each of the third plurality of memory cells to the second interval corresponding to a combination of the first temperature information and the second temperature information among the two （Ｐ＋Ｑ） second intervals, and execute a second programming operation A control circuit configured as such, A non-volatile memory comprising the above.

7. A first plurality of memory cells each having a gate connected to a word line, A temperature sensor, An interface configured to receive write data, A first program operation of obtaining first temperature information from the temperature sensor and setting the threshold voltage of each of a second plurality of memory cells among the first plurality of memory cells to a first interval corresponding to the write data among a plurality of first intervals by applying a programming voltage to the word line, setting the threshold voltage of each of a third plurality of memory cells different from the second plurality of memory cells among the first plurality of memory cells to a second interval corresponding to the first temperature information among two second intervals of the plurality of first intervals, and setting the threshold voltage of each of a fourth plurality of memory cells different from both the second plurality of memory cells and the third plurality of memory cells among the first plurality of memory cells to a third interval of the plurality of first intervals, After the first program operation, a second program operation of obtaining second temperature information from the temperature sensor and setting the threshold voltage of each of the second plurality of memory cells to a fourth interval corresponding to the write data among a plurality of fourth intervals provided in a range wider than the plurality of first intervals by applying a further programming voltage to the word line, and setting the threshold voltage of each of the fourth plurality of memory cells to a fifth interval corresponding to the second temperature information among two fifth intervals set to the same or higher voltage side as the third interval among the plurality of fourth intervals is executed, A control circuit configured as such, A non-volatile memory comprising the above.

8. The third interval is a first interval located second and subsequent from the low voltage side among the plurality of first intervals. The non-volatile memory according to Claim 7.

9. The two fifth intervals are separated from each other with two or more of the fourth intervals among the plurality of fourth intervals therebetween. The non-volatile memory according to Claim 7 or Claim 8.

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