Imaging device

Abstract

To provide an imaging apparatus capable of expanding a dynamic range by a simple constitution.SOLUTION: A circuit constitution and an operation method of an imaging apparatus can determine an electron saturation state in a charge detection part formed in a pixel and change an operation mode in accordance with a determination result. First, first imaging data are acquired, and if the charge detection part is not saturated, the first imaging data are read out as they are. When the charge detection part is saturated, saturation of the charge detection part is canceled and second image data are acquired and read out.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device and an operation method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operation methods, or their manufacturing methods. can be cited as an example.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. In addition, storage devices, display devices, imaging devices, and electronic devices may include semiconductor devices.

Background Art

[0004] Oxide semiconductors have attracted attention as semiconductor materials applicable to transistors. For example, technologies for manufacturing transistors using zinc oxide or In-Ga-Zn-based oxide semiconductors as the oxide semiconductor are disclosed (see Patent Document 1 and Patent Document 2).

[0005] In addition, an imaging device having a configuration in which a transistor having an oxide semiconductor is used as part of a pixel circuit is disclosed in Patent Document 3.

Prior Art Documents

Patent Document

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] CMOS image sensors are being increasingly installed in various devices, and an improvement in imaging performance is expected. The dynamic range of current CMOS image sensors is about three to four digits (60 dB to 80 dB), and it is desired to improve it to five to six digits (100 dB to 120 dB), which is equivalent to that of silver halide film or the human eye. To improve the dynamic range, methods such as switching the charge storage unit for imaging and performing analog data processing inside the pixel have been proposed. However, the former requires external control and a separate means for detecting illuminance and the like. Also, in the latter, since the number of transistors in the pixel increases, image degradation due to leakage current and noise of the transistor becomes a problem.

[0008] Therefore, one object of one aspect of the present invention is to provide an imaging device capable of expanding the dynamic range with a simple configuration. Or, one object is to provide an imaging device that changes the sensitivity of pixels after the first imaging and performs the second imaging. Or, one object is to provide an imaging device with low power consumption. Or, during the exposure period, the previous frame

[0009] ​​​​​​​​​ One of the purposes is to provide an imaging device that reads data. Or, noise One of the purposes is to provide an imaging device that can capture an image with less noise. Also One of the purposes is to provide an imaging device suitable for high-speed operation. Or, a high One of the purposes is to provide an imaging device with high resolution. Or, to provide an imaging device with high integration One of the purposes is to provide an imaging device that can capture an image under low illumination. Or, to provide an imaging device that can be used in a wide temperature range One of the purposes is to provide an imaging device with a high aperture ratio. Or, to provide an imaging device with high reliability. Or, to provide a novel imaging device or the like. Or, one of the purposes is to provide an operation method of the above imaging device. Or, to provide a novel semiconductor device or the like as one of the purposes. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention relates to an imaging device capable of automatically changing the sensitivity of pixels and capturing images. of.

[0012] One aspect of the present invention includes a first transistor to a sixth transistor, a photoelectric conversion element, and a first An imaging device having a first capacitive element and a second capacitive element, wherein one electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor, and one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, and the other of the source or drain of the first transistor is the third transistor is electrically connected to one of the source or drain of the third transistor, and the other of the source or drain of the first transistor is the fourth transistor is electrically connected to one of the source or drain of the fourth transistor, and the other of the source or drain of the first transistor is the fifth transistor is electrically connected to one of the source or drain of the fifth transistor, and the other of the source or drain of the first transistor is the fifth transistor is electrically connected to the gate electrode of the fifth transistor, and the other of the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, and the other of the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, and the other of the source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, and the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor, and the first transistor, the second transistor, the third transistor and the fourth transistor are characterized in that the region where the channel is formed has an oxide semiconductor. This is an imaging device.

[0013] The oxide semiconductor preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf). Also, the fifth transistor and the sixth transistor may also have an oxide semiconductor in the region where the channel is formed.

[0014] For the photoelectric conversion element, selenium or a compound containing selenium can be used for the photoelectric conversion layer. ​For example, as the selenium, amorphous selenium or crystalline selenium can be used.

[0015] Another aspect of the present invention is an imaging device having a pixel, a first circuit, a second circuit, a third circuit, a fourth circuit, and a fifth circuit, wherein the pixel is electrically connected to the first circuit, the first circuit is electrically connected to the second circuit, the second circuit is electrically connected to the third circuit, the second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The first circuit is electrically connected to the second circuit, the second circuit is electrically connected to the third circuit, the second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The second circuit is electrically connected to the third circuit, the second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The second circuit is electrically connected to the fourth circuit, the third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The third circuit is electrically connected to the fifth circuit, the fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The fifth circuit is electrically connected to the pixel, the pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The pixel has a function of acquiring first imaging data or second imaging data, the pixel has a function of accumulating the first imaging data or the second imaging data in a charge accumulation unit, the pixel has a function of transferring the first imaging data or the second imaging data accumulated in the charge accumulation unit to a charge detection unit, the first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The first circuit has a function of outputting a signal obtained by adding or subtracting the absolute value of the difference between the potential corresponding to the second imaging data and the potential corresponding to the reset potential of the charge detection unit with respect to a reference potential, the second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The second circuit has a function of determining whether the charge detection unit is saturated by the first imaging data, the third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The third circuit has a function of outputting, when it is determined that the charge detection unit is not saturated, a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. When it is determined that the charge detection unit is not saturated, the third circuit has a function of outputting a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. When it is determined that the charge detection unit is not saturated, the third circuit has a function of outputting a signal for not acquiring the second imaging data to the pixel via the fifth circuit, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting, when it is determined that the charge detection unit is saturated, a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. When it is determined that the charge detection unit is saturated, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. When it is determined that the charge detection unit is saturated, the third circuit has a function of eliminating the saturation of the charge detection unit and outputting a signal for acquiring the second imaging data to the pixel via the fifth circuit, and the second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data. The second circuit and the fourth circuit have a function of converting the signal output by the first circuit into digital data, and the imaging device is characterized in that.

[0016] Another aspect of the present invention is that in the nth (n is a natural number of 1 or more) frame period, the electric A first step of resetting the potential of the charge storage unit, a second step of storing charge in the charge storage unit, a third step of resetting the potential of the charge detection unit, a fourth step of transferring the potential of the charge storage unit to the charge detection unit, a fifth step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a sixth step of resetting the potential of the charge storage unit, a seventh step of storing charge in the charge storage unit, an eighth step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a ninth step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. A step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of resetting the potential of the charge detection unit, a step of transferring the potential of the charge storage unit to the charge detection unit, a step of reading out a signal corresponding to the potential of the charge detection unit and determining the presence or absence of saturation of the charge detection unit from the signal, are performed in the above order. In the fifth step, when it is determined that the charge detection unit is saturated, a step of resetting the potential of the charge storage unit, a step of storing charge in the charge storage unit, a step of temporarily increasing the capacitance of the charge detection unit to eliminate the saturation of the charge detection unit, and a step of transferring the potential of the charge storage unit to the charge detection unit, are performed in the above order. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the ninth step in the n-th frame period is read out. In the fifth step, when it is determined that the charge detection unit is not saturated, in parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. In parallel with the first step and the second step in the (n + 1)-th frame period, a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period is read out. This is a method of operating an imaging device, characterized by reading out a signal corresponding to the potential of the charge detection unit in the fourth step in the n-th frame period in parallel with the first step and the second step in the (n + 1)-th frame period. This is a method of operating an imaging device.

[0017] One aspect of the present invention is an imaging device having a first transistor to a seventh transistor, a photoelectric conversion element, a first capacitance element, a second capacitance element, and a third capacitance element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One aspect of the present invention is an imaging device having a first transistor to a seventh transistor, a photoelectric conversion element, a first capacitance element, a second capacitance element, and a third capacitance element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One aspect of the present invention is an imaging device having a first transistor to a seventh transistor, a photoelectric conversion element, a first capacitance element, a second capacitance element, and a third capacitance element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One aspect of the present invention is an imaging device having a first transistor to a seventh transistor, a photoelectric conversion element, a first capacitance element, a second capacitance element, and a third capacitance element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One aspect of the present invention is an imaging device having a first transistor to a seventh transistor, a photoelectric conversion element, a first capacitance element, a second capacitance element, and a third capacitance element. One electrode of the photoelectric conversion element is electrically connected to one of the source or drain of the first transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. One of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor. The other side of the in is electrically connected to one of the source or drain of the third transistor, and the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fourth transistor, and the other of the source or drain of the first transistor is electrically connected to the gate electrode of the fifth transistor, and the other of the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, and the other of the source or drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, and one of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the sixth transistor, and one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the sixth transistor, and one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the sixth transistor, and one of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the seventh transistor, and one of the source or drain of the fourth transistor is electrically connected to one electrode of the third capacitive element, and the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor have an oxide semiconductor in a region where a channel is formed, and the imaging device is characterized by this.

[0018] The oxide semiconductor preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). Also, the fifth transistor and the sixth transistor may also have an oxide semiconductor in a region where a channel is formed.

[0019] For the photoelectric conversion element, selenium or a compound containing selenium can be used for the photoelectric conversion layer. For example, as selenium, amorphous selenium or crystalline selenium can be used.

[0020] Another embodiment of the present invention is a semiconductor device including a pixel, a first circuit, a second circuit, a third circuit, and a third circuit. 4, and an imaging device having the circuit, The charge detection unit is electrically connected to the first capacitance element and the second capacitance element, and the pixel is a first circuit. the first circuit is electrically connected to a second circuit, the second circuit is electrically connected to a third circuit, the second circuit is electrically connected to a fourth circuit, and the third circuit is electrically connected to a pixel. The pixel is electrically connected to the first imaging data or the second imaging data. The pixel has a function of storing the first imaging data or the second imaging data in the charge storage section. The pixel detects the first imaging data or the second imaging data stored in the charge storage unit by charge detection. The first circuit has a function of transferring the electric potential corresponding to the second imaging data and a function of detecting the electric charge. The absolute value of the difference between the potential corresponding to the reset potential of the part is added to or subtracted from the reference potential. The second circuit has a function of detecting saturation of the charge detection unit by the first imaging data and outputting a signal obtained by the first imaging data. The third circuit has a function of judging whether the charge detection unit is saturated or not. and outputting a signal to the pixel to prevent conduction between the charge detection unit and one electrode of the second capacitance element. The third circuit has a function of disabling the charge detection unit when it is determined that the charge detection unit is saturated. a signal for connecting the first electrode of the second capacitor to the pixel; The pixel has a function of transferring the second imaging data from the charge storage unit to the charge detection unit after the determination. The second circuit and the fourth circuit convert the signal output by the first circuit into digital data. The imaging device is characterized by having the function of:

[0021] Also, another aspect of the present invention is that in the nth (n is a natural number of 1 or more) frame period, the electricity The first step of resetting the potential of the charge storage unit, the second step of storing charge in the charge storage unit, The third step of resetting the potential of the charge detection unit, the fourth step of transferring the potential of the charge storage unit to the charge Detection unit, reading a signal corresponding to the potential of the charge detection unit, and determining the presence or absence of saturation of the charge detection unit from the Signal, are performed in the above order, and in the fifth Step, when it is determined that the charge detection unit is saturated, the sixth step of increasing the capacitance of the charge detection unit, The seventh step of resetting the potential of the charge detection unit, are performed in the above order, and in the fifth step, when it is determined that the charge detection unit is not saturated, The seventh step is performed, and in parallel with the fifth step to the seventh step, the eighth step of resetting the potential of the charge storage unit, The ninth step of storing charge in the charge storage unit, are performed in the above order, the tenth step of transferring the potential of the charge storage unit to the charge detection unit Is performed, and in parallel with the first step and the second step in the (n + 1)th frame period, Reading a signal corresponding to the potential of the charge detection unit in the tenth step in the nth frame period. It is a method of operating an imaging device, characterized in that

Effect of the Invention

[0022] Imaging can be provided. Or, an imaging device with low power consumption can be provided It is possible. Or, an imaging device that reads data of the previous frame during the exposure period Can be provided. Or, an imaging device that reads data of the previous frame during the exposure period can be provided. Or, an imaging device capable of capturing an image with less noise can be provided. Or, an imaging device suitable for high-speed operation can be provided. Or, an imaging device with high resolution can be provided. Or, an imaging device with high integration can be provided. Or, an imaging device capable of capturing an image under low illuminance can be provided can be provided. Or, an imaging device that can be used in a wide temperature range can be provided can be provided. Or, an imaging device with a high aperture ratio can be provided. Or, a highly reliable imaging device can be provided. Or, a novel imaging device or the like can be provided. Also the operation method of the above imaging device can be provided. Or, a novel semiconductor device or the like can be provided.

[0023] Note that one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention in some cases, or depending on the situation, may also have effects other than these effects Or, for example, one aspect of the present invention, in some cases, or depending on the situation, may not have these effects.

Brief Description of Drawings

[0024]

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Mode for Carrying Out the Invention

[0025] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below. Note that the configuration of the invention described below is not limited to the description of the embodiments shown below. Note that the configuration of the invention described below In the following description, the same reference numerals are used for the same or similar parts in different drawings, and repeated descriptions thereof may be omitted. Note that the hatchings of the same elements constituting the drawings may be appropriately omitted or changed between different drawings. In addition, the ordinal numbers such as "first" and "second" are used for convenience only and do not indicate the order of steps or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and described. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify an aspect of the present invention. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is disclosed in this specification and the like that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also regarded as those described in the figure or the text.

[0026] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). As an example of the case where X and Y are directly connected, there is a case where an element (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode, a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y is not connected between X and Y.

[0027]

[0028]

[0029] ​​​​​​​​​​​​​element that enables electrical connection between X and Y (e.g., switch, transistor, capacitor element, inductor, resistor, diode, display element, light-emitting element, load, etc.), without passing through X and Y are connected.

[0030] As an example of the case where X and Y are electrically connected, an element that enables electrical connection between X and Y (e.g., switch, transistor, capacitor element, inductor, resistor, diode display element, light-emitting element, load, etc.) can be connected by one or more between X and Y. Note that the switch has a function of controlling on / off. That is, the switch becomes a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching the path through which current flows. Note that when X and Y are electrically connected, it shall include the case where X and Y are directly connected.

[0031] As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (e.g., logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion circuit (D / A conversion circuit, A / D conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), level shifter circuit that changes the potential level of a signal, etc.), voltage source, current source, switching circuit, amplifier circuit (circuit that increases the signal amplitude or current amount, etc., operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) can be connected by one or more between X and Y. ​​That is. As an example, even if there is another circuit between X and Y, when the signal output from X is transmitted to Y, X and Y shall be regarded as functionally connected. Note that when X and Y are functionally connected, it shall include the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0032] Note that when it is explicitly stated that X and Y are electrically connected, the case where X and Y are electrically connected (that is, when there is another element or another circuit between X and Y and they are connected), the case where X and Y are functionally connected (that is, when there is another circuit between X and Y and they are functionally connected), and the case where X and Y are directly connected (that is, when there is no other element or another circuit between X and Y and they are connected) shall be disclosed in this specification and the like. That is, when it is explicitly stated that they are electrically connected, it shall be regarded that the same content as when it is only explicitly stated that they are connected is disclosed in this specification and the like.

[0033] Note that, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z 2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. (or the first terminal, etc.) is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. It can be expressed as follows.

[0034] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." Using the same expression methods as these examples, by defining the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Or, as another expression method, for example, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path, and the second connection path is the path through the transistor from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor." By using the same expression methods as these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined.

[0035] Or, as another expression method, for example, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path, and the second connection path is the path through the transistor from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor, and the first connection path does not have a second connection path, and the second connection path is the path through the transistor from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) is a path between ) and , and the first connection path is a path via Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is a path via Z2. It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path and via Z1. The first connection path does not have the second connection path. The second connection path has a connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path and via Z2. The third connection path does not have the second connection path." It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first electrical path and via Z1. The first electrical path does not have the second electrical path. The second electrical path is an electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor. The drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path and via Z2. The third electrical path does not have the fourth electrical path. The fourth electrical path is an electrical path from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor." It can be expressed as "". By using an expression method similar to these examples to define the connection paths in the circuit configuration, the source (or the first terminal) of the transistor (or the second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is a path via Z2. It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path and via Z1. The first connection path does not have the second connection path. The second connection path has a connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path and via Z2. The third connection path does not have the second connection path." It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first electrical path and via Z1. The first electrical path does not have the second electrical path. The second electrical path is an electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor. The drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path and via Z2. The third electrical path does not have the fourth electrical path. The fourth electrical path is an electrical path from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor." It can be expressed as "". By using an expression method similar to these examples to define the connection paths in the circuit configuration, the source (or the first terminal) of the transistor (or the second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is a path via Z2. It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path and via Z1. The first connection path does not have the second connection path. The second connection path has a connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path and via Z2. The third connection path does not have the second connection path." It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first electrical path and via Z1. The first electrical path does not have the second electrical path. The second electrical path is an electrical path from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor. The drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third electrical path and via Z2. The third electrical path does not have the fourth electrical path. The fourth electrical path is an electrical path from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor." It can be expressed as "". By using an expression method similar to these examples to define the connection paths in the circuit configuration, the source (or the first terminal) of the transistor (or the second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is a path via Z2. It can be expressed as "". Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path and via Z1. The first connection path does not have the second connection path. The second connection path has a connection path via the transistor, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via at least the third connection path and via Z2. The third connection path does not have the second connection path." (or the second terminal, etc.) of the transistor is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is a path via Z2. distinguish between the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope is possible.

[0036] Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0037] Note that even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope. There may be a case where one component has the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope. For example, when a part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope. electrode. Therefore, the electrical connection in this specification refers to including such a case where one conductive film has the functions of multiple components within its scope. is also included in that category.

[0038] Note that the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases. Note that the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases. is possible.

[0039] Note that generally, potential (voltage) is relative and its magnitude is determined by the relative magnitude from a reference potential. Therefore, even when described as "ground", "GND", "ground", etc., it is not necessarily the case that the potential is 0 volts. is assumed. is not necessarily the case that the potential is 0 volts. For example, when defining "ground" or "GND" with reference to the lowest potential in a circuit, it is also the case. Or, there is also a case where "ground" or "GND" is defined with reference to a potential around the middle in a circuit. In that case, positive and negative potentials are defined with reference to that potential. And so on.

[0040] (Embodiment 1) In this embodiment, an imaging device which is an aspect of the present invention will be described with reference to the drawings.

[0041] One aspect of the present invention is a circuit configuration and an operation method of an imaging device capable of determining the saturation state of electrons in a charge detection unit provided in a pixel and changing an operation mode according to a determination result. First, first imaging data is acquired. When the charge detection unit is not saturated, the first imaging data is read out as it is. When the charge detection unit is saturated, the saturation of the charge detection unit is eliminated, and acquisition and readout of second imaging data are performed. The first imaging data corresponds to image data corresponding to low illuminance, and the second imaging data corresponds to image data corresponding to high illuminance. When the charge detection unit is saturated, the saturation of the charge detection unit is eliminated, and acquisition and readout of second imaging data are performed. The first imaging data corresponds to image data corresponding to low illuminance, and the second imaging data corresponds to image data corresponding to high illuminance. The first imaging data corresponds to image data corresponding to low illuminance, and the second imaging data corresponds to image data corresponding to high illuminance.

[0042] By the above operation, an image with a wide dynamic range with less noise and maintaining gradation can be acquired even under low illuminance. Also, in imaging in an environment including high illuminance, the gradation of the bright part can be maintained, and an image with a wide dynamic range can be acquired. By the above operation, an image with a wide dynamic range with less noise and maintaining gradation can be acquired even under low illuminance. Also, in imaging in an environment including high illuminance, the gradation of the bright part can be maintained, and an image with a wide dynamic range can be acquired. By the above operation, an image with a wide dynamic range with less noise and maintaining gradation can be acquired even under low illuminance. Also, in imaging in an environment including high illuminance, the gradation of the bright part can be maintained, and an image with a wide dynamic range can be acquired.

[0043] FIG. 1 is a circuit diagram of a pixel 10 included in an imaging device according to one aspect of the present invention. In FIG. 1 and the like, an example in the case where the transistor is an n-ch type is shown, but one aspect of the present invention is not limited to this, and some transistors may be replaced with p-ch type transistors. FIG. 1 is a circuit diagram of a pixel 10 included in an imaging device according to one aspect of the present invention. In FIG. 1 and the like, an example in the case where the transistor is an n-ch type is shown, but one aspect of the present invention is not limited to this, and some transistors may be replaced with p-ch type transistors. FIG. 1 is a circuit diagram of a pixel 10 included in an imaging device according to one aspect of the present invention. In FIG. 1 and the like, an example in the case where the transistor is an n-ch type is shown, but one aspect of the present invention is not limited to this, and some transistors may be replaced with p-ch type transistors.

[0044] In pixel 10, one electrode of the photoelectric conversion element PD is electrically connected to one of the source or drain of transistor 41. One of the source or drain of transistor 41 is electrically connected to one of the source or drain of transistor 42. The other of the source or drain of transistor 41 is electrically connected to one of the source or drain of transistor 43. The other of the source or drain of transistor 41 is electrically connected to one of the source or drain of transistor 44. The other of the source or drain of transistor 41 is electrically connected to the gate of transistor 45. The other of the source or drain of transistor 41 is electrically connected to one electrode of the capacitor element C1. The other of the source or drain of transistor 44 is electrically connected to one electrode of the capacitor element C2. One of the source or drain of transistor 45 is electrically connected to one of the source or drain of transistor 46.

[0045] Here, a node AN to which one electrode of the photoelectric conversion element PD, one of the source or drain of transistor 41, and one of the source or drain of transistor 42 are connected is used as a charge accumulation unit. Also, a node FD to which the other of the source or drain of transistor 41, one of the source or drain of transistor 4 3, one of the source or drain of transistor 44, the gate of transistor 45, and one electrode of the capacitor element C1 are connected is used as a charge detection unit.

[0046] The other electrode of the photoelectric conversion element PD is electrically connected to the wiring 71 (VPD). The transistor The other of the source or drain of the transistor 42 and the source or drain of the transistor 43 is electrically connected to the wiring 72 (VRS). The other electrode of the capacitor element C1 and the other electrode of the capacitor element C2 are electrically connected to the wiring 73 (VSS). The source or drain of the transistor 45 is electrically connected to the wiring 74 (VPI). The source or drain of the transistor 46 is electrically connected to the wiring 91 (OUT1).

[0047] In addition, in the connection form of each of the above elements, an example is shown in which a plurality of transistors or a plurality of capacitor elements share a wiring to be electrically connected, but each may be electrically connected to a different wiring.

[0048] The wiring 71 (VPD), the wiring 72 (VRS), the wiring 73 (VSS), and the wiring 74 (VP I) can have a function as a power supply line. For example, the wiring 71 (VPD) and the wiring 73 (VSS) can function as a low potential power supply line. The wiring 72 (VRS ) and the wiring 74 (VPI) can function as a high potential power supply line.

[0049] The gate of the transistor 41 is electrically connected to the wiring 61 (TX). The gate of the transistor 4 2 is electrically connected to the wiring 62 (GWRS). The gate of the transistor 43 is electrically connected to the wiring 63 (RS). The gate of the transistor 44 is the wiring 64 ( CN) is electrically connected. The gate of the transistor 46 is electrically connected to the wiring 65 (SE).

[0050] The wiring 61 (TX), the wiring 62 (GWRS), the wiring 63 (RS), the wiring 64 (CN) and ​​​The wiring 65 (SE) can function as a signal line that controls the conduction of the transistors to which they are respectively connected. The wiring 63 (RS) and the wiring 65 (SE) can be controlled on a per-row basis.

[0051] The transistor 41 can function as a transistor for transferring the potential of the node AN to the node FD. The transistor 42 can function as a transistor for resetting the potential of the node AN. The transistor 43 can function as a transistor for resetting the potential of the node FD. The transistor 44 can function as a transistor for controlling the electrical connection between the node FD and the capacitive element C2 and dividing the electrons accumulated in the node FD. The transistor 45 can function as a transistor for outputting according to the potential of the node FD. The transistor 46 can function as a transistor for selecting the pixel 10.

[0052] Note that the configuration of the pixel 10 described above is an example, and there may be cases where some circuits, some transistors, some capacitive elements, or some wirings are not included. Or, there may be cases where circuits, transistors, capacitive elements, wirings, etc. that are not included in the above-described configuration are included. Also, there may be cases where the connection form of some wirings is different from the above-described configuration.

[0053] FIG. 2(A) is a diagram for explaining an imaging device according to an aspect of the present invention. The imaging device includes a pixel array 11 having pixels 10 arranged in a matrix, a circuit 12 (load driver) having a function of driving the pixels 10, and CDS (Correlat with respect to the output signal of the pixel 10. A circuit 13 (CDS circuit) for performing a (correlated double sampling) operation, a circuit 14 (such as an A / D conversion circuit) having a function of determining the presence or absence of saturation of the node FD and converting the analog data output from the circuit 13 into digital data, a circuit 15 (column driver) having a function of selecting and reading out the data converted by the circuit 14, and a circuit 16 (pixel control circuit) for changing the operation mode of the pixel according to the presence or absence of saturation of the node FD. Note that the configuration without the circuit 13 can also be adopted.

[0054] FIG. 2(B) is a circuit diagram of the circuit 13 and a block diagram of the circuit 14 connected to one column of the pixel array 11. The circuit 13 can be configured to include a transistor 51, a transistor 52, a transistor 5 3, a capacitor element C3, and a capacitor element C4. Further, the circuit 14 can be configured to include a comparator circuit 17, a determination output circuit 18, and a counter circuit 19.

[0055] The transistor 54 has a function as a current source circuit. One of the source or drain of the transistor 54 is electrically connected to a wiring 91 (OUT1), and the other of the source or drain is connected to a power supply line. The power supply line can be, for example, a low-potential power supply line. Also, a bias voltage is constantly applied to the gate of the transistor 54.

[0056] In the circuit 13, one of the source or drain of the transistor 51 is electrically connected to one of the source or drain of the transistor 52. One of the source or drain of the transistor 51 is electrically connected to one electrode of the capacitor element C3. One of the source or drain of the transistor 52 ​​​​​​​​​The other of the source or drain is electrically connected to one of the source or drain of the transistor 53. The other of the source or drain of the transistor 52 is electrically connected to one of the electrodes of the capacitor element C4. The other of the source or drain of the transistor 52 is electrically connected to the wiring 9 2 (OUT2). The other of the source or drain of the transistor 53 and the other electrode of the capacitor element C3 are electrically connected to the wiring 91 (OUT1). The other of the source or drain of the transistor 51 is electrically connected to, for example, a high potential power supply line (CDSVDD) to which a reference potential is supplied. The other electrode of the capacitor element C4 is electrically connected to, for example, a low potential power supply line (CDSVSS).

[0057] An example of the operation of the circuit 13 when connected to the pixel 10 shown in FIG. 1 will be described. First, the transistors 51 and 52 are turned on. Next, the potential of the imaging data is output from the pixel 10 to the wiring 91 (OUT 1), and the reference potential (CDSVDD) is held on the wiring 92 (OUT2). Then, the transistor 51 is turned off, and a reset potential (here, a potential higher than the potential of the imaging data, for example, the VDD potential) is output from the pixel 10 to the wiring 91 (OUT1). At this time, the wiring 92 (OUT2) becomes a potential obtained by adding the absolute value of the difference between the potential of the imaging data and the reset potential to the reference potential (CDSVDD). Therefore, a potential signal with less noise, obtained by adding the potential of the net imaging data to the reference potential ( CDSVDD), can be supplied to the circuit 1 4. At this time, the wiring 92 (OUT2) becomes a potential obtained by adding the absolute value of the difference between the potential of the imaging data and the reset potential to the reference potential. Therefore, a potential signal with less noise, obtained by adding the potential of the net imaging data to the reference potential ( CDSVDD), can be supplied to the circuit 1 4. 4 can be supplied.

[0058] Note that when the reset potential is a potential lower than the potential of the imaging data (for example, the GND potential, etc.), the wiring 92 (OUT2) is the absolute value of the difference between the potential of the imaging data and the reset potential with respect to the reference potential. In the case of, the wiring 92 (OUT2) is the absolute value of the difference between the potential of the imaging data and the reset potential with respect to the reference potential. It becomes the potential subtracted from the bit (CDSVDD).

[0059] Also, when the transistor 53 is turned on, a bypass is formed, so the signal of the wiring 91 (OU T1) can be directly output to the wiring 92 (OUT2).

[0060] In the circuit 14, in the comparator circuit 17, the signal potential input from the circuit 13 and the reference potential (REF) are compared. To the comparator circuit 17, the signal potential corresponding to the first imaging data or the second imaging data is input via the wiring 92 (OUT2). Here, the first imaging data is the data of the first exposure, and is the data for determining the presence or absence of saturation of the node FD of the pixel 10. Also, the second imaging data is the second exposure data obtained according to the determination. First, when the first imaging data is input, the comparator circuit 17 outputs a determination result to the determination output circuit 18. The determination output circuit 18 has a function of adjusting the output timing and removing the noise output from the comparator circuit 1 7.

[0061] In the comparator circuit 17, it is determined whether or not the first imaging data saturates the node FD of the pixel 10. At this time, the reference potential (REF) input to the comparator circuit 17 is a constant potential corresponding to the saturation of the node FD, and the presence or absence of saturation is determined by comparing the potential with the signal potential corresponding to the first imaging data. In this embodiment, the signal potential corresponding to the first imaging data is configured to bypass the circuit 13 and input to the comparator circuit 1

[0062] 7, but it may be input to the comparator circuit 17 without bypassing the circuit 13. is input to the comparator circuit 17 without bypassing the circuit 13. By comparing the potential with the signal potential corresponding to the first imaging data, the presence or absence of saturation is determined. In this embodiment, the signal potential corresponding to the first imaging data is configured to bypass the circuit 13 and input to the comparator circuit 1 7, but it may be input to the comparator circuit 17 without bypassing the circuit 13. ​This is also fine.

[0063] If it is determined that the node FD is not saturated, the decision output circuit 18 outputs the second imaging data The signal not to be acquired is output to the circuit 16. Therefore, the signal voltage corresponding to the first imaging data is The value is input to the comparator circuit 17 via the circuit 13. The reference potential input to the first imaging data is a ramp wave, and is compared with the signal potential corresponding to the first imaging data. The result is output to the counter circuit 19. The counter circuit 19 then outputs the result to the wiring 94 (O The digital data corresponding to the first imaging data is output to the UT4).

[0064] If it is determined that the node FD is saturated, the decision output circuit 18 acquires the second imaging data. The circuit 16 outputs a signal to the pixel 10 to obtain second image data. The signal potential corresponding to the second image data is compared through a circuit 13. The reference potential input to the comparator circuit 17 is a ramp potential. The result of comparing the potential of the second image data with the potential of the signal corresponding to the second imaging data is output to the counter circuit 19. Then, the counter circuit 19 outputs the second imaging data to the wiring 94 (OUT4). The corresponding digital data is output.

[0065] The decision output circuit 18 may be, for example, a circuit shown in FIG. The input terminal (IN) is electrically connected to the output terminal of the comparator circuit 17. The output terminal (OUT) of the circuit is electrically connected to a wiring 93 (OUT3). The circuit 18 is reset by the JRES signal for each selected row, and then the comparator circuit The result of the determination in step 17 is output to circuit 16.

[0066] For circuit 16, for example, the circuit shown in FIG. 3(B) can be used. The input terminal (IN) of the circuit is electrically connected to wiring 93 (OUT3). Also, there are two output terminals of the circuit ( OUT), one of which is electrically connected to wiring 61 (TX), and the other is electrically connected to wiring 64 ( CN). From the circuit to wiring 61 (TX), one of the signals input to terminal TX1 or terminal TX2 is output. Also, from the circuit to wiring 64 (CN), one of the signals input to terminal CN1 or terminal CN2 is output. Note that a control signal is input to terminal GCN N, and the signals output from wiring 61 (TX) and wiring 64 (CN) can also be fixed. Since circuit 16 has a latch function, when it is determined that node FD is saturated , the signal output from determination output circuit 18 is held by circuit 16. Therefore, even if the determination is repeated until the last line, the signal is held.

[0067] The above-described circuit can be operated according to the timing chart shown in FIG. 4. In FIG. 4 , RCK1 / 2 and RCKB1 / 2 shown are clock signals and inverted clock signals input to circuit 12 (load driver), JRES is a signal input to the circuit in FIG. 3(A), GRES and JENB are signals input to the circuit in FIG. 3(B), EN_CDS is a signal input to the gate of transistor 53 of circuit 13, SE[1] is a signal input to wiring 65 of pixel 10 in the first row , and SE[N] is a signal input to wiring 65 of pixel 10 in the last row.

[0068] The period indicated by frame[n] corresponds to the period of the nth frame (n is a natural number of 2 or more). ​​​In the n-th frame, period 401 is the period for reading the data of the (n-1)-th frame, and period 4 02 is the period for reading the above-described first imaging data and making a determination, and period 400 is the period when the row driver does not operate. Also, in the (n+1)-th frame, period 403 is the period for reading the data of the n-th frame.

[0069] Next, the operation of the pixel 10 shown in FIG. 1 will be described using the flowchart shown in FIG. 5 and the timing chart shown in FIG. 6. The imaging device according to one aspect of the present invention operates in a global shutter mode, and the operations within one frame are roughly classified into acquisition of first imaging data, determination of the first imaging data , acquisition of second imaging data, and reading of the imaging data of the previous frame. Note that the acquisition of the first imaging data and the reading of the imaging data of the previous frame are performed in parallel. In FIGS. 5 and 6, the description will be made with reference to an arbitrary n-th frame. Also, the wiring 71 (VP

[0070] D) and the wiring 73 (VSS) are at a low potential ("L"), and the wiring 72 (VRS) and the wiring 74 (VPI) are at a high potential ("H"). Also, in FIG. 6, GWRS is the potential of the wiring 62 (GWRS), RS[1] is the potential of the wiring 63 (RS) at a specific pixel 10 in the first row

[0071] , RS[N] is the potential of the wiring 63 (RS) at a specific pixel 10 in the last row , CN is the potential of the wiring 64 (CN), TX is the potential of the wiring 61 (TX )), AN[1] is the potential of the node AN at a specific pixel 10 in the first row , AN[N] is the potential of the node AN at a specific pixel 10 in the last row, FD[1] is the potential of the node FD at a specific pixel 10 in the first row , and FD[N] is the potential of the node FD at a specific pixel 10 in the last row.

[0072] First, the acquisition of the first imaging data and the reading of the imaging data acquired in the previous frame will be described.

[0073] The imaging mode of the first imaging data has a relatively long exposure time, and an image with a wide dynamic range can be obtained in a low illuminance environment. On the other hand, since the exposure time is relatively long, the node FD saturates in a high illuminance environment. Note that the timing chart in FIG. 6 shows the operation when the node FD is saturated in the determination of the first imaging data.

[0074] At time T1, when GWRS is set to "H", AN[1:N] is reset to "H" (the potential of wiring 72 (VRS)) (S1).

[0075] At time T2, when GWRS is set to "L", AN[1:N] starts to decrease according to the illuminance (the first exposure, S2).

[0076] At time T3, when RS[1:N] is set to "H" and CN is set to "H", FD[1:N] is reset to "H" (the potential of wiring 72 (VRS)) (S3). At this time, the capacitor element C2 is electrically connected to the node FD via the transistor 44.

[0077] At time T4, when RS[1:N] is set to "L", CN is set to "L", and TX is set to "H", the electrical connection between the node FD and the capacitor element C2 is disconnected, and the potential of the node FD at the time of reset is held in the capacitor element C2. Also, the potential of the node AN is transferred to the node FD, and the potential of the node FD starts to decrease (S4).

[0078] ​​​​​​​​At time T5, if TX is set to "L", FD[1:N] is retained. This is the acquisition operation of the imaging data of the first frame.

[0079] Here, between times T1 to T3, SE[1] to SE[N] sequentially become "H" for a certain period, and the imaging data determined in the (n - 1)-th frame is read out (S10'). That is, the acquisition operation of the first imaging data of the n-th frame and the reading of the imaging data determined in the (n - 1)-th frame are performed in parallel. By reading the imaging data in the next frame in this way, even in the global shutter method, the time allocated for exposure and the like can be lengthened. Therefore, an image with a wide dynamic range and low noise can be obtained even under low illuminance.

[0080] FIG. 7(A) is a timing chart for explaining the reading of the imaging data of the first row. SH is the potential supplied to the gate of transistor 52 in circuit 13, CL is the potential supplied to the gate of transistor 51 in circuit 13, REF(RAMP) is the reference potential supplied to comparator circuit 17, OUT2 is the potential of wiring 92(OUT2), and COMP_OUT is the potential of the output terminal of comparator circuit 17.

[0081] In FIG. 6, before time T3, RS[1] to RS[N] sequentially become "H" for a certain period, and node FD is reset, which is an operation accompanying the operation of circuit 13 shown in FIG. 7(A).

[0082] Next, the determination of the first imaging data and the operations accompanying the determination result will be described.

[0083] At times T6 to T8, SE[1] to SE[N] sequentially become "H" for a fixed period, and for each row, the first imaging data is read out, and for all valid pixels, the presence or absence of saturation of the node FD is determined (S5).

[0084] FIG. 7(B) is a timing chart explaining the readout of the first imaging data at times T6 to T8. During the readout period of the first imaging data, EN_CDS is set to "H" and CL is set to "H", and the signal output from pixel 10 bypasses circuit 13 and is input to the comparator circuit 17. The potential of REF(CONST) is kept constant, and when the node FD is saturated, it is set to a value slightly larger than the potential output to the wiring 91 (OUT1). By operating in this way, the presence or absence of saturation of the node FD can be determined by the output of the comparator circuit 17. Note that FIG. 7(B) shows the state when the node FD of the selected specific pixel 10 is saturated, and an "L" is output from the output terminal of the comparator circuit 17. Note that the first imaging data may be read out without bypassing circuit 13 by setting EN_CDS to "L". At this time, an "H" is output from the output terminal of the comparator circuit 17. At this time, the first imaging data is used to determine the presence or absence of saturation of the node FD and is not output to the outside. Therefore, the operation of the output circuit such as circuit 15 (column driver) required for external output may be stopped. The determination result of the first imaging data is output to circuit 16 via the determination output circuit 18. Here, since the output terminals of the determination output circuits 18 of each column are all connected to the wiring 93 (OUT3),

[0085]

[0086] If it is determined that the node FD is saturated in even one of all the pixels 10, the circuit 16 performs an operation of setting CN to "H" and TX to "H" at the specified time, and switches to a mode of acquiring second imaging data . This is the operation for determining the first imaging data and the operation associated with the determination result .

[0087] Next, the acquisition of the second imaging data will be described. Note that the imaging mode of the second imaging data has a relatively short exposure time, and an image with a wide dynamic range can be obtained in a high illuminance environment .

[0088] Regardless of the determination result of the first imaging data, or even if the exposure operation for acquiring the second imaging data is performed before all the determination results are obtained. For example, as shown in FIG. 6, at time T7 GWRS is set to "H" and AN[1:N] is reset (S6). Then, at time T 8, GWRS is set to "L", and the second exposure is performed by time T10 (S7). Note that in the second exposure, the exposure time is made shorter than that of the first exposure so that the node FD does not saturate .

[0089] At time T9 before the second exposure ends, CN is set to "H" by the operation of the circuit 16, and the transistor 44 is turned on to electrically connect the node FD and the capacitive element C2 again

[0090] Just before time T9, the node FD is in a state where electrons are saturated, that is, the voltage is 0 state. However, since the capacitive element C2 that holds the potential at the time of resetting the node FD is electrically connected at time T9, the accumulated electrons are divided and the potential of the node FD rises (S8) .

[0091] At time T10, when the circuit 16 operates to set CN to "L" and TX to "H", the potential of node AN is transferred to node FD (S9).

[0092] At time T11, when TX is set to "L", FD[1:N] is held. This is the operation to acquire the second imaging data. Also, the second imaging data is read out as the imaging data of the nth frame in the (n + 1)th frame (S10).

[0093] FIG. 8 is a timing chart when it is determined that there is no saturation of node FD due to the first imaging data. When the nodes FD of all pixels 10 are not saturated, the circuit 16 does not perform the operation of setting CN and TX to "H". That is, it does not switch to the mode of acquiring the second imaging data. Therefore, the data acquired as the first imaging data is read out as it is. When it is determined that there is no saturation of node FD, the operation of setting GRS to "H" at times T7 to T8 may be disabled, and the second exposure may not be performed. Note that, as described above, the imaging device according to one aspect of the present invention operates in a global shutter method. Therefore, when it is determined that even one of the nodes FD of all pixels 10 is saturated, it switches to the mode of acquiring the second imaging data, and thus the second imaging data is acquired for all pixels 10.

[0094] Note that, as described above, the imaging device according to one aspect of the present invention operates in a global shutter method. Therefore, when it is determined that even one of the nodes FD of all pixels 10 is saturated, it switches to the mode of acquiring the second imaging data, and thus the second imaging data is acquired for all pixels 10.

[0095] By the above operation, the second imaging data can be automatically acquired as necessary, and the gradation of the bright part can be maintained even in imaging of a field where light and dark are mixed. That is, an image with a wide dynamic range can be acquired. Also, noise is reduced even under low illuminance. This allows for the acquisition of images with a wide dynamic range and with low image noise and with well-maintained gradation.

[0096] The pixel 10 may have a configuration as shown in Fig. 9. The pixel 10 shown in Fig. 9 has a photoelectric conversion element PD The pixel 10 shown in FIG. 9 has a different connection direction from that of the pixel 10 shown in FIG. 12 (with acquisition of the second imaging data) or the timing chart of FIG. 2 (no image data is acquired). PD) and wiring 74 (VPI) are at high potential ("H"); wiring 72 (VRS) and wiring 73 ( VSS) is set to low potential ("L").

[0097] In this case, nodes AN and FD are saturated with electrons at the time of reset, and If the current flows through the node AN and the node FD, the electrons in the nodes AN and FD become insufficient. The potentials of the nodes AN and FD change in a manner opposite to that of the pixel 10 shown in FIG. do.

[0098] The pixel 10 may have a configuration as shown in FIGS. 10(A) and 10(B). In this configuration, the transistor 42 is not provided. By doing so, the potential of the node AN can be reset. Either the source or the drain of the transistor 45 is connected to the wiring 91 (OUT).

[0099] The transistor used in the pixel 10 is, as shown in FIGS. A back gate may be provided for the transistors 41 to 46. ) is a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. 。In FIG. 13(A), as an example, wiring 71 (VPD) that supplies a low potential to the back gate is shown connected to wiring 73 (VSS) or wiring 75 (VSS2), but it may be configured to be connected to any one of the wirings. Further, FIG. 13(B) shows a configuration in which the same potential as the front gate is applied to the back gate, which can increase the on-current and decrease the off-current. Also, as a configuration that combines the configurations of FIGS. 13(A) and 13(B) so that the desired transistor has appropriate electrical characteristics. Note that there may be a transistor without a back gate. Further, the configurations of FIGS. 9, 10(A), (B), and 13(A), (B) can be combined as necessary.

[0100] As shown in FIG. 14, the pixel 10 may be configured such that transistors 43 to 46 are shared among a plurality of pixels. FIG. 14 illustrates a configuration in which transistors 43 to 46 are shared among a plurality of pixels in the vertical direction, but they may be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. By adopting such a configuration, the number of transistors per pixel can be reduced.

[0101] Also, in FIG. 14, a form in which transistors 43 to 46 are shared among 4 pixels is shown, but they may be shared among 2 pixels, 3 pixels, or 5 or more pixels. Note that this configuration and the configurations of FIGS. 9, 10(A), (B), and 13(A), (B) can be arbitrarily combined.

[0102] Also, an imaging device according to an aspect of the present invention includes a pixel array 11 and circuits 12 to 16. It can be formed into a stacked structure with the substrate 35. For example, when FIG. 15(A) is a top view of the pixel array 11 and FIG. 15(B) is a top view of the substrate 35, it can be formed into a stacked configuration of the pixel array 11 and the substrate 35 as shown in the front view of FIG. 15(C). By adopting such a configuration, transistors suitable for respective elements can be used, and the area of the imaging device can be reduced. Note that the circuit layout in FIG. 15(B) is an example, and other layouts may be used. When FIG. 15(A) is a top view of the pixel array 11 and FIG. 15(B) is a top view of the substrate 35, it can be formed into a stacked configuration of the pixel array 11 and the substrate 35 as shown in the front view of FIG. 15(C). By adopting such a configuration, transistors suitable for respective elements can be used, and the area of the imaging device can be reduced. By adopting such a configuration, transistors suitable for respective elements can be used, and the area of the imaging device can be reduced. Note that the circuit layout in FIG. 15(B) is an example, and other layouts may be used. Note that the circuit layout in FIG. 15(B) is an example, and other layouts may be used.

[0103] In order to achieve both high-speed operation and a CMOS circuit configuration, Circuits 12 to 16 are preferably formed using transistors using silicon (hereinafter referred to as Si transistors). For example, the substrate 35 can be a silicon substrate, and the above circuits can be formed on the silicon substrate. In order to achieve both high-speed operation and a CMOS circuit configuration, Circuits 12 to 16 are preferably formed using transistors using silicon (hereinafter referred to as Si transistors). For example, the substrate 35 can be a silicon substrate, and the above circuits can be formed on the silicon substrate. In order to achieve both high-speed operation and a CMOS circuit configuration, Circuits 12 to 16 are preferably formed using transistors using silicon (hereinafter referred to as Si transistors). For example, the substrate 35 can be a silicon substrate, and the above circuits can be formed on the silicon substrate. The pixel array 11 is preferably formed using transistors using an oxide semiconductor (hereinafter referred to as OS transistors). Note that some of the transistors included in Circuits 12 to 16 may be provided on the same surface as the pixel array 11. The pixel array 11 is preferably formed using transistors using an oxide semiconductor (hereinafter referred to as OS transistors). Note that some of the transistors included in Circuits 12 to 16 may be provided on the same surface as the pixel array 11. The pixel array 11 is preferably formed using transistors using an oxide semiconductor (hereinafter referred to as OS transistors). Note that some of the transistors included in Circuits 12 to 16 may be provided on the same surface as the pixel array 11.

[0104] A specific configuration example of the imaging device according to an aspect of the present invention will be described with reference to the drawings. The cross-sectional view shown in FIG. 16(A) shows an example of a specific connection form of the photoelectric conversion element PD, the transistor 41, the transistor 43, and the capacitor element C1 in the pixel 10 shown in FIG. 1. Note that the transistors 42, 44, 45, 46, and the capacitor element C2 are not shown in FIG. 16(A). The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200. The cross-sectional view shown in FIG. 16(A) shows an example of a specific connection form of the photoelectric conversion element PD, the transistor 41, the transistor 43, and the capacitor element C1 in the pixel 10 shown in FIG. 1. Note that the transistors 42, 44, 45, 46, and the capacitor element C2 are not shown in FIG. 16(A). The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200. Note that the transistors 42, 44, 45, 46, and the capacitor element C2 are not shown in FIG. 16(A). The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200. Note that the transistors 42, 44, 45, 46, and the capacitor element C2 are not shown in FIG. 16(A). The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200. The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200. The transistors 41 to 46 and the capacitor elements C1 and C2 can be provided in the layer 1100, and the photoelectric conversion element PD can be provided in the layer 1200.

[0105] In the cross-sectional views described in this embodiment, wiring, electrodes and contact plugs (conductors 8 1) are illustrated as separate elements, but when they are electrically connected In some cases, the wiring and the electrodes are connected via a conductor 81. The above embodiment is merely an example, and the electrodes may be directly connected to the wiring.

[0106] On each element, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film, and An insulating layer 83 and the like are provided. For example, the insulating layer 82 and the insulating layer 83 and the like are made of a silicon oxide film. Alternatively, an inorganic insulating film such as an acrylic resin film or a silicon oxynitride film can be used. An organic insulating film such as polyimide resin may be used. The top surface is polished by CMP (Chemical Mechanical Polish) if necessary. It is preferable to perform a planarization process by a planarization method or the like.

[0107] In addition, in some cases, wiring, etc., not shown in the drawings may not be provided, or wiring, etc., not shown in the drawings may not be provided. Each layer may contain transistors, etc. Also, layers not shown in the drawing may be included. Also, some layers shown in the drawings may not be included.

[0108] The transistors 41 to 46, which are components of the pixel 10, each have a low off-state current. It is preferable to use an OS transistor. OS transistors have extremely low off-state current characteristics. Since the pixel 10 shown in FIG. In this circuit configuration, when the intensity of light incident on the photoelectric conversion element PD is high, the nodes AN and The potential of the node FD is reduced. is low, even when the gate potential is extremely small, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened.

[0109] In addition, due to the low off-current characteristics of transistor 41, transistor 42, transistor 43, and transistor 44 the period during which charges can be held at node AN and node FD can be made extremely long. Therefore, without complicating the circuit configuration or the operation method, a global shutter method in which all pixels simultaneously perform a charge accumulation operation can be applied. Note that the imaging device according to one aspect of the present invention can also be operated in a rolling shutter method.

[0110] The operation method of the imaging device will be described with reference to FIGS. 17(A), (B), and (C). Note that in FIGS. 17 (A), (B), and (C), "E" represents a period during which an exposure operation can be performed, and "R" represents a period during which a readout operation can be performed. Also, n represents the nth frame (n is a natural number of 2 or more) of an arbitrary nth frame. Also, n - 1 represents the frame immediately before the nth frame, and n + 1 represents the frame immediately after the nth frame. Also, Line[1] represents the first row of pixel array 1 1, and Line[M] represents the Mth row of pixel array 11 (M is a natural number of 4 or more in FIG. 17) .

[0111] FIG. 17(A) is a diagram schematically showing the operation method of the rolling shutter method. The rolling shutter method is an operation method in which exposure and data readout are sequentially performed for each row. Since there is no simultaneity in imaging for all pixels image distortion occurs in imaging of moving objects.

[0112] FIG. 17(B) is a diagram schematically showing an operation method of a normal global shutter system. The global shutter system is an operation method in which all pixels are exposed simultaneously and data is read out for each row thereafter. Therefore, even when imaging a moving object, an image without distortion can be obtained.

[0113] FIG. 17(C) is a diagram schematically showing an operation method applied to an imaging device according to an aspect of the present invention. In this operation method, all pixels are simultaneously exposed in the n-th frame, and the data acquired in the n-th frame is read out in the (n + 1)-th frame. Therefore, since exposure and readout of the same frame are not performed within one frame period, the exposure time is not limited due to an increase in the readout time as in the conventional global shutter system. Therefore, the exposure time can be lengthened.

[0114] Since the OS transistor has a smaller temperature dependence of electrical characteristic variations than a transistor using silicon for an active region or an active layer, it can be used in an extremely wide temperature range. Therefore, imaging devices and semiconductor devices having an OS transistor are also suitable for mounting on automobiles, airplanes, spacecraft, etc.

[0115]

[0116] In a photoelectric conversion element having a selenium-based material as a photoelectric conversion layer, it is preferable to operate by applying a relatively high voltage (for example, 10 V or more) in order to utilize avalanche multiplication. Therefore, by combining an OS transistor and a photoelectric conversion element having a selenium-based material as a photoelectric conversion layer, a highly reliable imaging device can be obtained.

[0116] In FIG. 16(A), each transistor is illustrated in a form having a back gate. As shown in FIG. 16(B), it may be in a form without a back gate. Also, in FIG. 16 (C), it may be in a form in which only some transistors, for example, only transistor 41, have a back gate. The back gate may be electrically connected to the front gate of the opposing transistor. Or, a fixed potential different from the front gate may be supplied to the back gate. Note that the form regarding the presence or absence of the back gate can also be applied to the configurations of other pixels described in this embodiment mode. The photoelectric conversion element PD provided in layer 1200 can use various forms of elements. In FIG. 16(A), a form in which a selenium-based material is used for the photoelectric conversion layer 561 is illustrated. The photoelectric conversion element PD using a selenium-based material

[0117] has the characteristic of high external quantum efficiency with respect to visible light. Also, since the selenium-based material has a high light absorption coefficient, it has the advantage of easily thinning the photoelectric conversion layer 561. In the photoelectric conversion element PD using a selenium-based material, it can be made into a highly sensitive sensor with large amplification by avalanche multiplication. That is, by using a selenium-based material for the photoelectric conversion layer 561, even if the pixel area is reduced, a sufficient photocurrent can be obtained. Therefore, it can be said that the photoelectric conversion element PD using a selenium-based material is also suitable for imaging in a low illuminance environment. As the selenium-based material, amorphous selenium or crystalline selenium can be used. Crystalline selenium can be obtained, for example, by heat-treating after forming a film of amorphous selenium.

[0118] ​​​​​​By making the crystal grain size smaller than the pixel pitch, it is possible to reduce the characteristic variation for each pixel. In addition, crystalline selenium has characteristics such as higher spectral sensitivity and light absorption coefficient for visible light than amorphous selenium.

[0119] In FIG. 16(A), the photoelectric conversion layer 561 is shown as a single layer, but as shown in FIG. 18(A), gallium oxide, cerium oxide, or In-Ga-Zn oxide or the like may be provided as a hole injection blocking layer 568 on the light receiving surface side. Alternatively, as shown in FIG. 18(B), nickel oxide or antimony sulfide or the like may be provided as an electron injection blocking layer 569 on the electrode 566 side. Alternatively, as shown in FIG. 18(C), a configuration in which a hole injection blocking layer 568 and an electron injection blocking layer 569 are provided may be adopted. Note that, as shown in FIGS. 1 and 9, in the pixel 10, the connection direction of the photoelectric conversion element PD can be different. Therefore, the hole injection blocking layer 568 and the electron injection blocking layer 569 shown in FIGS. 18(A) to 18(C) may be interchanged.

[0120] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element utilizing avalanche multiplication can be formed in the same manner as a single layer of selenium.

[0121] The photoelectric conversion element PD using a selenium-based material can be configured to have a photoelectric conversion layer 561 between an electrode 566 formed of a metal material or the like and a transparent conductive layer 562, for example. In addition, CIS and CIGS are p-type semiconductors, and an n-type semiconductor sulfide is required to form a junction.​​​​​​​​ It may be provided in contact with cadmium, zinc sulfide, or the like.

[0122] In FIG. 16(A), the transparent conductive layer 562 and the wiring 71 are configured to be in direct contact, but as shown in FIG. 19 (A), they may be configured to be in contact with each other via the wiring 88. Also, in FIG. 16(A ), the photoelectric conversion layer 561 and the transparent conductive layer 562 are not separated between pixel circuits , but as shown in FIG. 19(B), they may be configured to be separated between circuits. Also, between pixels , a partition wall 567 is provided as an insulator in a region without the electrode 566 to prevent cracks from occurring in the photoelectric conversion layer 561 and the transparent conductive layer 562, but as shown in FIGS. 19(C , (D), a configuration without the partition wall 567 may also be used.

[0123] Also, the electrode 566, the wiring 71, etc. may be multilayered. For example, as shown in FIG. 20(A) , the electrode 566 may be made of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 71 may be made of two layers, a conductive layer 71a and a conductive layer 71b. In the configuration of FIG. 20(A), , for example, the conductive layer 566a and the conductive layer 71a are formed by selecting a low-resistance metal or the like, and the conductive layer 566b and the conductive layer 71b are formed by selecting a metal or the like with good contact characteristics with the photoelectric conversion layer 561 . By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved . Also, some metals may cause electrolytic corrosion when in contact with the transparent conductive layer 562. Even when such a metal is used for the conductive layer 71a, electrolytic corrosion can be prevented by passing through the conductive layer 71b .

[0124] For the conductive layer 566b and the conductive layer 71b, for example, molybdenum, tungsten, or the like is used It is possible. Further, for the conductive layer 566a and the conductive layer 71a, for example, aluminum , titanium, or a laminate such as aluminum sandwiched by titanium can be used.

[0125] Further, as shown in FIG. 20(B), the translucent conductive layer 562 and the wiring 71 may be connected via the conductor 81 and the wiring 88. Also, the insulating layer 82 or the like may have a multi-layer structure. For example, as shown in FIG. 20(B), the insulating layer 82 has the insulating layer 82a and the insulating layer 82b , and when the etching rate or the like of the insulating layer 82a and the insulating layer 82b is different, the conductor 81 will have a step. Similarly, when other insulating layers used for the interlayer insulating film or the planarization film are multi-layered , the conductor 81 will have a step. Here, an example where the insulating layer 82 has two layers is shown, but the insulating layer 82 and other insulating layers may have a structure of three or more layers. The partition wall 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. Also, the partition wall 567

[0126] may be colored black or the like to block light from the transistor or the like and / or to determine the area of the light receiving portion per pixel.

[0127] Further, for the photoelectric conversion element PD, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. For example, FIG. 21 shows an example in which a pin-type thin film photodiode is used for the photoelectric conversion element PD.

[0128] It is preferable to use silicon. Also, for the p-type semiconductor layer 563 and the n-type semiconductor layer 5 65, amorphous silicon or microcrystalline silicon containing a dopant that imparts each conductivity type can be used. A photodiode having an amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and is easy to detect weak visible light.

[0129] In the photoelectric conversion element PD shown in FIG. 21, the n-type semiconductor layer 565 acting as a cathode is in contact with an electrode 566 having an electrical connection with the transistor 41. Also, the p-type semiconductor layer 563 acting as an anode is electrically connected to the wiring 71 via the wiring 88.

[0130] Note that if the connection forms between the anode and cathode of the photoelectric conversion element PD and the electrode layer and the wiring are reversed, a configuration according to the circuit diagram shown in FIG. 9 can be obtained.

[0131] In any case, it is preferable to form the photoelectric conversion element PD such that the p-type semiconductor layer 563 becomes the light-receiving surface. By using the p-type semiconductor layer 563 as the light-receiving surface, the output current of the photoelectric conversion element PD can be increased.

[0132] Also, the configuration of the photoelectric conversion element PD having the form of a pin-type thin film photodiode, as well as the connection form between the photoelectric conversion element PD and the wiring may be as shown in FIGS. 22(A), (B), and (C). Note that the configuration of the photoelectric conversion element PD and the connection form between the photoelectric conversion element PD and the wiring are not limited to these and may be other forms.

[0133] FIG. 22(A) shows a transparent conductive layer 562 in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD. It is configured to provide. The translucent conductive layer 562 acts as an electrode and increases the output current of the photoelectric conversion element PD.

[0134] For the translucent conductive layer 562, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, graphene or graphene oxide etc. can be used. Also, the translucent conductive layer 562 is not limited to a single layer and may be a laminate of different films.

[0135] FIG. 22(B) shows a configuration in which the translucent conductive layer 562 and the wiring 71 are connected via the conductor 81 and the wiring 88. Note that the p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 71 may be connected via the conductor 81 and the wiring 88. In FIG. 22(B), it is also possible to adopt a configuration in which the translucent conductive layer 562 is not provided. In FIG. 22(B), a configuration in which the translucent conductive layer 562 is not provided is also possible.

[0136] FIG. 22(C) shows a configuration in which an opening portion where the p-type semiconductor layer 563 is exposed is provided in the insulating layer covering the photoelectric conversion element PD, and the translucent conductive layer 562 covering the opening portion and the wiring 71 have an electrical connection.

[0137] Also, as shown in FIG. 23, a photodiode in which a silicon substrate 600 is used as a photoelectric conversion layer can be used for the photoelectric conversion element PD.

[0138] The photoelectric conversion element PD formed using the above-described selenium-based materials, amorphous silicon, etc. is manufactured using general semiconductor manufacturing processes such as a film formation process, a lithography process, and an etching process. ​​​​​This is possible. Also, the selenium-based material has a high resistance, and as shown in Fig. 16(A), the photoelectric conversion layer 561 can be configured not to be separated between circuits. Therefore, the imaging device according to one aspect of the present invention has a high yield and can be manufactured at low cost. On the other hand, when forming a photodiode with the silicon substrate 600 as the photoelectric conversion layer, high-difficulty processes such as a polishing process and a bonding process are required. Moreover, the imaging device according to one aspect of the present invention may have a configuration in which a silicon substrate 600 on which circuits are formed is laminated. For example, as shown in Fig. 24(A), a layer 1400 having transistors 610 and 620 having active regions on the silicon substrate 600 can be configured to overlap with the pixel circuit. Fig. 24(B) corresponds to a cross-sectional view in the channel width direction of the transistor. Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). The circuit formed on the silicon substrate 600 can have functions such as reading out the signal output from the pixel circuit and performing processing for converting the signal. For example, it can be configured to include a CMOS inverter shown in the circuit diagram in Fig. 25(C). The gates of the transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected.

[0139] In addition, the imaging device according to one aspect of the present invention may have a configuration in which a silicon substrate 600 on which circuits are formed is laminated. For example, as shown in Fig. 24(A), a layer 1400 having transistors 610 and 620 having active regions on the silicon substrate 600 can be configured to overlap with the pixel circuit. Fig. 24(B) corresponds to a cross-sectional view in the channel width direction of the transistor. Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Fig. 24(B) corresponds to a cross-sectional view in the channel width direction of the transistor.

[0140] Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). Here, in Figs. 24(A) and (B), the Si transistor is illustrated as having a fin-type configuration, but it may be a planar type as shown in Fig. 25(A). Alternatively, as shown in Fig. 25(B), it may be a transistor having an active layer 650 of a silicon thin film. Also, the active layer 650 can be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator).

[0141] The circuit formed on the silicon substrate 600 can have functions such as reading out the signal output from the pixel circuit and performing processing for converting the signal. For example, it can be configured to include a CMOS inverter shown in the circuit diagram in Fig. 25(C). The gates of the transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. The circuit formed on the silicon substrate 600 can have functions such as reading out the signal output from the pixel circuit and performing processing for converting the signal. For example, it can be configured to include a CMOS inverter shown in the circuit diagram in Fig. 25(C). The gates of the transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. The circuit formed on the silicon substrate 600 can have functions such as reading out the signal output from the pixel circuit and performing processing for converting the signal. For example, it can be configured to include a CMOS inverter shown in the circuit diagram in Fig. 25(C). The gates of the transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. The gates of the transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. One of the source or drain of one transistor is electrically connected to one of the source or drain of the other transistor. Also, the other of the source or drain of both transistors are electrically connected to different wirings respectively.

[0142] The circuit formed on the silicon substrate 600 corresponds to, for example, circuits 12, 13, 14, 15, 16 shown in FIGS. 2(A) and 15(B).

[0143] Also, the silicon substrate 600 is not limited to a bulk silicon substrate, and substrates made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors can also be used.

[0144] Here, as shown in FIGS. 23 and 24(A), (B), an insulating layer 80 is provided between the region where a transistor having an oxide semiconductor is formed and the region where an Si device (Si transistor or Si photodiode) is formed.

[0145] Hydrogen in the insulating layer provided near the active regions of the transistors 610 and 620 terminates the dangling bonds of silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistors 610 and 620. On the other hand, hydrogen in the insulating layer provided near the oxide semiconductor layer which is an active layer such as the transistor 41 becomes one of the factors for generating carriers in the oxide semiconductor layer. Therefore, the hydrogen may be a factor for reducing the One layer having a transistor and the other layer having a transistor using an oxide semiconductor When laminating these layers, it is preferable to provide an insulating layer 80 having a function of preventing the diffusion of hydrogen therebetween By the insulating layer 80, the reliability of the transistors 610 and 620 can be improved by confining hydrogen in one layer Also, by suppressing the diffusion of hydrogen from one layer to the other layer, the reliability of the transistor 41 or the like can also be improved

[0146] As the insulating layer 80, for example, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide , hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used

[0147] In the configuration shown in FIGS. 24(A) and (B), a circuit (for example, a driving circuit) formed on the silicon substrate 600, the transistor 41 or the like, and the photoelectric conversion element PD can be formed so as to overlap each other Therefore, the integration degree of the pixels can be increased. That is, the resolution of the imaging device can be increased For example, it is suitable for use in an imaging device having a pixel number of 4K2K, 8K4K, or 16K8K or the like Note that the transistors 45 and 46 included in the pixel 10 are formed of Si transistors, and a configuration having an overlapping region with the transistors 41, 42, 43, 44, the photoelectric conversion element PD, or the like can also be employed

[0148] Also, an imaging device according to one aspect of the present invention can have a configuration shown in FIG. 26. The imaging device shown in FIG. 26 is a modified example of the imaging device shown in FIG. 24(A), and includes an OS transistor and an Si ​​​​​​​ An example of forming a CMOS inverter with transistors is illustrated.

[0149] Here, the transistor 620, which is a Si transistor provided in layer 1400, is of the p-ch type and the transistor 610, which is an OS transistor provided in layer 1100, is of the n-ch type. By providing only p-ch type transistors on the silicon substrate 600, processes such as well formation and n-type impurity layer formation can be omitted.

[0150] Although the imaging device shown in FIG. 26 shows an example using selenium or the like for the photoelectric conversion element PD, a configuration using a pin-type thin film photodiode may be employed in the same manner as in FIG. 21.

[0151] In the imaging device shown in FIG. 26, the transistor 610 can be fabricated in the same process as the transistors 41 and 43 formed in layer 1100. Therefore, the manufacturing process of the imaging device can be simplified.

[0152] Further, as shown in FIG. 27, an imaging device according to an aspect of the present invention may have a configuration in which pixels composed of a photoelectric conversion element PD formed on a silicon substrate 660 and an OS transistor formed thereon are bonded to a silicon substrate 600 on which a circuit is formed. With such a configuration, it becomes easy to increase the effective area of the photoelectric conversion element PD formed on the silicon substrate 660. Also, by highly integrating the circuit formed on the silicon substrate 600 with miniaturized Si transistors, a high-performance semiconductor device can be provided.

[0153] Also, as a modification of FIG. 27, as shown in FIG. 28, an OS transistor and a Si transistor It may be configured in a form using a dissta. By adopting such a configuration, it becomes easy to improve the effective area of the photoelectric conversion element PD formed on the silicon substrate 660. Also, it is possible to highly integrate the circuit formed on the silicon substrate 600 with miniaturized Si transistors, thereby providing a high-performance semiconductor device. In the case of the configuration shown in FIG. 28, a CMOS circuit can be configured with the Si transistors formed on the silicon substrate 600 and the OS transistors formed thereon. Since the OS transistors

[0154] have an extremely low off-current, it is possible to configure a CMOS circuit with an extremely small static leakage current. Note that the configurations of the transistors and the photoelectric conversion elements included in the imaging device in this embodiment are merely examples. Therefore, for example, any one or more of transistors 41 to 46 can be configured with transistors having silicon or the like in the active region or the active layer. Also, both or one of transistors 610 and 620 can be configured with transistors having an oxide semiconductor layer in the active layer.

[0155] FIG. 29(A) is a cross-sectional view of an example of a form in which a color filter or the like is added to the imaging device. This cross-sectional view shows a part of a region having pixel circuits for three pixels. An insulating layer 2500 is formed on the layer 1200 on which the photoelectric conversion element PD is formed. The insulating layer 2500 can be formed of a silicon oxide film or the like that is highly transparent to visible light. Also, a configuration in which a silicon nitride film is laminated as a passivation film may be adopted. Further, a configuration in which a dielectric film such as hafnium oxide is laminated as an antireflection film may be adopted.

[0156] ​​​​​​​​​​​

[0157] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 has a function of preventing color mixing of light passing through the upper color filter. The light-shielding layer 2510 may be configured by laminating a metal layer such as aluminum or tungsten and a dielectric film having a function as an antireflection film.

[0158] An organic resin layer 2520 may be provided as a planarizing film on the insulating layer 2500 and the light-shielding layer 2510. Further, color filters 2530 (color filters 2530a, 2530b, and 2530c) are formed for each pixel. For example, by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters 2530a, 2530b, and 2530 c, a color image can be obtained. c, a color image can be obtained.

[0159] An insulating layer 2560 having translucency or the like can be provided on the color filter 2530.

[0160] Further, as shown in FIG. 29(B), an optical conversion layer 2550 may be used instead of the color filter 2530. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0161] For example, if a filter that blocks light having a wavelength equal to or less than that of visible light is used for the optical conversion layer 2550, an infrared imaging device can be obtained. Also, if a filter that blocks light having a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 2550, a far-infrared imaging device can be obtained. Further, for the optical conversion layer 2550 ​​​​​If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0162] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then converted into Image data is obtained by detecting the radiation. A position may also be used.

[0163] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and These include substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. Cut.

[0164] In photoelectric conversion elements (PDs) made of selenium-based materials, radiation such as X-rays is directly converted into electric charges. Therefore, a configuration that does not require a scintillator can be provided.

[0165] As shown in FIG. 29C, the color filter 2530a and the color filter 2530 A microlens array 2540 may be provided on color filter 2530b and color filter 2530c. The light passing through each lens of the microlens array 2540 hits the color filter directly below. As shown in FIG. 29(D), the light A microlens array 2540 may be provided on the learning conversion layer 2550. Note that, regarding the regions other than the layer 1200 shown in FIGS. 29(A ), (B), (C), and (D), the layer 1600 is used.

[0166] FIG. 30 is a diagram illustrating a specific stacked structure such as the pixel 10 according to one aspect of the present invention and the microlens array 2 540 shown in FIG. 29(C). FIG. 30 is an example using the configuration of the pixel shown in FIG. 24(A). FIG. 31 is an example using the configuration of the pixel shown in FIG. 28.

[0167] In this way, since each of the photoelectric conversion element PD, the circuit included in the pixel 10, and the drive circuit can be configured to have an overlapping region with each other, the imaging device can be miniaturized.

[0168] Further, as shown in FIGS. 30 and 31, a configuration may be adopted in which a diffraction grating 1500 is provided above the microlens array 2540. An image of a subject (diffraction image) through the diffraction grating 1500 is captured by the pixel, and an input image (image of the subject) can be configured from the captured image in the pixel by arithmetic processing. Further, by using the diffraction grating 1500 instead of a lens, the cost of the imaging device can be reduced.

[0169] The diffraction grating 1500 can be formed of a material having translucency. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. Alternatively, a laminate of the inorganic insulating film and the organic insulating film may be used.

[0170] Further, the diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. ​It is possible. It can also be formed using a lithography process and an etching process. Also, it can be formed using nanoimprint lithography, laser scribing, or the like.

[0171] An interval X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be 1 mm or less, preferably 100 μm or less. This interval may be a space, or a material having translucency may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a noble gas can be confined in this interval. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided in this interval. Alternatively, a liquid such as silicone oil may be provided. Even when the microlens array 2540 is not provided, an interval X may be provided between the color filter 2530 and the diffraction grating 1500.

[0172] Also, the imaging device may be curved as shown in FIGS. 32(A1) and 32(B1). FIG. 32(A1) shows a state in which the imaging device is curved in the direction of the two-dot chain line X1-X2 in the figure. FIG. 32(A2) is a cross-sectional view of the portion indicated by the two-dot chain line X1-X2 in FIG. 32(A1). FIG. 32(A3) is a cross-sectional view of the portion indicated by the two-dot chain line Y1-Y2 in FIG. 32(A1).

[0173] FIG. 32(B1) shows a state in which the imaging device is curved in the direction of the two-dot chain line X3-X4 in the figure and is curved in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 32(B2) is a cross-sectional view of the portion indicated by the two-dot chain line X3-X4 in FIG. 32(B1). FIG. 32(B3) is a cross-sectional view of the portion indicated by the two-dot chain line Y3-Y4 in FIG. 32(B1). ​​​

[0174] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, enabling miniaturization of semiconductor devices using imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0175] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source-drain region of the transistor, etc. may have at least one of, for example, silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. Or, for example, in some cases, or depending on the situation, various transistors in one aspect of the present invention, the channel formation region of the transistor, or the source-drain region of the transistor do not have to have an oxide semiconductor.

[0176] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0177] (Embodiment 2) In this embodiment, an imaging device different from that in Embodiment 1 will be described with reference to the drawings. Details of the parts common to the imaging device described in Embodiment 1 will be omitted.

[0178] One aspect of the present invention is a circuit configuration and an operation method of an imaging device that determines the saturation state of electrons in a charge detection unit provided in a pixel and can change the operation mode according to the determination result. First, first imaging data is acquired, and when the charge detection unit is not saturated, control is performed not to change the capacitance value of the charge detection unit. Also, when the charge detection unit is saturated, control is performed to increase the capacitance value of the charge detection unit. After performing all these controls individually for all pixels, acquisition and reading of second imaging data are performed. The second imaging data acquired without changing the capacitance value of the charge detection unit corresponds to data corresponding to low illuminance. Also, the second imaging data acquired by increasing the capacitance value of the charge detection unit corresponds to data corresponding to high illuminance.

[0179] Through the above operation, an image with a wide dynamic range with less noise and maintained gradation can be obtained even under low illuminance conditions. Also, in imaging in an environment including high illuminance, the gradation of the bright part can be maintained, and an image with a wide dynamic range can be obtained.

[0180] FIG. 33 is a circuit diagram of a pixel 20 included in an imaging device according to an aspect of the present invention. Note that, in FIG. 33, an example in which the transistor is an n-ch type is shown, but an aspect of the present invention is not limited to this, and some of the transistors may be replaced with p-ch type transistors.

[0181] In pixel 20, one electrode of a photoelectric conversion element PD is electrically connected to one of the source or drain of transistor 741. One of the source or drain of transistor 741 is electrically connected to one of the source or drain of transistor 742. The other of the source or drain of transistor 741 is electrically connected to one of the source or drain of transistor 743. The other of the source or drain of transistor 741 is electrically connected to one of the source or drain of transistor 744. The other of the source or drain of transistor 741 is electrically connected to the gate of transistor 745. The other of the source or drain of transistor 741 is electrically connected to one electrode of a capacitive element C71. The other of the source or drain of transistor 744 is electrically connected to one electrode of a capacitive element C72. One of the source or drain of transistor 745 is electrically connected to one of the source or drain of transistor 746. The gate of transistor 744 is electrically connected to either the source or the drain of transistor 747. The gate of transistor 744 is electrically connected to one electrode of capacitor element C73. Here, a node AN to which one electrode of the photoelectric conversion element PD, either the source or the drain of transistor 741, and either the source or the drain of transistor 742 are connected is used as a charge storage section.

[0182] Also, a node FD to which the other of the source or the drain of transistor 741, either the source or the drain of transistor 743, either the source or the drain of transistor 744, the gate of transistor 745, and one electrode of capacitor element C71 are connected is used as a charge detection section. Further, a node CN to which the gate of transistor 744, either the source or the drain of transistor 747, and one electrode of capacitor element C73 are connected is used as a signal holding section.

[0183] The other electrode of the photoelectric conversion element PD is electrically connected to wiring 771 (VPD). The other of the source or the drain of transistor 742 and the other of the source or the drain of transistor 743 are electrically connected to wiring 772 (VRS). The other electrode of capacitor element C1, the other electrode of capacitor element C72, and the other electrode of capacitor element C73 are electrically connected to wiring 773 (VSS). The other of the source or the drain of transistor 745 is electrically connected to wiring 774 (VPI). The other of the source or the drain of transistor 746 is electrically connected to wiring 791 (OUT1).

[0184] Note that in the connection forms of the above elements, a plurality of transistors or a plurality of capacitor elements are electrically Although an example of sharing the connected wiring is shown, each may be electrically connected to different wiring. It is also possible.

[0185] Wiring 771 (VPD), wiring 772 (VRS), wiring 773 (VSS), and wiring 77 4 (VPI) can function as a power supply line. For example, wiring 771 (VP D) and wiring 773 (VSS) can function as a low-potential power supply line. Wiring 772 (VRS) and wiring 774 (VPI) can function as a high-potential power supply line. It is possible.

[0186] The gate of transistor 741 is electrically connected to wiring 761 (TX). The transistor The gate of 742 is electrically connected to wiring 762 (GWRS). Transistor 74 The gate of 3 is electrically connected to wiring 763 (RS). The gate of transistor 746 Is electrically connected to wiring 764 (SE). The gate of transistor 747 is wiring 7 65 (SE2) is electrically connected. The source or drain of transistor 747 The other is electrically connected to wiring 793 (OUT3).

[0187] Wiring 761 (TX), wiring 762 (GWRS), wiring 763 (RS), wiring 764 (SE ) and wiring 765 (SE2) can each function as a signal line for controlling the conduction of the connected transistor. Note that wiring 763 (RS), wiring 764 (SE) And wiring 765 (SE2) can be controlled for each row. And wiring 765 (SE2) can be controlled for each row.

[0188] Transistor 741 is a transistor for transferring the potential of node AN to node FD. and can be made to function. Transistor 742 can function as a transistor for resetting the potential of node AN and can be made to function. Transistor 743 can function as a transistor for resetting the potential of node FD and can be made to function. Transistor 744 can function as a transistor for controlling the electrical connection between node FD and capacitor element C72 and can be made to function. Transistor 745 can function as a transistor for outputting according to the potential of node FD and can be made to function. Transistor 746 can function as a transistor for selecting pixel 20 and can be made to function. Transistor 747 can function as a transistor for holding the potential of node CN Note that the configuration of pixel 20 described above is an example, and there may be cases where some circuits, some transistors, some capacitor elements, or some wirings are not included. Or, there may be cases where circuits, transistors, capacitor elements, wirings, etc. not included in the above-described configuration are included. Also, there may be cases where the connection form of some wirings is different from the above-described configuration

[0189] Note that the configuration of pixel 20 described above is an example, and there may be cases where some circuits, some transistors, some capacitor elements, or some wirings are not included. Or, there may be cases where circuits, transistors, capacitor elements, wirings, etc. not included in the above-described configuration are included. Also, there may be cases where the connection form of some wirings is different from the above-described configuration capacitor elements, or some wirings are not included. Or, there may be cases where circuits, transistors, capacitor elements, wirings, etc. not included in the above-described configuration are included. Also, there may be cases where the connection form of some wirings is different from the above-described configuration capacitor elements, or some wirings are not included. Or, there may be cases where circuits, transistors, capacitor elements, wirings, etc. not included in the above-described configuration are included. Also, there may be cases where the connection form of some wirings is different from the above-described configuration

[0190] FIG. 34(A) is a diagram for explaining an imaging device according to an aspect of the present invention. The imaging device includes a pixel array 21 having pixels 20 arranged in a matrix form, a circuit 22 (load driver) having a function of driving pixels 20, a circuit 23 (CDS circuit) for performing a CDS (Correlated Double Sampling) operation on the output signal of pixels 20 and a circuit 23 (CDS circuit) for performing a CDS (Correlated Double Sampling) operation on the output signal of pixels 20 ted Double Sampling) operation on the output signal of pixels 20, a function of determining the presence or absence of saturation of node FD, a function of controlling the operation mode of the pixel according to the determination result, and a function of converting the analog data output from circuit 23 into digital data and a circuit 23 (CDS circuit) for performing a CDS (Correlated Double Sampling) operation on the output signal of pixels 20, a function of determining the presence or absence of saturation of node FD, a function of controlling the operation mode of the pixel according to the determination result, and a function of converting the analog data output from circuit 23 into digital data and a circuit 23 (CDS circuit) for performing a CDS (Correlated Double Sampling) operation on the output signal of pixels 20, a function of determining the presence or absence of saturation of node FD, a function of controlling the operation mode of the pixel according to the determination result, and a function of converting the analog data output from circuit 23 into digital data A circuit 24 (such as an A / D conversion circuit) having a function, and a circuit 25 (column driver) having a function of selecting and reading out the data converted by the circuit 24. Note that the circuit 23 may not be provided. It can also be configured without the circuit 23.

[0191] FIG. 34(B) is a circuit diagram of the circuit 23 and a block diagram of the circuit 24 connected to one column of the pixel array 21. The circuit 23 can be configured to include a transistor 751, a transistor 752, a transistor 753, a capacitor element C74, and a capacitor element C75. Further, the circuit 24 can be configured to include a comparator circuit 27, a determination output circuit 28, and a counter circuit 29.

[0192] The transistor 754 has a function as a current source circuit. One of the source or drain of the transistor 754 is electrically connected to a wiring 791 (OUT1), and the other of the source or drain is connected to a power supply line. The power supply line can be, for example, a low potential power supply line. Also, a bias voltage is constantly applied to the gate of the transistor 754.

[0193] In the circuit 23, one of the source or drain of the transistor 751 is electrically connected to one of the source or drain of the transistor 752. One of the source or drain of the transistor 751 is electrically connected to one electrode of the capacitor element C74. The other of the source or drain of the transistor 752 is electrically connected to one of the source or drain of the transistor 753. The other of the source or drain of the transistor 752 is electrically connected to one electrode of the capacitor element C75. ​​​​​​​​​​​​​The other side of the is electrically connected to the wiring 792 (OUT2). The other side of the source or drain of the transistor 753 and the other electrode of the capacitor element C74 are electrically connected to the wiring 791 (OUT1). The other side of the source or drain of the transistor 751 is, for example, electrically connected to the high potential power supply line (CDSVDD) to which the reference potential is supplied. The other electrode of the capacitor element C7 5 is electrically connected to, for example, the low potential power supply line (CDSVSS).

[0194] An example of the operation of the circuit 23 when connected to the pixel 20 shown in FIG. 33 will be described. First, the transistors 751 and 752 are turned on. Next, the potential of the imaging data is output from the pixel 20 to the wiring 791 (OUT1), and the reference potential (CDS VDD) is held on the wiring 792 (OUT2). Then, the transistor 751 is turned off, and a reset potential (here, a potential higher than the potential of the imaging data, for example, the VD D potential) is output from the pixel 20 to the wiring 79 1 (OUT1). At this time, the wiring 792 (OUT2) becomes a potential obtained by adding the absolute value of the difference between the potential of the imaging data and the reset potential to the reference potential (CDSVDD). Therefore, a potential signal with less noise, obtained by adding the potential of the actual imaging data to the reference potential (CDSVDD), can be supplied to the circuit 24.

[0195] Note that when the reset potential is a potential lower than the potential of the imaging data (for example, the GND potential), the wiring 792 (OUT2) becomes a potential obtained by subtracting the absolute value of the difference between the potential of the imaging data and the reset potential from the reference potential (CDSVDD).

[0196] Also, when the transistor 753 is turned on, a bypass is formed, so the wiring 791 ( The signal of OUT1) can be directly output to the wiring 792 (OUT2).

[0197] In circuit 24, in the comparator circuit 27, the signal potential input from circuit 23 is compared with the reference potential (REF). The comparator circuit 27 receives the signal potential corresponding to the first imaging data or the second imaging data via the wiring 792 (OUT2). Here, the first imaging data is the data of the first exposure, which is used to determine whether the node FD of the pixel 20 is saturated. The second imaging data is the data of the second exposure obtained according to the determination. First, when the first imaging data is input, the comparator circuit 27 outputs the determination result to the determination output circuit 28. The determination output circuit 28 has a function of adjusting the output timing and removing the noise output from the comparator circuit 27. In the comparator circuit 27, it is determined whether the first imaging data saturates the node FD of the pixel 20. At this time, the reference potential (REF) input to the comparator circuit 27 is a certain potential corresponding to the saturation of the node FD, and the presence or absence of saturation is determined by comparing this potential with the signal potential corresponding to the first imaging data. In this embodiment, the signal potential corresponding to the first imaging data is configured to bypass circuit 23 and input to the comparator circuit 27, but it may also be input to the comparator circuit 27 without bypassing circuit 23. If it is determined that the node FD is not saturated, the determination output circuit 28 outputs the capacitance value of the node FD.

[0198]

[0199]

[0200] Outputs a signal that does not change to the pixel. Specifically, the potential at which the transistor 744 is non-conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, the capacitance value of the node FD does not change. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases. After performing the above operations for all valid pixels, the node FD is reset, and second imaging data is acquired. The signal potential corresponding to the second imaging data is input to the comparator circuit 27 via the circuit 23. At this time, the reference potential (REF) input to the comparator circuit 27 is a ramp wave, and the result of comparing with the signal potential corresponding to the second imaging data is output to the counter circuit 29. Then, the counter circuit 29 outputs digital data corresponding to the second imaging data to the wiring 794 (OUT4).

[0201] For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases. After performing the above operations for all valid pixels, the node FD is reset, and second imaging data is acquired. The signal potential corresponding to the second imaging data is input to the comparator circuit 27 via the circuit 23. At this time, the reference potential (REF) input to the comparator circuit 27 is a ramp wave, and the result of comparing with the signal potential corresponding to the second imaging data is output to the counter circuit 29. Then, the counter circuit 29 outputs digital data corresponding to the second imaging data to the wiring 794 (OUT4). For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases.

[0202] After performing the above operations for all valid pixels, the node FD is reset, and second imaging data is acquired. The signal potential corresponding to the second imaging data is input to the comparator circuit 27 via the circuit 23. At this time, the reference potential (REF) input to the comparator circuit 27 is a ramp wave, and the result of comparing with the signal potential corresponding to the second imaging data is output to the counter circuit 29. Then, the counter circuit 29 outputs digital data corresponding to the second imaging data to the wiring 794 (OUT4). For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases. After performing the above operations for all valid pixels, the node FD is reset, and second imaging data is acquired. The signal potential corresponding to the second imaging data is input to the comparator circuit 27 via the circuit 23. At this time, the reference potential (REF) input to the comparator circuit 27 is a ramp wave, and the result of comparing with the signal potential corresponding to the second imaging data is output to the counter circuit 29. Then, the counter circuit 29 outputs digital data corresponding to the second imaging data to the wiring 794 (OUT4). For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases.

[0203] For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases. After performing the above operations for all valid pixels, the node FD is reset, and second imaging data is acquired. The signal potential corresponding to the second imaging data is input to the comparator circuit 27 via the circuit 23. At this time, the reference potential (REF) input to the comparator circuit 27 is a ramp wave, and the result of comparing with the signal potential corresponding to the second imaging data is output to the counter circuit 29. Then, the counter circuit 29 outputs digital data corresponding to the second imaging data to the wiring 794 (OUT4). For the determination output circuit 28, for example, the circuit shown in FIG. 35 can be used. The output terminal of the comparator circuit 27 is electrically connected to the input terminal (IN) of the circuit. Also, the wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. The determination output circuit 28 is reset by the JRES signal for each selected row, and then outputs the determination result of the comparator circuit 27 to the wiring 793 (OUT3). A control signal is input to the terminal GCN. When the node FD is determined to be saturated, the determination output circuit 28 outputs a signal to increase the capacitance value of the node FD to the pixel. Specifically, the potential at which the transistor 744 is conductive is output to the wiring 793 (OUT3), and this potential is held at the node CN of the pixel 20. At this time, since the capacitive element C72 is electrically connected to the node FD, the capacitance value of the node FD increases. The signal output to the wiring 793 (OUT3) can also be fixed.

[0204] The circuit shown in FIG. 35 can be operated according to the timing chart shown in FIG. 36. . RCK1 / 2 and RCKB1 / 2 shown in FIG. 36 are clock signals and inverted clock signals input to the circuit 22 (load driver), JRES and JENB are signals input to the circuit of FIG. 35, EN_CDS is a signal input to the gate of the transistor 753 of the circuit 23, SE[1] is a signal input to the wiring 764 of the pixel 20 in the first row, SE[N] is a signal input to the wiring 764 of the pixel 20 in the last row, SE2[1] is a signal input to the wiring 765 of the pixel 20 in the first row, and SE2[N] is a signal input to the wiring 765 of the pixel 20 in the last row.

[0205] The period indicated by frame[n] corresponds to the period of the nth frame (n is a natural number of 2 or more). In the nth frame, the period 401 is the period for reading the data of the (n - 1)th frame, the period 402 is the period for reading and determining the first imaging data described above, and the period 400 is the period when the load driver does not operate. Also, the period 403 in the (n + 1)th frame is the period for reading the data of the nth frame.

[0206] Next, the operation of the pixel 20 shown in FIG. 33 will be described using the flowchart shown in FIG. 37 and the timing chart shown in FIG. 38. The imaging device according to one aspect of the present invention operates in a global shutter method, and the operation within one frame is roughly divided into acquisition of the first imaging data, determination of the first imaging data, acquisition of the second imaging data, and reading of the imaging data of the previous frame. Oh, the acquisition of the first imaging data and the reading of the imaging data of the previous frame are performed in parallel. This is done.

[0207] In FIGS. 37 and 38, an arbitrary nth frame is used as a reference for explanation. Also, wiring 771 (VPD) and wiring 773 (VSS) are at a low potential ("L"), and wiring 772 (VRS) and wiring 774 (VPI) are at a high potential ("H").

[0208] Also, in FIG. 38, GWRS is the potential of wiring 762 (GWRS), RS[1] is the potential of wiring 763 (RS) at a specific pixel 20 in the first row, RS[N] is the potential of wiring 763 (RS) at a specific pixel 20 in the last row, CN[1] is the potential of node CN at a specific pixel 20 in the first row, CN[N] is the potential of node CN at a specific pixel 20 in the last row, T X is the potential of wiring 761 (TX), AN[1] is the potential of node AN at a specific pixel 20 in the first row, AN[N] is the potential of node AN at a specific pixel 20 in the last row, FD[1] is the potential of node FD at a specific pixel 20 in the first row, FD[N] is the potential of node FD at a specific pixel 20 in the last row.

[0209] First, the acquisition of the first imaging data and the reading of the imaging data acquired in the previous frame will be described. This will be explained.

[0210] The first imaging data is data for distinguishing the illuminance (low illuminance or high illuminance) of the imaging target. In the imaging mode of the first imaging data, imaging is performed at a low capacitance value where only the capacitive element C71 is connected to node FD. Therefore, in a high-illuminance environment, node FD saturates. Thus, by determining the presence or absence of saturation of node FD, the illuminance of the imaging target can be distinguished. This can be achieved by determining whether node FD is saturated. In the timing chart of FIG. 38, in the first imaging data, the first row shows the operation when node F D is not saturated, and the Nth row (last row) shows the operation when node FD is saturated .

[0211] At time T1, when GWRS is set to "H", AN[1:N] is reset to "H" (the potential of wiring 772 (VRS)) (S1).

[0212] At time T2, when GWRS is set to "L", AN[1:N] starts to decrease according to the illuminance (first exposure, S2).

[0213] At time T3, when RS[1:N] is set to "H" and CN[1:N] is set to "H", FD 1:N] is reset to "H" (the potential of wiring 772 (VRS)) (S3). At this time, a capacitive element C72 is electrically connected to node FD via transistor 744 . To set CN[1:N] to "H", set wiring 765 (SE2)[1:N] to "H" to turn on transistor 747 and set the input signal of terminal GCN of determination output circuit 28 to "H" .

[0214] At time T4, when SE2[1:N] is set to "H" and CN[1:N] is set to "L", the trans istor 744 becomes non-conductive, so the electrical connection between node FD and capacitive element C72 is cut off. To set CN[1:N] to "L", reset determination output circuit 28 and set terminal GCN to "L". After time T4, if SE2[1:N] is set to "L" to turn off transistor 747, CN[1:N] is held by capacitive element C73 etc .

[0215] Also, at time T4, when RS[1:N] is set to "L" and TX is set to "H", and also, the potential of node AN is transferred to node FD, and the potential of node FD starts to decrease (S4).

[0216] At time T5, when TX is set to "L", FD[1:N] is held. This is the acquisition operation of the first imaging data.

[0217] Here, between times T1 to T3, SE[1] to SE[N] sequentially become "H" for a certain period, and the imaging data determined in the (n - 1)-th frame is read out (S10'). That is, the acquisition operation of the first imaging data of the n-th frame and the reading of the imaging data determined in the (n - 1)-th frame are performed in parallel. By reading the imaging data in the next frame in this way, even in the global shutter method, the time allocated for exposure and the like can be increased. Therefore, an image with a wide dynamic range and low noise can be obtained even under low illuminance conditions.

[0218] FIG. 39(A) is a timing chart for explaining the reading of the imaging data in the first row. S H is the potential supplied to the gate of transistor 752 in circuit 23, CL is the potential supplied to the gate of transistor 751 in circuit 23, REF(RAMP) is the reference potential supplied to comparator circuit 27, OUT2 is the potential of wiring 792 (OUT2), and COMP _OUT is the potential of the output terminal of comparator circuit 27.

[0219] In FIG. 38, before time T3, RS[1] to RS[N] sequentially become "H" for a certain period, and node FD is reset, which is an operation accompanying the operation of circuit 23 shown in FIG. 39(A). ​

[0220] Next, the determination of the first imaging data and the operations associated with the determination result will be described.

[0221] At times T6 to T8, SE[1] to SE[N] sequentially become "H" for a certain period, and for each row, the first imaging data is read out, and for all valid pixels 20, the saturation of the node FD is determined (S5).

[0222] FIG. 39(B) is a timing chart for explaining the reading of the first imaging data at times T6 to T8. During the reading period of the first imaging data, EN_CDS is set to "H" and CL is set to "H", and the signal output from the pixel 20 bypasses the circuit 23 and is input to the comparator circuit 27. The potential of REF(CONST) is kept constant and is set to a value slightly larger than the potential output to the wiring 791(OUT1) when the node FD is saturated. By operating in this way, the presence or absence of saturation of the node FD can be determined by the output of the comparator circuit 27. Note that FIG. 39(B) shows the state when the node FD of the selected specific pixel 20 is saturated, and an "L" is output from the output terminal of the comparator circuit 27. Note that the first imaging data may be read out without bypassing the circuit 23 by setting EN_CDS to "L". At this time, an "H" is output from the output terminal of the comparator circuit 27. At this time, the first imaging data is used to determine the presence or absence of saturation of the node FD and is not output to the outside. Therefore, the operation of the output circuit such as the circuit 25 (column driver) required for external output may be stopped. Note that FIG. 39(B) shows the state when the node FD of the selected specific pixel 20 is saturated, and an "L" is output from the output terminal of the comparator circuit 27. Note that the first imaging data may be read out without bypassing the circuit 23 by setting EN_CDS to "L". At this time, an "H" is output from the output terminal of the comparator circuit 27. At this time, the first imaging data is used to determine the presence or absence of saturation of the node FD and is not output to the outside. Therefore, the operation of the output circuit such as the circuit 25 (column driver) required for external output may be stopped. is output.

[0223] At this time, the first imaging data is used to determine the presence or absence of saturation of the node FD and is not output to the outside. Therefore, the operation of the output circuit such as the circuit 25 (column driver) required for external output may be stopped. Therefore, the operation of output circuits such as the circuit 25 (column driver) necessary for external output may be stopped. is output.

[0224] The determination result of the first imaging data is output to the pixel 20 that has read the first imaging data via the determination output circuit 28. Here, in order to input the determination result to the node CN of the pixel 20, the wiring 765 (SE2) in the same row is set to "H" for a certain period in accordance with the timing of outputting the determination result. for a certain period "H".

[0225] In the pixel 20 where it is determined that the node FD is not saturated, since "L" is input to the node CN, the transistor 744 does not conduct. Therefore, the capacitor element C71 of the node FD is electrically connected, and the capacitance value of the node FD does not change. That is, the pixel 20 is set to an imaging mode suitable for imaging in low illumination.

[0226] In the pixel 20 where it is determined that the node FD is saturated, since "H" is input to the node CN, the transistor 744 conducts. Therefore, the capacitor elements C71 and C72 are electrically connected to the node FD, and the capacitance value of the node FD increases (S6). That is, the pixel 20 is set to an imaging mode suitable for imaging in high illumination. The above is the determination of the first imaging data and the operations accompanying the determination result.

[0227] Next, the acquisition of the second imaging data will be described.

[0228] Before all the determination results are obtained, the exposure operation for obtaining the second imaging data may be performed. For example, as shown in FIG. 38, at time T7, GWRS is set to "H" and AN[1:N] is reset (S7). Then, at time T8, GWRS is set to "L", and the second exposure is performed until time T10 (S8). Note that the second exposure time is the same as the first exposure time. ​​​​​​​​​​​ It is sufficient. Or, it may be shorter than the exposure time of the first time.

[0229] If RS[1:N] is set to "H" at time T9 before the end of the second exposure, FD[1:N is reset and becomes "H" (the potential of wiring 772 (VRS)) (S9).

[0230] When wiring 761 (TX) is set to "H" at time T10, the potential of node AN is transferred to node FD (S10).

[0231] When wiring 761 (TX) is set to "L" at time T11, FD[1:N] is held This is the acquisition operation of the second imaging data. Also, the second imaging data is read as the imaging data of the nth frame in the (n + 1)th frame (S11).

[0232] By the above operation, the imaging mode of the second imaging data can be set for each pixel 20 Even in imaging of a field of view with a mixture of light and dark, an image with a wide dynamic range with maintained gradation can be obtained.

[0233] The pixel 20 may have the configuration shown in FIG. 40. The pixel 20 shown in FIG. 40 has a different direction in which the photoelectric conversion element PD is connected from the pixel 20 shown in FIG. 33. The pixel 20 shown in FIG. 40 can be operated according to the timing chart of FIG. 4 2. At this time, wiring 771 (VPD) and wiring 774 (VPI) are at a high potential ("H"), and wiring 772 (VRS) and wiring 77 3 (VSS) are at a low potential ("L").

[0234] In this case, electrons in node AN and node FD become saturated at the time of reset, and the illuminance is high The electrons in the ito node AN and the node FD become deficient. Therefore, contrary to the description of the operation of the pixel 20 shown in FIG. 33 described above, the potentials of the node AN and the node FD change. Also, the pixel 20 may have the configuration shown in FIGS. 41(A) and (B). FIG. 41(A) shows a configuration without the transistor 742. In this configuration, the potential of the node AN can be reset by setting the potential of the wiring 771 (VPD) to a high potential. FIG. 41(B) shows a configuration in which one of the source or drain of the transistor 745 is connected to the wiring 791 (OUT).

[0235]

[0236] Also, the transistor used for the pixel 20 may have a configuration in which a back gate is provided to the transistors 741 to 747 as shown in FIGS. 43(A) and (B). FIG. 43(A) shows a configuration in which a fixed potential is applied to the back gate, and the threshold voltage can be controlled. In FIG. 43(A), as an example, an example is shown in which the back gate is connected to the wiring 771 (VPD), the wiring 773 (VSS), or the wiring 775 (VSS2) that supplies a low potential, but it may be configured to be connected to any one of the wirings. Also, FIG. 43(B) shows a configuration in which the same potential as the front gate is applied to the back gate, and the on-current can be increased and the off-current can be decreased. Also, in order for the desired transistor to have appropriate electrical characteristics, a configuration combining the configurations of FIGS. 43(A) and 43(B) may be used. Note that there may be a transistor without a back gate. Also, the configurations of FIGS. 40, 41(A), (B), and 43(A), (B) can be combined as necessary.

[0237] As shown in FIG. 44, the pixel 20 may be configured to share the transistors 743 to 747 among a plurality of pixels. FIG. 44 illustrates a configuration in which the transistors 743 to 747 are shared among a plurality of pixels in the vertical direction, but they may also be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. By adopting such a configuration, the number of transistors per pixel can be reduced. In FIG. 44, the transistors 743 to 747 are shared among four pixels, but they may also be shared among two, three, or five or more pixels. Additionally, the configurations of FIG. 40, FIGS. 41(A) and (B), and FIGS. 43(A) and (B) can be arbitrarily combined with this configuration. Moreover, FIG. 44 shows a form in which the transistors 743 to 747 are shared among four pixels, but they may also be shared among two, three, or five or more pixels. Note that the configurations of FIG. 40, FIGS. 41(A) and (B), and FIGS. 43(A) and (B) can be arbitrarily combined with this configuration. Furthermore, FIG. 44 illustrates a form in which the transistors 743 to 747 are shared among four pixels, but they may also be shared among two, three, or five or more pixels. Also, the configurations of FIG. 40, FIGS. 41(A) and (B), and FIGS. 43(A) and (B) can be arbitrarily combined with this configuration. Also, in FIG. 44, a form in which the transistors 743 to 747 are shared among four pixels is illustrated, but they may also be shared among two, three, or five or more pixels. Additionally, the configurations of FIG. 40, FIGS. 41(A) and (B), and FIGS. 43(A) and (B) can be arbitrarily combined with this configuration.

[0238] In addition, FIG. 44 shows a form in which the transistors 743 to 747 are shared among four pixels, but they may also be shared among two, three, or five or more pixels. Moreover, FIG. 44 depicts a form where the transistors 743 to 747 are shared among four pixels, but they may also be shared among two, three, or five or more pixels. In addition, the configurations of FIG. 40, FIGS. 41(A) and (B), and FIGS. 43(A) and (B) can be arbitrarily combined with this configuration. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0239] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is.

[0240] (Embodiment 3) In this embodiment, a transistor having an oxide semiconductor that can be used in one aspect of the present invention will be described with reference to the drawings. Note that in the drawings of this embodiment, some elements are enlarged, reduced, or omitted for clarity. In the drawings of this embodiment, some elements are enlarged, reduced, or omitted for clarity. For clarity, some elements are enlarged, reduced, or omitted in the drawings of this embodiment.

[0241] FIGS. 45(A) and (B) are a top view and a cross-sectional view of a transistor 101 according to one aspect of the present invention. FIG. 45(A) is a top view, and the cross-section in the direction of the dashed-dotted line B1 - B2 shown in FIG. 45(A) corresponds to FIG. 45(B). Also, the cross-section in the direction of the dashed-dotted line B3 - B4 shown in FIG. 45(A) corresponds to FIG. 47(A). Further, the direction of the dashed-dotted line B1 - B2 is the channel length direction, and the direction of the dashed-dotted line B FIGS. 45(A) and (B) are a top view and a cross-sectional view of transistor 101 according to one aspect of the present invention. FIG. 45(A) is a top view, and the cross-section along the dash-dot line B1 - B2 shown in FIG. 45(A) corresponds to FIG. 45(B). Also, the cross-section along the dash-dot line B3 - B4 shown in FIG. 45(A) corresponds to FIG. 47(A). Further, the dash-dot line B1 - B2 direction is the channel length direction, and the dash-dot line B FIGS. 45(A) and (B) are a top view and a cross-sectional view of transistor 101 according to one aspect of the present invention. FIG. 45(A) is a top view, and the cross-section along the dash-dot line B1 - B2 shown in FIG. 45(A) corresponds to FIG. 45(B). Also, the cross-section along the dash-dot line B3 - B4 shown in FIG. 45(A) corresponds to FIG. 47(A). Further, the dash-dot line B1 - B2 direction is the channel length direction, and the dash-dot line B FIGS. 45(A) and (B) are a top view and a cross-sectional view of transistor 101 according to one aspect of the present invention. FIG. 45(A) is a top view, and the cross-section along the dash-dot line B1 - B2 shown in FIG. 45(A) corresponds to FIG. 45(B). Also, the cross-section along the dash-dot line B3 - B4 shown in FIG. 45(A) corresponds to FIG. 47(A). Further, the dash-dot line B1 - B2 direction is the channel length direction, and the dash-dot line B The 3-B4 direction is referred to as the channel width direction.

[0242] The transistor 101 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 that are electrically connected to the oxide semiconductor layer 130, an insulating layer 1 60 in contact with the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 1 75 in contact with the conductive layer 140, the conductive layer 150, the insulating layer 1 60, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Further, a function as a planarization film may be added to the insulating layer 180 as necessary. .

[0243] Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer, respectively. Also, the region 231 shown in FIG. 45(B) can function as a source region, the region 232 can function as a drain region, and the region 2

[0244] 33 can function as a channel formation region. The regions 231 and 232 are in contact with the conductive layer 140 and the conductive layer 150, respectively. If a conductive material that easily binds with oxygen is used for the conductive layer 140 and the conductive layer 150, the regions 231 and 232 can be made to have low resistance. Specifically, when the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen deficiency occurs in the oxide semiconductor layer 130. Due to the interaction between the oxygen deficiency and hydrogen remaining in or diffusing from the outside into the oxide semiconductor layer 130, the regions 231 and 232 become low-resistance n-type regions. and the conductive layer 150, respectively.

[0245] Specifically, when the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen deficiency occurs in the oxide semiconductor layer 130. Due to the interaction between the oxygen deficiency and hydrogen remaining in or diffusing from the outside into the oxide semiconductor layer 130, the regions 231 and 232 become low-resistance n-type regions. and hydrogen remaining in or diffusing from the outside into the oxide semiconductor layer 130, the regions 231 and 232 become low-resistance n-type regions. ​​​​

[0246] Note that the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. Also, the "electrode layer" can be referred to as "wiring".

[0247] In addition, although an example in which the conductive layer 170 is formed of two layers, the conductive layer 171 and the conductive layer 172, is illustrated, it may be a single layer or a laminate of three or more layers. This configuration can also be applied to other transistors described in this embodiment.

[0248] Also, although an example in which the conductive layers 140 and 150 are formed as single layers is illustrated, they may be a laminate of two or more layers. This configuration can also be applied to other transistors described in this embodiment.

[0249] Further, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 45(C) and (D). FIG. 45(C) is a top view of the transistor 102, and the cross section in the direction of the dashed-dotted line C1-C2 shown in FIG. 45(C) corresponds to FIG. 45(D). Also, the cross section in the direction of the dashed-dotted line C3-C4 shown in FIG. 45(C) corresponds to FIG. 47(B). Also, the direction of the dashed-dotted line C1-C2 is referred to as the channel length direction, and the direction of the dashed-dotted line C3-C4 is referred to as the channel width direction.

[0250] The transistor 102 is the same as the transistor 101 except that the end of the insulating layer 160 acting as a gate insulating film and the end of the conductive layer 170 acting as a gate electrode layer do not coincide. ​​​​has such a configuration. The structure of the transistor 102 is such that the conductive layer 140 and the conductive layer 150 are widely covered by the insulating layer 160, so that the resistance between the conductive layer 140 and the conductive layer 150 and the conductive layer 170 is high, and it has the characteristic of low gate leakage current. Since the conductive layer 140 and the conductive layer 150 are widely covered by the insulating layer 160, the resistance between the conductive layer 140 and the conductive layer 150 and the conductive layer 170 is high, and it has the characteristic of low gate leakage current. has the characteristic of low gate leakage current.

[0251] The transistors 101 and 102 have a top gate structure in which the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. The width of the channel in the longitudinal direction of the channel in this region is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current. The transistors 101 and 102 have a top gate structure in which the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. The width of the channel in the longitudinal direction of the channel in this region is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current. The width of the channel in the longitudinal direction of the channel in this region is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current.

[0252] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 45(E) and (F). FIG. 45(E) is a top view of the transistor 103, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 45(E) corresponds to FIG. 45(F). Also, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 45(E) corresponds to FIG. 47(A). Also, the direction of the dashed-dotted line D1-D2 is referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 is referred to as the channel width direction. FIG. 45(E) is a top view of the transistor 103, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 45(E) corresponds to FIG. 45(F). Also, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 45(E) corresponds to FIG. 47(A). Also, the direction of the dashed-dotted line D1-D2 is referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 is referred to as the channel width direction. FIG. 45(E) is a top view of the transistor 103, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 45(E) corresponds to FIG. 45(F). Also, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 45(E) corresponds to FIG. 47(A). Also, the direction of the dashed-dotted line D1-D2 is referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 is referred to as the channel width direction. FIG. 45(E) is a top view of the transistor 103, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 45(E) corresponds to FIG. 45(F). Also, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 45(E) corresponds to FIG. 47(A). Also, the direction of the dashed-dotted line D1-D2 is referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 is referred to as the channel width direction. FIG. 45(E) is a top view of the transistor 103, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 45(E) corresponds to FIG. 45(F). Also, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 45(E) corresponds to FIG. 47(A). Also, the direction of the dashed-dotted line D1-D2 is referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 is referred to as the channel width direction.

[0253] The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. and has a conductive layer 150. Further, if necessary, it may have an insulating layer 180, a conductive layer 140, and an insulating layer (planarization film) in contact with the conductive layer 150, etc. It may have an insulating layer (planarization film) in contact with the conductive layer 150, etc.

[0254] Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer, respectively. Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer, respectively.

[0255] Further, the region 231 shown in FIG. 45(F) can function as a source region, the region 232 can function as a drain region, and the region 233 can function as a channel formation region. The regions 231 and 232 are in contact with the insulating layer 175. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the regions 231 and 232 can be made to have low resistance. Further, the region 231 shown in FIG. 45(F) can function as a source region, the region 232 can function as a drain region, and the region 233 can function as a channel formation region. The regions 231 and 232 are in contact with the insulating layer 175. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the regions 231 and 232 can be made to have low resistance. Further, the region 231 shown in FIG. 45(F) can function as a source region, the region 232 can function as a drain region, and the region 233 can function as a channel formation region. The regions 231 and 232 are in contact with the insulating layer 175. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the regions 231 and 232 can be made to have low resistance. Further, the region 231 shown in FIG. 45(F) can function as a source region, the region 232 can function as a drain region, and the region 233 can function as a channel formation region. The regions 231 and 232 are in contact with the insulating layer 175. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the regions 231 and 232 can be made to have low resistance.

[0256] Specifically, due to the interaction between the oxygen vacancies generated in the regions 231 and 232 by the process until the insulating layer 175 is formed and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232, the regions 231 and 232 become low-resistance n-type. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, etc. can be used. Specifically, due to the interaction between the oxygen vacancies generated in the regions 231 and 232 by the process until the insulating layer 175 is formed and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232, the regions 231 and 232 become low-resistance n-type. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, etc. can be used. Specifically, due to the interaction between the oxygen vacancies generated in the regions 231 and 232 by the process until the insulating layer 175 is formed and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232, the regions 231 and 232 become low-resistance n-type. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, etc. can be used. Specifically, due to the interaction between the oxygen vacancies generated in the regions 231 and 232 by the process until the insulating layer 175 is formed and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232, the regions 231 and 232 become low-resistance n-type. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, etc. can be used.

[0257] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(A) and (B). FIG. 46(A) is a top view of the transistor 104, and the cross-section in the dash-dotted line E1-E2 direction shown in FIG. 46(A) corresponds to FIG. 46(B). Also, the cross-section in the dash-dotted line E3-E4 direction shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the dash-dotted line E1-E2 direction is referred to as the channel length direction, and the dash-dotted line E3-E4 direction is referred to as the channel width direction. Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(A) and (B). FIG. 46(A) is a top view of the transistor 104, and the cross-section in the dash-dotted line E1-E2 direction shown in FIG. 46(A) corresponds to FIG. 46(B). Also, the cross-section in the dash-dotted line E3-E4 direction shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the dash-dotted line E1-E2 direction is referred to as the channel length direction, and the dash-dotted line E3-E4 direction is referred to as the channel width direction. Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(A) and (B). FIG. 46(A) is a top view of the transistor 104, and the cross-section in the dash-dotted line E1-E2 direction shown in FIG. 46(A) corresponds to FIG. 46(B). Also, the cross-section in the dash-dotted line E3-E4 direction shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the dash-dotted line E1-E2 direction is referred to as the channel length direction, and the dash-dotted line E3-E4 direction is referred to as the channel width direction. Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(A) and (B). FIG. 46(A) is a top view of the transistor 104, and the cross-section in the dash-dotted line E1-E2 direction shown in FIG. 46(A) corresponds to FIG. 46(B). Also, the cross-section in the dash-dotted line E3-E4 direction shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the dash-dotted line E1-E2 direction is referred to as the channel length direction, and the dash-dotted line E3-E4 direction is referred to as the channel width direction. Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(A) and (B). FIG. 46(A) is a top view of the transistor 104, and the cross-section in the dash-dotted line E1-E2 direction shown in FIG. 46(A) corresponds to FIG. 46(B). Also, the cross-section in the dash-dotted line E3-E4 direction shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the dash-dotted line E1-E2 direction is referred to as the channel length direction, and the dash-dotted line E3-E4 direction is referred to as the channel width direction.

[0258] Transistor 104 has the same configuration as transistor 103, except that the conductive layer 140 and the conductive layer 150 are in contact with each other so as to cover the end of the oxide semiconductor layer 130. Also, regions 331 and 334 shown in FIG. 46(B) can function as source regions, regions 332 and

[0259] region 335 can function as drain regions, and region 333 can function as a channel formation region. .

[0260] Regions 331 and 332 can be made to have low resistance in the same manner as regions 231 and 23 2 in transistor 101.

[0261] Also, regions 334 and 335 can be made to have low resistance in the same manner as regions 231 and the region 232 in transistor 103. Note that when the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not significantly decrease due to the contribution of the gate electric field. Therefore, regions 334 and 33 5 may not be made to have low resistance.

[0262] Transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layer 140 and the conductive layer 150. A self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer and the source electrode layer and the drain electrode layer, and thus is suitable for high-speed operation applications.

[0263] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 46(C) and (D). FIG. 46(C) is a top view of transistor 105, and the dashed-dotted line F shown in FIG. 46(C) is ​​​The cross section in the 1-F2 direction corresponds to FIG. 46(D). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 47(A). The direction of the dashed dotted line F3-F4 is referred to as the channel width direction.

[0264] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0265] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0266] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. And the conductive layer 142) can function as a source electrode layer, and the conductive layer 150 (conductive layer 151 and conductive layer 152) can function as a drain electrode layer.

[0267] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 46(E) and (F). FIG. 46(E) is a top view of the transistor 106, and the cross section in the direction of the dashed line G 1-G2 shown in FIG. 46(E) corresponds to FIG. 46(F). Also, the cross section in the direction of the dashed line G3 -G4 shown in FIG. 46(A) corresponds to FIG. 47(A). Also, the direction of the dashed line G1-G2 is referred to as the channel length direction, and the direction of the dashed line G3-G4 is referred to as the channel width direction.

[0268] The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 respectively through openings provided in the insulating layer 175 and the insulating layer 180. Also, an insulating layer (planarization film ) in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided as necessary.

[0269] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and are not in contact with the side surfaces.

[0270] Transistor 106 has the same configuration as transistor 103, except that it has conductive layers 141 and 151. Conductive layer 140 (conductive layers 141 and 142) can act as a source electrode layer, and conductive layer 150 (conductive layers 151 and 152) can act as a drain electrode layer. In the configurations of transistors 105 and 106, since conductive layers 140 and 150 do not contact insulating layer 120, oxygen in insulating layer 120 is less likely to be taken away by conductive layers 140 and 150, and the supply of oxygen from insulating layer 120 into oxide semiconductor layer 130 can be facilitated. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed.

[0271] In the configurations of transistors 105 and 106, since conductive layers 140 and 150 do not contact insulating layer 120, oxygen in insulating layer 120 is less likely to be taken away by conductive layers 140 and 150, and the supply of oxygen from insulating layer 120 into oxide semiconductor layer 130 can be facilitated. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used.

[0272] In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used.

[0273] When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. In regions 231 and 232 of transistor 103, and regions 334 and 335 of transistors 104 and 106, impurities may be added to form oxygen deficiencies and increase conductivity. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As methods for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. By the interaction between the oxygen deficiency and hydrogen remaining in or added later to the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased.

[0274] When hydrogen is added to an oxide semiconductor in which oxygen deficiency is formed by the addition of impurity elements, hydrogen enters the oxygen deficiency sites and donor levels are formed near the conduction band. As a result, an oxide conductor can be formed. Here, the oxide semiconductor that has been made conductive is referred to as an oxide conductor. Note that the oxide conductor has translucency similar to that of the oxide semiconductor. The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. Therefore, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced.

[0275] The oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide. Therefore, the contact between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer is an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive layer functioning as the source electrode layer and the drain electrode layer can be reduced. In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 48(A), (B), (C), (D), (E ), (F), and the cross-sectional views in the channel width direction shown in FIGS. 47(C), (D). By using the conductive layer as a second gate electrode layer (back gate), the on-current can be increased and the threshold voltage can be controlled. In the cross-sectional views shown in FIGS. 48(A), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170.

[0276] In addition, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction shown in FIGS. 48(A), (B), (C), (D), (E ), (F), and the cross-sectional views in the channel width direction shown in FIGS. 47(C), (D). By using the conductive layer as a second gate electrode layer (back gate), the on-current can be increased and the threshold voltage can be controlled. In the cross-sectional views shown in FIGS. 48(A), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170. The conductive layer can be used as a second gate electrode layer (back gate) to increase the on-current and control the threshold voltage. In the cross-sectional views shown in FIGS. 48(A), (B), (C), (D), (E), (F), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170. (B), (C), (D), (E), (F), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170. The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 170. The width of the conductive layer 173 may be shorter than the width of the conductive layer 170.

[0277] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 may be set to the same potential and driven as a double gate transistor. To control the threshold voltage, a fixed potential different from that of the conductive layer 170 may be supplied to the conductive layer 173. To set the conductive layer 170 and the conductive layer 1 73 to the same potential, for example, as shown in FIG. 47(D), the conductive layer 170 and the conductive layer 1 73 may be electrically connected via a contact hole.

[0278] Also, in the transistors 101 to 106 in FIGS. 45 and 46, an example in which the oxide semiconductor layer 130 is a single layer is illustrated, but the oxide semiconductor layer 130 may be laminated. The oxide semiconductor layers 130 of the transistors 101 to 106 can be replaced with the oxide semiconductor layers 130 shown in FIG. 49 (B), (C) or FIG. 49(D), (E). FIG. 49(A) is a top view of the oxide semiconductor layer 130, and FIGS. 49(B), (C) are cross-sectional views of the oxide semiconductor layer 130 having a two-layer structure. Also, FIGS. 49(D), (E) are cross-sectional views of the oxide semiconductor layer 130 having a three-layer structure.

[0279] For the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, oxide semiconductor layers having different compositions can be used, respectively.

[0280]

[0281] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 50(A), (B). FIG. 50(A) is a top view of the transistor 107, and the cross-section in the one-dot chain line H 1-H2 direction shown in FIG. 50(A) corresponds to FIG. 50(B). Also, the one-dot chain line H3 shown in FIG. 50(A) - The cross-section in the -H4 direction corresponds to FIG. 52(A). Also, the direction of the dashed-dotted line H1-H2 is defined as the channel longitudinal direction, and the direction of the dashed-dotted line H3-H4 is defined as the channel width direction.

[0282] The transistor 107 includes a stacked layer composed of an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and conductive layers 140 and 150 that are electrically connected to the stacked layer, an oxide semiconductor layer 130c in contact with the stacked layer, the conductive layer 140, and the conductive layer 15 0, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Also, a function as a planarization film may be added to the insulating layer 180 as needed.

[0283] The transistor 107 has a structure similar to that of the transistor 101, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in regions 231 and 232, a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 140 and 150 and the insulating layer 160.

[0284] Also, the transistor according to one aspect of the present invention may have the structure shown in FIGS. 50(C) and (D). FIG. 50(C) is a top view of the transistor 108, and the dashed-dotted line I shown in FIG. 50(C) ​​​​​​​The cross-section in the 1-I2 direction corresponds to FIG. 50(D). Also, the dashed-dotted line I3 shown in FIG. 50(C) - The cross-section in the I4 direction corresponds to FIG. 52(B). Also, the dashed-dotted line I1-I2 direction is defined as the channel length direction, and the dashed-dotted line I3-I4 direction is defined as the channel width direction.

[0285] The transistor 108 is different from the transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130c do not coincide with the ends of the conductive layer 17 0.

[0286] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 50(E) and (F). FIG. 50(E) is a top view of the transistor 109. The cross-section in the dashed-dotted line J1-J2 direction shown in FIG. 50(E) corresponds to FIG. 50(F). Also, the cross-section in the dashed-dotted line J3-J4 direction shown in FIG. 50(E) corresponds to FIG. 52(A). Also, the dashed-dotted line J1-J2 direction is defined as the channel length direction, and the dashed-dotted line J3-J4 direction is defined as the channel width direction.

[0287] The transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack composed of an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, an oxide semiconductor layer 130c in contact with the stack, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 140 and 150 that are electrically connected to the stack through an opening provided in the insulating layer 175 and the insulating layer 180. Also, if necessary, it may have an insulating layer (planarization film) in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150.

[0288] The transistor 109 has a structure similar to that of the transistor 103, except that in regions 231 and 232, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 233, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 109 has a structure similar to that of the transistor 103, except that in regions 231 and 232, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 233, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 109 has a structure similar to that of the transistor 103, except that in regions 231 and 232, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 233, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 109 has a structure similar to that of the transistor 103, except that in regions 231 and 232, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 233, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c).

[0289] Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(A) and 51(B). FIG. 51(A) is a top view of the transistor 110, and a cross-section taken along the dash-dotted line K1-K2 direction shown in FIG. 51(A) corresponds to FIG. 51(B). Also, a cross-section taken along the dash-dotted line K3-K4 direction shown in FIG. 51(A) corresponds to FIG. 52(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(A) and 51(B). FIG. 51(A) is a top view of the transistor 110, and a cross-section taken along the dash-dotted line K1-K2 direction shown in FIG. 51(A) corresponds to FIG. 51(B). Also, a cross-section taken along the dash-dotted line K3-K4 direction shown in FIG. 51(A) corresponds to FIG. 52(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(A) and 51(B). FIG. 51(A) is a top view of the transistor 110, and a cross-section taken along the dash-dotted line K1-K2 direction shown in FIG. 51(A) corresponds to FIG. 51(B). Also, a cross-section taken along the dash-dotted line K3-K4 direction shown in FIG. 51(A) corresponds to FIG. 52(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(A) and 51(B). FIG. 51(A) is a top view of the transistor 110, and a cross-section taken along the dash-dotted line K1-K2 direction shown in FIG. 51(A) corresponds to FIG. 51(B). Also, a cross-section taken along the dash-dotted line K3-K4 direction shown in FIG. 51(A) corresponds to FIG. 52(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(A) and 51(B). FIG. 51(A) is a top view of the transistor 110, and a cross-section taken along the dash-dotted line K1-K2 direction shown in FIG. 51(A) corresponds to FIG. 51(B). Also, a cross-section taken along the dash-dotted line K3-K4 direction shown in FIG. 51(A) corresponds to FIG. 52(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction.

[0290] The transistor 110 has a structure similar to that of the transistor 104, except that in regions 331 and 332, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 333, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 110 has a structure similar to that of the transistor 104, except that in regions 331 and 332, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 333, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 110 has a structure similar to that of the transistor 104, except that in regions 331 and 332, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 333, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). The transistor 110 has a structure similar to that of the transistor 104, except that in regions 331 and 332, the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in region 333, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c).

[0291] Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(C) and 51(D). FIG. 51(C) is a top view of the transistor 111, and a cross-section taken along the dash-dotted line L1-L2 direction shown in FIG. 51(C) corresponds to FIG. 51(D). Also, a cross-section taken along the dash-dotted line L3-L4 direction shown in FIG. 51(C) corresponds to FIG. 52(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(C) and 51(D). FIG. 51(C) is a top view of the transistor 111, and a cross-section taken along the dash-dotted line L1-L2 direction shown in FIG. 51(C) corresponds to FIG. 51(D). Also, a cross-section taken along the dash-dotted line L3-L4 direction shown in FIG. 51(C) corresponds to FIG. 52(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(C) and 51(D). FIG. 51(C) is a top view of the transistor 111, and a cross-section taken along the dash-dotted line L1-L2 direction shown in FIG. 51(C) corresponds to FIG. 51(D). Also, a cross-section taken along the dash-dotted line L3-L4 direction shown in FIG. 51(C) corresponds to FIG. 52(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. Also, a transistor according to an aspect of the present invention may have a structure shown in FIGS. 51(C) and 51(D). FIG. 51(C) is a top view of the transistor 111, and a cross-section taken along the dash-dotted line L1-L2 direction shown in FIG. 51(C) corresponds to FIG. 51(D). Also, a cross-section taken along the dash-dotted line L3-L4 direction shown in FIG. 51(C) corresponds to FIG. 52(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. The longitudinal direction and the direction of the dash-dotted line L3-L4 are referred to as the channel width direction.

[0292] The transistor 111 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and conductive layers 141 and 151 electrically connected to the stack. an oxide semiconductor layer 130c in contact with the stack, the conductive layer 141, and the conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the stack, the conductive layer 141, the conductive layer 151, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and conductive layers 142 and 152 that are electrically connected to the conductive layer 141 and the conductive layer 151, respectively, through openings provided in the insulating layer 175 and the insulating layer 180. Further, if necessary, an insulating layer (planarization film) and the like in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 may be provided.

[0293] The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160.

[0294] Further, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 51(E) and 51(F). Yes. FIG. 51(E) is a top view of the transistor 112, and the dashed-dotted line M shown in FIG. 51(E) The cross-section in the M1-M2 direction corresponds to FIG. 51(F). Also, the dashed-dotted line M3 shown in FIG. 51(E) -The cross-section in the M4 direction corresponds to FIG. 52(A). Also, the direction of the dashed-dotted line M1-M2 is defined as the channel length direction, and the direction of the dashed-dotted line M3-M4 is defined as the channel width direction.

[0295] The transistor 112 has the same structure as the transistor 106, except that in the regions 331, 332, 334, and 335, the oxide semiconductor layer 130 is composed of two layers (oxide semiconductor layer 130a and oxide semiconductor layer 130b), and in the region 333, the oxide semiconductor layer 130 is composed of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c). has the same structure.

[0296] Also, the transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as shown in the cross-sectional views in the channel length direction in FIGS. 53(A), (B), (C), (D), (E ), (F), and the cross-sectional views in the channel width direction shown in FIGS. 52(C) and (D). By using this conductive layer as a second gate electrode layer (back gate), it is possible to further increase the on-current and control the threshold voltage. In the cross-sectional views shown in FIGS. 53( A), (B), (C), (D), (E), (F), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 1 70. A), (B), (C), (D), (E), (F), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Further, the width of the conductive layer 173 may be shorter than the width of the conductive layer 1 70.

[0297] Also, the transistor according to one aspect of the present invention has the configuration shown in FIGS. 54(A) and 54(B), It can also be done. FIG. 54(A) is a top view, and FIG. 54(B) is a cross-sectional view corresponding to the dashed-dotted lines N1-N2 and N3-N4. In the top view of FIG. 54(A), some elements are omitted for clarity of the figure. It is a cross-sectional view corresponding to the dashed-dotted lines N1-N2 and N3-N4. Note that in the top view of FIG. 54(A), some elements are omitted for clarity of the figure. (A), some elements are shown with omission for clarity of the figure.

[0298] The transistor 113 shown in FIGS. 54(A) and 54(B) includes a substrate 115, an insulating layer 120 on the substrate 115, an oxide semiconductor layer 130 (oxide semiconductor layers 130a, 130b, 130c) on the insulating layer 120, conductive layers 140 and 150 that are in contact with the oxide semiconductor layer 130 and are arranged with a gap therebetween, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and a conductive layer 170 in contact with the insulating layer 160. Note that the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are provided in openings that reach the oxide semiconductor layers 130a and 130b provided in the insulating layer 190 on the transistor 113 and the insulating layer 120. 5, an insulating layer 120 on the substrate 115, and an oxide semiconductor layer 130 (oxide semiconductor layers 130a, 130b, 130c) on the insulating layer 120. a, oxide semiconductor layers 130b and 130c), and conductive layers 140 and 150 that are in contact with the oxide semiconductor layer 130 and are arranged with a gap therebetween. And an insulating layer 160 in contact with the oxide semiconductor layer 130c and a conductive layer 170 in contact with the insulating layer 160. Note that the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are provided in openings that reach the oxide semiconductor layers 130a and 130b provided in the insulating layer 190 on the transistor 113 and the insulating layer 120. The configuration of the transistor 113 has less overlapping area between the conductor serving as the source electrode or drain electrode and the conductor serving as the gate electrode compared with the configurations of the other transistors described above. Therefore, the parasitic capacitance can be reduced. Thus, the transistor 113 is suitable as an element of a circuit that requires high-speed operation. The top surface of the transistor 113 is preferably planarized using a method such as CMP (Chemical Mechanical Polishing) as shown in FIG. 54(B), but it can also be configured without planarization. 0 and is provided in an opening that reaches the insulating layer 120.

[0299] The configuration of the transistor 113 has less overlapping area between the conductor serving as the source electrode or drain electrode and the conductor serving as the gate electrode compared with the configurations of the other transistors described above. Therefore, the parasitic capacitance can be reduced. Thus, the transistor 113 is suitable as an element of a circuit that requires high-speed operation. The top surface of the transistor 113 is preferably planarized using a method such as CMP (Chemical Mechanical Polishing) as shown in FIG. 54(B), but it can also be configured without planarization. Therefore, the parasitic capacitance can be reduced. Thus, the transistor 113 is suitable as an element of a circuit that requires high-speed operation. The top surface of the transistor 113 is preferably planarized using a method such as CMP (Chemical Mechanical Polishing) as shown in FIG. 54(B), but it can also be configured without planarization. as shown in FIG. 54(B), but it can also be configured without planarization. using a method such as CMP (Chemical Mechanical Polishing) as shown in FIG. 54(B), but it can also be configured without planarization.

[0300] Also, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is a top view (oxide semiconductor layer 1) shown in FIG. 30, conductive layer 140 and conductive layer 150 are shown), O S ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. Also, as shown in FIG. 55(C), the conductive layer 140 and the conductive layer The insulating film 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0301] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0302] In addition, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. This is possible. Therefore, by increasing the thickness of the oxide semiconductor layer 130b, the on-current can be improved. This may occur.

[0303] With the above configuration, the electrical characteristics of the transistor can be improved.

[0304] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. This can be done.

[0305] (Embodiment 4) In this embodiment, the components of the transistor shown in Embodiment 2 will be described in detail. This will be done.

[0306] For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. This can be done. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. - For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. - For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramics substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. When the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. When the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased.

[0307] The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115. In addition, it can play a role in supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. The insulating layer 120 preferably has an oxygen release amount converted to oxygen atoms measured by the TDS method of 1.0×10 19 atoms / cm 3 or more. Note that the surface temperature of the film during the above TDS analysis is in the range of 100°C or higher and 700°C or lower, or 10 0°C or higher and 500°C or lower. When the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 also has a function as an interlayer insulating film. In that case, it is preferable to perform a planarization process by a CMP method or the like so that the surface becomes flat.

[0308] For example, the insulating layer 120 may be made of an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, a nitride insulating film such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride, or a mixed material thereof. Further, a laminate of the above materials may be used.

[0309] In this embodiment, the case where the oxide semiconductor layer 130 included in the transistor has a three-layer structure in which the oxide semiconductor layer 130 a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side will be mainly described in detail.

[0310] Note that when the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 13 shown in this embodiment ​​​​​​​​​A layer corresponding to 0b may be used.

[0311] In addition, when the oxide semiconductor layer 130 has two layers, a stack in which the layer corresponding to the oxide semiconductor layer 130a and the layer corresponding to the oxide semiconductor layer 130b shown in this embodiment are stacked in order from the insulating layer 120 side may be used. In this case, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can also be interchanged.

[0312] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, a configuration in which another oxide semiconductor layer is added to the three-layer oxide semiconductor layer 130 described in this embodiment can be adopted.

[0313] As an example, for the oxide semiconductor layer 130b, an oxide semiconductor having a larger electron affinity (energy from the vacuum level to the lower end of the conduction band) than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is used. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the lower end of the conduction band and the upper end of the valence band from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band.

[0314] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain one or more metal elements constituting the oxide semiconductor layer 130b. For example, the energy of the lower end of the conduction band is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more higher than that of the oxide semiconductor layer 130b, and it is preferably formed of an oxide semiconductor close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less.

[0315] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that the nucleus has a region that functions in a specific manner.

[0316] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0317] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0318] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , materials containing Ge, Y, Zr, Sn, La, Ce, or Hf at an atomic ratio higher than that of the oxide semiconductor layer 130b can be used. Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. Since the aforementioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen deficiency in the oxide semiconductor layer. That is, it can be said that the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are less likely to have oxygen deficiency than the oxide semiconductor layer 130b.

[0319] Also, the oxide semiconductors that can be used as the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 c preferably contain at least In or Zn. Or, it is preferable to contain both In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistors using the oxide semiconductor, it is preferable to contain a stabilizer along with them.

[0320] Examples of the stabilizer include Ga, Sn, Hf, Al, or Zr, etc. Also, other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, G d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0321] For example, as the oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide ​​​​​​​Substances, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In -Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm- Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxide s, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In -Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn oxides, In-Sn- Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, I n-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides can be used.

[0322] Here, for example, the In-Ga-Zn oxide means an oxide having In, Ga, and Zn as main components. Also, metal elements other than In, Ga, and Zn may be included. Also, in this specification, a film composed of an In-Ga-Zn oxide is also referred to as an IGZO film.

[0323] Also, materials represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Also, materials represented by In2SnO5(ZnO) (n > 0 and n is an integer) may be used. n (n > 0, and n is an integer) may be used.

[0324] Also, the oxide semiconductor layer 130b preferably has a higher indium content than the oxide semiconductor layer 130a and the oxide semiconductor layer 130 c. In oxide semiconductors, mainly the s orbitals of heavy metals ​​The path contributes to carrier conduction. By increasing the In content, more s-orbitals overlap. Therefore, an oxide with a composition in which In is more than M has a higher mobility than an oxide with a composition in which In is equal to or less than M. Therefore, by using an oxide with a high indium content for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

[0325] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, more preferably 5 nm or more and 25 nm or less. Also, the thickness of the oxide semiconductor layer 130b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, more preferably 10 nm or more and 100 nm or less. Also, the thickness of the oxide semiconductor layer 130c is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, more preferably 3 nm or more and 15 nm or less. Also, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130c.

[0326] In order to impart stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic (i-type) or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less 19 than 1×10 3 / cm 15 / cm 3 less than 1×10 ×10 13 / cm 3 less than 1×10 8 / cm 3 less than 1×10 -9 / cm 3 This indicates the above.

[0327] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main components become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Also, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, and at their respective interfaces.

[0328] To make the oxide semiconductor layer intrinsic or substantially intrinsic, the hydrogen concentration estimated by SIMS (Secondary Ion Mass Spectrometry) analysis is 2 ×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, even more preferably 5×10 18 a toms / cm 3 or less, and has a region of 1×10 17 atoms / cm 3 or more. Also, the nitrogen concentration is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm3 The following is controlled to have a region of 5×10 16 atoms / cm 3 or more.

[0329] In addition, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order not to reduce the crystallinity of the oxide semiconductor layer, the silicon concentration is controlled to be less than 1×10 19 atoms / cm 3 and preferably less than 5×10 18 atoms / cm 3 and is controlled to have a region of 1× 10 18 atoms / cm 3 or more. Also, the carbon concentration is controlled to be less than 1×10 19 atoms / cm 3 and preferably less than 5×10 18 atoms / cm 3 and more preferably less than 1×10 10 18 atoms / cm 3 and is controlled to have a region of 6×10 17 ato ms / cm 3 or more.

[0330] In addition, the off-current of the transistor using the oxide semiconductor layer purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current per channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0331] As the gate insulating film of the transistor, an insulating film containing silicon is often used. For the reasons described above, the region that becomes the channel of the oxide semiconductor layer is that of the transistor according to one aspect of the present invention. It can be said that a structure that does not contact the gate insulating film is preferable. Further, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering may occur at the interface and the field-effect mobility of the transistor may be reduced. From this point of view as well, it can be said that the region serving as the channel of the oxide semiconductor layer is preferably separated from the gate insulating film.

[0332] Therefore, by forming the oxide semiconductor layer 130 into a stacked structure of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b , and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b , and a transistor having high field-effect mobility and stable electrical characteristics can be formed.

[0333] In the band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the energy at the lower end of the conduction band changes continuously. This is understood also from the fact that the compositions of the oxide semiconductor layer 1 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are approximated, and oxygen diffuses easily among them. Therefore, although the oxide semiconductor layer 130a , the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are a laminate of layers having different compositions , it can also be said that they are physically continuous, and in the drawings, the respective interfaces of the laminate are represented by dotted lines.

[0334] The oxide semiconductor layer 130 laminated with a common main component is fabricated not simply by laminating the respective layers but by forming a continuous junction (here, in particular, a U-shaped well structure (U Shape Well) in which the energy at the lower end of the conduction band changes continuously between the layers). That is, each layer There are no impurities that form defect energy levels such as trap centers or recombination centers on the interface. A stacked structure is formed so that no impurities are present. If impurities are mixed between the stacked oxide semiconductor layers, the continuity of the energy bands is lost, and carriers are trapped or recombined at the interface and disappear.

[0335] For example, in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, 1:9: 6, 1:10:1 or their approximate values (atomic ratio), etc., such as In-Ga-Zn oxides, and Ga:Zn = 10:1 or their approximate values (atomic ratio), etc., such as Ga-Zn oxides can be used. Also, in the oxide semiconductor layer 130b, In:Ga:Zn = 1:1:1, 2: 1:3, 5:5:6, 3:1:2, 4:2:3, 4:2:4.1 or their approximate values ( atomic ratio), etc., such as In-Ga-Zn oxides can be used. When the above oxides are used as sputtering targets for film formation, the atomic ratios of the formed oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c do not necessarily have to be the same.

[0336] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b serves as a well, and a channel is formed in the oxide semiconductor layer 130b. Since the energy of the lower end of the conduction band of the oxide semiconductor layer 130 changes continuously, it can also be called a U-shaped well. Also, the channel formed in such a configuration can be called a buried channel.

[0337] Also, between the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and a silicon oxide film, etc. Near the interface with the insulating layer, trap levels can be formed due to impurities and defects. Oxide Due to the presence of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 0b can be kept away from the trap levels.

[0338] However, when the difference in energy between the lower conduction band edges of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c and the energy of the lower conduction band edge of the oxide semiconductor layer 130b is small, electrons in the oxide semiconductor layer 130b may reach the trap levels across the energy difference. When electrons are trapped at the trap levels, negative charges are generated at the insulating layer interface, and the threshold voltage of the transistor shifts in the positive direction. are trapped at the trap levels, negative charges are generated at the insulating layer interface, and the threshold voltage of the transistor shifts in the positive direction.

[0339] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably contain crystalline portions. In particular, by using crystals oriented along the c-axis, stable electrical characteristics can be imparted to the transistor . Also, crystals oriented along the c-axis are resistant to distortion, and the reliability of semiconductor devices using flexible substrates can be improved.

[0340] For the conductive layer 140 acting as the source electrode layer and the conductive layer 1 50 acting as the drain electrode layer, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and alloys of the metal materials can be used . Typically, it is more preferable to use W with a high melting point, such as Ti which easily binds with oxygen and can withstand a relatively high subsequent process temperature . Also, a laminate of an alloy such as low-resistance Cu or Cu-M n and the above materials may be used. Transistor 105, transistor 1 06. In the transistors 111 and 112, for example, W can be used for the conductive layer 141 and the conductive layer 151, and a laminated film of Ti and Al can be used for the conductive layer 142 and the conductive layer 152.

[0341] The above materials have the property of extracting oxygen from the oxide semiconductor layer. Therefore, in a part of the region of the oxide semiconductor layer in contact with the above materials, oxygen in the oxide semiconductor layer desorbs, forming oxygen vacancies. The hydrogen slightly contained in the film combines with the oxygen vacancies, causing the region to be significantly n-type. Therefore, the n-type region can act as the source or drain of the transistor.

[0342] Also, when W is used for the conductive layer 140 and the conductive layer 150, nitrogen can be doped. By doping nitrogen, the property of extracting oxygen can be moderately weakened, and the expansion of the n-type region to the channel region can be prevented. Also, by laminating the conductive layer 140 and the conductive layer 150 with an n-type semiconductor layer and bringing the n-type semiconductor layer into contact with the oxide semiconductor layer, the expansion of the n-type region to the channel region can be prevented. As the n-type semiconductor layer, indium-gallium-zinc oxide doped with nitrogen, zinc oxide, indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0343] For the insulating layer 160 that acts as the gate insulating film, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, etc. can be used. An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0344] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0345] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0346] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0347] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 cm -3 5×10 or more 19 cm -3 The amount of ammonia released is as follows: The surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount of release is the amount of

[0348] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0349] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine-based compound.

[0350] For the insulating layer 175, a silicon nitride film containing hydrogen, an aluminum nitride film, or the like can be used. In the transistors 103, 104, 106, 109, 110, and 112 shown in Embodiment 2, by using an insulating film containing hydrogen as the insulating layer 175, a part of the oxide semiconductor layer can be made n-type. In addition, the nitride insulating film also acts as a blocking film for moisture and the like, and can improve the reliability of the transistor.

[0351] In addition, an aluminum oxide film can also be used as the insulating layer 175. In particular, in the transistors 101, 102, 105, 107, 108, and 111 shown in Embodiment 2, it is preferable to use an aluminum oxide film for the insulating layer 175. The aluminum oxide film has a high blocking effect of not allowing the film to permeate impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film is suitable for use as a protective film that prevents the mixing of impurities such as hydrogen and moisture into the oxide semiconductor layer 130, prevents the release of oxygen from the oxide semiconductor layer, and prevents the unnecessary release of oxygen from the insulating layer 120 during and after the manufacturing process of the transistor. In addition, the oxygen contained in the aluminum oxide film can also be diffused into the oxide semiconductor layer.

[0352] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. Examples of the insulating layer include magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, and lanthanum oxide. ​ An insulating film containing one or more of tantum, neodymium oxide, hafnium oxide, and tantalum oxide can be used. Also, the insulating layer may be a laminate of the above materials.

[0353] Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can be diffused through the insulating layer 160 to the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen deficiency formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. To highly integrate a semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor. In particular, when the channel width is reduced, the on-current decreases.

[0354] In the transistors 107 to 112 according to one aspect of the present invention, an oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which the channel is formed, and the channel formation layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased.

[0355]

[0356]

[0356] In addition, in the transistor according to one aspect of the present invention, as described above, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130. Therefore, in addition to the gate electric field from the direction perpendicular to the upper surface with respect to the oxide semiconductor layer 130, A gate electric field is applied from a direction perpendicular thereto. That is, since the gate electric field is applied to the entire channel formation layer and the effective channel width is expanded, the on-current can be further increased.

[0357] Also, in the case where the oxide semiconductor layer 130 in one aspect of the present invention is a two-layer or three-layer transistor, forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a has an effect of making it difficult to form interface levels. Further, in the case where the oxide semiconductor layer 130 in one aspect of the present invention is a three-layer transistor, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, it is possible to eliminate the influence of impurity mixing from above and below, and the like. Therefore, in addition to the improvement of the on-current of the transistor described above, it is possible to achieve stabilization of the threshold voltage and reduction of the S value (subthreshold value). Therefore, the current when the gate voltage VG is 0 V can be reduced, and the power consumption can be reduced. Further, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. Also, the transistor according to one aspect of the present invention is suitable for forming a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization can be suppressed.

[0358] Various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment can typically be formed by a sputtering method or a plasma CVD method, but may also be formed by other methods, for example, a thermal CVD method. Examples of the thermal CVD method include MOCVD (Metal Organic Chemical Vapor Deposition) method and ALD (Atomic Layer Deposition) method. ​​​​​​​​​​​​​​​​

[0359] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. It has the advantage of not being generated.

[0360] Also, in the thermal CVD method, the source gas and the oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to deposit on the substrate, thereby film formation may be performed.

[0361] In the ALD method, the inside of the chamber is under atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas ( argon, nitrogen, etc.) may be introduced as a carrier gas together with the source gas. For example, two or more types of source gases may be supplied to the chamber in order. At that time, after the reaction of the first source gas so that a plurality of types of source gases do not mix, an inert gas is introduced, and the second source gas is introduced. Or, instead of introducing an inert gas, after exhausting the first source gas by evacuation, the second source gas may be introduced. The first source gas is adsorbed and reacted on the surface of the substrate to form the first layer, and the second source gas introduced later is adsorbed and reacted, and the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions of the gas introduction, precise film thickness adjustment is possible and it is suitable for fabricating fine FETs. and the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions of the gas introduction, precise film thickness adjustment is possible and it is suitable for fabricating fine FETs. times, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions of the gas introduction, precise film thickness adjustment is possible and it is suitable for fabricating fine FETs. and it is suitable for fabricating fine FETs.

[0362] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described so far. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. For example, when forming an In-Ga -Zn-O film, trimethylindium (In(CH3)3), trimeth ylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used . It is not limited to these combinations, and triethyl gallium (Ga(C2H5)3) can also be used instead of trimethylgallium, and diethyl zinc (Zn(C2H5)2) can also be used instead of dimethylzinc.

[0363] For example, when forming a hafnium oxide film by a film-forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4), hafnium amide such as tetrakis(ethylmethylamide) hafnium) is vaporized to obtain a source gas, and two types of gases, ozone ( O3) as an oxidizing agent, are used. ) hafnium and the like) are vaporized to obtain a source gas, and two types of gases, ozone ( O3) as an oxidizing agent, are used.

[0364] For example, when forming an aluminum oxide film by a film-forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 ) etc.) is vaporized to obtain a source gas, and two types of gases, H2O as an oxidizing agent, are used. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, al uminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. are available.

[0365] For example, when forming a silicon oxide film by a film-forming apparatus using ALD, hexachloro disilane is adsorbed on the film-forming surface, and radicals of an oxidizin...

Claims

1. The semiconductor device includes a photoelectric conversion element, a capacitor, a first transistor, and a second transistor, which are formed on a silicon substrate; when an anode of the photoelectric conversion element arranged on a light receiving surface side of the photoelectric conversion element is regarded as an upper side, the capacitive element, the first transistor, and the second transistor have a region arranged below the anode, a cathode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to the capacitive element, a first conductive layer having a function as one electrode of the capacitor element and having a region in which an upper surface of the first conductive layer is in contact with a first insulating layer; a second conductive layer having a function as the other electrode of the capacitor element and having a region where a lower surface of the second conductive layer is in contact with the second insulating layer; a third conductive layer electrically connected to the anode and having an upper surface that contacts the first insulating layer; a fourth conductive layer electrically connected to the anode via the third conductive layer and having a function as a wiring for controlling the potential of the anode; a fifth conductive layer that functions as a first signal line electrically connected to a gate of the first transistor and has a lower surface that is in contact with the second insulating layer; a sixth conductive layer having a function as a second signal line electrically connected to a gate of the second transistor and having a lower surface having a region in contact with the second insulating layer; a hafnium oxide layer having a region disposed above the light receiving surface; a light-shielding layer having a region disposed above the light-receiving surface with the hafnium oxide layer therebetween; having the other of the source and the drain of the first transistor is electrically connected to the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the first conductive layer; the fourth conductive layer has a region disposed below the third conductive layer; a region of the anode that does not overlap with the light-shielding layer overlaps with a channel formation region of the first transistor and also overlaps with a channel formation region of the second transistor; Imaging device.

2. The semiconductor device includes a photoelectric conversion element, a capacitor, a first transistor, and a second transistor, which are formed on a silicon substrate; when an anode of the photoelectric conversion element arranged on a light receiving surface side of the photoelectric conversion element is regarded as an upper side, the capacitive element, the first transistor, and the second transistor have a region arranged below the anode, a cathode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to the capacitive element, a first conductive layer having a function as one electrode of the capacitor element and having a region in which an upper surface of the first conductive layer is in contact with a first insulating layer; a second conductive layer having a function as the other electrode of the capacitor element and having a region where a lower surface of the second conductive layer is in contact with the second insulating layer; a third conductive layer electrically connected to the anode and having an upper surface that contacts the first insulating layer; a fourth conductive layer electrically connected to the anode via the third conductive layer and having a function as a wiring for controlling the potential of the anode; a fifth conductive layer that functions as a first signal line electrically connected to a gate of the first transistor and has a lower surface that is in contact with the second insulating layer; a sixth conductive layer having a function as a second signal line electrically connected to a gate of the second transistor and having a lower surface having a region in contact with the second insulating layer; a hafnium oxide layer having a region disposed above the light receiving surface; a light-shielding layer having a region disposed above the light-receiving surface with the hafnium oxide layer therebetween; having the other of the source and the drain of the first transistor is electrically connected to the first conductive layer; one of a source and a drain of the second transistor is electrically connected to the first conductive layer; the fourth conductive layer has a region disposed below the third conductive layer; a region of the anode that does not overlap with the light-shielding layer overlaps with a channel formation region of the first transistor, overlaps with a channel formation region of the second transistor, and overlaps with the first conductive layer; Imaging device.

3. In claim 1 or 2, a second layer including a third transistor and a fourth transistor, the second layer being stacked with a first layer including the first transistor, the second transistor, and the capacitance element; the second layer having a region disposed below the first layer; Imaging device.

Images