Current-mode feedforward ripple cancellation

Abstract

In one example, the apparatus includes an error amplifier (202), a buffer (206), a transistor (208), and a current-mode feed-forward ripple canceller (CFFRC) (106). The error amplifier has an amplifier output, a first input, and a second input, with the error amplifier second input configured to receive a reference voltage (Vref). The buffer has a buffer input and a buffer output, with the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, with the gate coupled to the buffer output and the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at its source and provide an output voltage at its drain. The CFFRC has a CFFRC input and a CFFRC output, with the CFFRC output coupled to the gate, with the CFFRC input configured to receive VIN.

Description

Technical Field

[0001] A low dropout regulator (LDO) is a direct current (DC) linear voltage regulator that adjusts an output voltage (VOUT) based on an input voltage (VIN). When VIN is greater than a reference voltage (VREF) indicating a programmed setpoint for VOUT, the LDO adjusts VIN downward to provide VOUT. The LDO can be used as a filtering device following a switching regulator to condition a signal before providing it to a load. VIN can include signal noise or other variations in value, and the power supply rejection ratio (PSR) of the LDO can define the ability of the LDO to suppress the passing of this noise or other variations in value to VOUT.

Summary of the Invention

[0002] In one example, an apparatus includes an error amplifier, a buffer, a transistor, and a current mode feed forward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, and the second input is configured to receive a reference voltage (Vref). The buffer has a buffer input and a buffer output, and the buffer input is coupled to the amplifier output. The transistor has a gate, a source, and a drain, the gate is coupled to the buffer output, and the drain is coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage (VOUT) at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output is coupled to the gate, and the CFFRC input is configured to receive VIN.

[0003] In one example, a device includes a transistor, an error amplifier, a buffer, and a CFFRC. The transistor has a gate, a source, and a drain, and the source is configured to receive VIN. The error amplifier is configured to compare VOUT at the drain with Vref and provide an error signal in response to the comparison. The buffer is configured to provide the error signal to the gate. The CFFRC is configured to sense a voltage ripple at VIN, convert the sensed voltage ripple to a current representation of the voltage ripple, and provide the current representation of the voltage ripple to the gate.

[0004] In one example, a system includes a load and a low dropout regulator (LDO). The LDO is adapted to be coupled to the load and is configured to provide a regulated VOUT to the load based on VIN. The LDO includes a transistor, an error amplifier, a buffer, and a CFFRC. The transistor has a gate, a source, and a drain, and the source is configured to receive VIN. The error amplifier is configured to compare VOUT at the drain with Vref and provide an error signal in response to the comparison. The buffer is configured to provide the error signal to the gate. The CFFRC is configured to sense a voltage ripple at VIN, convert the sensed voltage ripple to a current representation of the voltage ripple, and provide the current representation of the voltage ripple to the gate.

Brief Description of the Drawings

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Figure 1

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Figure 8A

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Figure 8B

Mode for Carrying Out the Invention

[0014] In a low-dropout regulator (LDO), it can be advantageous to have a high power supply rejection (PSR) ratio over a wide range of frequencies (such as a PSR exceeding about 45 decibels (dB) over a frequency range of about 2 megahertz (MHz)). The high PSR over a wide range of frequencies makes the LDO suitable for implementation in many applications, such as following a switching regulator that may provide an input voltage (VIN) with high or low frequency noise, and also enables providing an output voltage (VOUT) to components that may be sensitive to noise, such as, for example, system-on-chip (SOC), sensor modules, low-resolution power systems, and other noise-sensitive circuits (radio frequency (RF) circuits, analog-to-digital converters (ADC), phase-locked loops (PLL), etc.). Some LDO topologies can provide PSR within their loop bandwidth. However, their PSR performance degrades as the loop gain outside their loop bandwidth decreases. An LDO with an external filtering capacitor can have spectral peaks in its PSR response, which may cause an increase in system-level supply noise. Also, a large capacitor for improving the PSR response can increase the quiescent power consumption of the LDO, increase the silicon surface area consumed by the LDO, and thereby increase the cost of the LDO.

[0015] Aspects of the present disclosure relate to low dropout regulators (LDOs) having a wide frequency range and a high PSR rate. For example, at least one implementation of an LDO according to the present disclosure achieves a PSR exceeding 68 dB over a frequency up to 2 MHz and over a range of load currents from about 100 microamps (μA) to about 250 milliamps (mA). At least at some frequencies, this represents an improvement or increase in PSR of up to about 25 dB over other approaches. In at least some implementations, the above performance is achieved via a current-mode approach that does not use an adder amplifier in providing the PSR. At least one example of an LDO includes a current-mode feed-forward ripple canceller (CFFRC). The feed-forward path of an LDO including a CFFRC can be matched to the forward gain of the LDO. Thus, in at least some implementations, the CFFRC can be implemented without specific calibration for the LDO.

[0016] In at least some implementation environments, a low dropout regulator (LDO) including a p-type pass device such as a p-type transistor, a p-type field effect transistor (PFET), or a p-type metal oxide semiconductor (PMOS) FET can be implemented without including a charge pump to provide a drive signal to the gate of the p-type pass device. In contrast, an LDO including an n-type pass device (e.g., NFET) can use a charge pump to provide a drive signal to the gate of the n-type pass device. The charge pump can increase the quiescent current consumption of the LDO. Thus, in some situations, in LDO applications where a low quiescent current can be advantageous, it can be advantageous to use an LDO having a p-type pass device instead of an n-type pass device. For robust power supply rejection (PSR) performance, semiconductor physics can dictate that an n-type pass device can use a constant voltage on the gate of the pass device, and a p-type pass device can use a replicated supply voltage ripple on the gate of the pass device, as arising from its operation in a common source configuration. In at least some examples, the charge feed forward replica circuit (CFFRC) of the LDO described herein is configured to replicate the supply ripple of VIN received by the LDO to the gate of the p-type pass device of the LDO. The CFFRC can replicate the ripple to the gate of the pass device without regard to the frequency of the ripple and without using a summing amplifier, as described above.

[0017] FIG. 1 is a diagram of an exemplary system 100. At least some implementations of system 100 represent an application environment for an LDO including a CFFRC, as described above. In at least some examples, system 100 includes a power supply 102, an LDO 104 including a CFFRC 106, and a load 108. The LDO 104 can be coupled between the power supply 102 and the load 108 and can be configured to provide a regulated VOUT to the load 108 based on VIN received from the power supply 102. In some examples, VIN includes noise or other variations in value. For example, the power supply 102 can be any power supply suitable for the LDO 104, such as a battery, a switching power converter (such as a switch mode power supply), a transformer that can provide the LDO 104 with a VIN having some amount of noise or other variations in value.

[0018] In at least some examples, load 108 is noise sensitive or includes one or more components that are noise sensitive. Thus, in at least some such examples, it may be advantageous for LDO 104 to have a high PSR ratio to suppress noise or other variations at VIN to reduce the occurrence of noise or other variations at VOUT. To at least partially mitigate the passing of VIN noise to load 108 at VOUT, CFFRC 106 can detect the noise and replicate the noise onto the gate of a pass device (not shown) of LDO 104 to increase the PSR of LDO 104, thereby increasing the amount of VIN noise suppressed at VOUT.

[0019] FIG. 2 is a block diagram of an exemplary implementation of LDO 104. In at least some examples, LDO 104 includes CFFRC 106, error amplifier 202, compensation circuit 204, buffer 206, pass FET 208, current sense FET 210, adaptive bias generation circuit 212, and dynamic bias generation circuit 214. In at least some examples, LDO 104 is adapted to be coupled to one or more components at the output of LDO 104, such as resistor 216 and / or capacitor 218. Error amplifier section 202 may be any suitable operational transconductance amplifier (OTA), and the scope thereof is not limited herein.

[0020] In the exemplary architecture of LDO104, error amplifier 202 has a first input (e.g., positive or non - inverting input) coupled to the drain of pass FET 208, a second input (e.g., negative or inverting input) configured to receive a reference voltage (Vref), and an output. Compensation circuit 204 is coupled between the output of error amplifier 202 and ground 220. In at least some examples, compensation circuit 204 includes one or more passive components (not shown), such as capacitors and / or resistors, that can filter or otherwise compensate the error amplifier output signal (V_ea) from the output of error amplifier 202. Buffer 206 has an input coupled to the output of error amplifier 202 and an output coupled to the gate of pass FET 208. CFFRC106 has an input coupled to the source of pass FET 208 and configured to receive VIN, and an output coupled to the gate of pass FET 208. In at least some examples, an impedance can be provided at the output of buffer 206. This is shown in LDO104 as impedance 222 coupled between the output of buffer 206 and ground 220. However, in at least some examples, impedance 222 may not be a physical component. Instead, impedance 222 can represent the output impedance that is inherent to buffer 206 and provided at the output of buffer 206. Current sense FET 210 has a source coupled to the source of pass FET 208, a gate coupled to the gate of pass FET 208, and a drain coupled to the input of adaptive bias generation circuit 212. Adaptive bias generation circuit 212 has a first output coupled to compensation circuit 204 and a second output coupled to the first input of dynamic bias generation circuit 214. Dynamic bias generation circuit 214 has a first output coupled to the bias input of buffer 206, a second output coupled to the first input of error amplifier 202, a second input configured to receive Vref, and a third input coupled to the drain of pass FET 208. In at least some examples, the output of LDO104 (where VOUT is provided) is the drain of pass FET 208.In at least some examples, resistor 216 and capacitor 218 can be coupled in series between the drain of pass FET 208 and ground 220. In at least some examples, capacitor 218 can be an off-chip capacitor that is adapted to be coupled to LDO 104 and sets a dominant pole in the frequency response of VOUT provided by LDO 104. Although not shown in FIG. 2, in at least some implementations, a resistor divider is coupled between the drain of pass FET 208 and ground 220, and the first input of error amplifier 202 is coupled to the output of the resistor divider rather than directly to the drain of pass FET 208.

[0021] In an exemplary operation of LDO 104, since VIN is received and passed by pass FET 208, LDO 104 can provide it as VOUT. Pass FET 208 passes VIN (for providing as VOUT) based on the value of the signal received at the gate of pass FET 208. The amount of current flowing through pass FET 208 is related to the value of the signal received at the gate of pass FET 208, and thus a larger value signal at the gate of pass FET 208 (such as causing a larger gate-source voltage difference of pass FET 208) can result in a VOUT having a closer value of VIN. To provide a signal at the gate of pass FET 208, error amplifier 202 compares VOUT with Vref and provides V_ea having a value indicative of the difference between VOUT and Vref. In some implementations, error amplifier 202 is a folded cascode operational transconductance amplifier (OTA)-based error amplifier that can be biased with a combination of a static bias current (e.g., without load operation) and an adaptive or dynamic bias (e.g., for transient and high load current operation) such as provided by adaptive bias generation circuit 212 and / or dynamic bias generation circuit 214 as described below. In at least some examples, compensation is provided to V_ea by compensation circuit 204, such as under the control of adaptive bias generation circuit 212. Buffer 206 provides V_ea to the gate of pass FET 208.

[0022] In at least some examples, CFFRC106 also provides a signal to the gate of pass FET208. For example, CFFRC106 can sense the voltage ripple at VIN, convert the voltage ripple to a current representation of the voltage ripple shown as i_ripple, and provide i_ripple to the gate of pass FET208. The current provided by buffer 206 when providing the current of i_ripple and V_ea is summed at the gate of pass FET208 and has a voltage that is at least partially determined according to impedance 222. In at least some examples, this reflects the voltage ripple of VIN at the gate of pass FET208 and increases the PSR ratio of LDO104. For example, the voltage ripple of the signal provided at the gate of pass FET208 can be made approximately equal to the VIN ripple multiplied by the ratio of the transconductance of CFFRC106 to the transconductance of buffer 206. By matching the transistor-level characteristics of at least some components of buffer 206 and CFFRC106, the ratio can be controlled to 1, thereby making the voltage ripple of the signal provided at the gate of pass FET208 approximately equal to the VIN ripple. In response to being controlled to have a ratio of 1, the VOUT of LDO104 can be made approximately equal to (Gain / (1 + Gain))×Vref, where Gain is the closed-loop gain of LDO104. Having this ripple as a common-mode input to both the gate and source of pass FET208 can reduce the amount of ripple coupled onto the drain of pass FET208 by pass FET208, which is the output of LDO104 (as described above). In this way, the PSR ratio of LDO104 is increased. In at least some examples, the PSR ratio of LDO104 is increased without using a voltage addition amplifier, thereby resulting in a reduced quiescent current of LDO104. For example, at least some implementations of LDO104 have a no-load quiescent current of approximately 5.6 microamps (μA).

[0023] In at least some examples, the current sensing FET 210 is a scaled replica of the pass FET 208, and the current flowing through the current sensing FET 210 (shown as Ibias_adap) is provided to the adaptive bias generation circuit 212. In at least some implementations, the adaptive bias generation circuit 212 implements a 1:M sense FET-based architecture with a sensing ratio of approximately 1:12000 (e.g., the sense FET 210 has a size approximately 12000 times the size of the pass FET 208). Based on Ibias_adap, the adaptive bias generation circuit 212 may change the bandwidth of components of the LDO 104, such as the compensation circuit 204 and / or the dynamic bias generation circuit 214. For example, based on Ibias_adap, the adaptive bias generation circuit 212 may provide a compensation current (Icomp) to the compensation circuit 204 to control (or bias) the compensation circuit 204. The compensation circuit 204 may implement a pole-zero tracking compensation technique where a frequency response zero is introduced at the output of the error amplifier 202. For example, the LDO 104 may be a two-pole system (e.g., a pole resulting from the capacitor 218 and a pole resulting from the output of the error amplifier 202 as described above). To maintain the stability of the LDO 104, compensation is provided by the compensation circuit 204 for the pole introduced at the output of the error amplifier 202. The compensation may be a frequency response zero having a position modulated according to Icomp (e.g., based on the load current of the LDO 104) to maintain the stability of the LDO 104 over a range of load currents.

[0024] Based on Ibias_adap and / or VOUT, the adaptive bias generation circuit 212 may also provide an adaptive current (Iadp) to the dynamic bias generation circuit 214. Based on Iadp, Vref, and / or VOUT (such as in response to an undershoot or overshoot occurring at VOUT with respect to VIN), the dynamic bias generation circuit 214 may provide a dynamic bias current (Idyn) to the error amplifier 202 and the buffer 206. In at least some examples, Idyn is configured to provide a current burst to the error amplifier 202 and the buffer 206 to mitigate a voltage overshoot or undershoot during a load transition (e.g., at the drain of the pass FET 208). Similarly, the dynamic bias generation circuit 214 may pull down the drain of the pass FET 208 via Vpulldown (e.g., a load) to decrease the value of VOUT, thereby reducing the recovery time (e.g., to less than about 10 microseconds in some implementations) and the overshoot amount in response to an overshoot at VOUT. In at least some examples, the adaptive bias generation circuit 212 and / or the dynamic bias generation circuit 214 facilitate tracking the transconductance of the transistor 307 or being controlled to be approximately equal to the transconductance of the transistor 326 via one or more signals provided by the adaptive bias generation circuit 212 and / or the dynamic bias generation circuit 214.

[0025] FIG. 3 is a schematic diagram of an exemplary implementation of LDO104. In at least some examples, FIG. 3 represents at least a partial transistor-level implementation of LDO104 as shown in FIG. 2. For example, as shown in FIG. 3, LDO104 includes CFFRC106, buffer 206, pass FET 208, and impedance 222. In at least some examples, CFFRC106 includes resistor 302, capacitor 304, differential amplifier 306, p-type FET (PFET) 307, PFET 308, current mirror 310 including n-type FETs (NFETs) 312 and 314, and current mirror 316 including PFETs 318 and 320. In some examples, buffer 206 includes PFETs 322, 324, and 326.

[0026] In the exemplary architecture of LDO104, resistor 302 has a first terminal configured to receive bias voltage Vgs_adap and a second terminal coupled to a first input (e.g., positive or non-inverting input) of differential amplifier 306. Capacitor 304 is coupled between the first input of differential amplifier 306 and ground 220. Differential amplifier 306 has an output coupled to the gate of PFET308. The source of PFET308 is coupled to a second input (e.g., negative or inverting input) of differential amplifier 306. The gate of PFET307 is coupled to the second input of differential amplifier 306, the drain of PFET307 is coupled to the second input of differential amplifier 306, and the source of PFET307 is configured to receive VIN. The drain of PFET308 is coupled to the drain and gate of NFET312. Also, NFET312 has a source coupled to ground 220. NFET314 has a gate coupled to the gate of NFET312, a source coupled to ground 220, and a drain coupled to the drain of PFET318, the gate of PFET318, and the gate of PFET320. PFET318 and PFET320 each have a source configured to receive VIN. PFET320 has a drain coupled to or adapted to be coupled to the gate of pass FET 208. PFET322 and PFET324 each have a source configured to receive VIN. The drain of PFET322 is coupled to the gate of PFET322 and is adapted to be coupled to adaptive bias generation circuit 212 as described above. In at least some examples, adaptive bias generation circuit 212 sinks Ibias_adap through PFET322. Also, PFET322 is diode-connected and provides bias voltage Vgs_adap at the gate of PFET322 coupled to the gate of PFET320. In at least some examples, sense FET 210 and PFET322 can be implemented as the same. PFET324 also has a drain coupled to the gate of pass FET 208.PFET326 has a gate coupled to the output of error amplifier 202 and configured to receive V_ea, a source coupled to the gate of pass FET208, and a drain coupled to ground 220. In at least some examples, the transconductances of PFET307 and PFET326 can be matched to provide a transconductance ratio of 1, as described above.

[0027] In the exemplary operation of LDO104 as shown in FIG. 2, resistor 302 and capacitor 304 form a low-pass filter having an output coupled to the first input of differential amplifier 306. In at least some examples, the low-pass filter defines the cutoff frequency of CFFRC106 based on the resistance value of resistor 302 and the capacitance value of capacitor 304. In at least some examples, the cutoff frequency is approximately 150 Hertz (Hz) resulting from a resistance of resistor 302 of approximately 100 megaohms and a capacitance of capacitor 304 of approximately 10 picofarads. At a cutoff frequency of 150 Hz, the gate of PFET307 can be held at AC ground relative to the source of PFET307. Differential amplifier 306 can set a value for the DC bias current (Ibias) flowing through PFET307 via the control of PFET308. In at least some examples, differential amplifier 306 is implemented as a 5-transistor OTA. The low-pass filter can form a servo high-pass filter in combination with differential amplifier 306.

[0028] In at least some examples, since the gate of PFET324 is configured to receive Vgs_adap and be biased by Vgs_adap, similar to differential amplifier 306 through the filter of resistor 302 and capacitor 304, the transconductances of PFET307 and PFET326 can be matched, thereby providing a transconductance ratio of 1, as described above. The current flowing through PFET307 can be determined according to g_pfet307×VIN_ripple, where g_pfet307 is the transconductance of PFET307 and VIN_ripple is the ripple present in VIN. Also, in at least some examples where impedance 222 is dominated by the output impedance of buffer 206 (for example, this is the impedance provided at the gate of pass FET 208), impedance 222 can have an approximate value determined according to 1 / g_pfet326, where g_pfet326 is the transconductance of PFET326. V_ripple, which is the voltage ripple provided to the gate of pass FET 208 by CFFRC106, is approximately equal to the current flowing through PFET307 multiplied by impedance 222. Therefore, by substituting the above, V_ripple is approximately equal to (g_pfet307 / g_pfet326)×VIN_ripple. When g_pfet307 / g_pfet326 is controlled to be 1 as described above, V_ripple becomes approximately equal to VIN_ripple.

[0029] By providing V_ripple at the gate of the pass FET 208 having the source of the pass FET 208 that receives VIN_ripple (for example, providing substantially VIN_ripple as a common mode input to the gate and source of the pass FET 208), the amount of VIN_ripple passed to VOUT is reduced and the PSR ratio of the LDO 104 is increased. FIG. 4 is a diagram 400 of exemplary signal waveforms, showing a comparison of the PSR ratios of the LDO 104 including CFFRC106 and an LDO not including CFFRC106. In FIG. 400, the horizontal axis represents frequency in Hz on a logarithmic scale, and the vertical axis represents PSR in dB on a linear scale. As shown in FIG. 400, CFFRC106 provides the LDO 104 with an increased PSR ratio over a wide frequency range as compared to an LDO not including CFFRC106.

[0030] FIG. 5 is a diagram 500 of exemplary signal waveforms, showing another comparison of the PSR ratios, explaining the load current (shown as IL) that varies between the LDO 104 including CFFRC106 and an LDO not including CFFRC106. The waveforms in FIG. 500 assume a VIN of about 5V, a VOUT of about 4.5V, and a load capacitance of about 2.2 microfarads (μF). In FIG. 500, the horizontal axis represents frequency in Hz on a logarithmic scale, and the vertical axis represents PSR in dB on a linear scale. As shown in FIG. 500, CFFRC106 provides the LDO 104 with an increased PSR ratio over a wide frequency range as compared to an LDO not including CFFRC106. Also, as shown in FIG. 500, CFFRC106 provides the LDO 104 with an increased PSR ratio over a range of load currents in units of μA or milliamperes (mA) (for example, for load currents of 100 μA, 20 mA, and 250 mA).

[0031] FIG. 6 is FIG. 600 of an exemplary signal waveform, showing another comparison of the PSR ratio to explain the varying output capacitance (shown as Cout) of LDO104. The waveform of FIG. 600 assumes a VIN of about 5V, a VOUT of about 4.5V, and a load current of about 20 mA. In FIG. 600, the horizontal axis represents frequency on a logarithmic scale in Hz units, and the vertical axis represents PSR on a linear scale in dB units. As shown in FIG. 600, CFFRC106 provides LDO104 with a similarly increased PSR ratio over a range of output capacitances shown for output capacitances of 1 μF, 2.2 μF, and 12.2 μF.

[0032] FIG. 7 is FIG. 700 of an exemplary signal waveform, showing another comparison of the PSR ratio to explain the varying values of VOUT of LDO104. The waveform of FIG. 700 assumes a VIN of about 5V, a load capacitance of about 2.2 μF, and a load current of about 20 mA. In FIG. 700, the horizontal axis represents frequency on a logarithmic scale in Hz units, and the vertical axis represents PSR on a linear scale in dB units. As shown in FIG. 700, CFFRC106 provides LDO104 with a similarly increased PSR ratio over a range of VOUT values shown for VOUT values of 4.8V, 4.7V, 4.5V, and 4V.

[0033] Figures 8A and 8B are diagrams of exemplary signal waveforms. For example, FIG. 8A is a diagram 805 of the load transient response of LDO104 to a load current step-up from about 100 μA to about 250 mA. FIG. 8B is a diagram 810 of the load transient response of LDO104 to a load current step-down from about 250 mA to about 100 μA. As shown in FIGS. 805 and 810, compared with an LDO that does not include the adaptive bias generation circuit 212 and the dynamic bias generation circuit 214, the undershoot and overshoot of the value of VOUT are reduced by the adaptive bias generation circuit 212 and the dynamic bias generation circuit 214. For example, by injecting current into LDO104, the undershoot of the value of VOUT is reduced in LDO104 compared with an LDO that does not include the adaptive bias generation circuit 212 and the dynamic bias generation circuit 214 (also, by pulling down VOUT, the overshoot of VOUT is reduced).

[0034] As used herein, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, when device A provides a signal for controlling device B to perform a certain action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, when an intervening component C does not substantially change the functional relationship between device A and device B, device A is indirectly coupled to device B via the intervening component C, and thus, device B is controlled by device A via the control signal provided by device A.

[0035] A device “configured to” perform a task or function is configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the configuration and / or layout of hardware components, via the device's interconnections, or via a combination thereof.

[0036] A circuit or device described herein as including particular components may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) that are coupled to those components and adapted to form the described circuit or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, either at the time of manufacture or after manufacture, by an end user and / or a third party, etc., to form the described structure.

[0037] Although specific components may be described herein as being of a particular process technology, these components may be exchanged with components of other process technologies. The circuits described herein are reconfigurable to include the exchanged components in order to provide at least partially similar functions as the functions available prior to component exchange. A component shown as a resistor generally represents any one or more elements connected in series and / or in parallel to provide the amount of impedance represented by the shown resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors, respectively, connected in series or in parallel between the same two nodes as a single resistor or capacitor.

[0038] The use of the phrase "ground voltage potential" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this specification. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means ±10% of the value.

[0039] Within the scope of the claims of the present invention, modifications may be made to the described exemplary embodiments and other embodiments are possible.

Claims

1. A circuit comprising: a first amplifier having an output, a first input, and a second input coupled to a reference voltage terminal; a buffer having an input coupled to the output of the first amplifier and an output; a first transistor coupled between the first input of the first amplifier and an input voltage terminal, the first transistor having a first control terminal coupled to the output of the buffer; a current mode feed forward ripple canceller (CFFRC) having a CFFRC input coupled to the input voltage terminal and a CFFRC output coupled to the first control terminal; a first capacitor coupled to a ground terminal; a first resistor coupled between a bias voltage terminal and the first capacitor; a second amplifier having an output, a first input coupled to the first capacitor and the first resistor, and a second input; a second transistor coupled between the second input of the second amplifier and the input voltage terminal, the second transistor having a second control terminal coupled to the second input of the second amplifier; a third transistor having a third control terminal coupled to the output of the second amplifier and a first current terminal coupled to the second input of the second amplifier; the CFFRC; the circuit.

2. The circuit according to claim 1, further comprising a compensation circuit coupled to the output of the first amplifier.

3. The circuit according to claim 1, further comprising a second capacitor and a second resistor, wherein the second resistor and the second capacitor are coupled in series between the first transistor and the ground terminal.

4. The circuit according to claim 1, further comprising a fourth transistor coupled between the input voltage terminal and a bias current terminal, the fourth transistor having a fourth control terminal coupled to the output of the buffer.

5. The circuit according to claim 4, further comprising an adaptive bias generation circuit having an input coupled to the bias current terminal.

6. The circuit according to claim 1, ​ ​ ​ ​ ​ The CFFRC is first and second current mirrors coupled in series between the first control terminal and the third transistor and configured to mirror a current flowing through the third transistor, and the circuit further includes the first and second current mirrors.

7. The circuit according to claim 1, wherein the buffer is a fourth transistor coupled between the input voltage terminal and the first control terminal and having a fourth control terminal coupled to the bias voltage terminal, the fourth transistor; a fifth transistor coupled between the first control terminal and the ground terminal and having a fifth control terminal coupled to the output of the first amplifier, the fifth transistor; and the circuit includes.

8. The circuit according to claim 7, wherein the second transistor is configured to have the same mutual conductance as the fifth transistor.

9. The circuit according to claim 1, wherein the CFFRC is configured to provide a current proportional to a ripple component of a signal at the input voltage terminal to the CFFRC output.

10. An apparatus, a first transistor having a first control terminal, a first current terminal coupled to an input voltage terminal, and a second current terminal; a first amplifier having a first input coupled to the second current terminal, a second input coupled to a reference voltage terminal, and an output; a buffer having an input coupled to the output of the first amplifier and an output coupled to the first control terminal; a current mode feedforward ripple canceller (CFFRC) having a CFFRC input coupled to the input voltage terminal and a CFFRC output coupled to the first control terminal, the CFFRC being configured to provide a current proportional to a voltage ripple on a signal at the input voltage terminal to the CFFRC output, a first capacitor coupled to the ground terminal; a first resistor coupled between the bias voltage terminal and the first capacitor; a second amplifier having a first input, a second input, and an output, the first input being coupled to the first capacitor; a second transistor coupled between the second input of the second amplifier and the input voltage terminal and having a second control terminal coupled to the second input of the second amplifier. A third transistor coupled to a second input of the second amplifier and having a third control terminal coupled to an output of the second amplifier, the third transistor; Including the CFFRC; An apparatus including.

11. The apparatus according to claim 10, Wherein the CFFRC is Increasing the power signal rejection ratio (PSRR) of the apparatus, Reducing the amount of the voltage ripple coupled across the first transistor, An apparatus further configured as such.

12. The apparatus according to claim 10, An apparatus further including a compensation circuit configured to provide compensation to a signal at an output of the first amplifier by modulating a position of a frequency response zero in a frequency response of the signal.

13. The apparatus according to claim 10, An apparatus further including a bias circuit configured to bias the first amplifier and the buffer by injecting current into the first amplifier and the buffer.

14. The apparatus according to claim 10, An apparatus further including a bias circuit configured to compensate for a voltage overshoot at a second current terminal.

15. The apparatus according to claim 10, An apparatus wherein the CFFRC and the buffer are configured to have the same mutual conductance.

16. A system, A voltage regulator configured to provide a regulated output voltage at an output voltage terminal in response to an input voltage at an input voltage terminal, A first transistor having a first control terminal, a first current terminal coupled to the input voltage terminal, and a second current terminal coupled to the output voltage terminal, An error amplifier having first and second inputs and outputs, Comparing the regulated output voltage with a reference voltage at a reference voltage terminal, Configured to provide an error signal to an output of the error amplifier in response to the comparison, The error amplifier, A buffer having an input coupled to an output of the error amplifier and an output coupled to the first control terminal, A current mode feedforward ripple canceller (CFFRC), A first capacitor coupled to a ground terminal, A first resistor coupled between a bias voltage terminal and the first capacitor, A differential amplifier having a first input, a second input, and an output coupled to the first capacitor, a second transistor having a second control terminal coupled to a second input of the differential amplifier, a third current terminal coupled to the second control terminal, and a fourth current terminal coupled to the input voltage terminal; a third transistor having a third control terminal coupled to an output of the differential amplifier and a fifth current terminal coupled to a second input of the differential amplifier; a CFFRC including the same; a system including the voltage regulator including the same.

17. The system according to claim 16, wherein a second input of the error amplifier is coupled to the reference voltage terminal; the CFFRC has a CFFRC input coupled to the input voltage terminal and a CFFRC output coupled to the first control terminal.

18. The system according to claim 16, wherein the CFFRC and the buffer are configured to have substantially the same mutual conductance.

19. The system according to claim 16, wherein the CFFRC is configured to increase a power signal rejection ratio of the voltage regulator and decrease an amount of voltage ripple coupled across the first transistor.

20. The system according to claim 16, wherein the voltage regulator further includes a compensation circuit configured to provide compensation to the error signal by modulating a position of a frequency response zero in a frequency response of the error signal. ​

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