Semiconductor device

Abstract

To provide a semiconductor device which enables more stable operation.SOLUTION: A semiconductor device includes an element part, an insulating part, and a quench part. The element part includes a first conductivity type first semiconductor region, a first conductivity type second semiconductor region, a second conductivity type third semiconductor region, and a second conductivity type fourth semiconductor region. The second semiconductor region is provided on the first semiconductor region, and has first conductivity type impurity concentration higher than that of the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided around the second semiconductor region and the third semiconductor region along a first surface crossing a first direction toward the second semiconductor region from the first semiconductor region. The fourth semiconductor region has second conductivity type impurity concentration lower than that of the third semiconductor region. The insulating part is provided around the element part along the first surface. The quench part is electrically connected to the third semiconductor region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device.

Background Art

[0002] There is a semiconductor device that detects light. It is desirable that the operation of the semiconductor device be more stable.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device that can operate more stably.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes an element portion, an insulating portion, and a quench portion. The element portion includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, and a fourth semiconductor region of the second conductivity type. The second semiconductor region is provided on the first semiconductor region and has a higher impurity concentration of the first conductivity type than the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided around the second semiconductor region and the third semiconductor region along a first plane that intersects a first direction from the first semiconductor region toward the second semiconductor region. The fourth semiconductor region has a lower impurity concentration of the second conductivity type than the third semiconductor region. The insulating portion is provided around the element portion along the first plane. The quench portion is electrically connected to the third semiconductor region.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In the present specification and each figure, the same elements as those already described are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted. In the following description and drawings, n + , n and p + , p, p - The notations represent the relative levels of the respective impurity concentrations. That is, the notation with “+” has a relatively higher impurity concentration than the notation without either “+” or “-”, and the notation with “-” has a relatively lower impurity concentration than the notation without either. When both p - type impurities and n - type impurities are included in each region, these notations represent the relative levels of the net impurity concentration after those impurities have compensated for each other. For each of the embodiments described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG. 1. As shown in FIGS. 1 and 2, the semiconductor device 100 according to the first embodiment includes a conductive layer 1, an element portion 10, an insulating portion 20, a quench portion 30, an insulating layer 40, and a wiring 41. In FIG. 1, the insulating layer 40 is omitted. Also, the contact plugs are represented by broken lines.

[0009] As shown in FIG. 2, the element portion 10 includes a p - -type (first conductivity type) semiconductor region 11 (first semiconductor region), a p + -type semiconductor region 12 (second semiconductor region), an n + -type (second conductivity type) semiconductor region 13 (third semiconductor region), and an n-type semiconductor region 14 (fourth semiconductor region).

[0010] Here, the direction from the p - -type semiconductor region 11 to the p + -type semiconductor region 12 is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). Also, for the sake of explanation, the direction from the p - -type semiconductor region 11 to the p + -type semiconductor region 12 is referred to as "up", and the opposite direction is referred to as "down". These directions are independent of the direction of gravity based on the relative positional relationship between the p - -type semiconductor region 11 and the p + -type semiconductor region 12.

[0011] The p + -type semiconductor region 12 is provided above the p - -type semiconductor region 11. The p-type impurity concentration in the p + -type semiconductor region 12 is higher than the p-type impurity concentration in the p - -type semiconductor region 11. The n + -type semiconductor region 13 is the p+ is provided on the p-type semiconductor region 12 and is in contact with the p + -type semiconductor region 12. The p + -type semiconductor region 12 and the n + -type semiconductor region 13 form a pn junction therebetween. For example, the pn junction surface extends along the X-Y plane (the first plane) perpendicular to the Z direction. The n-type semiconductor region 14 is provided around the p + -type semiconductor region 12 and the n + -type semiconductor region 13.

[0012] The insulating portion 20 is provided around the element portion 10 along the X-Y plane. The insulating portion 20 includes a first insulating region 21. The lower end of the first insulating region 21 is located below the lower end of the p + -type semiconductor region 12. For example, the first insulating region 21 extends below the depletion layer that extends into the p - -type semiconductor region 11.

[0013] The insulating portion 20 may further include a second insulating region 22. The second insulating region 22 is provided on the first insulating region 21 and extends along the X-Y plane. For example, the second insulating region 22 is aligned with the n + -type semiconductor region 13 in the X direction and the Y direction.

[0014] A plurality of element portions 10 are provided in the X direction and the Y direction. A plurality of first insulating regions 21 are respectively provided around the plurality of element portions 10 along the X-Y plane. One second insulating region 22 is provided on the plurality of first insulating regions 21. That is, all the first insulating regions 21 are in contact with a common one second insulating region 22.

[0015] The plurality of first insulating regions 21 are separated from each other. A semiconductor region 25 is provided between adjacent first insulating regions 21 in the X direction or the Y direction. The p-type impurity concentration in the semiconductor region 25 may be the same as or different from the p - -type impurity concentration in the p-type semiconductor region 11.

[0016] The plurality of element portions 10 and the insulating portion 20 are provided on the conductive layer 1. Each p - -type semiconductor region 11 is electrically connected to the conductive layer 1. For example, the lower end of the first insulating region 21 is separated from the conductive layer 1 in the Z direction.

[0017] The quench portion 30 is provided above the element portion 10 and is electrically connected to the n + -type semiconductor region 13. As shown in FIG. 1, for example, the n + -type semiconductor region 13 is electrically connected to the wiring 41 via the contact plug 30a, the wiring 30b, the contact plug 30c, the quench portion 30, and the contact plug 30d. The quench portion 30 is preferably provided on the insulating portion 20. Thereby, it is possible to suppress the light traveling toward the element portion 10 from being blocked by the quench portion 30.

[0018] The insulating layer 40 is provided on the element portion 10 and the insulating portion 20. The above-described contact plugs, wirings, and quench portion 30 are provided in the insulating layer 40. The insulating layer 40 may include a plurality of insulating films laminated in the Z direction.

[0019] The operation of the semiconductor device 100 will be described. When light is incident on the element portion 10, charges are generated in the element portion 10. For example, a reverse voltage exceeding the breakdown voltage is applied between the p + -type semiconductor region 12 and the n + -type semiconductor region 13, and the element portion 10 operates in the Geiger mode. Breakdown occurs due to the charges generated in the element portion 10, and a large amount of charges are generated. The charges flow through the n + -type semiconductor region 13 and the quench portion 30 to the wiring 41 and are taken out to the outside of the semiconductor device 100.

[0020] The electrical resistance of the quench section 30 is greater than the electrical resistance of each of the contact plugs 30a, 30c, 30d, and the wiring 30b. The electrical resistance of the quench section 30 is preferably greater than 10 kΩ and less than 10 MΩ. The quench section 30 is provided to suppress the continuation of the avalanche breakdown when light is incident on the element section 10 and the avalanche breakdown occurs. When the avalanche breakdown occurs and a current flows through the quench section 30, a voltage drop occurs according to the electrical resistance of the quench section 30. Due to the voltage drop, the potential difference between the p + -type semiconductor region 12 and the n + -type semiconductor region 13 becomes smaller, and the avalanche breakdown stops. As a result, the light incident on the element section 10 next can be detected.

[0021] As described above, a resistor that causes a large voltage drop may be provided as the quench section 30. Instead of the resistor, a quench section 30 including a transistor to which an active quench method is applied may be provided.

[0022] An example of the material of each element will be described. p - -type semiconductor region 11, p + -type semiconductor region 12, n + -type semiconductor region 13, and the n-type semiconductor region 14 include semiconductor materials such as silicon, silicon carbide, gallium arsenide, and gallium nitride. When silicon is used as the semiconductor material, phosphorus, arsenic, or antimony is used as the n-type impurity. Boron is used as the p-type impurity.

[0023] The conductive layer 1 is a p + -type semiconductor layer. The conductive layer 1 includes the semiconductor material described above. The p-type impurity concentration in the conductive layer 1 is higher than the p-type impurity concentration in the p - -type semiconductor region 11. The conductive layer 1 may include a metal. For example, the conductive layer 1 includes at least one selected from the group consisting of aluminum, copper, titanium, gold, and nickel.

[0024] The insulating portion 20 and the insulating layer 40 contain an insulating material. In order to reduce crosstalk between the element portions 10, it is preferable that the refractive index of the insulating material contained in the insulating portion 20 is lower than the refractive index of the semiconductor material contained in the element portion 10. For example, the insulating portion 20 and the insulating layer 40 contain silicon oxide.

[0025] The quenching portion 30 as a resistor contains polysilicon. The quenching portion 30 may be doped with n-type impurities or p-type impurities. Each contact plug and each wiring contain a metal material. The metal material is at least one selected from the group consisting of titanium, tungsten, copper, and aluminum.

[0026] The effects of the first embodiment will be described. FIG. 3 is a cross-sectional view showing a semiconductor device according to a reference example. In the semiconductor device 100r according to the reference example, in the element portion 10, an n-type semiconductor region 14 is not provided. The p + type semiconductor region 12 and the n + type semiconductor region 13 are in contact with the insulating portion 20.

[0027] In the semiconductor device 100r, in the portion P located at the lower outer periphery of the n + type semiconductor region 13, the electric field strength becomes large. As a result, in the vicinity of the portion P, avalanche breakdown is more likely to occur compared to other portions. For example, in the vicinity of the portion P, edge breakdown in which breakdown occurs earlier than other portions is likely to occur. Also, in the vicinity of the portion P, unintended breakdown may occur, which may increase noise.

[0028] In the semiconductor device 100 according to the first embodiment, the element portion 10 includes an n-type semiconductor region 14. The n-type semiconductor region 14 is provided around the p + type semiconductor region 12 and the n + type semiconductor region 13 along the X-Y plane. When the n-type semiconductor region 14 is provided, the n +It is possible to reduce the electric field strength at the lower outer periphery of the n-type semiconductor region 13. Also, the electric field strength in the n-type semiconductor region 14 is lower than the electric field strength at the portion P of the semiconductor device 100r. Therefore, an increase in the local electric field strength in the element portion 10 can be suppressed. As a result, for example, the occurrence of edge breakdown can be suppressed, and the operation of the semiconductor device 100 can be made more stable. Also, the noise of the semiconductor device 100 can be reduced.

[0029] The lower end of the n-type semiconductor region 14 is preferably located above the lower end of the p- + type semiconductor region 12. When the lower end of the n-type semiconductor region 14 is located below the lower end of the p- + type semiconductor region 12, carriers generated at the time of breakdown easily flow into the n-type semiconductor region 14. When carriers flow into the n-type semiconductor region 14, the signal flowing through the wiring 41 becomes smaller than when the carriers flow into the n- + type semiconductor region 13. The n-type semiconductor region 14 is substantially an insensitive region. By positioning the lower end of the n-type semiconductor region 14 above the lower end of the p- + type semiconductor region 12, the amount of carriers flowing into the n-type semiconductor region 14 can be reduced, and the sensitivity of the semiconductor device 100 to light can be improved.

[0030] For example, the position of the lower end of the p- + type semiconductor region 12 is specified by the following method. The p-type impurity concentration (first concentration) near the pn junction surface of the p- + type semiconductor region 12 is measured. The p-type impurity concentration (second concentration) of the p- + type semiconductor region 11 at a position away from the p- - type semiconductor region 12 in the Z direction is measured. Between the p- - type semiconductor region 11 and the p- + type semiconductor region 12, a position having a p-type impurity concentration intermediate between the first concentration and the second concentration is specified. That position corresponds to the position of the lower end of the p- + type semiconductor region 12.

[0031] (Second Embodiment) FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment. In the semiconductor device 200 according to the second embodiment, the element portion 10 further includes a p-type semiconductor region 15 (fifth semiconductor region) as compared with the semiconductor device 100.

[0032] The p-type semiconductor region 15 is provided under the n-type semiconductor region 14. For example, the p-type semiconductor region 15 is in contact with the insulating portion 20 (first insulating region 21). The p-type impurity concentration in the p-type semiconductor region 15 is higher than the p-type impurity concentration in the p - -type semiconductor region 11 and lower than the p-type impurity concentration in the p + -type semiconductor region 12.

[0033] FIG. 5 is a schematic diagram showing the electric lines of force when a voltage is applied to the semiconductor device according to the second embodiment. As described above, when the amount of carriers flowing into the n-type semiconductor region 14 is reduced, the sensitivity to light is improved. In the semiconductor device 200, as shown in FIG. 5, in the p-type semiconductor region 15, the electric lines of force EL can be directed inward of the element portion 10. Thereby, the flow of carriers into the n-type semiconductor region 14 can be suppressed, and the carriers tend to flow toward the p + -type semiconductor region 12. According to the second embodiment, the light reception sensitivity of the semiconductor device 200 can be improved as compared with the first embodiment.

[0034] The p-type semiconductor region 15 is preferably separated from the n-type semiconductor region 14 in the Z direction. The lower the p-type semiconductor region 15 is located, the more inward the electric lines of force EL can be directed at a position farther from the n-type semiconductor region 14. Thereby, the flow of carriers into the n-type semiconductor region 14 can be further suppressed.

[0035] The p-type impurity concentration in the p-type semiconductor region 15 is higher than the p-type impurity concentration in the p - -type semiconductor region 11. The carrier lifetime in the p-type semiconductor region 15 is p -Shorter than the carrier lifetime in the p-type semiconductor region 11. If the length L1 in the Z direction of the p-type semiconductor region 15 shown in FIG. 4 is excessively long, the carriers generated in the element portion 10 are likely to disappear. That is, the effective light-receiving area decreases. For this reason, the length L1 is preferably shorter than, for example, the length L2 in the Z direction of the n-type semiconductor region 14. Thereby, while suppressing the decrease in the effective light-receiving area, the light-receiving sensitivity can be improved.

[0036] For example, p - The boundary between the p-type semiconductor region 11 and the p-type semiconductor region 15 is specified by the following method. Measure the maximum p-type impurity concentration (first concentration) in the p-type semiconductor region 15. Measure the p-type impurity concentration (second concentration) of the p-type semiconductor region 11 at a position away from the p-type semiconductor region 15. - Measure the p-type impurity concentration (second concentration) of the p-type semiconductor region 11. p - Between the p-type semiconductor region 11 and the p-type semiconductor region 15, identify the position having a p-type impurity concentration intermediate between the first concentration and the second concentration. That position corresponds to the boundary between the p-type semiconductor region 11 and the p-type semiconductor region 15. -

[0037] FIG. 6(a) is a cross-sectional view taken along line A1 - A2 of FIG. 5. FIG. 6(b) is a cross-sectional view taken along line B1 - B2 of FIG. 5. The length L3 of the p-type semiconductor region 15 shown in FIG. 6(a) is preferably longer than 0.8 times and less than 1.2 times the length L4 of the n-type semiconductor region 14 shown in FIG. 6(b). The lengths L3 and L4 are the lengths of the p-type semiconductor region 15 and the n-type semiconductor region 14, respectively, in the direction from the element portion 10 toward the insulating portion 20. If the length L3 is less than 0.8 times the length L4, the effect of suppressing the flow of carriers into the n-type semiconductor region 14 weakens. If the length L3 exceeds 1.2 times the length L4, the effect of suppressing the flow of carriers into the n-type semiconductor region 14 does not substantially change, but the capacitance of the p-type semiconductor region 15 increases. When the length L3 is longer than 0.8 times and less than 1.2 times the length L4, while suppressing the increase in the capacitance of the p-type semiconductor region 15, the flow of carriers into the n-type semiconductor region 14 can be effectively suppressed.

[0038] For example, n​+ The boundary between the p-type semiconductor region 13 and the n-type semiconductor region 14 is specified by the following method. n + Measure the maximum n-type impurity concentration (first concentration) in the n-type semiconductor region 13. Measure the minimum n-type impurity concentration (second concentration) near the insulating portion 20 of the n-type semiconductor region 14. n + Identify the position having an n-type impurity concentration intermediate between the first concentration and the second concentration between the p-type semiconductor region 13 and the n-type semiconductor region 14. That position corresponds to + the boundary between the p-type semiconductor region 13 and the n-type semiconductor region 14.

[0039] As an example, p + the depth of the pn junction surface between the p-type semiconductor region 12 and the n + type semiconductor region 13 is deeper than 0.5 μm and shallower than 1 μm. p + The depth of the lower end of the p-type semiconductor region 12 is deeper than 0.8 μm and shallower than 1.6 μm. The depth of the lower end of the n-type semiconductor region 14 is deeper than 0.8 μm and shallower than 1.2 μm. The depth of the lower end of the p-type semiconductor region 15 is deeper than 2.5 μm and shallower than 4 μm. The depth corresponds to the distance in the Z direction from the upper surface of the element portion 10.

[0040] (Third Embodiment) FIG. 7 is a circuit diagram showing a semiconductor device according to the third embodiment. The semiconductor device 300 according to the third embodiment includes a plurality of element arrays Ar1 to Arn and a plurality of transistors Tr1 to Trn.

[0041] Each of the plurality of element arrays Ar1 to Arn includes a plurality of element portions 10 and a plurality of quench portions 30. One element portion 10 is directly connected to one quench portion 30. A set of one element portion 10 and one quench portion 30 connected in series is connected in parallel a plurality of times to form one element array. The configuration of the element portion 10 in the semiconductor device 300 is the same as, for example, the configuration of the element portion 10 in the semiconductor device 100 or 200.

[0042] The plurality of transistors Tr1 to Trn are each electrically connected to a plurality of element arrays Ar1 to Arn. When one of the plurality of transistors Tr1 to Trn is selected, one of the corresponding plurality of element arrays Ar1 to Arn operates. A signal generated in one of the plurality of element arrays Ar1 to Arn is taken out from the terminal T through one of the selected plurality of transistors Tr1 to Trn.

[0043] Due to repeated occurrence of yielding in the element portion 10, temperature changes repeatedly occur in the element portion 10. As the usage period of the semiconductor device 300 elapses, the sensitivity of the element portion 10 may decrease. For example, in the semiconductor device 300, one transistor is selected and one element array is used. When the sensitivity of the element array decreases with the use of the semiconductor device 300, another transistor is selected. Thereby, another element array with no decrease in sensitivity can be used for light detection. According to the third embodiment, it is possible to suppress a decrease in the sensitivity of the semiconductor device 300 due to use.

[0044] As described above, some embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope. Also, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0045] 1: Conductive layer, 10: Element portion, 11: p - -type semiconductor region, 12: p + -type semiconductor region, 13: n +n-type semiconductor region, 14: n-type semiconductor region, 15: p-type semiconductor region, 20: insulating portion, 21: first insulating region, 22: second insulating region, 25: semiconductor region, 30: quench portion, 30a, 30c, 30d: contact plug, 30b: wiring, 40: insulating layer, 41: wiring, 100, 100r, 200, 300: semiconductor device, Ar1~Arn: element array, EL: electric line of force, P: portion, T: terminal, Tr1~Trn: transistor

Claims

1. A conductive layer, An element portion provided on the conductive layer, a first semiconductor region of a first conductivity type electrically connected to the conductive layer; a second semiconductor region of a first conductivity type provided on the first semiconductor region and having a higher impurity concentration of the first conductivity type than the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; a fourth semiconductor region of a second conductivity type that is provided on the first semiconductor region, is located around the second semiconductor region and the third semiconductor region along a first surface that intersects with a first direction that is parallel to an upward direction from the first semiconductor region toward the second semiconductor region, and has a lower impurity concentration of the second conductivity type than the third semiconductor region; a fifth semiconductor region of a first conductivity type provided under the fourth semiconductor region, the fifth semiconductor region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration in the first semiconductor region and lower than a first conductivity type impurity concentration in the second semiconductor region; the element portion including: a length of the fifth semiconductor region in the first direction that is shorter than a length of the fourth semiconductor region in the first direction; and the fifth semiconductor region being located between a part of the first semiconductor region and another part of the first semiconductor region in the first direction; an insulating portion provided around the element portion along the first surface, the insulating portion having an end portion in a downward direction opposite to the upward direction located lower than an end portion in the downward direction of the fifth semiconductor region, the fifth semiconductor region being located between the first semiconductor region and the insulating portion in a direction from the element portion toward the insulating portion; a quench portion electrically connected to the third semiconductor region; A semiconductor device comprising:

2. A semiconductor device as described in claim 1, wherein the impurity concentration of the first conductivity type in the fifth semiconductor region is higher than the impurity concentration of the first conductivity type in the portion of the first semiconductor region and is higher than the impurity concentration of the first conductivity type in the other portion of the first semiconductor region.

3. The semiconductor device according to claim 1 , wherein an end portion of the fourth semiconductor region in the downward direction is located higher than an end portion of the second semiconductor region in the downward direction.

4. the fifth semiconductor region is spaced from the fourth semiconductor region in the first direction, 4. The semiconductor device according to claim 1, wherein a distance in the first direction between an upper surface of the element portion and a lower end of the fifth semiconductor region is longer than 2.5 μm and shorter than 4 μm.

5. A semiconductor device according to any one of claims 1 to 4, wherein the length of the fifth semiconductor region in the direction from the element portion toward the insulating portion is greater than 0.8 times and less than 1.2 times the length of the fourth semiconductor region in the direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein the element portion is provided in a plurality of directions, a second direction intersecting the first direction, and a third direction intersecting a plane along the first direction and the second direction.

7. 7. The semiconductor device according to claim 1, wherein the element portion is operated in a Geiger mode.

8. 8. The semiconductor device according to claim 1, further comprising a transistor electrically connected to the element portion.

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