Semiconductor device

Abstract

To provide a semiconductor device having improved reliability.SOLUTION: A semiconductor device 10a comprises: a substrate 11a having insulation properties; an adhesion layer 12a disposed on the substrate 11a; a metal plate 13a on which a circuit pattern 18a is formed and which is made to adhere to the substrate 11a by the adhesion layer 12a; a semiconductor chip 17a electrically connected to the metal plate 13a; and a joint material 16a that joins the metal plate 13a with the semiconductor chip 17a. The metal plate 13a includes: a plurality of ribs 32a, 32b disposed apart from each other; and a recess 31a disposed adjacently to the plurality of ribs 32a, 32b. The joint material 16a includes: a first portion 33a disposed in the recess 31a; and second portions 34a, 34b that have thicknesses thinner than that of the first portion 33a and are disposed between the semiconductor chip 17a and the ribs 32a, 32b.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device in which semiconductor elements are arranged on a substrate is known (see, for example, Patent Document 1). The semiconductor elements included in the semiconductor device disclosed in Patent Document 1 are mounted on the upper surface of a metal circuit board via solder. A frame-shaped groove in which the outer periphery of the semiconductor element is located between the inner periphery and the outer periphery is formed in the metal circuit board.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the semiconductor device disclosed in Patent Document 1, the semiconductor element is joined to the metal circuit board by solder disposed inside the inner periphery of the frame-shaped groove. Here, when the semiconductor element is joined, if there is a bias in the amount of solder, the semiconductor element may be joined while being inclined. Then, non-uniformity in the thickness of the solder occurs, and cracks may occur due to thermal stress generated during the operation of the semiconductor device. Such a semiconductor device may impair reliability. Also, from the viewpoint of improving reliability, in a semiconductor device, it is required to accurately join the semiconductor element at a desired position.

[0005] Therefore, one of the objects is to provide a semiconductor device with improved reliability.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes an insulating substrate, an adhesive layer disposed on the substrate, a metal plate on which a circuit pattern is formed and which is adhered to the substrate by the adhesive layer, a semiconductor chip electrically connected to the metal plate, and a bonding material that bonds the metal plate and the semiconductor chip. The metal plate includes a plurality of ribs disposed at intervals from each other, and recesses disposed adjacent to the plurality of ribs. The bonding material includes a first portion disposed in the recesses, and a second portion that is thinner than the thickness of the first portion and is disposed between the ribs and the semiconductor chip.

Advantages of the Invention

[0007] According to the above semiconductor device, the reliability can be improved.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes an insulating substrate, an adhesive layer disposed on the substrate, a metal plate on which a circuit pattern is formed and which is adhered to the substrate by the adhesive layer, a semiconductor chip electrically connected to the metal plate, and a bonding material for bonding the metal plate and the semiconductor chip. The metal plate includes a plurality of ribs arranged at intervals and recesses arranged adjacent to the plurality of ribs. The bonding material includes a first portion disposed in the recess and a second portion thinner than the thickness of the first portion and disposed between the rib and the semiconductor chip.

[0010] According to the semiconductor device of the present disclosure, since the thickness of the first portion of the bonding material disposed in the recess is relatively thick, cracks due to thermal stress are suppressed from occurring in the bonding material, and the semiconductor chip can be reliably bonded to the metal plate. The first portion of the bonding material is disposed in the recess. Therefore, during manufacturing, for example, it is possible to suppress the bonding material from melting and flowing out onto the surface of the metal plate and the arrangement position of the bonding material from shifting. Therefore, the first portion of the bonding material can be accurately arranged. That is, by precisely providing the position of the recess in the metal plate, the first portion of the bonding material disposed in the recess and the semiconductor chip can be bonded, and the semiconductor chip can be accurately bonded to the desired position on the metal plate. Further, since the thickness of the second portion of the bonding material disposed between the rib and the semiconductor chip is thinner than that of the first portion, unevenness in the thickness of the bonding material is less likely to occur on the second portion. Therefore, it is possible to suppress the semiconductor chip bonded to the metal plate from being inclined during bonding. That is, the second portion of the bonding material disposed on the plurality of ribs arranged at intervals can accurately bond the semiconductor chip to be bonded onto the metal plate without tilting the posture of the semiconductor chip. Therefore, heat generated from the semiconductor chip during the operation of the semiconductor device can be evenly dissipated to the substrate side. Therefore, according to such a semiconductor device, the reliability can be improved.

[0011] In the above semiconductor device, the semiconductor chip may be a chip resistor, a capacitor, a vertical transistor, a diode, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), or an IGBT (Insulated Gate Bipolar Transistor). The semiconductor chip may include a first pad and a second pad. The first pad may be bonded to the first rib. The second pad may be bonded to the second rib. By doing so, when bonding a chip resistor, a capacitor, a vertical transistor, a diode, a MOSFET, or an IGBT including the first pad and the second pad to the metal plate, it becomes easy to bond while reducing the risk of the first pad and the second pad coming into contact with each other.

[0012] In the semiconductor device, the recess may include a first recess and a second recess spaced apart in a first direction. The plurality of ribs may include a first rib disposed adjacent to the first recess in the first direction and a second rib disposed adjacent to the second recess in the first direction and spatially separated from the first rib. The first rib and the second rib may be spaced apart in the first direction. By doing so, when the semiconductor chip is bonded to the metal plate, the first pad is bonded by the bonding material disposed on the first rib and the bonding material disposed in the first recess, and the second pad is bonded by the bonding material disposed on the second rib and the bonding material disposed in the second recess. Since the first rib and the second rib are spaced apart, it is easy to maintain the spatial separation state of the pads on both sides of the semiconductor chip. Therefore, the risk of contact between the first pad and the second pad can be more reliably reduced.

[0013] In the semiconductor device, each of the plurality of ribs may have a wall surface along the thickness direction of the metal plate. By doing so, even if the intervals between the plurality of ribs are narrowed, the risk of contact between the ribs can be reduced. Therefore, for example, when bonding a small chip resistor, the risk of pads contacting each other and short-circuiting can be reduced. Therefore, miniaturization can be easily achieved.

[0014] In the semiconductor device, the recess may be disposed so as to include the outer edges of the plurality of ribs when viewed in the thickness direction of the metal plate. By doing so, since the recess is disposed around the plurality of ribs when viewed in the thickness direction of the metal plate, the position of the semiconductor chip bonded by the bonding material can be more accurately controlled.

[0015] In the semiconductor device described above, the plurality of ribs may be columnar. When viewed in the thickness direction of the metal plate, the recess may have a rectangular outer shape. The plurality of ribs may be respectively arranged near the corners of the rectangle. By doing so, when the recess is rectangular, by arranging columnar ribs near the corners of the rectangle, it is possible to more effectively suppress the tilting of the posture of the semiconductor chip.

[0016] In the semiconductor device described above, plating may be applied to the surface of the metal plate. By doing so, when using solder as the bonding material, the bonding property with the metal plate can be improved.

[0017] In the semiconductor device described above, the thickness of the first portion may be 0.2 mm or more and 0.5 mm or less. The thickness of the second portion may be 1 / 2 or more of the thickness of the first portion. By doing so, by defining the thickness of the first portion and the thickness of the second portion, the above effects can be achieved more reliably. Note that the thickness of the first portion is preferably 0.3 mm or more. Also, the thickness of the first portion is preferably 0.4 mm or less.

[0018] In the semiconductor device described above, the bonding material may be a plate solder or a solder paste. Since the plate solder is plate-shaped, its handleability during manufacturing is good. Also, since the solder paste has high adhesiveness, it is not easily displaced when placed at a desired position. Therefore, by doing so, productivity can be improved.

[0019] [Details of Embodiments of the Present Disclosure] Next, an embodiment of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated.

[0020] (Embodiment 1) The configuration of the semiconductor device in Embodiment 1 of the present disclosure will be described. FIG. 1 is a schematic plan view of the semiconductor device in Embodiment 1. FIG. 2 is a schematic cross-sectional view when the semiconductor device shown in FIG. 1 is cut along the section indicated by II-II. FIG. 3 is an exploded perspective view showing a part of the semiconductor device shown in FIG. 1 disassembled. FIG. 4 is a schematic cross-sectional view schematically showing a part of the cross-section of the semiconductor device shown in FIG. 2. For ease of understanding, in FIG. 2, the plating described later is shown thickly. Further, in FIG. 4, the illustration of the plating and the like described later is omitted, and the thicknesses D1 and D2 described later are exaggerated and shown thickly.

[0021] Referring to FIGS. 1, 2, 3, and 4, the semiconductor device 10a in Embodiment 1 includes a substrate 11a, a first adhesive layer 12a, a first metal plate 13a, a second adhesive layer 14a, a second metal plate 15a, a bonding material 16a, and semiconductor chips 17a, 17b, 17c, 17d, 17e.

[0022] The substrate 11a is rectangular in shape such that the length in the X direction is longer than the length in the Y direction when viewed in the thickness direction. The substrate 11a has insulating properties. The substrate 11a is made of, for example, ceramic. The substrate 11a includes a first surface 21a located on one side in the thickness direction and a second surface 21b located on the other side in the thickness direction. Note that the substrate 11a may be rectangular in shape such that the length in the Y direction is longer than the length in the X direction when viewed in the thickness direction, or may be square.

[0023] The first adhesive layer 12a is disposed on the substrate 11a, specifically, on the first surface 21a of the substrate 11a. The first adhesive layer 12a includes a first surface 22a located on one side in the thickness direction and a second surface 22b located on the other side in the thickness direction. The first adhesive layer 12a is disposed such that the second surface 22b contacts the first surface 21a of the substrate 11a. As the first adhesive layer 12a, for example, a brazing material composed of an alloy of Ag (silver) and Cu (copper) is selected. Plating 19a is applied to a part of the first surface 22a of the first adhesive layer 12a, specifically, in a region where the recesses 31a, 31b, 31c, 31d, 31e described later are located, etc., in a region where the first metal plate 13a is not disposed.

[0024] Circuit patterns 18a, 18b, 18c, 18d are formed on the first metal plate 13a. The first metal plate 13a includes a first surface 23a located on one side in the thickness direction and a second surface 23b located on the other side in the thickness direction. The first metal plate 13a is adhered to the substrate 11a by the first adhesive layer 12a. In this case, the second surface 23b of the first metal plate 13a is disposed so as to contact the first surface 22a of the first adhesive layer 12a. As the first metal plate 13a, for example, a metal plate composed of Cu is selected. Note that as the thickness (length in the Z direction) of the first metal plate 13a, those having a thickness of 0.2 mm to 0.3 mm or 0.4 mm to 0.5 mm are adopted. Plating 19a is applied to the first surface 23a of the first metal plate 13a.

[0025] The first metal plate 13a includes a plurality of ribs 32a, 32b, 32c, 32d arranged at intervals from each other and a recess 31a arranged adjacent to the plurality of ribs 32a, 32b, 32c, 32d. In the present embodiment, the first metal plate 13a includes recesses 31b, 31c, 31d, 31e arranged at intervals in the X direction and a plurality of ribs (not shown) arranged adjacent to each of the recesses 31b, 31c, 31d, 31e.

[0026] The ribs 32a, 32b, 32c, 32d are each columnar, specifically, cylindrical. Each of the plurality of ribs 32a, 32b has wall surfaces 35a, 35b along the thickness direction (Z direction) of the first metal plate 13a. The recesses 31a each have a rectangular outer shape when viewed in the thickness direction of the first metal plate 13a. The ribs 32a, 32b, 32c, 32d are each disposed near the corners of the recess 31a. Since the configurations of the recesses 31b, 31c, 31d, 31e and the plurality of ribs are the same as those of the recess 31a and the ribs 32a, 32b, 32c, 32d, their descriptions are omitted.

[0027] The second adhesive layer 14a is disposed on the substrate 11a, specifically, on the second surface 21b of the substrate 11a. The second adhesive layer 14a includes a first surface 24a located on one side in the thickness direction and a second surface 24b located on the other side in the thickness direction. The second adhesive layer 14a is disposed such that the first surface 24a contacts the second surface 21b of the substrate 11a. As the second adhesive layer 14a, similar to the first adhesive layer 12a, for example, a brazing material composed of an alloy of Ag and Cu is selected.

[0028] The second metal plate 15a is flat. The second metal plate 15a includes a first surface 25a located on one side in the thickness direction and a second surface 25b located on the other side in the thickness direction. The second metal plate 15a is adhered to the substrate 11a by the second adhesive layer 14a. In this case, the first surface 25a of the second metal plate 15a is disposed to contact the second surface 24b of the second adhesive layer 14a. Similar to the first metal plate 13a, for the second metal plate 15a, for example, a metal plate made of Cu is selected. A plating 19b is applied to the second surface 25b of the second metal plate 15a. Note that a heat sink (not shown) is joined to the second surface 25b side of the second metal plate 15a.

[0029] In this embodiment, the planar shape of the semiconductor chip 17a is square. That is, when viewed in the thickness direction, the outer shape of the semiconductor chip 17a is square. Note that the planar shape of the semiconductor chip 17a is not limited to square. The semiconductor chip 17a includes a first surface 27a located on one side in the thickness direction and a second surface 27b located on the other side in the thickness direction. The second surface 27b of the semiconductor chip 17a is arranged to face the first surface 23a of the first metal plate 13a. The semiconductor chip 17a is, for example, a Schottky barrier diode. Since the configurations of the semiconductor chips 17b, 17c, 17d, and 17e are equivalent to the configuration of the semiconductor chip 17a, their descriptions are omitted. In this embodiment, the semiconductor chips 17a, 17b, 17c, 17d, and 17e are arranged at intervals in the X direction. Also, the positions of the semiconductor chips 17a, 17b, 17c, 17d, and 17e in the Y direction are arranged to be the same.

[0030] The bonding material 16a is arranged to be interposed between the first surface 23a of the first metal plate 13a and the second surface 27b of the semiconductor chip 17a. The bonding material 16a includes a first surface 26a located on one side in the thickness direction and a second surface 26b located on the other side in the thickness direction. The bonding material 16a bonds the first metal plate 13a and the semiconductor chip 17a. The bonding material 16a has conductivity. By bonding the first metal plate 13a and the semiconductor chip 17a with the conductive bonding material 16a, the first metal plate 13a and the semiconductor chip 17a are electrically connected. As the bonding material 16a, for example, solder, specifically, plate solder is adopted. Note that the semiconductor chips 17b, 17c, 17d, and 17e are similarly bonded to the first metal plate 13a by the bonding material 16a. And the semiconductor chips 17b, 17c, 17d, and 17e are each electrically connected to the first metal plate 13a.

[0031] The bonding material 16a includes a first portion 33a and second portions 34a and 34b. The first portion 33a is disposed within the recess 31a. The second portion 34a is disposed between the rib 32a and the semiconductor chip 17a. The second portion 34b is disposed between the rib 32b and the semiconductor chip 17a. The thickness D2 of each of the second portions 34a and 34b is smaller than the thickness D1 of the first portion 33a (see particularly FIG. 4).

[0032] According to the semiconductor device 10a, since the thickness D1 of the first portion 33a of the bonding material 16a disposed within the recess 31a is relatively large, it is possible to suppress the occurrence of cracks due to thermal stress in the bonding material 16a and reliably bond the semiconductor chip 17a to the first metal plate 13a. The first portion 33a of the bonding material 16a is disposed within the recess 31a. Thus, during manufacturing, for example, it is possible to suppress the bonding material 16a from melting and flowing out onto the surface of the first metal plate 13a and the displacement of the arrangement position of the bonding material 16a. Thus, the first portion 33a of the bonding material 16a can be accurately arranged. That is, by precisely providing the position of the recess 31a in the first metal plate 13a, the first portion 33a of the bonding material 16a disposed within the recess 31a and the semiconductor chip 17a are bonded, and the semiconductor chip 17a can be accurately bonded to the desired position on the first metal plate 13a. Further, since the thickness D2 of the second portion 34a of the bonding material 16a disposed between the ribs 32a and 32b and the semiconductor chip 17a is smaller than the thickness D1 of the first portion 33a, it is difficult for unevenness in the thickness of the bonding material 16a to occur on the second portions 34a and 34b. Thus, it is possible to suppress the semiconductor chip 17a bonded to the first metal plate 13a from being inclined during bonding. That is, the second portions 34a and 34b of the bonding material 16a disposed on the plurality of ribs 32a and 32b arranged at intervals can accurately bond the semiconductor chip 17a to the first metal plate 13a without inclining the posture of the bonded semiconductor chip 17a. Thus, heat generated from the semiconductor chip 17a during the operation of the semiconductor device 10a can be evenly dissipated to the substrate 11a side. Therefore, according to such a semiconductor device 10a, it is possible to improve the reliability.

[0033] In the semiconductor device 10a described above, the recess 31a is arranged so as to include the outer edges of the plurality of ribs 32a and 32b. Therefore, when viewed in the thickness direction of the first metal plate 13a, the recess 31a is arranged around the plurality of ribs 32a and 32b. Thus, such a semiconductor device 10a is a semiconductor device capable of more accurately controlling the position of the semiconductor chip 17a joined by the bonding material 16a.

[0034] In the semiconductor device 10a described above, the plurality of ribs 32a and 32b are columnar. When viewed in the thickness direction of the first metal plate 13a, the recess 31a has a rectangular outer shape. The plurality of ribs 32a and 32b are respectively arranged near the corners of the rectangle. Thus, when the recess 31a is rectangular, by arranging the columnar ribs 32a and 32b near the corners of the rectangle, it is possible to more suppress the inclination of the posture of the semiconductor chip 17a. Therefore, such a semiconductor device 10a is a more reliable semiconductor device.

[0035] In the semiconductor device 10a described above, plating 19a is applied to the surface of the first metal plate 13a. Therefore, when using solder as the bonding material 16a, the bondability with the first metal plate 13a can be improved. Thus, such a semiconductor device 10a is a more reliable semiconductor device. In the present embodiment, since the plating 19a is applied to the region where the first metal plate 13a is not arranged, such as the region where the recesses 31a, 31b, 31c, 31d, and 31e are located, the bondability with the first adhesive layer 12a can be improved when using solder as the bonding material 16a. Therefore, such a semiconductor device 10a is a more reliable semiconductor device.

[0036] In the semiconductor device 10a, the thickness D1 of the first portion 33a is 0.2 mm or more and 0.5 mm or less. The thickness D2 of the second portions 34a and 34b is 1 / 2 or more of the thickness D1 of the first portion 33a. By thus defining the thickness D1 of the first portion 33a and the thickness D2 of the second portions 34a and 34b, the semiconductor device can more surely achieve the above-described effect. Note that the thickness D1 of the first portion 33a is preferably 0.3 mm or more. Also, the thickness D1 of the first portion 33a is preferably 0.4 mm or less.

[0037] In the semiconductor device 10a, the bonding material 16a is a plate solder. Since the plate solder is plate-shaped, the handleability during manufacturing is good. Therefore, by doing so, the productivity can be improved.

[0038] Next, a method for manufacturing the semiconductor device 10a will be briefly described. FIGS. 5, 6, 7, 8, 9, 10, and 11 are schematic perspective views showing some states of the manufacturing process of the semiconductor device 10a. FIG. 5 is a schematic perspective view showing the outer shape of the substrate 11a. FIG. 6 is a schematic perspective view showing a state where a brazing material as the first adhesive layer 12a is printed. FIG. 7 is a schematic perspective view showing a state where the first metal plate 13a is joined. FIG. 8 is a schematic perspective view showing a state where a resist pattern is printed. FIG. 9 is a schematic perspective view showing a state where the first metal plate 13a is etched. FIG. 10 is a schematic perspective view showing a state where plate solder is placed. FIG. 11 is a schematic perspective view showing a state where the semiconductor chips 17a, 17b, 17c, 17d, and 17e are joined.

[0039] First, referring to FIG. 5, a substrate 11a having a rectangular outer shape is prepared. Then, referring to FIG. 6, a brazing material as the first adhesive layer 12a is disposed on the first surface 21a of the substrate 11a. In this case, the brazing material as the first adhesive layer 12a is disposed by printing it in regions 36a, 36b, 36c, and 36d corresponding to the circuit patterns 18a, 18b, 18c, and 18d on the first surface 21a.

[0040] Next, referring to FIG. 7, the first metal plate 13a is joined onto the first adhesive layer 12a being disposed. In this case, the first metal plate 13a is joined onto the first adhesive layer 12a in which regions 36a, 36b, 36c, 36d corresponding to the shapes of the circuit patterns 18a, 18b, 18c, 18d are formed. Here, for regions where the regions 36a, 36b, 36c, 36d are not located, the first metal plate 13a is to be disposed on the first surface 21a of the substrate 11a. Then, referring to FIG. 8, a resist pattern 37a is printed onto the first metal plate 13a. Here, the resist pattern 37a is printed onto regions 38a, 38b, 38c, 38d corresponding to the shapes of the circuit patterns 18a, 18b, 18c, 18d and regions 39a, 39b, 39c, 39d corresponding to the shapes of the plurality of ribs described above.

[0041] Next, referring to FIG. 9, the first metal plate 13a is etched. In this case, the brazing material constituting the first adhesive layer 12a serves as a stop-etch layer during the etching of the first metal plate 13a. By etching, a plurality of ribs 32a, 32b, 32c, 32d and recesses 31a, 31b, 31c, 31d, 31e are formed. Then, plating 19a is applied to the surface. In this case, plating 19a is applied to the surface of the first metal plate 13a including the plurality of ribs 32a, 32b, 32c, 32d and the recesses 31a, 31b, 31c, 31d, 31e and the surface of the brazing material constituting the exposed first adhesive layer 12a.

[0042] Next, with reference to FIG. 10, a bonding material 16a composed of solder is placed on the recesses 31a, 31b, 31c, 31d, 31e. Here, a rectangular plate solder along the outer shape of the recesses 31a, 31b, 31c, 31d, 31e is used as the bonding material 16a. Next, semiconductor chips 17a, 17b, 17c, 17d, 17e are placed on the bonding material 16a. Thereafter, reflow is performed to melt the bonding material 16a and bond the semiconductor chips 17a, 17b, 17c, 17d, 17e and the first metal plate 13a as shown in FIG. 11. Here, if necessary, the semiconductor chips 17a, 17b, 17c, 17d, 17e may be pressed in the Z direction. By doing so, bonding can be achieved more reliably. Since the bonding material 16a composed of solder has conductivity, the semiconductor chips 17a, 17b, 17c, 17d, 17e and the first metal plate 13a are electrically connected. Thereafter, wiring etc. are performed to the semiconductor chips 17a, 17b, 17c, 17d, 17e, and the semiconductor device 10a shown in FIG. 1 etc. is manufactured.

[0043] According to such a manufacturing method, plating 19a can be easily applied to the surface of the first metal plate 13a including the plurality of ribs 32a, 32b, 32c, 32d and the recesses 31a, 31b, 31c, 31d, 31e and the surface of the brazing material constituting the exposed first adhesive layer 12a. Also, it becomes easy to make the shapes of the ribs 32a, 32b, particularly the wall surfaces 35a, 35b of the ribs 32a, 32b, along the thickness direction of the first metal plate 13a.

[0044] (Embodiment 2) Next, Embodiment 2, which is another embodiment, will be described. FIG. 12 is a schematic cross-sectional view showing a part of the semiconductor device in Embodiment 2. FIG. 13 is a schematic plan view when a part of the semiconductor device shown in FIG. 12 is viewed in the thickness direction of the substrate. FIG. 14 is an enlarged schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 12. FIG. 15 is an enlarged view schematically showing the portion indicated by the region XV in FIG. 12. Note that in FIGS. 14 and 15, illustrations of plating etc. to be described later are omitted, and the thicknesses D3, D4 to be described later are exaggerated and shown thickly.

[0045] Referring to FIGS. 12, 13, 14, and 15, the semiconductor device 50a of Embodiment 2 includes a substrate 51a, a first adhesive layer 52a, a first metal plate 53a, a second adhesive layer 54a, a second metal plate 55a, a bonding material 56a, a chip resistor 57a which is a semiconductor chip, and an electrode 79a bonded to the bonding material 56a.

[0046] The substrate 51a has a rectangular shape in which the length in the X direction is longer than the length in the Y direction when viewed in the thickness direction. The substrate 51a has insulating properties. The substrate 51a is made of, for example, ceramic. The substrate 51a includes a first surface 61a located on one side in the thickness direction and a second surface 61b located on the other side in the thickness direction. Note that the substrate 51a may have a rectangular shape in which the length in the Y direction is longer than the length in the X direction or may be square when viewed in the thickness direction.

[0047] The first adhesive layer 52a is disposed on the substrate 51a, specifically, on the first surface 61a of the substrate 51a. The first adhesive layer 52a includes a first surface 62a located on one side in the thickness direction and a second surface 62b located on the other side in the thickness direction. The first adhesive layer 52a is disposed such that the second surface 62b contacts the first surface 61a of the substrate 51a. As the first adhesive layer 52a, for example, a brazing material composed of an alloy of Ag and Cu is selected. Plating 59a is applied to a part of the first surface 62a of the first adhesive layer 52a, specifically, in a region where the recesses 71a and 71b described later are located and other regions where the first metal plate 53a is not disposed.

[0048] A circuit pattern 58a is formed on the first metal plate 53a. The first metal plate 53a includes a first surface 63a located on one side in the thickness direction and a second surface 63b located on the other side in the thickness direction. The first metal plate 53a is adhered to the substrate 51a by the first adhesive layer 52a. In this case, the second surface 63b of the first metal plate 53a is arranged to contact the first surface 62a of the first adhesive layer 52a. As the first metal plate 53a, for example, a metal plate made of Cu is selected. Note that as the thickness (length in the Z direction) of the first metal plate 53a, those with a thickness of 0.2 mm to 0.3 mm or 0.4 mm to 0.5 mm are adopted. Plating 59a is applied to the first surface 63a of the first metal plate 53a.

[0049] The first metal plate 53a includes a plurality of ribs 72a, 72b arranged at intervals and recesses 71a, 71b arranged adjacent to the plurality of ribs 72a, 72b. The recesses 71a, 71b include a first recess 71a and a second recess 71b arranged at intervals in the X direction which is the first direction. The plurality of ribs 72a, 72b include a first rib 72a arranged adjacent to the first recess 71a in the X direction which is the first direction, and a second rib 72b arranged adjacent to the second recess 71b in the X direction which is the first direction and spatially separated from the first rib 72a. The first rib 72a and the second rib 72b are arranged at intervals in the X direction which is the first direction. In the present embodiment, the recess 71a is arranged adjacent to the rib 72a in the X direction, and the recess 71b is arranged adjacent to the rib 72b in the X direction.

[0050] The ribs 72a, 72b are ridge-shaped extending in the Y direction respectively. The plurality of ribs 72a, 72b each have wall surfaces 75a, 75b along the thickness direction (Z direction) of the first metal plate 53a. The wall surfaces 75a, 75b are arranged to face each other with an interval in the X direction. The length in the X direction between the wall surfaces 75a, 75b is indicated by the length L1. The recesses 71a, 71b each have a rectangular outer shape when viewed in the thickness direction of the first metal plate 53a.

[0051] The second adhesive layer 54a is disposed on the substrate 51a, specifically, on the second surface 61b of the substrate 51a. The second adhesive layer 54a includes a first surface 64a located on one side in the thickness direction and a second surface 64b located on the other side in the thickness direction. The second adhesive layer 54a is disposed such that the first surface 64a contacts the second surface 61b of the substrate 51a. As the second adhesive layer 54a, similar to the first adhesive layer 52a, for example, a brazing material made of an alloy of Ag and Cu is selected.

[0052] The second metal plate 55a is flat. The second metal plate 55a includes a first surface 65a located on one side in the thickness direction and a second surface 65b located on the other side in the thickness direction. The second metal plate 55a is adhered to the substrate 51a by the second adhesive layer 54a. In this case, the first surface 65a of the second metal plate 55a is disposed so as to contact the second surface 64b of the second adhesive layer 54a. Similar to the first metal plate 53a, for the second metal plate 55a as well, for example, a metal plate made of Cu is selected. Note that a heat sink (not shown) is joined to the second surface 65b side of the second metal plate 55a.

[0053] In the present embodiment, the semiconductor chip is a chip resistor 57a. The chip resistor 57a includes a first pad 76a, a second pad 77a, and a resistor body 78a. The chip resistor 57a has a configuration in which the resistor body 78a is disposed between the first pad 76a and the second pad 77a.

[0054] The bonding material 56a is arranged to be interposed between the first surface 63a of the first metal plate 53a and the chip resistor 57a. The bonding material 56a includes a first surface 66a located on one side in the thickness direction and a second surface 66b located on the other side in the thickness direction. The bonding material 56a bonds the first metal plate 53a and the chip resistor 57a. Specifically, the second surface 67a of the first pad 76a of the chip resistor 57a is bonded to the first rib 72a. The second surface 67b of the second pad 77a of the chip resistor 57a is bonded to the second rib 72b. The bonding material 56a has conductivity. By bonding the first metal plate 13a and the chip resistor 57a with the conductive bonding material 56a, the first metal plate 13a and the chip resistor 57a are electrically connected. As the bonding material 56a, for example, solder, specifically, plate solder is adopted.

[0055] The bonding material 56a includes first portions 73a, 73b and second portions 74a, 74b. The first portion 73a is arranged in the recess 71a. The first portion 73b is arranged in the recess 71b. The second portion 74a is arranged between the rib 72a and the chip resistor 57a, specifically, the first pad 76a of the chip resistor 57a. The second portion 74b is arranged between the rib 72b and the chip resistor 57a, specifically, the second pad 77a of the chip resistor 57a. The thickness D4 of the second portions 74a, 74b is thinner than the thickness D3 of the first portions 73a, 73b, respectively.

[0056] According to the semiconductor device 50a, the thickness of the first portions 73a, 73b of the bonding material 56a arranged in the recesses 71a, 71b DSince 3 is relatively thick, it is possible to suppress the occurrence of cracks due to thermal stress in the bonding material 56a and reliably bond the chip resistor 57a to the first metal plate 53a. The first portion 73a of the bonding material 56a is disposed within the recess 71a. Also, the first portion 73b of the bonding material 56a is disposed within the recess 71b. Therefore, during manufacturing, for example, it is possible to suppress the bonding material 56a from melting and flowing out onto the surface of the first metal plate 53a and the displacement of the arrangement position of the bonding material 56a. Thus, the first portions 73a and 73b of the bonding material 56a can be accurately arranged. That is, by precisely providing the positions of the recesses 71a and 71b in the first metal plate 53a, the first portions 73a and 73b of the bonding material 56a disposed within the recesses 71a and 71b and the chip resistor 57a are bonded, and the chip resistor 57a can be accurately bonded to the desired position arranged on the first metal plate 53a. Also, the thickness of the second portions 74a and 74b of the bonding material 56a disposed between the ribs 72a and 72b and the chip resistor 57a D 4 is the thickness of the first portion 73a D is thinner than 3, so that on the second portions 74a and 74b, unevenness in the thickness of the bonding material 56a hardly occurs. Therefore, it is possible to suppress the chip resistor 57a bonded to the first metal plate 53a from being inclined during bonding. That is, the second portions 74a and 74b of the bonding material 56a disposed on the plurality of ribs 72a and 72b arranged at intervals can accurately bond the chip resistor 57a to the first metal plate 53a without tilting the posture of the bonded chip resistor 57a. Therefore, during the operation of the semiconductor device 50a, heat generated from the chip resistor 57a can be evenly dissipated to the substrate 51a side. Therefore, according to such a semiconductor device 50a, it is possible to improve the reliability.

[0057] According to the semiconductor device 50a described above, the recesses 71a and 71b include a first recess 71a and a second recess 71b spaced apart in a first direction. The plurality of ribs 72a and 72b include a first rib 72a disposed adjacent to the first recess 71a in the first direction and a second rib 72b disposed adjacent to the second recess 71b in the first direction and spatially separated from the first rib 72a. The first rib 72a and the second rib 72b are spaced apart in the first direction. Therefore, when bonding the chip resistor 57a to the first metal plate 53a, one pad, the first pad 76a, is bonded by the bonding material 56a disposed on the first rib 72a and the bonding material 56a disposed within the first recess 71a, and the other pad, the second pad 77a, can be bonded by the bonding material 56a disposed on the second rib 72b and the bonding material 56a disposed within the second recess 71b. Since the first rib 72a and the second rib 72b are spaced apart, it is easy to maintain the spatial separation state of the pads 76a and 77a on both sides of the chip resistor 57a. Therefore, such a semiconductor device 50a is a semiconductor device that can more reliably reduce the risk of contact between the first pad 76a and the second pad 77a.

[0058] According to the semiconductor device 50a described above, the semiconductor chip is the chip resistor 57a. The chip resistor 57a, which is the semiconductor chip, includes a first pad 76a and a second pad 77a. The first pad 76a is bonded to the first rib 72a. The second pad 77a is bonded to the second rib 72b. Therefore, such a semiconductor device 50a is a semiconductor device that can easily bond the chip resistor 57a including the first pad 76a and the second pad 77a to the first metal plate 53a while reducing the risk of contact between the first pad 76a and the second pad 77a.

[0059] According to the semiconductor device 50a described above, the plurality of ribs 72a and 72b each have wall surfaces 75a and 75b along the thickness direction of the first metal plate 53a. Therefore, even if the intervals between the plurality of ribs 72a and 72b are narrowed, the risk of contact between the ribs 72a and 72b can be reduced. Thus, for example, when bonding a small chip resistor 57a, the risk of the pads 76a and 77a contacting each other and short-circuiting can be reduced. Therefore, miniaturization can be easily achieved.

[0060] Next, a method for manufacturing the semiconductor device 50a will be briefly described. FIGS. 16, 17, 18, and 19 are schematic cross-sectional views showing partial states of the manufacturing process of the semiconductor device 50a. FIG. 16 is a schematic cross-sectional view showing a state in which a brazing material, which is the first adhesive layer 52a, is printed on the substrate 51a. FIG. 17 is a schematic cross-sectional view showing a state in which a resist pattern is printed. FIG. 18 is a schematic cross-sectional view showing a state in which the first metal plate 53a is etched. FIG. 19 is a schematic cross-sectional view showing a state in which plating is performed.

[0061] First, referring to FIG. 16, a brazing material, which is the first adhesive layer 52a, is disposed on the first surface 61a of the prepared substrate 51a. In this case, the brazing material as the first adhesive layer 52a is disposed by printing it on a part of the first surface 61a using a mask member 81a.

[0062] Next, referring to FIG. 17, the first metal plate 53a is bonded on top of the first adhesive layer 52a. In this case, the first metal plate 53a is disposed on the first surface 61a of the substrate 51a in the region where the first adhesive layer 52a is not located. A resist pattern 82a is printed on the first metal plate 53a. Here, using a mask member 83a, a resist pattern is printed in a region 39a corresponding to the shape of the rib.

[0063] Next, referring to FIG. 18, the first metal plate 53a is etched. In this case, the brazing material constituting the first adhesive layer 52a serves as a stop-etch layer during the etching of the first metal plate 53a. Ribs 72b and recesses 71b are formed by etching. Then, referring to FIG. 19, plating 59a is applied to the surface. In this case, plating 59a is applied to the surface of the brazing material constituting the exposed first adhesive layer 52a and on the first metal plate 53a including the ribs 72b and recesses 71b.

[0064] Next, a bonding material 56a composed of solder is placed in the recess 71b, and a chip resistor 57a is placed thereon. Then, reflow is performed to melt the bonding material 56a composed of solder and bond the chip resistor 57a and the first metal plate 13a. Here, if necessary, the chip resistor 57a may be pressed in the Z direction. Since the bonding material 56a has conductivity, the chip resistor 57a and the first metal plate 53a are electrically connected. Then, wiring etc. are performed to the chip resistor 57a, and the semiconductor device 50a shown in FIG. 12 etc. is manufactured.

[0065] According to such a manufacturing method, it becomes easy to form the wall surface 75a constituting the first rib 72a and the wall surface 75b constituting the second rib 72b in a shape along the thickness direction of the first metal plate 53a. Also, plating 59a can be easily applied to the surface of the brazing material constituting the exposed first adhesive layer 52a and on the first metal plate 53a including the plurality of ribs 72a, 72b and recesses 71a, 71b.

[0066] In the above-described Embodiment 1, the semiconductor chip is assumed to be a Schottky barrier diode, and in the above-described Embodiment 2, the semiconductor chip is assumed to be a chip resistor. However, the present invention is not limited to this, and the semiconductor chip may be a chip resistor, a capacitor, a vertical transistor, a diode, a MOSFET, or an IGBT.

[0067] (Other Embodiments) In addition, in the above-described embodiment, the surface of the metal plate does not necessarily need to be plated. That is, the metal plate may have a configuration that does not include plating.

[0068] Also, in the above-described embodiment, solder paste was used, but the present invention is not limited thereto, and other bonding materials, for example, solder paste, may be used. Since the solder paste has high adhesiveness, it is difficult to shift when disposed at a desired position. Therefore, productivity can also be improved in this way.

[0069] The embodiments disclosed this time should be understood as illustrative in all respects and not restrictive in any way. The scope of the present disclosure is defined not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Industrial Applicability

[0070] The semiconductor device of the present disclosure can be particularly advantageously applied when it is required to improve reliability.

Explanation of Reference Numerals

[0071] 10a, 50a Semiconductor device 11a, 51a Substrate 12a, 52a First adhesive layer 13a, 53a First metal plate 14a, 54a Second adhesive layer 15a, 55a Second metal plate 16a, 56a Bonding material 17a, 17b, 17c, 17d, 17e Semiconductor chip 18a, 18b, 18c, 18d, 58a Circuit pattern 19a, 19b, 59a Plating 21a, 22a, 23a, 24a, 25a, 26a, 27a, 61a, 62a, 63a, 64a, 65a First surface 21b, 22b, 23b, 24b, 25b, 26b, 27b, 61b, 62b, 63b, 64b, 65b, 66b, 67b Second surface 31a, 31b, 31c, 31d, 31e, 71a, 71b Concave portion 32a, 32b, 32c, 32d, 72a, 72b Rib 33a, 73a, 73b First part 34a, 34b, 74a, 74b Second part 35a, 35b, 75a, 75b Wall surface 36a, 36b, 36c, 36d, 38a, 38b, 38c, 38d, 39a, 39b, 39c, 39d Region 37a, 82a Resist pattern 57a Chip resistor 76a, 77a Pad 78a Resistor 79a Electrode 81a, 83a Mask member D1, D2, D3, D4 Thickness L1 Length

Claims

1. A substrate having insulation properties, An adhesive layer disposed on the substrate, A metal plate on which a circuit pattern is formed and which is adhered to the substrate by the adhesive layer, A chip resistor electrically connected to the metal plate, A bonding material for bonding the metal plate and the chip resistor, and comprising: The metal plate is A plurality of ribs that are spaced apart from each other and have wall surfaces along the thickness direction of the metal plate, A recess disposed adjacent to the plurality of ribs, and comprising: The bonding material is A first portion disposed within the recess, A semiconductor device including a second portion that is thinner than the thickness of the first portion and is disposed between the rib and the chip resistor.

2. The chip resistor is A first pad, A second pad, A resistor disposed between the first pad and the second pad, and comprising: The plurality of ribs are A first rib, A second rib that is spaced apart from the first rib in a first direction and is spatially separated from the first rib, and comprising: The first pad is joined to the first rib, The semiconductor device according to claim 1, wherein the second pad is joined to the second rib.

3. The recess is A first recess, A second recess that is spaced apart from the first recess in the first direction, and comprising: The first rib is disposed adjacent to the first recess in the first direction, The semiconductor device according to claim 2, wherein the second rib is disposed adjacent to the second recess in the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein each of the plurality of ribs has a wall surface along the thickness direction of the metal plate.

5. The semiconductor device according to claim 1, wherein the recess is disposed so as to include the outer edges of the plurality of ribs when viewed in the thickness direction of the metal plate.

6. The semiconductor device according to claim 5, wherein the recess has a rectangular outer shape when viewed in the thickness direction of the metal plate.

7. The semiconductor device according to any one of claims 1 to 6, wherein plating is applied to the surface of the metal plate.

8. The thickness of the first portion is 0.2 mm or more and 0.5 mm or less, The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the second portion is 1 / 2 or more of the thickness of the first portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein the bonding material is a solder paste.

10. The semiconductor device according to claim 2 or claim 3, wherein the resistor is disposed at a distance from the substrate. **Claim 11** The semiconductor device according to any one of claims 1 to 10, further comprising an electrode to be joined to the joining material.

Images