Semiconductor device

Abstract

To provide a semiconductor device in which the resistance difference between gate trench portions can be reduced.SOLUTION: A semiconductor device includes: a first trench portion 141 having a predetermined first trench length L1; a second trench portion 142 having a second trench length L2 longer than the first trench length; a first gate wiring portion 149 configured to be electrically connected to an end portion of the first trench portion; and a second gate wiring portion 150 configured to be electrically connected to the first gate wiring portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate wiring portion is larger than a resistivity per unit length of the second gate wiring portion.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 and 2). Patent Document 1 Japanese Patent Application Laid-Open No. 2017-103400 Patent Document 2 Japanese Patent Application Laid-Open No. 2015-207736

Summary of the Invention

Problems to be Solved by the Invention

[0003] If the resistance difference between gate trench portions is large, there is a risk of breakdown due to current concentration.

Means for Solving the Problems

[0004] In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first trench portion having a predetermined first trench length, a second trench portion having a second trench length longer than the first trench length, a first gate wiring portion electrically connected to an end of the first trench portion, and a second gate wiring portion electrically connected to the first gate wiring portion and electrically connected to an end of the second trench portion. The resistivity per unit length of the first gate wiring portion is greater than the resistivity per unit length of the second gate wiring portion.

[0005] The width of the first gate wiring portion may be narrower than the width of the second gate wiring portion.

[0006] The second gate wiring portion may include a polysilicon wiring and a metal wiring provided at least partially above the polysilicon wiring and electrically connected to the polysilicon wiring.

[0007] The first gate wiring portion may not be provided with a metal wiring.

[0008] The semiconductor device may include a polysilicon bridge portion that electrically connects metal wirings to each other.

[0009] The semiconductor device may further include a temperature sense portion and a temperature sense pad connected to the temperature sense portion via a temperature sense wiring, and the polysilicon bridge portion may be provided below the temperature sense wiring positioned between the metal wirings.

[0010] The metal wiring may be provided along the temperature sense pad in the trench extending direction.

[0011] The width of the polysilicon wiring adjacent to the temperature sense portion may be equal to or greater than the width of the polysilicon wiring of the first gate wiring portion.

[0012] The semiconductor device may further include an additional gate wiring portion provided above the first trench portion and the second trench portion and electrically connected to each of the first trench portion and the second trench portion.

[0013] The additional gate wiring portion may extend so as to pass through the centers of the first trench length and the second trench length.

[0014] The difference between the resistivity per unit length of the first gate wiring portion and the resistivity per unit length of the second gate wiring portion may be 10% or less.

[0015] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

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Figure 19

Embodiments for Carrying Out the Invention

[0017] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0018] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "front" or "top", and the other side is referred to as "back" or "bottom". Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "front", "top", "back", and "bottom" are not limited to the direction of gravity or the direction during mounting of the semiconductor device.

[0019] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without specifying positive or negative, it means directions parallel to the +Z-axis and -Z-axis. Also, in this specification, viewing from the +Z-axis direction may be referred to as a top view.

[0020] In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0021] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. However, the conductivity type of each doped region may be of the opposite polarity. Also, when described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of the P-type or N-type, and when described as P- type or N- type, it means that the doping concentration is lower than that of the P-type or N-type.

[0022] In this specification, the doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors may be taken as the higher concentration of donors or acceptors. The concentration difference can be measured by the voltage-capacitance measurement method (CV method). Also, the carrier concentration measured by the spreading resistance measurement method (SR) may be taken as the concentration of donors or acceptors. Further, when the concentration distribution of donors or acceptors has a peak, the peak value may be taken as the concentration of donors or acceptors in the region. In cases where the concentration of donors or acceptors in the region where donors or acceptors exist is substantially uniform, etc., the average value of the donor concentration or acceptor concentration in the region may be taken as the donor concentration or acceptor concentration.

[0023] FIG. 1 shows an example of the arrangement of each component on the front surface of the semiconductor device 100 according to Example 1. The semiconductor device 100 includes a semiconductor substrate 10, a gate pad 50, a current sense pad 172, a temperature sense unit 178, an anode pad 174 and a cathode pad 176 electrically connected to the temperature sense unit 178, a bidirectional diode unit 210, and an output comparison diode unit 220. The region where the current sense pad 172, the anode pad 174, the cathode pad 176, the bidirectional diode unit 210, and the output comparison diode unit 220 are provided may be collectively referred to as the pad region.

[0024] The semiconductor substrate 10 has an edge 102. In this specification, in the top view of FIG. 1, the direction of one edge 102-1 of the semiconductor substrate 10 is taken as the X axis, and the direction perpendicular to the X axis is taken as the Y axis. In this example, the X axis is taken in the direction of the edge 102-1. Also, the direction perpendicular to the X-axis direction and the Y-axis direction and forming a right-handed system is referred to as the Z-axis direction. The temperature sense unit 178 of this example is provided in the +Z axis direction of the semiconductor substrate 10.

[0025] The semiconductor substrate 10 is made of a semiconductor material such as silicon or a compound semiconductor. In the semiconductor substrate 10, the side where the temperature sense portion 178 is provided is referred to as the front surface, and the opposite side surface is referred to as the back surface. In this specification, the direction connecting the front surface and the back surface of the semiconductor substrate 10 is referred to as the depth direction. The semiconductor substrate 10 of this example has a substantially rectangular shape on the front surface, but may have a different shape.

[0026] The semiconductor substrate 10 has an active portion 120 on the front surface. The active portion 120 is a region where a main current flows in the depth direction between the front surface and the back surface of the semiconductor substrate 10 when the semiconductor device 100 is turned on. The gate conductive portion 44 of the active portion 120 described later is electrically connected to the gate pad 50 by the gate wiring portion described later.

[0027] The active portion 120 may be divided and arranged into an active portion 120-1, an active portion 120-2, an active portion 120-3, an active portion 120-4, an active portion 120-5, and an active portion 120-6. In particular, the active portion 120-1, the active portion 120- 3 , and the active portion 120- 4 may be separated in the X-axis direction by the separation portion 90. Similarly, the active portion 120- 2 , the active portion 120-5, and the active portion 120-6 may be separated in the X-axis direction by the separation portion 90. In this example, the active portion 120-1, the active portion 120- 3 , and the active portion 120- 4 arranged apart in the X-axis direction are electrically connected to each other by the emitter electrode 52 described later. Similarly, the active portion 120- 2 , the active portion 120-5, and the active portion 120-6 are also electrically connected to each other by the emitter electrode 52 described later.

[0028] The active part 120 may be provided with a transistor part 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors). The active part 120 may be provided with a diode part 80 including diode elements such as FWDs (Free Wheeling Diodes). When an IGBT and an FWD are provided in the active part 120, the transistor part 70 and the diode part 80 form an RC-IGBT (Reverse Conducting IGBT). The active part 120 may be a region where at least one of the transistor part 70 and the diode part 80 is provided.

[0029] In this example, in the active part 120, the symbol "I" is attached to the region where the transistor part 70 is arranged, and the symbol "F" is attached to the region where the diode part 80 is arranged. The transistor part 70 and the diode part 80 may be alternately arranged side by side in the X-axis direction in each region of the active part 120.

[0030] However, the arrangement of the transistor part 70 and the diode part 80 in this example is illustrative, and different arrangements may be possible. In the active part 120-3, the diode part 80 may be arranged on the negative side in the X-axis direction.

[0031] The semiconductor device 100 has a P+ type well region 130 outside the active part 120 on the front surface. Further outside, it has an edge termination structure part. The edge termination structure part has, for example, a guard ring provided annularly surrounding the active part 120, a field plate, and a structure combining these.

[0032] The temperature sensing unit 178 may be disposed in a wide portion near the center of the front surface of the semiconductor substrate 10. The active portion 120 is not provided in the wide portion. When the active portion 120 of the semiconductor substrate 10 is integrated, the central portion of the semiconductor substrate 10 is likely to be heated by the heat generated from the switching elements formed in the active portion 120. By providing the temperature sensing unit 178 in the wide portion near the center, the temperature of the transistor unit 70 can be monitored. Thereby, it is possible to prevent the transistor unit 70 from overheating beyond the junction temperature which is the normal operating temperature range.

[0033] The temperature sensing unit 178 may be provided by a temperature sensing diode. As an example, the temperature sensing unit 178 is provided by a Schottky diode. Also, the temperature sensing unit 178 may be provided by a PN junction diode made of polycrystalline silicon provided above the semiconductor substrate 10 via an insulating film.

[0034] A metal anode wiring 180 and a cathode wiring 182 are connected to the anode and cathode of the temperature sensing diode, respectively. The anode wiring 180 and the cathode wiring 182 are wirings containing a metal such as aluminum. The anode wiring 180 and the cathode wiring 182 are an example of temperature sensing wirings.

[0035] The cathode pad 176 is connected to the temperature sensing unit 178 via the cathode wiring 182. The anode pad 174 is connected to the temperature sensing unit 178 via the anode wiring 180. The cathode pad 176 and the anode pad 174 are electrodes containing a metal such as aluminum.

[0036] The current sensing pad 172 is electrically connected to the current sensing unit 110. The current sensing pad 172 is an example of a front surface electrode. The current sensing unit 110 has the same structure as the transistor unit 70 of the active portion 120 and simulates the operation of the transistor unit 70. A current proportional to the current flowing through the transistor unit 70 flows through the current sensing unit 110. Thereby, the current flowing through the transistor unit 70 can be monitored.

[0037] Note that, unlike the transistor section 70, the current sense section 110 is not provided with an emitter region 12 to be described later. As a result, the current sense section 110 does not operate as a transistor. A gate trench section is provided in the current sense section 110. The gate trench section of the current sense section 110 is electrically connected to the gate wiring section.

[0038] The bidirectional diode section 210 is disposed between the anode pad 174 and the cathode pad 176 on the front surface of the semiconductor device 100. The bidirectional diode section 210 includes diodes electrically connected in series in a bidirectional manner between the anode pad 174 and the cathode pad 176. The bidirectional diode section 210 prevents the temperature sense section 178 from being damaged by electrostatic discharge (ESD).

[0039] The output comparison diode section 220 is provided between the anode pad 174 and the cathode pad 176. The output comparison diode section 220 is electrically connected to the anode pad 174 and the cathode pad 176. The output comparison diode section 220 includes an output comparison diode having a direction of a PN junction connected in an antiparallel manner to the direction of the PN junction of the temperature sense diode of the temperature sense section 178.

[0040] The output comparison diode of the output comparison diode section 220 may have the same design as the diode of the temperature sense section 178 except for the direction of the PN junction. During the operation of the semiconductor device 100, no current is passed through the output comparison diode section 220. An output comparison operation is performed at predetermined intervals. During the output comparison operation, current is passed through the output comparison diode section 220. The output comparison operation enables the timing of replacement of the temperature sense diode of the temperature sense section 178 to be grasped.

[0041] In parallel with the output comparison diode section 220, a protection diode having the same forward direction as the output comparison diode section 220 may be provided. In that case, the protection diode prevents an overvoltage from being applied to the temperature sense section 178 or an overcurrent from flowing into the temperature sense section 178 due to noise or the like during the operation of the temperature sense section 178.

[0042] FIG. 2 shows an example of the arrangement of the gate wiring section on the front surface of the semiconductor device 100. The gate wiring section may be electrically connected to the gate pad 50. Further, the gate wiring section is connected to a gate conductive section 44, which will be described later, of the transistor section 70 disposed in the active section 120, and sets the gate conductive section 44 to the gate potential. The gate conductive section 44 corresponds to the gate electrode of the transistor section 70. Thereby, the transistor of the transistor section 70 is switched ON.

[0043] The gate wiring section includes an outer peripheral gate wiring section 48 that extends annularly along the outer periphery of the active section 120, and an inner gate wiring section 148 that extends between the active sections 120 and is electrically connected to the outer peripheral gate wiring section 48.

[0044] The gate wiring section has at least either a metal wiring or a polysilicon wiring provided below the metal wiring and electrically connected to the metal wiring. The metal wiring is formed by covering a conductive material such as aluminum or an aluminum-silicon alloy with an insulating film such as polyimide, and the polysilicon wiring is formed by covering polysilicon doped with impurities with an insulating film such as polyimide.

[0045] In this example, the outer peripheral gate wiring section 48 has a metal wiring 47 and a polysilicon wiring 46, and the inner gate wiring section 148 has a polysilicon wiring 146. In FIG. 2, on the front surface of the semiconductor substrate 10, the positions where the metal wiring is provided are indicated by a two-dot chain line, and the positions where the polysilicon wiring is provided are indicated by a broken line. However, the positions of these wirings in the figure only show approximate positions so as not to be entangled with other wirings. The detailed positions of the gate wiring section will be described later.

[0046] The gate wiring portion may be disposed above the well region 130 around the active portion 120. The outer peripheral gate wiring portion 48 may extend annularly along the outer periphery of the active portion 120. The inner gate wiring portion 148 may be disposed to surround the pad region together with the outer peripheral gate wiring portion 48, and may be disposed to surround the temperature sensing portion 178 in a wide portion near the center of the semiconductor substrate 10, which is sandwiched between the active portions 120-1 and 120-2.

[0047] The gate pad 50 is electrically connected to an external control terminal. The gate pad 50 is provided by a conductor of a metal such as aluminum. The gate pad 50 may be externally connected by wire bonding.

[0048] FIG. 3 is an example of the arrangement of the emitter electrode 52 provided on the front surface of the semiconductor device 100. The emitter electrode 52 is provided by a conductor of a metal such as aluminum. The emitter electrode 52 is set to an emitter potential which is a predetermined reference potential.

[0049] The emitter potential may be set to the ground potential. The emitter electrode 52 is also an example of a front surface electrode, similar to the current sense pad 172.

[0050] The emitter electrode 52 is disposed in the region indicated by the diagonal lines. The emitter electrode 52 has a main metal portion 203 provided to cover the entire active portion 120. Further, the emitter electrode 52 is also provided in the region above the separation portion 90 that separates the active portions 120-1, 120- 3 and 120- 4 from each other in the X-axis direction, and the emitter electrodes 52 are electrically connected to each other. Similarly, the active portions 120- 2 , 120-5, and 120-6 are also electrically connected to each other by the emitter electrode 52.

[0051] FIG. 4 is an example of a top view of the semiconductor device 100. FIG. 4 shows the vicinity of the negative side end portion of the active portion 120-2 in the Y-axis direction. The semiconductor device 100 includes a semiconductor substrate 10 having a transistor portion 70 including transistor elements such as IGBTs and a diode portion 80 including diode elements such as a freewheeling diode (FWD).

[0052] The semiconductor device 100 in this example includes a gate trench portion 40, a dummy trench portion 30, a well region 130, an emitter region 12, a base region 14, and a contact region 15 provided inside the front surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0053] Further, the semiconductor device 100 in this example includes a metal wiring 47 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The metal wiring 47 and the emitter electrode 52 are provided separately from each other. The metal wiring 47 and the emitter electrode 52 are electrically insulated from each other.

[0054] An interlayer insulating film is provided between the emitter electrode 52 and the metal wiring 47 and the front surface of the semiconductor substrate 10, but is omitted in FIG. 4. Contact holes 49, 54, and 56 are provided through the interlayer insulating film in the interlayer insulating film of this example. In FIG. 4, each contact hole is hatched with oblique lines.

[0055] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 130, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 through the contact hole 54.

[0056] Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connection portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate through insulating films such as an interlayer insulating film and the dummy insulating film of the dummy trench portion 30.

[0057] The metal wiring 47 is electrically connected to the polysilicon wiring 46 through the contact hole 49. The polysilicon wiring 46 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The polysilicon wiring 46 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 and the emitter electrode 52.

[0058] The polysilicon wiring 46 and the emitter electrode 52 are electrically separated by an insulator such as an interlayer insulating film and an oxide film. The polysilicon wiring 46 of this example is provided from below the contact hole 49 to the tip portion (Y-axis direction end portion) of the gate trench portion 40. The gate conductive portion is exposed on the front surface of the semiconductor substrate 10 at the tip portion of the gate trench portion 40 and is connected to the polysilicon wiring 46.

[0059] The emitter electrode 52 is formed of a conductive material containing metal. For example, it is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium or a titanium compound or the like under a region formed of aluminum or the like.

[0060] Each electrode may have a plug formed of tungsten or the like in the contact hole. The plug has a barrier metal on the side in contact with the semiconductor substrate 10, tungsten is embedded so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0061] The plug is provided in a contact hole that contacts the contact region 15 or the base region 14. Also, a P++-type plug region is formed under the contact hole of the plug, The plug area has which has a higher doping concentration than the contact region 15. This can improve the contact resistance between the barrier metal and the contact region 15. Also, the depth of the plug region is about 0.1 μm or less, and it has a region that is 10% or less of the depth of the contact region 15.

[0062] By improving the contact resistance of the plug region, the latch-up tolerance is improved in the operation of the transistor portion 70. On the other hand, in the operation of the diode portion 80, an increase in conduction loss and switching loss can be suppressed.

[0063] The well region 130 extends overlapping the outer peripheral region outside the polysilicon wiring 46 and is provided in an annular shape in top view. The well region 130 also extends with a predetermined width to the active portion 120 inside the polysilicon wiring 46 and is provided in an annular shape in top view. The well region 130 of this example is provided in a range farther from the polysilicon wiring 46 side than the Y-axis direction end of the contact hole 54. The well region 130 is a region of the second conductivity type having a higher doping concentration than the base region 14. The doping concentration of the well region 130 may be the same as or lower than the doping concentration of the contact region 15. The polysilicon wiring 46 is electrically insulated from the well region 130.

[0064] The base region 14 of this example is of P-type, and the well region 130 is of P+-type. Also, the well region 130 is formed from the front surface of the semiconductor substrate to a position deeper than the lower end of the base region 14. The base region 14 is provided in contact with the well region 130 in the transistor portion 70 and the diode portion 80. The well region 130 is electrically connected to the emitter electrode 52.

[0065] Each of the transistor portion 70 and the diode portion 80 has a plurality of trench portions arranged in the array direction. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the array direction. In the diode portion 80 of this example, a plurality of dummy trench portions 30 are provided along the array direction.

[0066] In this example, the array direction of the trench portions is the X-axis direction, and the extending direction perpendicular to the array direction is the Y-axis direction. The gate trench portion 40 of this example may have two extending portions 39 (portions of the trench that are linear along the extending direction) extending along the extending direction and a connecting portion 41 that connects the two extending portions 39.

[0067] At least a part of the connecting portion 41 may be provided in a curved shape in a top view. By connecting the connecting portion 41 to the polysilicon wiring 46 at the ends of the two extending portions 39 in the Y-axis direction, it functions as a gate electrode for the gate trench portion 40. On the other hand, by making the connecting portion 41 curved, the electric field concentration at the ends can be alleviated more than when it is completed by the extending portion 39.

[0068] In the transistor portion 70, the dummy trench portion 30 is provided between the respective extending portions 39 of the gate trench portion 40. In the example of FIG. 4, one dummy trench portion 30 is provided between the respective extending portions 39, but two or more dummy trench portions 30 may be provided.

[0069] Also, between the respective extending portions 39, the dummy trench portion 30 may not be provided, and the gate trench portion 40 may be provided. With such a structure, the electron current from the emitter region 12 can be increased, so the on-voltage is reduced.

[0070] The dummy trench portion 30 may have a linear shape extending in the extending direction, and similar to the gate trench portion 40, may have an extending portion 29 and a connecting portion 31. In the semiconductor device 100 shown in FIG. 4, only the dummy trench portion 30 having the connecting portion 31 is arranged. However, in other examples, the semiconductor device 100 may include a linear dummy trench portion 30 not having the connecting portion 31.

[0071] The diffusion depth of the well region 130 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 130 in a top view. That is, at the ends of each trench portion in the Y-axis direction, the bottom in the depth direction (positive Z-axis direction) of each trench portion is covered by the well region 130. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated.

[0072] A mesa portion is provided between the trench portions in the arrangement direction. The mesa portion refers to a region sandwiched by the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the lower end of the trench portion.

[0073] The mesa portion in this example is sandwiched by adjacent trench portions in the X-axis direction and is provided to extend in the extending direction (Y-axis direction) along the trench on the front surface of the semiconductor substrate 10.

[0074] A base region 14 is provided in each mesa portion. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in a region sandwiched by the base region 14 in a top view. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction. The dopant of the emitter region 12 is, for example, arsenic (As), phosphorus (P), antimony (Sb), or the like.

[0075] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. A contact region 15 exposed on the front surface of the semiconductor substrate 10 is provided in the mesa portion in contact with the gate trench portion 40.

[0076] Each of the contact region 15 and the emitter region 12 in the mesa portion is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion are alternately arranged along the extending direction (Y-axis direction) of the trench portion.

[0077] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched by the emitter regions 12.

[0078] The emitter region 12 is not provided in the mesa portion of the diode section 80. A base region 14 may be provided on the upper surface of the mesa portion of the diode section 80. The base region 14 may be arranged over the entire mesa portion of the diode section 80. The base region 14 of the diode section 80 operates as an anode.

[0079] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched by the base region 14 in its extending direction (Y-axis direction). The contact hole 54 in this example is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 may be arranged at the center in the arrangement direction (X-axis direction) of the mesa portions.

[0080] In the diode section 80, an N+-type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate. On the back surface of the semiconductor substrate, a P+-type collector region 22 may be provided in a region where the cathode region 82 is not provided. In FIG. 4, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0081] The cathode region 82 is arranged away from the well region 130 in the Y-axis direction. Thereby, by securing the distance between the P-type region (well region 130) having a relatively high doping concentration and formed to a deep position and the cathode region 82, hole injection from the well region 130 can be suppressed, and thus reverse recovery loss can be reduced. The end portion of the cathode region 82 in the Y-axis direction in this example is arranged farther from the well region 130 than the end portion of the contact hole 54 in the Y-axis direction. In other examples, the end portion of the cathode region 82 in the Y-axis direction may be arranged between the well region 130 and the contact hole 54.

[0082] FIG. 5 is an example of a top view of the semiconductor device 100. FIG. 5 illustrates the relationship between the gate trench portions 40 provided in the active portions 120-1 and 120-3 and the gate wiring portions adjacent thereto.

[0083] The lengths in the Y-axis direction of the active portions 120-1, 120-2, 120-3, 120-4, 120-5, and 120-6 are different. That is, the lengths (lengths in the Y-axis direction) of the gate trench portions 40 provided in these active portions are also different.

[0084] In this example, the gate trench portions 40 provided in the active portions 120-1 and 120-3 are respectively taken as the first trench portion 141 and the second trench portion 142. The length of the predetermined first trench portion 141 is taken as the first trench length L1, and the length of the second trench portion 142 is taken as the second trench length L2. In FIG. 5, the first trench length L1 and the second trench length L2 are respectively the maximum lengths in the Y-axis direction (extension direction) combining the extension portion 39 and the connection portion 41, but in other examples, it may be only the length of the extension portion 39. As shown in FIG. 5, the first trench length L1 is shorter than the second trench length L2.

[0085] The gate trench portion 40 is electrically connected to the gate wiring portion via the contact hole 49 at the end in the extension direction. The first trench portion 141 and the second trench portion 142 are electrically connected to the outer peripheral gate wiring portion 48 at the end on the positive side in the Y-axis direction (extension direction), and are electrically connected to the inner gate wiring portion 148 at the end on the negative side in the Y-axis direction. In this example, in the inner gate wiring portion 148, the portions electrically connected to the ends on the negative side in the Y-axis direction of the first trench portion 141 and the second trench portion 142 are respectively taken as the first gate wiring portion 149 and the second gate wiring portion 150. In FIG. 5, both the first gate wiring portion 149 and the second gate wiring portion 150 are polysilicon wirings 146.

[0086] The resistance of the gate trench portion 40 is obtained from the sum of the resistance of the gate trench portion 40 itself and the resistance of the gate wiring portion. The resistance of the gate trench portion 40 itself is calculated according to the dimensions and the number of the gate trench portion 40. The resistance of the gate wiring portion is calculated from the resistivity per unit length and the length, and when the gate wiring portion has a polysilicon wiring and a metal wiring, it is calculated from the average value of the respective resistances.

[0087] The resistance of the gate trench portion 40 increases in proportion to the distance from the gate wiring portion and reaches its maximum near the center in the extending direction. In such a high-resistance portion of the gate trench portion 40, the channel remains open during turn-off. Due to this delay, the electron current increases in the high-resistance portion, and further, the hole current attracted by the electron current concentrates. Therefore, if the resistance difference between the gate trench portions 40 is large, a high-resistance portion the delay increases and the current further concentrates, which may cause destruction.

[0088] To prevent such current concentration, the resistivity per unit length of the first gate wiring portion 149 is larger than the resistivity per unit length of the second gate wiring portion 150. In this example, the width of the first gate wiring portion 149 is narrower than the width of the second gate wiring portion 150. Here, the width of the gate wiring portion refers to the dimension in the direction orthogonal to the extending direction.

[0089] In this example, both the first trench portion 141 and the second trench portion 142 are connected to the polysilicon wiring 146, and since the first trench length L1 is shorter than the second trench length L2, the maximum resistance value of the second trench portion 142 is larger than the maximum resistance value of the first trench portion 141. Therefore, by making the resistivity per unit length of the second gate wiring portion 150 smaller than the resistivity per unit length of the first gate wiring portion 149, the resistance difference between the first trench portion 141 and the second trench portion 142 can be reduced, current concentration in the high-resistance portion (near the center in the extending direction of the second trench portion 142) can be suppressed, and destruction can be prevented.

[0090] Alternatively, the second gate wiring portion 150 may further have a metal wiring that is at least partially provided above the polysilicon wiring 146 and is electrically connected to the polysilicon wiring 146 in addition to the polysilicon wiring 146. In contrast, since no metal wiring is provided in the first gate wiring portion 149, the resistance of the second gate wiring portion 150 calculated from the average value of the resistances of the polysilicon wiring 146 and the metal wiring is smaller than the resistance of the first gate wiring portion 149, and the resistance difference between the first trench portion 141 and the second trench portion 142 can be reduced.

[0091] The difference between the resistivity per unit length of the first gate wiring portion 149 and the resistivity per unit length of the second gate wiring portion 150 may be set to be equal to or less than a predetermined threshold value. For example, the predetermined threshold value is 10%. Thus, by setting the resistance difference between the gate trench portions 40 to be equal to or less than the predetermined threshold value, a high-resistance portion the concentration of current in can be suppressed, and breakdown can be prevented.

[0092] Next, with reference to FIGS. 6 to 11, the configuration of the gate wiring portion of the semiconductor device 100 for suppressing the concentration of current will be described. FIGS. 6 to 11 are partial cross-sectional views of the semiconductor device 100 shown in FIG. 2, respectively. In the semiconductor device 100 of this example, as described above, a polysilicon wiring 46 and a metal wiring 47 are provided as the outer peripheral gate wiring portion 48, and a polysilicon wiring 146 is provided as the inner gate wiring portion 148.

[0093] FIG. 6 is an example of the a-a' cross-section of FIG. 2. The a-a' cross-section is a YZ cross-section passing through the outer peripheral gate wiring portion 48 and the tip portion (the positive side end portion in the Y-axis direction) of the gate trench portion 40. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section.

[0094] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass to which impurities such as boron or phosphorus are added. The interlayer insulating film 38 may be in contact with the front surface 21, and another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. A contact hole 49 is provided in the interlayer insulating film 38.

[0095] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing metal or a laminated film thereof.

[0096] The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0097] The semiconductor substrate 10 has a drift region 18 of the first conductivity type. The drift region 18 in this example is of the N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being provided.

[0098] One or more accumulation regions may be provided in the Z-axis direction above the drift region 18. The accumulation region is a region where the same dopant as in the drift region 18 accumulates at a higher concentration than in the drift region. The doping concentration of the accumulation region is higher than that of the drift region.

[0099] The accumulation region in this example is of the N-type. The accumulation region may be provided only in the transistor portion 70, or may be provided in both the transistor portion 70 and the diode portion 80. By providing the accumulation region, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0100] A buffer region 20 of the first conductivity type may be provided below the drift region 18. The buffer region 20 in this example is of the N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0101] In the transistor portion 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0102] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a free-wheeling diode (FWD) that conducts a reverse-direction free-wheeling current when the transistor section 70 turns off.

[0103] The gate trench section 40 is provided so as to reach the drift region 18 from the front surface 21. The gate trench section 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive section 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film.

[0104] The gate conductive section 44 is provided so as to embed the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive section 44 may be in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive section 44 and the semiconductor substrate 10. The gate conductive section 44 is formed of polysilicon doped with impurities or the like.

[0105] The gate trench section 40 is covered by an interlayer insulating film 38 on the front surface 21. When a predetermined voltage is applied to the gate conductive section 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0106] Although not shown in FIG. 6, the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film, and a dummy conductive portion provided on the front surface 21. The dummy insulating film is provided to cover the inner wall of the dummy trench. The dummy insulating film may be formed of an oxide film or a nitride film. The dummy conductive portion is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film. The upper surface of the dummy conductive portion may be in the same XY plane as the front surface 21. The dummy insulating film insulates the dummy conductive portion from the semiconductor substrate 10. The dummy conductive portion may be formed of the same material as the gate conductive portion 44.

[0107] The gate trench portion 40 and the dummy trench portion 30 of this example are covered by the interlayer insulating film 38 on the front surface 21. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be a convex curved surface (curved in cross section) downward.

[0108] The gate conductive portion 44 of the gate trench portion 40 is exposed on the front surface 21 of the semiconductor substrate 10 at the tip of the gate trench portion 40 and is electrically connected to the polysilicon wiring 46. The polysilicon wiring 46 is electrically connected to a metal wiring 47 provided above through a contact hole 49. The metal wiring 47 and the emitter electrode 52 are separated by a distance at which insulation is maintained.

[0109] In this way, the outer peripheral gate wiring portion 48 has the metal wiring 47 while maintaining insulation from the emitter electrode 52, thereby reducing the resistance of the entire gate wiring portion.

[0110] FIG. 7 is an example of the b-b' cross section of FIG. 2. The b-b' cross section is an XZ cross section passing through the inner gate wiring portion 148 extending in the X-axis direction between the active portion 120-3 and the pad region.

[0111] FIG. 8 is an example of the c-c' cross-section of FIG. 2. Similar to the b-b' cross-section, the c-c' cross-section is a YZ cross-section passing through the inner gate wiring portion 148 that extends in the X-axis direction between the active portion 120-3 and the pad region. Further, the c-c' cross-section passes through the tip portion (negative end in the Y-axis direction) of the gate trench portion 40 provided in the active portion 120-3.

[0112] As shown in FIGS. 7 and 8, the gate conductive portion 44 of the gate trench portion 40 is exposed on the front surface 21 of the semiconductor substrate 10 at the tip portion of the gate trench portion 40 and is electrically connected to the polysilicon wiring 146.

[0113] In this way, even in a region where the emitter electrode 52 and other electrodes (such as the current sense pad 172) are close to each other and it is impossible to secure a space for providing metal wiring, the polysilicon wiring 146 is provided as the inner gate wiring portion 148 to assist the outer peripheral gate wiring portion 48.

[0114] FIG. 9 is an example of the d-d' cross-section of FIG. 2. The d-d' cross-section is an XZ cross-section of the inner gate wiring portion 148 that extends in the X-axis direction between the active portion 120-1 and the active portion 120-2. The d-d' cross-section passes near the gate pad 50. An emitter electrode 52 and a gate pad 50 are provided above the semiconductor substrate 10. The polysilicon wiring 146 is insulated from the emitter electrode 52 by the interlayer insulating film 38, but is electrically connected to the gate pad 50.

[0115] FIG. 10 is an example of the e-e' cross-section of FIG. 2. The e-e' cross-section is a YZ cross-section of the inner gate wiring portion 148 that extends in the X-axis direction between the active portion 120-1 and the active portion 120-2. The e-e' cross-section passes between the pad region and the temperature sense portion 178. In the active portion 120-1 and the active portion 120-2, an emitter electrode 52 is provided above the semiconductor substrate 10. A pair of anode wiring 180 and cathode wiring 182 is provided between the emitter electrodes 52.

[0116] The polysilicon wiring 146 is provided so as to straddle the tip portions of the gate trench portions 40 provided in the active portions 120-1 and 120-2. The gate conductive portions 44 of the gate trench portions 40 provided in the active portions 120-1 and 120-2 are exposed on the front surface 21 of the semiconductor substrate 10 at the tip portions of the gate trench portions 40 and are electrically connected to the polysilicon wiring 146.

[0117] FIG. 11 is an example of the f-f' cross section of FIG. 2. The f-f' cross section is a YZ cross section of the inner gate wiring portion 148 extending in the X-axis direction between the active portion 120-1 and the active portion 120-2. The f-f' cross section passes through the temperature sense portion 178. Different from the e-e' cross section shown in FIG. 10, the temperature sense portion 178 is provided between the anode wiring 180 and the cathode wiring 182.

[0118] The temperature sense portion 178 has a PN junction diode made of polycrystalline silicon provided via an interlayer insulating film 38 above the semiconductor substrate 10. The polysilicon wiring 146 branches in the vicinity of the PN junction diode and extends so as to surround the PN junction diode. Thereby, the polysilicon wiring 146 ensures insulation from the temperature sense portion 178.

[0119] The width of the polysilicon wiring 146 adjacent to the temperature sense portion 178 is equal to or greater than the width of the polysilicon wiring 146 of the first gate wiring portion 149 shown in FIG. 5. Here, the polysilicon wiring 146 adjacent to the temperature sense portion 178 refers to the width of the polysilicon wiring 146 surrounding the PN junction diode.

[0120] The central part of the semiconductor substrate 10 provided with the temperature sensing section 178 is liable to be damaged due to heat generation from the switching elements formed in the active section 120. Also, the gate trench sections 40 provided in the active section 120-1 and the active section 120-2 have a shorter trench length in the vicinity of the temperature sensing section 178. In the region where the trench length changes, current concentrates during turn-off, making it liable to cause damage. Therefore, by increasing the width of the adjacent polysilicon wiring 146, the resistance of the gate trench section 40 in the vicinity of the temperature sensing section 178 is reduced, preventing current concentration during turn-off.

[0121] Thus, the semiconductor device 100 of this example includes a gate wiring section provided so as to reduce the resistance difference between the gate trench sections 40. Here, the outer peripheral gate wiring section 48 has the metal wiring 47 and the polysilicon wiring 46, and the inner gate wiring section 148 has only the polysilicon wiring 146, but it is not limited to this as long as the resistance difference between the gate trench sections 40 is below a predetermined threshold value.

[0122] The outer peripheral gate wiring section 48 may have only the metal wiring 47 without having the polysilicon wiring 46. Alternatively, the inner gate wiring section 148 may further have a metal wiring in addition to the polysilicon wiring 146 in a region where a sufficient distance required for insulation can be ensured between the emitter electrode 52 and other electrodes.

[0123] FIG. 12 shows an example of the arrangement of the gate wiring section on the front surface of the semiconductor device 200 according to the second embodiment. In the semiconductor device 200, unlike the semiconductor device 100, at least a part of the inner gate wiring section 148 has the polysilicon wiring 146 and the metal wiring 147. In the semiconductor device 200, the same reference numerals are given to the parts common to the semiconductor device 100, and the description thereof is omitted.

[0124] FIG. 13 is an example of the g-g' cross-section of FIG. 12. The g-g' cross-section is a YZ cross-section passing through the inner gate wiring portion 148 extending in the X-axis direction between the active portion 120-3 and the pad region. Further, the g-g' cross-section passes through the tip (negative end in the Y-axis direction) of the gate trench portion 40 provided in the active portion 120-3. The gate conductive portion 44 of the gate trench portion 40 is exposed on the front surface 21 of the semiconductor substrate 10 at the tip of the gate trench portion 40 and is electrically connected to the polysilicon wiring 146.

[0125] FIG. 14 is an example of the h-h' cross-section of FIG. 12. The h-h' cross-section is an XZ cross-section passing through the inner gate wiring portion 148 extending in the X-axis direction between the active portion 120-3 and the pad region.

[0126] As shown in FIGS. 13 and 14, the metal wiring 147 extends above the polysilicon wiring 146 and is electrically connected to the polysilicon wiring 146 via the contact hole 49. The metal wiring 147 is provided separated from the emitter electrode 52 and other electrodes. Thus, by further including the metal wiring 147 in the inner gate wiring portion 148, the resistance of the gate trench portion 40 can be reduced.

[0127] FIG. 15 is an example of the k-k' cross-section of FIG. 12. The k-k' cross-section is an XZ cross-section of the inner gate wiring portion 148 extending in the X-axis direction between the active portion 120-1 and the active portion 120-2. The k-k' cross-section passes between the pad region and the temperature sense portion 178 and passes through the anode wiring 180 adjacent to the inner gate wiring portion 148 in the vicinity of the pad region.

[0128] On the positive side in the X-axis direction of the pad region, the gate wiring portion may be close to the emitter electrode 52 or the anode wiring 180 and the cathode wiring 182. In such a region, since there is a risk of short circuit, it is difficult to provide the metal wiring 147.

[0129] The semiconductor device 200 of this example further includes a polysilicon bridge portion 145 that electrically connects the metal wirings 147 to each other. The polysilicon bridge portion 145 may be a part of the polysilicon wiring 146 or may be a separate member formed of polysilicon. The polysilicon bridge portion 145 is electrically connected to the metal wiring 147 provided above via the contact hole 49.

[0130] In FIG. 15, the metal wiring 147 is provided to the extent that insulation from the anode wiring 180 can be ensured. In the region where the metal wiring 147 is not provided, the polysilicon bridge portion 145 is provided below the anode wiring 180. Although not shown, the metal wiring 147 may be provided to the extent that insulation from the cathode wiring 182 can be ensured, and the polysilicon bridge portion 145 may also be provided below the cathode wiring 182. Further, when the anode wiring 180 and the cathode wiring 182 are not provided, only one metal wiring 147 may be provided.

[0131] The polysilicon bridge portion 145 may be further provided between the metal wiring 147 extending in the X-axis direction between the active portions 120-1 and 120-2 and the metal wiring 147 surrounding the gate pad 50.

[0132] Since the temperature sense wiring is not provided in the vicinity of the gate pad 50, which is different from the vicinity of the pad region, it is possible to provide a metal wiring from the viewpoint of insulation. However, by providing the polysilicon bridge portion 145 instead of the metal wiring 147 in the vicinity of the gate pad 50, the configuration of the gate wiring portion becomes symmetric on both sides of the temperature sense portion 178, and concentration of current due to imbalance can be prevented.

[0133] FIG. 16 is an example of the m-m' cross-section of FIG. 12. The m-m' cross-section is a YZ cross-section of the inner gate wiring portion 148 extending in the X-axis direction between the active portions 120-1 and 120-2. The m-m' cross-section passes between the pad region and the temperature sensing portion 178. In the active portions 120-1 and 120-2, an emitter electrode 52 is provided above the semiconductor substrate 10. Between the emitter electrodes 52, a pair of an anode wiring 180 and a cathode wiring 182 is provided.

[0134] The polysilicon wiring 146 is provided so as to straddle the tip portions of the gate trench portions 40 provided in the active portions 120-1 and 120-2. The gate conductive portion 44 of the gate trench portion 40 provided in the active portions 120-1 and 120-2 is exposed on the front surface 21 of the semiconductor substrate 10 at the tip portion of the gate trench portion 40 and is electrically connected to the polysilicon wiring 146.

[0135] The metal wiring 147 is provided between the emitter electrode 52 and the anode wiring 180 and between the emitter electrode 52 and the cathode wiring 182. The metal wiring 147 is spaced apart from each of the emitter electrode 52, the anode wiring 180, and the cathode wiring 182 so as to sufficiently secure the distance required for insulation.

[0136] The metal wiring 147 extends above the polysilicon wiring 146 and is electrically connected to the polysilicon wiring 146 through the contact hole 49. Thus, by further including the metal wiring 147 in the inner gate wiring portion 148, the resistance of the gate trench portion 40 can be reduced. FIG. 17 is an example of the n-n' cross-section of FIG. 12. The n-n' cross-section is a YZ cross-section of the inner gate wiring portion 148 extending in the X-axis direction between the active portions 120-1 and 120-2. The n-n' cross-section passes through the temperature sensing portion 178.

[0137] The polysilicon wiring 146 branches near the PN junction diode and extends so as to surround the PN junction diode. Thereby, the polysilicon wiring 146 secures insulation from the temperature sense section 178.

[0138] Similar to FIG. 16, the metal wiring 147 is provided between the emitter electrode 52 and the anode wiring 180, and between the emitter electrode 52 and the cathode wiring 182. The metal wiring 147 is spaced apart from each of the emitter electrode 52, the anode wiring 180, and the cathode wiring 182 so as to sufficiently secure the distance required for insulation.

[0139] The metal wiring 147 extends above the polysilicon wiring 146 and is electrically connected to the polysilicon wiring 146 via the contact hole 49. Thus, by further including the metal wiring 147 in the inner gate wiring portion 148, the resistance of the gate trench portion 40 can be reduced.

[0140] FIG. 18 shows an example of the arrangement of the gate wiring portion on the front surface of the semiconductor device 300 according to the third embodiment. In the semiconductor device 300, the same reference numerals are given to the portions common to the semiconductor device 100, and the description thereof is omitted.

[0141] In the semiconductor device 300, the inner gate wiring portion 148 mostly has only the polysilicon wiring 146 and locally has the metal wiring 147. In this example, the metal wiring 147 extends in the Y-axis direction along the positive X-axis direction end of the pad region. The positive X-axis direction of the pad region is the boundary between the active portion 120-3 and the active portion 120-1. As described with reference to FIG. 5, with this position as the boundary, the length of the gate trench portion 40 changes from the trench length L1 to the trench length L2. As described above, in the region where the trench length changes, current concentrates during turn-off and breakdown is likely to occur.

[0142] Therefore, the inner gate wiring portion 148 has the metal wiring 147 at least along the positive X-axis end portion of the pad region, thereby reducing the resistance of the gate wiring portion in the region where the trench length changes. Thus, even when the inner gate wiring portion 148 is formed of the polysilicon wiring 146 due to safety constraints, the local provision of the metal wiring 147 prevents current concentration during turn-off.

[0143] FIG. 19 shows an example of the arrangement of the gate wiring portion on the front surface of the semiconductor device 400 according to the fourth embodiment. In the semiconductor device 400, the same reference numerals are given to the portions common to the semiconductor device 100, and the description thereof is omitted.

[0144] The semiconductor device 400 further includes an additional gate wiring portion 152 provided above the gate trench portion 40 and electrically connected to the gate trench portion 40. Here, above the gate trench portion 40 means the +Z-axis direction in the range between the Y-axis end portions of the gate trench portion 40 in a top view. The additional gate wiring portion 152 is electrically connected to the gate trench portion 40 via a contact hole (not shown).

[0145] The additional gate wiring portion 152 extends over the active portions 120-3, 120-1, and 120-4, is provided above the first trench portion 141 and the second trench portion 142 shown in FIG. 5, and may be electrically connected to each of the first trench portion 141 and the second trench portion 142. An additional gate wiring portion 152 extending over the active portions 120-5, 120-2, and 120-6 may be further provided.

[0146] The additional gate wiring portion 152 may have at least one of the polysilicon wiring 146 and the metal wiring 147, similar to the inner gate wiring portion 148. The polysilicon wiring 146 thereof.In this case, at a position where the polysilicon wiring 146 and the gate trench portion 40 overlap, the gate conductive portion 44 may be exposed on the front surface 21 of the semiconductor substrate 10, and the polysilicon wiring 146 and the gate conductive portion 44 may be electrically connected. The metal wiring 147 may be electrically connected to the gate conductive portion 44 via a contact hole.

[0147] The additional gate wiring portion 152 may extend so as to pass through the center in the extending direction of the gate trench portion 40. For example, the additional gate wiring portion 152 extends so as to pass through the centers of the first trench length L1 and the second trench length L2 shown in FIG. 5. That is, the additional gate wiring portion 152 extends in the X-axis direction along the Y-axis center of the gate trench portion 40 within the active portion 120, and extends in the Y-axis direction so as to adjust the Y-axis position between the active portions 120.

[0148] As described above, the resistance of the gate trench portion 40 increases in proportion to the distance from the gate wiring portion and reaches a maximum near the center in the extending direction. Therefore, by providing the additional gate wiring portion 152 and shortening the maximum distance from the gate wiring portion, the resistance difference between the gate trench portions 40 can be reduced, current concentration in the high-resistance portion can be suppressed, and breakdown can be prevented.

[0149] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0150] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "before" or "preceding" etc. in particular, and it should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if explanations are given using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Signs

[0151] 10 ··· semiconductor substrate, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 18 ··· drift region, 20 ··· buffer region, 21 ··· front surface, 22 ··· collector region, 23 ··· back surface, 24 ··· collector electrode, 25 ··· connection part, 29 ··· extension part, 30 ··· dummy trench part, 31 ··· connection part, 38 ··· interlayer insulating film, 39 ··· extension part, 40 ··· gate trench part, 41 ··· connection part, 42 ··· gate insulating film, 44 ··· gate conductive part, 46 ··· polysilicon wiring, 47 ··· metal wiring, 48 ··· outer peripheral gate wiring part, 49 ··· contact hole, 50 ··· gate pad, 52 ··· emitter electrode, 54 ··· contact hole, 56 ··· contact hole, 70 ··· transistor part, 80 ··· diode part, 82 ··· cathode region, 90 ··· isolation part, 100 ··· semiconductor device, 102 ··· side edge, 110 ··· current sense part, 120 ··· active part, 130 ··· well region, 141 ··· first trench part, 142 ··· second trench part, 145 ··· polysilicon bridge part, 146 ··· polysilicon wiring, 147 ··· metal wiring, 148 ··· inner gate wiring part, 149 ··· first gate wiring part, 150 ··· second gate wiring part, 152 ··· additional gate wiring part, 172 ··· current sense pad, 174 ··· anode pad, 176 ··· cathode pad, 178 ··· temperature sense part, 180 ··· anode wiring, 182 ··· cathode wiring, 200 ··· semiconductor device, 203 ··· main metal part, 210 ··· bidirectional diode part, 220 ··· output comparison diode part, 300 ··· semiconductor device, 400 ··· semiconductor device

Claims

1. a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate wiring portion electrically connected to an end of the first trench portion; a second gate wiring portion electrically connected to the first gate wiring portion and electrically connected to an end of the second trench portion ; comprising wherein a resistivity per unit length of the first gate wiring portion is greater than a resistivity per unit length of the second gate wiring portion; the second gate wiring portion has a polysilicon wiring and a metal wiring provided at least partially above the polysilicon wiring and electrically connected to the polysilicon wiring; and further comprising a polysilicon bridge portion for electrically connecting the metal wirings a semiconductor device.

2. wherein a width of the first gate wiring portion is narrower than a width of the second gate wiring portion The semiconductor device according to claim 1.

3. wherein the metal wiring is not provided in the first gate wiring portion The semiconductor device according to claim 1.

4. further comprising a temperature sense portion and a temperature sense pad connected to the temperature sense portion via a temperature sense wiring; wherein the polysilicon bridge portion is provided below the temperature sense wiring located between the metal wirings The semiconductor device according to claim 1.

5. wherein the metal wiring is provided along the temperature sense pad in a trench extending direction The semiconductor device according to claim 4.

6. wherein a width of the polysilicon wiring adjacent to the temperature sense portion is equal to or greater than a width of the polysilicon wiring of the first gate wiring portion The semiconductor device according to claim 4 or 5.

7. A first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate wiring portion electrically connected to an end of the first trench portion; a second gate wiring portion electrically connected to the first gate wiring portion and electrically connected to an end of the second trench portion ; comprising wherein a resistivity per unit length of the first gate wiring portion is greater than a resistivity per unit length of the second gate wiring portion; further comprising an additional gate wiring portion provided above the first trench portion and the second trench portion and electrically connected to each of the first trench portion and the second trench portion, The additional gate wiring portion extends so as to pass through the centers of the first trench length and the second trench length. Semiconductor device. **Claim 8**: A first trench portion having a predetermined first trench length, a second trench portion having a second trench length longer than the first trench length, a first gate wiring portion electrically connected to an end of the first trench portion, a second gate wiring portion electrically connected to the first gate wiring portion and electrically connected to an end of the second trench portion and comprising: The resistivity per unit length of the first gate wiring portion is greater than the resistivity per unit length of the second gate wiring portion, and the difference between the resistivity per unit length of the first gate wiring portion and the resistivity per unit length of the second gate wiring portion is 10% or less. Semiconductor device.

Images