Superconducting device

Abstract

To provide a superconducting device capable of suppressing disconnection of a terminal connected to the outside and securing a terminal connected to the outside.SOLUTION: A superconducting device according to an embodiment includes a superconducting chip 10, an interposer 20 on which the superconducting chip 10 is mounted, a socket 40 disposed opposite the interposer 20, and including a movable pin 47 and a housing 45 supporting the movable pin 47, and a board 50 arranged to face the socket 40 and formed with a connector for external input / output, and in the board 50, one end of the terminal of a via hole 52 is electrically connected to one end of the terminal of the movable pin 47, and the hole diameter of the via hole 52 is smaller than the diameter of the tip of movable pin 47 connected to the via hole.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a superconducting device.

Background Art

[0002] Patent Document 1 describes a quantum device (superconducting device) in which a superconducting chip using a superconducting state is flip-chip mounted on an interposer. In order to use such a superconducting device in a superconducting state, it is necessary to cool the superconducting device to an extremely low temperature.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a superconducting chip is cooled to an extremely low temperature, the contact points with the terminals connected to the outside may be disconnected due to stress and strain caused by volume changes during cooling. Further, in the superconducting device described above, when one side of the interposer is used for cooling by a sample stage, there is a limit to the number of terminals connected to the outside.

[0005] An object of the present disclosure is to solve such problems, and to provide a superconducting device that can suppress disconnection of terminals connected to the outside and secure terminals connected to the outside.

Means for Solving the Problems

[0006] The superconducting device according to the present disclosure includes a superconducting chip configured with quantum bits, an interposer on which the superconducting chip is mounted, a socket disposed opposite to the interposer and including a movable pin and a housing that supports the movable pin, and a board disposed opposite to the socket and having a connector formed thereon for input / output to the outside. The board has via holes formed therein, and one end of the terminal of the via hole is electrically connected to one end of the terminal of the movable pin, and the hole diameter of the via hole is slightly smaller than the diameter of the tip portion of the movable pin connected to the via hole.

Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a superconducting device that suppresses disconnection of terminals connected to the outside and secures terminals connected to the outside.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Best Mode for Carrying Out the Invention

[0009] Quantum computing is a field that manipulates data using quantum mechanical phenomena (qubits). Quantum mechanical phenomena include superposition of multiple states (where a quantum variable takes multiple different states simultaneously), entanglement (where multiple quantum variables are related states regardless of space or time), etc. A superconducting chip is provided with a quantum circuit that generates qubits. For clarity of explanation, the following descriptions and drawings have been appropriately omitted and simplified. Also, in each drawing, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted as necessary. (Embodiment 1) The superconducting device according to Embodiment 1 will be described. FIG. 1 is a cross-sectional view illustrating the superconducting device according to Embodiment 1. FIG. 2 is an exploded perspective view illustrating a superconducting chip and an interposer in the superconducting device according to Embodiment 1. As shown in FIGS. 1 and 2, the superconducting device 1 includes a superconducting chip 10, an interposer 20, a socket 40, and a board 50.

[0010] The superconducting chip 10 includes a chip substrate 15 and a wiring layer 16. The chip substrate 15 includes, for example, silicon (Si). Note that the chip substrate 15 is not limited to including silicon as long as the superconducting chip 10 can form qubits, and may include other electronic materials such as sapphire and compound semiconductor materials (Group IV, III-V, II-VI). Also, a single crystal is desirable, but a polycrystal or amorphous material may also be acceptable.

[0011] The shape of the chip substrate 15 is, for example, plate-shaped, and has one plate surface and the other plate surface on the opposite side of one plate surface. One plate surface is called the first surface 11, and the other plate surface is called the second surface 12. Therefore, the superconducting chip 10 and the chip substrate 15 have the first surface 11 and the second surface 12. For example, the first surface 11 and the second surface 12 are rectangular. In the superconducting device 1, the first surface 11 faces the interposer 20 side. The first surface 11 is mounted on the interposer 20 by bumps BP.

[0012] The wiring layer 16 is provided on the first surface 11 side of the chip substrate 15. The wiring layer 16 contains, for example, a superconducting material such as niobium (Nb). Note that the superconducting material used for the wiring layer 16 is not limited to, for example, niobium (Nb), and may be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), or an alloy containing at least any of these.

[0013] The wiring layer 16 includes a quantum circuit 17. In the quantum circuit 17, a resonator 17c having a loop circuit 17b in which a superconducting material is connected in a ring by a Josephson junction 17a is formed. The material used for the Josephson junction is preferably Al, but other superconducting materials may also be used. The quantum circuit 17 performs processing using the resonator 17c in the quantum state in superconductivity. Thus, the superconducting chip 10 includes the quantum circuit 17 and performs processing using the quantum state.

[0014] The wiring layer 16 is mounted on the interposer 20 via the bumps BP. Therefore, the superconducting chip 10 is flip-chip mounted on the interposer 20.

[0015] The bump BP may contain the superconducting material described above. The bump BP may contain the same superconducting material as the wiring layer 16 or a different superconducting material from the wiring layer 16. Further, when the bump BP includes a plurality of metal layers, it is preferable that at least one layer contains a superconducting material. The bump BP may be a layered structure including Nb (wiring surface of the superconducting chip 10) / In (Sn, Pb, and an alloy containing at least any of these) / Ti / Nb (wiring surface of the interposer 20) / Cu, or may be a layered structure including Nb (wiring surface of the superconducting chip 10) / Nb (wiring surface of the interposer 20) / Cu, or may be a layered structure including Nb (wiring surface of the superconducting chip 10) / In (Sn, Pb, and an alloy containing at least any of these) / Ta (wiring surface of the interposer 20) / Cu. Also, in the case of the bump BP containing Al and In, TiN may be used as a barrier layer to prevent alloying between Al and In. In that case, the bump BP may be a layered structure including Al (wiring surface of the superconducting chip 10) / Ti / TiN / In (Sn, Pb, and an alloy containing at least any of these) / TiN / Ti / Al (wiring surface of the interposer 20) / Cu. Here, Ti is an adhesion layer. A preferable flip chip connection is Nb (wiring of the superconducting chip 10) / In / Ti / Nb (wiring surface of the interposer 20) / Cu, or Nb (wiring of the superconducting chip 10) / Nb (wiring surface of the interposer 20) / Cu. It is preferable to provide a bump with a diameter of φ100 μm by adding the thickness of Cu in the range of 2 to 10 μm to the 2 μm thickness of the interposer wiring layer 23.

[0016] The interposer 20 includes an interposer wiring layer 23 and 24, an interposer substrate 25, and a through via (hereinafter referred to as TV26). In FIG. 1, TV26 is omitted so that the figure does not become complicated.

[0017] The interposer substrate 25 is, for example, plate-shaped. The interposer substrate 25 contains, for example, silicon (Si). Note that the interposer substrate 25 is not limited to those containing silicon as long as the superconducting chip 10 can be mounted thereon, and may contain other electronic materials such as sapphire, compound semiconductor materials (Group IV, III-V, II-VI), glass, and ceramics. The surface of the interposer substrate 25 is preferably covered with a silicon oxide film (SiO2, TEOS film, etc.). The interposer substrate 25 and the interposer 20 have a mounting surface 21 on which the superconducting chip 10 is mounted and an opposite surface 22 on the side opposite to the mounting surface 21.

[0018] Here, for the convenience of explaining the superconducting device 1, an XYZ orthogonal coordinate axis is introduced. A plane parallel to the opposite surface 22 of the interposer 20 is defined as the XY plane, and the direction perpendicular to the opposite surface 22 is defined as the Z-axis direction. The +Z-axis direction is upward, and the -Z-axis direction is downward. Note that the upward and downward directions are for the convenience of explanation and do not indicate the direction in which the actual superconducting device 1 is arranged when in use.

[0019] For example, the superconducting chip 10 is arranged on the -Z-axis direction side of the interposer 20. The wiring layer 16 arranged on the +X-axis direction side of the superconducting chip 10 and the mounting surface 21 arranged on the -Z-axis direction side of the interposer 20 are connected via bumps BP.

[0020] The interposer wiring layer 23 is formed on the mounting surface 21 side of the interposer 20, that is, on the -Z axis direction side of the interposer 20. The interposer wiring layer 23 contains the superconducting material described above. The interposer wiring layer 23 may contain the same superconducting material as the wiring layer 16 or a different superconducting material from the wiring layer 16. For example, the interposer wiring layer 23 preferably contains Nb (0.1 μm thick), Cu (2 μm thick), and Ti in order from the surface to the interposer substrate 25. For example, when the interposer substrate 25 contains silicon, the mounting surface 21 side of the interposer 20 preferably has a configuration of Nb / Cu / Ti / SiO2 / Si (interposer substrate 25). The interposer wiring layer 23 is connected to the wiring layer 16 of the superconducting chip 10 via the bump BP.

[0021] The interposer wiring layer 23 may be a single layer or a multilayer. The interposer wiring layer 23 may include a magnetic field application circuit 23a and a reading unit 23b. The magnetic field application circuit 23a generates a magnetic field to be applied to the loop circuit 17b. By applying a magnetic field to the loop circuit 17b, the quantum circuit 17 can function as a transmitter. The reading unit 23b reads information from the quantum circuit 17.

[0022] The interposer wiring layer 24 is formed on the opposite surface 22 side of the interposer substrate 25, that is, on the +Z-axis direction side of the interposer 20. The interposer wiring layer 24 may contain the superconducting material described above. The interposer wiring layer 24 may contain the same superconducting material as the wiring layer 16 and the interposer wiring layer 23, or may contain a superconducting material different from the wiring layer 16 and the interposer wiring layer 23. Further, the interposer wiring layer 24 may contain a normal conducting material. The normal conducting material is, for example, copper (Cu), silver (Ag), gold (Au), platinum (Pt), and an alloy containing at least any of these. For example, the interposer wiring layer 24 preferably contains Cu and Ti in order from the surface to the interposer substrate 25. For example, when the interposer substrate 25 contains silicon, the opposite surface 22 side of the interposer 20 preferably has a configuration of Cu / Ti / SiO2 / Si (interposer substrate 25).

[0023] The interposer wiring layer 24 may be a single layer or a multilayer. The interposer wiring layer 24 includes a terminal 24a for extracting information from the superconducting chip 10 via the TV26. In FIG. 2, only one terminal 24a is shown, but a plurality of terminals 24a may be formed. In the superconducting device 1 of the present embodiment, the opposite surface 22 can be utilized to the maximum extent for the terminal 24a for extracting information.

[0024] The TV26 penetrates from the mounting surface 21 side of the interposer substrate 25 to the opposite surface 22 side. The interposer wiring layer 23 and the interposer wiring layer 24 are connected by the TV26.

[0025] TV26 may include the superconducting material described above. TV26 may include the same superconducting material as the wiring layer 16 or the like, or may include a superconducting material different from that of the wiring layer 16 or the like. Further, TV26 may include the normal conducting material described above. TV26 may include the same normal conducting material as the interposer wiring layer 24 or may include a normal conducting material different from that of the interposer wiring layer 24. For example, TV26 is formed by forming SiO2 (e.g., a thermal oxide film) on the side wall of a through hole with a diameter of φ50 μm and filling Cu with Ti as an adhesion layer.

[0026] Socket 40 is disposed to face the interposer 20. For example, in the present embodiment, socket 40 is disposed to face the opposite surface 22 of interposer 20. Socket 40 includes a housing 45 and movable pins 47. Note that in FIG. 1, some reference numerals are omitted so as not to complicate the drawing.

[0027] Housing 45 has one end face 41 and the other end face 42 on the side opposite to one end face 41. Further, housing 45 has a side face 43 connecting the periphery of one end face 41 and the periphery of the other end face 42. One end face 41 faces downward, for example, toward the interposer 20 side, and the other end face 42 faces upward. Housing 45 holds movable pins 47. Housing 45 may hold a plurality of movable pins 47.

[0028] Housing 45 preferably includes an insulating material. At least the portion of housing 45 in contact with movable pins 47 includes an insulating material. Further, housing 45 preferably includes a non-magnetic material. Furthermore, housing 45 preferably includes a material having the same coefficient of thermal expansion as that of interposer 20.

[0029] The housing 45 may include a low thermal expansion composite material containing aluminum oxide (Al2O3, also called alumina), mica-based machinable ceramic, aluminum nitride (AlN), zirconia (ZrO2), macor-based machinable ceramic, glass, resin, filler, etc., and may include a superconducting material as long as insulation from the movable pin 47 can be achieved.

[0030] The movable pin 47 is held by the housing 45. The movable pin 47 has one end and the other end on the opposite side of one end. The movable pin 47 extends in the Z-axis direction, one end faces downward, and the other end faces upward. Thus, one end of the movable pin 47 protrudes from one end face 41 of the housing 45. One end of the movable pin 47 is electrically connected to, for example, the terminal 24a of the interposer 20. The other end of the movable pin 47 protrudes from the other end face 42 and is electrically connected to the terminal of the board 50. In this way, the housing 45 has one end face 41 from which one end of the movable pin 47 protrudes and the other end face 42 from which the other end of the movable pin 47 protrudes. In FIG. 1, a space is formed between one end face 41 of the housing 45 and the interposer 20, but the space may not be formed as long as one end of the movable pin 47 can be connected to the terminal 24a. Similarly, a space is formed between the other end face 42 of the housing 45 and the board 50, but the space may not be formed as long as the other end of the movable pin 47 can be connected to the terminal of the board 50.

[0031] One end and the other end of the movable pin 47 are connected in a conductive state with elastic means such as a coil spring or a leaf spring interposed therebetween. The movable pin 47 may include a superconducting material or a normal conducting material. The movable pin 47 may include the same superconducting material as the wiring layer 16 or the like, or a different superconducting material from the wiring layer 16 or the like. Also, the movable pin 47 may include the same normal conducting material as the interposer wiring layer 24 or a different normal conducting material from the interposer wiring layer 24. The movable pin 47 is preferably a non-magnetic material. The movable pin 47 preferably contains, for example, a palladium alloy, a gold alloy, beryllium copper (BeCu), phosphor bronze, gold (plated finish), niobium (Nb), niobium titanium (Nb-Ti), titanium (Ti).

[0032] Socket 40 may have a positioning pin 48. The positioning pin 48 is a pin that determines the placement position of the socket 40. The positioning pin 48 is held by the housing 45. The positioning pin 48 has, for example, one end protruding from one end face 41. The placement position of the socket 40 is determined by connecting one end of the positioning pin 48 to a predetermined position on the opposite face 22 of the interposer 20. Note that a hole may be formed in the opposite face 22 of the interposer 20, and the placement position of the socket 40 may be determined by inserting the positioning pin 48 into the hole. Thereby, displacement of the socket 40 can be suppressed.

[0033] The board 50 is disposed opposite to the other end face 42 of the socket 40. The board 50 includes a connector 51, via holes 52, a board substrate 55, and terminals. The board substrate 55 is, for example, plate-shaped and has an upper surface and a lower surface. The board substrate 55 may have a single-layer structure or a multilayer structure. The lower surface of the board substrate 55 faces the socket 40. Terminals are provided on the lower surface of the board substrate 55. A connector 51 for external input / output is formed on the upper surface of the board substrate 55. The connector 51 of the board 50 is connected to the terminals of the board 50. The other end of the movable pin 47 is in electrical contact with the terminals of the board 50. Note that a plurality of terminals formed on the lower surface of the board 50 may be connected to each other. In this case, it is connected to the connector 51 of the board 50 via the terminals formed on the mounting surface 21 of the interposer 20, one end of the movable pin 47, the other end of the movable pin 47, the terminals formed on the lower surface of the board 50, and the terminals formed on the upper surface of the board 50 in this order. Note that the terminals formed on the lower surface of the board 50 and the terminals formed on the upper surface (connector 51 side) of the board 50 are in electrical contact.

[0034] Figure 3 is an enlarged cross-sectional view of the connection portion between the movable pin 47 and the via hole 52. As shown in Figure 3, a via hole 52 is formed inside the board substrate 55. Also, a plating layer 53 of copper or gold is formed on the inner wall of the via hole 52 by plating. The thickness of the plating layer 53 is, for example, 0.01 - 0.02 mm (10 - 20 μm). In this embodiment, the hole diameter R of the via hole 52 refers to the portion obtained by excluding the thickness of the plating layer 53 from the hole diameter of the via hole itself. As shown in Figure 3, the tip portion of the movable pin 47 contacts the outer edge of the terminal of the via hole 52, and the terminal on the socket 40 side of the via hole 52 is electrically connected to the terminal on the other end side of the movable pin 47. The hole diameter R of the via hole 52 is slightly smaller than the diameter L of the tip portion of the other end of the movable pin 47, for example, Φ0.1 mm or less. Specifically, the hole diameter R of the via hole 52 is 10 - 50% smaller than the diameter L of the tip portion of the other end of the movable pin 47. Also, as shown in Figure 3, the through hole of the housing 45 is slightly larger than the diameter of the movable pin 47, and there is a slight gap (between the socket 40 and the movable pin 47) around the movable pin 47.

[0035] The board 50 on which the connector 51 for external input and external output is formed performs input and output of power supply, signals, etc. with the superconducting chip 10 via the socket 40 and the interposer 20.

[0036] Next, the effects of this embodiment will be described. In the superconducting device 1 of this embodiment, the hole diameter R of the via hole 52 formed in the board substrate 55 is slightly smaller than the diameter L of the tip portion of the other end of the movable pin 47. Therefore, the other end of the movable pin 47 is fitted into the recess of the via hole 52. As a result, even if the movable pin 47 moves due to the volume change based on the difference in the thermal expansion coefficients of the board substrate 55 and the socket 40 that occurs when the superconducting device 1 is cooled to an extremely low temperature, the other end of the movable pin 47 can maintain the state of being fitted into the recess of the via hole 52. Therefore, the connection to the terminal of the via hole 52 can be maintained. Thus, disconnection can be more effectively prevented. Further, if the hole diameter R of the via hole 52 is slightly smaller than the diameter L of the tip portion of the other end of the movable pin 47, the movable pin 47 does not fall into the via hole 52, and an electrically good connection state between the tip portion of the movable pin 47 and the terminal of the via hole 52 can be maintained. Also, the through hole of the housing 45 is slightly larger than the diameter of the movable pin 47, and there is a slight gap around the movable pin 47. As a result, the movable pin 47 fitted into the recess of the via hole 52 can follow corresponding to the difference in thermal contraction.

[0037] Also, by providing the positioning pin 48, the arrangement position of the socket 40 can be easily determined. Further, by inserting the positioning pin 48 into the hole on the opposite surface 22, the displacement of the socket 40 can be suppressed.

[0038] Next, a modification of Embodiment 1 will be described. FIG. 4 is a cross-sectional view showing a modification of the via hole of Embodiment 1. As shown in FIG. 4, the board substrate 55 has a multilayer structure. The via hole of the present invention is not limited to the via hole shown in Embodiment 1 as long as the other end of the movable pin 47 fits into the depression of the via hole 52. In the via hole described in Embodiment 1, a plating layer 53 of copper or gold was formed on the inner wall surface of the via hole as in the via hole 52 of FIG. 4, but in the via hole 52a, the inside of the via hole is filled with a metal such as copper or gold. Further, in the via hole 52b, the plating layer extends horizontally between the layers, and the positions of the via holes are different on the upper and lower surfaces of the board substrate 55. Also, the inside of the via hole is filled with a metal. Note that the modified examples of the via holes shown in FIG. 4 are examples of the via holes of the present invention, and the via holes of the present invention are not limited thereto. For example, if there is a depression or the like on the surface of the board substrate 55 and it is recessed, the inside may or may not be filled with a metal. (Embodiment 2) Next, a superconducting device according to Embodiment 2 will be described. FIG. 5 is a cross-sectional view illustrating a superconducting device according to Embodiment 2. As shown in FIG. 5, a board wiring layer 54 electrically connected to the via hole 52 is provided on the upper surface of the board substrate 55 (the surface opposite to the surface facing the socket 40).

[0039] The board 50 is disposed to face the other end surface 42 of the socket 40 in the same manner as in the foregoing embodiments. And, a board wiring layer 54 electrically connected to the plating layer 53 of the via hole 52 is provided on the upper surface of the board substrate 55. The board wiring layer 54 is electrically connected to the connector 51. The board wiring layer 54 preferably contains a non-magnetic material, for example, copper or gold. In this case, it is connected from the terminals formed on the mounting surface 21 of the interposer 20 to the connector 51 via one end of the movable pin 47a, the other end of the movable pin 47a, the plating layer 53 of the via hole 52, and the board wiring layer 54. Therefore, the connector 51 performs input / output of power supply, signals, etc. with the superconducting chip 10 via the board 50, the socket 40, and the interposer 20.

[0040] Next, the effects of this embodiment will be described. In the superconducting device 2 of this embodiment, a board wiring layer 54 electrically connected to the via hole 52 is provided on the upper surface of the board substrate 55. According to this configuration, since the upper surface of the board substrate 55 is a space, it is easy to match the impedance. Therefore, compared with the case of wiring on the lower surface (socket 40 side) of the board substrate 55, transmission loss due to impedance mismatch can be suppressed. Further, by providing the board wiring layer 54 on the upper surface of the board substrate 55, the contact area between the sample stage 30 described later and the lower surface of the board 50 can be increased.

[0041] (Modification example) Next, a modification example of the superconducting device according to Embodiment 2 will be described. In the superconducting device 2a according to the modification example of Embodiment 2, the board substrate 55 has a multilayer structure including a plurality of insulating layers and a plurality of conductor layers, and a wiring layer is formed inside the board substrate 55. Specifically, the board wiring layer 54 is formed on at least a part of a plurality of conductor layers excluding the surface of the board substrate 55 facing the movable pin 47. For example, as shown in FIG. 6, a board wiring layer 54 is provided inside the board substrate 55. The board wiring layer 54 is disposed between layers in the multilayer board substrate 55 and extends in a direction (Y-axis direction) orthogonal to the direction (Z-axis direction) in which the via hole 52 extends. Both ends of the board wiring layer 54 are respectively connected to the connector 51 of the board 50. In this case, it is connected to the connector 51 of the board 50 via the terminal formed on the mounting surface 21 of the interposer 20, one end of the movable pin 47, the other end of the movable pin 47, the terminal formed on the lower surface of the board 50, and the board wiring layer 54 in this order.

[0042] In the superconducting device 2a, the board wiring layer 54 is provided inside the board substrate 55. Thereby, regardless of the installation state of the socket 40, it is possible to perform wiring design only with the board substrate 55, and it is possible to more easily match the impedance. (Embodiment 3) Next, a superconducting device according to Embodiment 3 will be described. FIG. 7 is a cross-sectional view of a modified example of the superconducting device according to Embodiment 3. As shown in FIG. 7, at least a part of the interposer 20 and at least a part of the board 50 according to Embodiment 3 are each in contact with a sample stage 30 having a cooling function. Further, in the superconducting device 3, the side surface 43 of the housing 45 is disposed with a space therebetween from the sample stage 30 having a cooling function.

[0043] The sample stage 30 has a cooling function. For example, the sample stage 30 is a cold stage that can be cooled to an extremely low temperature of about 10 [mK] by a refrigerator. The sample stage 30 preferably contains a metal such as Cu, a Cu alloy, or Al, for example. In the case of the sample stage 30 containing Al, insulation treatment by anodizing may be performed. The superconducting device 2 of the present embodiment uses, for example, a superconducting phenomenon at an extremely low temperature of 9.2 [K] or less when containing Nb and 1.2 [K] or less when containing Al as the superconducting material of the superconducting chip 10. For this reason, such a sample stage 30 that can be cooled to such an extremely low temperature is used.

[0044] A recess 31 is formed in the sample stage 30. When the superconducting chip 10 is viewed through the interposer 20 from above, it is smaller than the recess 31. On the other hand, when viewed from above, the interposer 20 is larger than the recess 31. The superconducting chip 10 is disposed inside the recess 31 formed in the sample stage 30 having a cooling function, and the second surface 12 of the superconducting chip 10 is not in contact with the sample stage 30. Further, a part of the mounting surface 21 on which the superconducting chip 10 of the interposer 20 is mounted is in contact with the upper surface of the sample stage 30, and the opposite surface 22 of the interposer 20 is not in contact with the sample stage 30.

[0045] The portion of the mounting surface 21 of the interposer 20 that is in contact with the sample stage 30 may not have the interposer wiring layer 23 formed thereon. Also, an insulating film may be formed on the portion of the mounting surface 21 that is in contact with the sample stage 30 to prevent electrical conduction with the sample stage 30, in which case the interposer wiring layer 23 may be formed. To improve the heat insulation property for reducing the temperature change around the superconducting chip, it is preferable to make the area around the superconducting chip 10 in a vacuum state or a reduced-pressure atmosphere.

[0046] Next, the effects of this embodiment will be described. In the superconducting device 2 of this embodiment, at least a part of the interposer 20 and at least a part of the board 50 are brought into contact with the sample stage 30. Thereby, by using the interposer 20 and the board 50 as heat flow paths, the quantum circuit 17 in the superconducting chip 10 can be cooled to an extremely low temperature, and the superconducting phenomenon can be utilized.

[0047] Also, since the opposite surface 22 of the interposer 20 is not in contact with the sample stage 30, the opposite surface 22 of the interposer 20 can be maximally used as the terminal 24a for extracting information from the superconducting chip 10. Therefore, the number of information extraction terminals can be increased.

[0048] Also, the superconducting chip 10 is disposed inside the sample stage 30 having a cooling function and is not in contact with the sample stage 30. That is, the second surface 12 of the superconducting chip 10 is disposed with a space therebetween from the inner surface of the recess 31 of the sample stage 30. By adopting such a configuration, the stress and strain due to the shrinkage difference between the superconducting chip 10 and the sample stage 30 caused by the temperature change to an extremely low temperature can be suppressed. Other configurations and effects are included in the descriptions of Embodiments 1 and 2. (Modification 1) Next, a modified example of the superconducting device according to Embodiment 3 will be described. FIG. 8 is a cross-sectional view of the superconducting device according to the modified example of Embodiment 3. As shown in FIG. 8, in the superconducting device 3a, a part of the lower surface of the board 50 is in contact with the sample stage 30 having a cooling function. Also, in the superconducting device 3a, the side surface 43 of the housing 45 is in contact with the sample stage 30 having a cooling function. The sample stage 30 includes, for example, a plate-like portion 30a. The plate-like portion 30a sandwiches the side surface 43 of the housing 45. Note that, in the superconducting device 2, not only the side surface 43 of the housing 45 but also a part of one end surface 41 of the housing 45 may be in contact with the sample stage 30, or a part of the other end surface 42 of the housing 45 may be in contact with the sample stage 30.

[0049] In the superconducting device 3a of the present embodiment, at least a part of the lower surface of the board 50 and the side surface 43 of the housing 45 are brought into contact with the sample stage 30. Thereby, by using the board 50 as a heat flow path, the quantum circuit 17 in the superconducting chip 10 can be cooled to an extremely low temperature, and the superconducting phenomenon can be utilized. (Modified Example 2) Next, another modified example of the superconducting device according to Embodiment 3 will be described. In the superconducting device 3b according to another modified example of Embodiment 3, at least a part of the superconducting chip 10, at least a part of the interposer 20, at least a part of the socket 40, and at least a part of the board 50 are each in contact with the sample stage 30 having a cooling function. FIG. 9 is a cross-sectional view of the superconducting device according to another modified example of Embodiment 3.

[0050] As shown in FIG. 9, in the superconducting device 3b, at least a part of the superconducting chip 10, at least a part of the interposer 20, at least a part of the socket 40, and at least a part of the board 50 are in contact with the sample stage 30. Specifically, for example, the superconducting chip 10, the interposer 20, and the socket 40 are disposed inside the recess 31 of the sample stage 30. Then, the second surface 12 of the superconducting chip 10, the side surface of the interposer 20, and the side surface 43 of the socket 40 are in contact with the inner surface of the recess 31 of the sample stage 30, and the lower surface of the board 50 is in contact with the plate-like portion 30a of the sample stage 30. Further, at least one of a part of the mounting surface 21 and the opposite surface 22 of the interposer 20 and a part of one end surface 41 and the other end surface 42 of the socket 40 may be in contact.

[0051] When the superconducting chip 10 is viewed through the interposer 20 from above, it is smaller than the recess 31. On the other hand, when the interposer 20 is viewed from above, it is larger than the recess 31. The superconducting chip 10 is disposed inside the recess 31 formed in the sample stage 30 having a cooling function. On the other hand, a part of the mounting surface 21 of the interposer 20 on which the superconducting chip 10 is mounted is in contact with the upper surface of the sample stage 30.

[0052] In the superconducting device 3b, since a part of each of the superconducting chip 10, the interposer 20, the socket 40, and the board 50 is in contact with the sample stage 30, the cooling performance of the superconducting device 3 can be improved.

[0053] Further, the superconducting chip 10 is disposed inside the sample stage 30 having a cooling function. Also, the second surface 12 of the superconducting chip 10 is in contact with the inner surface of the recess 31 of the sample stage 30. Note that at least a part of the second surface 12 may be in contact with the inner surface of the recess 31. With such a configuration, the superconducting chip 10 can be cooled by the heat conduction of the sample stage 30 from the second surface 12 side, and the cooling performance can be improved. Therefore, the quantum circuit 17 in the superconducting chip 10 can operate stably.

[0054] The present invention has been described with reference to the embodiments above. However, the present invention is not limited to the above embodiments and can be appropriately modified without departing from the spirit thereof. For example, those in which a plurality of superconducting chips 10 are connected to the interposer 20 and those in which a plurality of interposers 20 are connected to the socket 40 are also included in the scope of the technical idea of this embodiment.

Description of Reference Numerals

[0055] 1, 2, 2a, 3, 3a, 3b Superconducting device 10 Superconducting chip 11 First surface 12 Second surface 15 Chip substrate 16 Wiring layer 17 Quantum circuit 17a Josephson junction 17b Loop circuit 17c Resonator 20 Interposer 21 Mounting surface 22 Opposite surface 23 Interposer wiring layer 23a Magnetic field application circuit 23b Reading section 24 Interposer wiring layer 24a Terminal 25 Interposer substrate 26 TV 30 Sample stage 30a Plate-like portion 31 Recess 40 Socket 41 One end face 42 The other end face 43 Side face 45 Housing 47 Movable pin 48 Positioning pin 50 Board 51 Connector 52 Via hole 53 Plating layer 54 Board wiring layer 55 Board substrate BP Bump

Claims

1. A superconducting chip, an interposer on which the superconducting chip is mounted, a socket disposed opposite to the interposer, the socket including movable pins, positioning pins, and a housing that supports the movable pins and the positioning pins, a board disposed opposite to the socket and having a connector formed thereon for external input / output, wherein the board has via holes formed therein, one end of a terminal of each via hole is electrically connected to one end of a terminal of the movable pin, and a hole diameter of the via hole is smaller than a diameter of a tip portion of the movable pin connected to the via hole, the positioning pins are provided side by side with the movable pins, one end of each positioning pin protrudes from one end surface of the socket and is connected to the interposer, a superconducting device.

2. The board includes a wiring layer connected to the via holes, and the wiring layer is electrically connected to the connector, The superconducting device according to claim 1.

3. The superconducting device according to claim 2, wherein the wiring layer is disposed on a surface opposite to a surface facing the socket.

4. The superconducting device according to claim 2, wherein the board has a multilayer structure including a plurality of insulating layers and a plurality of conductor layers, and the wiring layer is formed inside the board.

5. At least a part of the superconducting chip, the interposer, the socket, and the board is in contact with a sample stage having a cooling function, The superconducting device according to any one of claims 1 to 4.

6. The superconducting chip is disposed inside a recess formed in a sample stage having a cooling function, a part of the interposer is in contact with the sample stage, The superconducting device according to claim 5.

7. The superconducting chip has a first surface mounted on the interposer and a second surface opposite to the first surface, at least a part of the second surface is in contact with an inner surface of the recess, The superconducting device according to claim 6.

8. The housing has one end surface from which one end of the movable pin protrudes, another end surface from which the other end of the movable pin protrudes, and a side surface connecting a periphery of the one end surface and a periphery of the other end surface, at least a part of the one end surface, the other end surface, and the side surface is in contact with a sample stage having a cooling function, The superconducting device according to any one of claims 1 to 7.

9. The via holes are filled with metal inside, One end of the terminal of the via hole is formed with a depression, and the depression is electrically connected to one end of the terminal of the movable pin. The superconducting device according to any one of claims 1 to 8.

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