Interposer, semiconductor package, and method of manufacturing an interposer

Abstract

To provide an interposer, a semiconductor package and a method of manufacturing the interposer.SOLUTION: An interposer for semiconductor package includes: an interposer substrate 110 which has a first principal surface 110A and a second principal surface 110B on the opposite side from the first principal surface 110A; a first through electrode structure 131 and a second through electrode structure 133 which penetrate the interposer substrate 110 to protrude on the first principal surface 110A respectively; a connection terminal structure 140 which comes into contact with both the first through electrode structure 131 and the second through electrode structure 133; and a photosensitive polymer layer 160 which is arranged between the connection terminal structure 140 and the interposer substrate 110 between the first through electrode structure 131 and the second through electrode structure 133.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an interposer, a semiconductor package, and a method for manufacturing an interposer. More specifically, the present invention relates to an interposer, a semiconductor package, and a method for manufacturing an interposer that can significantly simplify the manufacturing process and greatly reduce the manufacturing cost.

Background Art

[0002] Due to the increasing requirements for miniaturization and high speed, various packaging technologies have been tried and applied to semiconductor chips. In particular, the interposer of the 2.5D package has caused complex and expensive manufacturing. Therefore, it is required to simplify the manufacturing and reduce the manufacturing cost.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The first technical problem to be solved by the present invention is to provide an interposer that can significantly simplify the manufacturing process and greatly reduce the manufacturing cost.

[0004] The second technical problem to be solved by the present invention is to provide a semiconductor package that can significantly simplify the manufacturing process and greatly reduce the manufacturing cost.

[0005] The third technical problem to be solved by the present invention is to provide a method for manufacturing an interposer that can significantly simplify the manufacturing process and greatly reduce the manufacturing cost.

Means for Solving the Problems

[0006] In order to solve the first technical problem, the present invention provides an interposer for a semiconductor package, which includes an interposer substrate having a first main surface and a second main surface opposite to the first main surface, a first through electrode structure and a second through electrode structure that penetrate the interposer substrate and protrude on the first main surface respectively, a connection terminal structure that contacts both the first through electrode structure and the second through electrode structure, and a photosensitive polymer layer disposed between the connection terminal structure and the interposer substrate between the first through electrode structure and the second through electrode structure.

[0007] In order to solve the second technical problem, the present invention provides a semiconductor package, which includes a package substrate, an interposer disposed on the package substrate, and a first semiconductor device and a second semiconductor device that are respectively disposed so as to at least partially overlap with the interposer. The interposer includes an interposer substrate having a first main surface facing the package substrate and a second main surface opposite to the first main surface, a first through electrode structure and a second through electrode structure that penetrate the interposer substrate and protrude on the first main surface respectively, a passivation layer covering the side surfaces of the protruding portions of the first through electrode structure and the second through electrode structure and the first main surface, a photosensitive polymer layer provided on the passivation layer between the first through electrode structure and the second through electrode structure, and a connection terminal structure that contacts both the first through electrode structure and the second through electrode structure.

[0008] Another aspect of the present invention provides a semiconductor package including a package substrate, an interposer disposed on the package substrate, and a first semiconductor device and a second semiconductor device each disposed so as to at least partially overlap the interposer. The package substrate includes a base layer, an upper connection pad provided on an upper surface of the base layer, and a lower connection pad provided on a lower surface of the base layer. The interposer includes an interposer substrate having a first main surface facing the package substrate and a second main surface opposite to the first main surface, a first through electrode structure and a second through electrode structure each protruding on the first main surface through the interposer substrate, a passivation layer covering side surfaces of protruding portions of the first through electrode structure and the second through electrode structure and the first main surface, a photosensitive polymer layer provided on the passivation layer between the first through electrode structure and the second through electrode structure, and a connection terminal structure in contact with both the first through electrode structure and the second through electrode structure and connected to the upper connection pad of the package substrate. The first semiconductor device is a memory device in which a plurality of memory chips are stacked, and the second semiconductor device is a memory controller configured to control the memory device.

[0009] In order to solve the third technical problem, the present invention provides a method for manufacturing an interposer for a semiconductor package, including the steps of: forming a first through - electrode structure and a second through - electrode structure protruding on a first main surface of an interposer substrate having a first main surface and a second main surface opposite to the first main surface; forming a passivation layer so as to cover the exposed portions of the first through - electrode structure and the second through - electrode structure and the first main surface; forming a photosensitive polymer layer on the passivation layer; partially and simultaneously removing the passivation layer and the photosensitive polymer layer so that the conductor plug portions of the first through - electrode structure and the second through - electrode structure are exposed; and forming a connection terminal structure in contact with the conductor plug portion of the first through - electrode structure, the conductor plug portion of the second through - electrode structure, and the remaining photosensitive polymer layer between the first through - electrode structure and the second through - electrode structure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the same components in the drawings, the same reference numerals are used, and redundant descriptions thereof are omitted.

[0012] FIG. 1 is a perspective view showing an interposer 100 according to an embodiment of the present invention. FIG. 2 is a side view showing a cross section of the interposer 100 in FIG. 1 cut along the line II-II'.

[0013] Referring to FIGS. 1 and 2, the interposer 100 includes an interposer substrate 110 having a first main surface 110A and a second main surface 110B which is the opposite surface of the first main surface 110A.

[0014] The interposer substrate 110 can be made of a semiconductor material or an insulating material. In some embodiments, the interposer substrate 110 may include silicon, germanium, silicon germanium, gallium arsenide (GaAs), glass, ceramic, etc. The first main surface 110A and the second main surface 110B can be parallel to each other. The first main surface 110A and the second main surface 110B can be two opposite main surfaces of the interposer substrate 110.

[0015] The interposer 100 may include a number of through electrode structures 131, 133 penetrating the interposer substrate 110. The first through electrode structure 131 and the second through electrode structure 133 are connected to a common connection terminal structure 140. In some embodiments, the first through electrode structure 131 and the second through electrode structure 133 form redundancy vias, and even if a defect occurs in any one of the first through electrode structure 131 and the second through electrode structure 133, the entire interposer 100 is configured to be prevented from becoming defective by the operation of the other one.

[0016] The connection terminal structure 140 is provided for electrical connection with an external device, such as a printed circuit board, and is provided on the first main surface 110A. The connection terminal structure 140 may be a solder ball.

[0017] Each of the plurality of through - electrode structures 131, 133 is electrically connected to the connection pad 120 on the second main surface 110B so that other semiconductor devices can be mounted on the second main surface 110B. In FIG. 1, the first region R1, which is the region where the first semiconductor device is mounted, and the second region R2, which is the region where the second semiconductor device is mounted, are shown by virtual lines. However, an ordinary technician will understand that there may be more than two such mounting regions and they can be arranged in various ways.

[0018] FIG. 3 is a partially enlarged view that extracts and enlarges the portion shown at III in FIG. 2.

[0019] Referring to FIGS. 2 and 3, the first through - electrode structure 131 and the second through - electrode structure 133 each penetrate the first main surface 110A of the interposer substrate 110 and protrude onto the first main surface 110A. In FIG. 2, for the sake of illustration, the specific shapes in which the first through - electrode structure 131 and the second through - electrode structure 133 protrude onto the first main surface 110A are not shown.

[0020] The first through - electrode structure 131 may be disposed within the first via - hole 131h and may include a first core conductor 131a, a first barrier film 131b, and a first via dielectric film 131d. The second through - electrode structure 133 may be disposed within the second via - hole 133h and may include a second core conductor 133a, a second barrier film 133b, and a second via dielectric film 133d.

[0021] Each of the first core conductor 131a and the second core conductor 133a may include, for example, one or more of aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tin (Sn), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr).

[0022] The first barrier film 131b and the second barrier film 133b are in contact with the side walls of the first core conductor 131a and the second core conductor 133a, and surround the first core conductor 131a and the second core conductor 133a laterally. The first barrier film 131b and the second barrier film 133b are composed of a conductive layer having a relatively low wiring resistance. For example, the first barrier film 131b and the second barrier film 133b are composed of a single film or a multilayer film including at least one selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. For example, the first barrier film 131b and the second barrier film 133b may be composed of a multilayer film of TaN / W, TiN / W, or WN / W. In some embodiments, the first barrier film 131b and the second barrier film 133b each have a thickness of about 50 Å to about 1000 Å.

[0023] In some embodiments, the first barrier film 131b and the second barrier film 133b each have a substantially uniform thickness along the longitudinal direction of the first through - electrode structure 131 and the second through - electrode structure 133, respectively. In some embodiments, the first barrier film 131b and the second barrier film 133b can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0024] The first via dielectric film 131d and the second via dielectric film 133d serve to electrically insulate the first core conductor 131a and the second core conductor 133a from the interposer substrate 110. The first via dielectric film 131d and the second via dielectric film 133d can be made of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. In some embodiments, the first via dielectric film 131d and the second via dielectric film 133d can be formed by a CVD process. In some embodiments, the first via dielectric film 131d and the second via dielectric film 133d can have a thickness of about 500 Å to about 2500 Å.

[0025] The first through - electrode structure 131 and the second through - electrode structure 133 extend through the first main surface 110A by a predetermined length. The first through - electrode structure 131 and the second through - electrode structure 133 protrude through the first main surface 110A by a length of several μm to several tens of μm, for example, about 3 μm to about 20 μm.

[0026] The passivation layer 150 can cover the first main surface 110A. Also, the passivation layer 150 can laterally surround the portions where the first through - electrode structure 131 and the second through - electrode structure 133 protrude through the first main surface 110A.

[0027] The passivation layer 150 may include a first passivation layer 151 and a second passivation layer 153. The first passivation layer 151 and the second passivation layer 153 can each independently be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In some embodiments, the first passivation layer 151 can be a silicon oxide film, and the second passivation layer 153 can be a silicon nitride film or a silicon oxynitride film. Specifically, the first passivation layer 151 can be a TEOS (tetraethylorthosilicate) film, an HDP (high density plasma) oxide film, a BPSG (boro - phospho - silicate glass) oxide film, an FCVD (flowable chemical vapor The first passivation layer is an oxide film, and the second passivation layer 153 can be silicon nitride or silicon oxynitride.

[0028] The first passivation layer 151 has a thickness of about 1.0 μm to about 3.0 μm, about 1.2 μm to about 2.5 μm, about 1.4 μm to about 2.2 μm, about 1.5 μm to about 2.1 μm, or about 1.6 μm to about 2.0 μm. Also, the first passivation layer 151 has a Young's modulus of about 60 GPa to about 80 GPa, about 65 GPa to about 75 GPa, or about 68 GPa to about 72 GPa.

[0029] The second passivation layer 153 has a thickness of about 0.35 μm to about 0.75 μm, about 0.40 μm to about 0.70 μm, about 0.45 μm to about 0.65 μm, about 0.48 μm to about 0.62 μm, or about 0.50 μm to about 0.60 μm. Also, the second passivation layer 153 has a Young's modulus of about 100 GPa to about 160 GPa, about 120 GPa to about 140 GPa, or about 125 GPa to about 135 GPa.

[0030] The first passivation layer 151 is formed to contact the first main surface 110A. Also, the first passivation layer 151 can contact the side surface of the first through - electrode structure 131 and cover the side surface. The second passivation layer 153 extends horizontally along the first main surface 110A with the first passivation layer 151 interposed therebetween. Also, the second passivation layer 153 extends vertically along the protruding portion of the first through - electrode structure 131 with the first passivation layer 151 interposed therebetween.

[0031] The upper ends of the first passivation layer 151 and the second passivation layer 153 surrounding the side surface of the first through electrode structure 131 can form the first upper surface 156p_1. Also, the upper ends of the first passivation layer 151 and the second passivation layer 153 surrounding the side surface of the second through electrode structure 133 can form the second upper surface 156p_2. In some embodiments, the upper surface of the first through electrode structure 131 can be located substantially on the same plane as the first upper surface 156p_1. In some embodiments, the upper surface of the second through electrode structure 133 can be located substantially on the same plane as the second upper surface 156p_2.

[0032] A photosensitive polymer layer 160 is provided on the passivation layer 150. The photosensitive polymer layer 160 may include, for example, a photoimageable dielectric (PID) material as a material applicable to a photolithography process. The PID material may include, for example, a polyimide-based photosensitive polymer, a novolak-based photosensitive polymer, polybenzoxazole, a silicone-based polymer, an acrylate-based polymer, or an epoxy-based polymer.

[0033] The photosensitive polymer layer 160 can fill the space between the two passivation layers 150 that laterally surround the first through electrode structure 131 and the second through electrode structure 133 protruding and extending on the first main surface 110A. That is, the photosensitive polymer layer 160 is disposed between the passivation layer that laterally surrounds the first through electrode structure 131 and the passivation layer that laterally surrounds the second through electrode structure 133.

[0034] In some embodiments, the upper surface of the photosensitive polymer layer 160 can be located substantially on the same plane as the upper surfaces of the first through electrode structure 131 and the second through electrode structure 133. In some embodiments, the upper surface of the photosensitive polymer layer 160 can be located substantially on the same plane as the first upper surface 156p_1 and the second upper surface 156p_2.

[0035] The connection terminal structure 140 is in contact with and electrically connected to the first through electrode structure 131 and the second through electrode structure 133. The connection terminal structure 140 includes a seed metal layer 145 that is in direct contact with both the first through electrode structure 131 and the second through electrode structure 133, a first conductor layer 141 formed on the seed metal layer 145, and a solder metal layer 143 provided on the first conductor layer 141.

[0036] The seed metal layer 145 may be made of, for example, titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or an alloy thereof. The seed metal layer 145 is formed by a physical vapor deposition (PVD) method such as sputtering, for example. The seed metal layer 145 may have a thickness of, for example, about 1 μm to about 20 μm, about 3 μm to about 15 μm, or about 4 μm to about 10 μm.

[0037] The first conductor layer 141 formed on the seed metal layer 145 may be, for example, a metal such as copper (Cu), tungsten (W), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), an alloy thereof, or a metal nitride, but is not limited thereto. The first conductor layer 141 may have a thickness of about 10 μm to about 100 μm, about 15 μm to about 80 μm, or about 20 μm to about 60 μm.

[0038] On the first conductor layer 141, a solder metal layer 143 is provided. The solder metal layer 143 can be, for example, an alloy mainly composed of tin (Sn) and containing silver (Ag), copper (Cu), palladium (Pd), aluminum (Al), and silicon (Si). Here, the "main component" means that the component exceeds 50% in the weight of the entire alloy.

[0039] The lower surface of the seed metal layer 145 can contact the upper surface of the photosensitive polymer layer 160. In particular, the seed metal layer 145 can contact the portion of the photosensitive polymer layer 160 located between the first through - electrode structure 131 and the second through - electrode structure 133 that contacts the seed metal layer 145. That is, the lower surface of the seed metal layer 145 can be located substantially on the same plane as the upper surface of the portion of the photosensitive polymer layer 160 disposed therebelow.

[0040] In some embodiments, an alignment key 170 is further provided adjacent to the first through - electrode structure 131. The alignment key 170 has a recessed form that penetrates the photosensitive polymer layer 160. In some embodiments, the alignment key 170 has a groove form that penetrates the photosensitive polymer layer 160 and extends a predetermined length in a direction parallel to the first main surface 110A.

[0041] In some embodiments, the alignment key 170 is configured to penetrate the photosensitive polymer layer 160 and at least partially penetrate the passivation layer 150. In some embodiments, the alignment key 170 may completely penetrate the passivation layer 150 such that the first main surface 110A is exposed.

[0042] FIG. 4 is a partial detailed view showing an enlarged view of the portion indicated by IV in FIG. 3.

[0043] Referring to FIG. 4, the side wall 170sw of the alignment key 170 can be inclined while making an acute angle with respect to the first main surface 110A. The angle α formed by the side wall 170sw and the first main surface 110A can be about 80° to about 88°, or about 83° to about 87°. In some embodiments, the side wall 170sw can be formed by anisotropic etching as described below. Since the traveling directions of some ions and plasmas used in the anisotropic etching are not perpendicular to the first main surface 110A, the inclination of the side wall 170sw is not completely perpendicular to the first main surface 110A.

[0044] Also, the side wall 170sw may not be a complete plane and may be partially curved. In some embodiments, the side wall 170sw is generally planar at the portion corresponding to the photosensitive polymer layer 160, but is a different plane or a curved surface at the portion corresponding to the passivation layer 150. In that case, the angle can be defined by the angle formed by the extension line of the portion corresponding to the photosensitive polymer layer 160 and the first main surface 110A.

[0045] The upper surface 160u of the photosensitive polymer layer 160 is not completely parallel to the first main surface 110A. In some embodiments, the vertical thickness t of the photosensitive polymer layer 160 between the connection terminal structure 140 and the alignment key 170 can decrease as it approaches the alignment key 170.

[0046] Referring to FIG. 3 again, connection pads 120 are provided at the ends on the second main surface 110B side of the first through electrode structure 131 and the second through electrode structure 133. The connection pads 120 are made of aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), cobalt (Co), tungsten (W), zinc (Zn), or alloys thereof.

[0047] In FIG. 1, the planar shape of the connection pad 120 is shown as a circle, but the planar shape of the connection pad 120 may be any polygon such as a square or a rectangle, an ellipse, etc., and is not particularly limited.

[0048] FIG. 5 and FIG. 6 are partial enlarged views respectively showing and enlarging the part shown by III in FIG. 2 in an interposer according to another embodiment of the present invention.

[0049] The embodiment of FIG. 5 is the same as the embodiment of FIG. 3, except that the first conductor layer 141a is of a pillar type. Therefore, the embodiment of FIG. 5 will be described below mainly focusing on such differences.

[0050] Referring to FIG. 5, the pillar-type first conductor layer 141a has a greater dimension in the vertical direction as compared with the first conductor layer 141 shown in FIG. 3. Further, the first conductor layer 141a may be made of, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), cobalt (Co), tungsten (W), zinc (Zn), or an alloy thereof, and particularly may be copper (Cu).

[0051] The embodiment of FIG. 6 is equal to the embodiment of FIG. 3, except that the passivation layer 150 is omitted. Therefore, the embodiment of FIG. 6 will be described below mainly focusing on such differences.

[0052] Referring to FIG. 6, since the passivation layer 150 is omitted, the photosensitive polymer layer 160 can be in direct contact with the first main surface 110A of the interposer substrate 110. Further, the photosensitive polymer layer 160 can be in direct contact with the side walls of the first through electrode structure 131 and the second through electrode structure 133 protruding on the first main surface 110A.

[0053] The alignment key 170 can be formed in the photosensitive polymer layer 160 adjacent to the first through electrode structure 131 and / or the second through electrode structure 133. At this time, the alignment key 170 does not penetrate the photosensitive polymer layer 160. In some embodiments, the alignment key 170 penetrates the photosensitive polymer layer 160, and in that case, a part of the first main surface 110A can be exposed by the alignment key 170.

[0054] In one embodiment, the upper surface of the first through - electrode structure 131 is located substantially on the same plane as the upper surface of the photosensitive polymer layer 160. Also, the upper surface of the second through - electrode structure 133 is located substantially on the same plane as the upper surface of the photosensitive polymer layer 160.

[0055] FIG. 7 is a partial enlarged view showing an enlarged excerpt of the portion indicated by III in FIG. 2 in an interposer according to still another embodiment of the present invention.

[0056] The embodiment of FIG. 7 is the same as the embodiment of FIG. 3, except that it further includes a rewiring layer 120RDL. Therefore, hereinafter, the embodiment of FIG. 7 will be described centering on such differences.

[0057] Referring to FIG. 7, a rewiring layer 120RDL is further provided on the connection pad 120. The rewiring layer 120RDL may include contact plugs 122_V1, 122_V2 and metal horizontal wirings 122_L1, 122_L2. The contact plugs 122_V1, 122_V2 can electrically connect the vertically adjacent metal horizontal wirings 122_L1, 122_L2 and / or the connection pad 120 at each level. The rewiring layer 120RDL may further include an interlayer insulating film 128 in order to electrically insulate many components included herein. The interlayer insulating film may include silicon oxide, silicon nitride, silicon oxynitride, a polymer, or a combination thereof.

[0058] FIG. 8 is a side view showing a semiconductor package 10 including an interposer 100 according to an embodiment of the present invention.

[0059] Referring to FIG. 8, the semiconductor package 10 may include a package substrate 200, an interposer 100 disposed on the package substrate 200, and a first semiconductor device 310 and a second semiconductor device 320 mounted on the interposer 100.

[0060] The package substrate 200 may include a base board layer 210, and an upper surface pad 222 and a lower surface pad 224 disposed on the upper surface and the lower surface of the base board layer 210, respectively.

[0061] In some embodiments, the package substrate 200 may be a printed circuit board (PCB). For example, the package substrate 200 may be a multi-layer printed circuit board (multi-layer PCB). The base board layer 210 is made of at least one selected substance among phenol resin, epoxy resin, and polyimide. The base board layer 210 may include, for example, at least one selected substance among FR4 (Frame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0062] An upper surface solder resist layer 232 and a lower surface solder resist layer 234 for exposing the upper surface pad 222 and the lower surface pad 224 are formed on the upper surface and the lower surface of the base board layer 210, respectively. A connection terminal structure 140 is connected to the upper surface pad 222, and an external connection terminal 250 is connected to the lower surface pad 224.

[0063] The package substrate 200 may include a wiring pattern that electrically connects the upper surface pads 222 and the lower surface pads 224, and conductive vias that electrically connect between the wiring patterns. The wiring pattern is disposed on the upper surface, the lower surface, and / or inside of the base board layer 210. The wiring pattern may be made of, for example, ED (electrolytically deposited) copper foil, RA (rolled-annealed) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foils, sputtered copper, copper alloys, and the like.

[0064] The conductive via is formed to penetrate at least a part of the base board layer 210. In some embodiments, the conductive via may be made of copper, nickel, stainless steel, or beryllium copper.

[0065] In some embodiments, when the semiconductor package 10 does not include the package substrate 200, the connection terminal structure 140 can perform the function of an external connection terminal.

[0066] The interposer 100 has been described in detail with reference to FIGS. 1 to 7, and thus detailed description thereof is omitted here.

[0067] On the first region R1 (see FIG. 1) of the interposer 100, a first semiconductor device 310 is mounted. The first semiconductor device 310 is connected to the redistribution layer 120RDL of the interposer 100 through a chip connection member 314. The chip connection member 314 can be, for example, a bump, a solder ball, or a conductive pillar.

[0068] The first semiconductor device 310 can be, for example, a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, or an application processor (AP) chip. In some embodiments, the first semiconductor device 310 can be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable and programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0069] The second semiconductor device 320 is mounted on the second region R2 (see FIG. 1) on the interposer 100.

[0070] The second semiconductor device 320 can be, for example, a High Bandwidth Memory (HBM) DRAM semiconductor chip. The second semiconductor device 320 may include a stack of a plurality of memory semiconductor chips. Here, "stack" is defined as all the memory chips included together as one assembly based on JEDEC definitions.

[0071] The second semiconductor device 320 may include a plurality of memory chips 323a, 323b, 323c, 323d. The plurality of memory chips 323a, 323b, 323c, 323d are electrically connected to each other by connection terminals 336. The connection terminals 336 can be bumps or solder balls.

[0072] Each of the memory chips 323a, 323b, 323c, and 323d may include through silicon vias (TSVs) 338 that electrically connect chip pads disposed on the inactive surface and chip pads disposed on the active surface.

[0073] The plurality of memory chips 323a, 323b, 323c, and 323d are fixed to each other by an adhesive layer 382. In some embodiments, the adhesive layer 382 may be a non-conductive film (NCF).

[0074] The second semiconductor device 320 may further include a logic chip 325. The plurality of memory chips 323a, 323b, 323c, and 323d are stacked on the logic chip 325, and the logic chip 325 is mounted on the interposer 100.

[0075] The logic chip 325 can be a control chip for controlling the plurality of memory chips 323a, 323b, 323c, and 323d, and may include, for example, a logic circuit such as a SER / DES (serializer / deserializer) circuit. The logic chip 325 is connected to the redistribution layer 120RDL of the interposer 100 through a chip connection member 324. The chip connection member 324 can be, for example, a bump, a solder ball, or a conductive pillar.

[0076] In some embodiments, the interposer 100, the first semiconductor device 310, and the second semiconductor device 320 can be encapsulated by an encapsulant, but in FIG. 8, the illustration of the encapsulant is omitted for easy identification of the components.

[0077] The semiconductor package 10 may further include a heat dissipation member such as a heat slug or a heat sink. The heat dissipation member is configured to contact the first semiconductor device 310, the second semiconductor device 320, and / or the encapsulant.

[0078] FIG. 9 is a side view showing a semiconductor package 10A including an interposer 100A according to another embodiment of the present invention.

[0079] Referring to FIG. 9, the semiconductor package 10A may include a package substrate 200A having a recess portion SR, an interposer 100A accommodated in the recess portion SR and electrically connected to the package substrate 200A, and first and second semiconductor devices 310 and 320 that are mounted over the interposer 100A and the package substrate 200A while partially overlapping the interposer 100A.

[0080] The package substrate 200A may include a recess portion SR. The depth of the recess portion SR is determined in consideration of the level that the upper surface of the interposer 100A must have when the interposer 100A is accommodated. In some embodiments, the upper surface of the package substrate 200A can be located substantially in the same plane as the upper surface of the interposer 100A accommodated in the recess portion SR.

[0081] The interposer 100A may only partially overlap the first semiconductor device 310 in the third region R3. Also, the interposer 100A may only partially overlap the second semiconductor device 320 in the fourth region R4. In some embodiments, the interposer 100A is configured to completely overlap one of the first semiconductor device 310 and the second semiconductor device 320 and only partially overlap the other one.

[0082] The first semiconductor device 310 and the second semiconductor device 320 are electrically connected to the interposer 100A through chip connection members 314 and 324. Also, the first semiconductor device 310 and the second semiconductor device 320 are electrically connected to the package substrate 200A through chip connection members 314a and 324a.

[0083] In FIG. 9, the redistribution layer 120RDL is oriented to face the package substrate 200A. However, in other embodiments, the redistribution layer 120RDL may be oriented to face the first semiconductor device 310 and the second semiconductor device 320.

[0084] The first semiconductor device 310 and the second semiconductor device 320 have been described in detail with reference to FIG. 8, and thus redundant descriptions are omitted here.

[0085] FIG. 10 is a side view showing a semiconductor package 10B including an interposer 100B according to still another embodiment of the present invention.

[0086] Referring to FIG. 10, the semiconductor package 10B may include an interposer 100B, a first semiconductor device 310 and a second semiconductor device 320 mounted on different surfaces of the interposer 100B, respectively, and a package substrate 200B on which the interposer 100B is mounted.

[0087] The first semiconductor device 310 is mounted on the first main surface 110A of the interposer 100B, and the second semiconductor device 320a is mounted on the second main surface 110B of the interposer 100B, more specifically, on the redistribution layer 120RDL. In FIG. 10, the first semiconductor device 310 and the second semiconductor device 320a are illustrated as single semiconductor chips, but a person of ordinary skill in the art will understand that the first semiconductor device 310 and the second semiconductor device 320a can each independently include a plurality of semiconductor chips.

[0088] The interposer 100B is mounted on the package substrate 200B by the connection terminal structure 140. Also, the first semiconductor device 310 is mounted on the interposer 100B by the connection terminal structure 140. The second semiconductor device 320a is electrically connected to the redistribution layer 120RDL by the chip connection member 324.

[0089] The package substrate 200B may include a recess SR capable of at least partially accommodating the first semiconductor device 310.

[0090] FIGS. 11A to 11R are side views exemplarily showing a method of manufacturing an interposer 100 according to an embodiment of the present invention.

[0091] Referring to FIG. 11A, an etching mask 101 for opening positions where a first through-electrode structure and a second through-electrode structure are to be formed on an interposer substrate 110 can be formed. The etching mask 101 can be a hard mask and / or a photoresist mask, and is formed by a photolithography process. The hard mask may include a material such as silicon nitride, spin-on hardmask (SOH), or amorphous carbon layer (ACL). The photoresist mask uses a photosensitive polymer considering the wavelength band of the light to be exposed.

[0092] Referring to FIG. 11B, anisotropic etching is performed on the portions exposed using the etching mask 101, whereby a first via hole 131h and a second via hole 133h can be formed. At this time, a CFx-based gas such as C4F8 and an additive gas such as Ar, N2, O2, or H2 can be used as the etching gas.

[0093] In some embodiments, the first via hole 131h and the second via hole 133h are performed by deep reactive-ion etching (DRIE), also known as the Bosch process. In that case, scallops can be formed at least partially on the sidewalls of the first via hole 131h and the second via hole 133h.

[0094] In some other embodiments, laser drilling technology may be utilized to form the first via hole 131h and the second via hole 133h.

[0095] Referring to FIG. 11C, a via dielectric film 131dm and a barrier film 131bm that cover the inner sidewalls and bottom surfaces of the first via hole 131h and the second via hole 133h and the upper surface of the interposer substrate 110 can be sequentially formed. The via dielectric film 131dm can be formed by CVD or PVD. The barrier film 131bm can be formed by CVD, PVD, or ALD.

[0096] Thereafter, a core conductor material film 131am can be formed in the space defined by the barrier film 131bm. The core conductor material film 131am can be formed by an electroplating process. For this purpose, first, a seed layer is formed on the surface of the barrier film 131bm, and a conductor film can be grown from the metal seed layer by an electroplating process to form the core conductor material film 131am. The metal seed layer may be made of Cu, Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu. The metal seed layer is formed by a PVD process. The main material of the core conductor material film 131am may be made of Cu or W.

[0097] In some embodiments, the core conductor material film 131am may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or a W alloy, but is not limited thereto. The electroplating process is performed at a temperature of about 10°C to about 65°C, respectively. In some embodiments, the electroplating process is performed at room temperature, respectively. After the core conductor material film 131am is formed, if necessary, the resultant product on which the core conductor material film 131am is formed can be annealed at a temperature of about 150°C to about 450°C.

[0098] Referring to FIG. 11D, the core conductor material film 131am, the barrier material film 131bm, and the via dielectric material film 131dm outside the first via hole 131h and the second via hole 133h can be removed by chemical mechanical polishing (CMP). As a result, the first through electrode structure 131 and the second through electrode structure 133 limited inside the first via hole 131h and the second via hole 133h are formed.

[0099] After that, the first through electrode structure 131 and the second through electrode structure 133 can be heat-treated to improve the roughness of the exposed surface. In some embodiments, the heat treatment is performed at a temperature of about 400°C to about 500°C.

[0100] Referring to FIG. 11E, connection pads 120 are formed on the exposed surfaces of the first through electrode structure 131 and the second through electrode structure 133.

[0101] The connection pads 120 are made of aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), cobalt (Co), tungsten (W), zinc (Zn), or an alloy thereof. In some embodiments, the connection pads 120 are made of copper and can be formed by the damascene method. That is, after forming a sacrificial film pattern corresponding to the shape of the connection pads 120, forming a copper material film by plating, flattening it to form the connection pads 120 in the sacrificial film pattern, and removing the sacrificial film pattern, the connection pads 120 as shown in FIG. 11E can be formed.

[0102] Referring to FIG. 11F, the interposer substrate 110 is partially removed from the bottom surface so that the first through electrode structure 131 and the second through electrode structure 133 protrude on the first main surface 110A of the interposer substrate 110. The interposer substrate 110 can be partially removed from the bottom surface by etch-back.

[0103] FIG. 11F shows the shape covering the interposer of FIG. 11E. Therefore, in FIG. 11E, the connection pad 120 is located on the first through electrode structure 131 and the second through electrode structure 133, while in FIG. 11F, the connection pad 120 is located below the first through electrode structure 131 and the second through electrode structure 133.

[0104] Referring to FIG. 11G, a passivation layer 150 can be formed on the first main surface of the interposer substrate 110, the exposed surfaces of the first through electrode structure 131, and the second through electrode structure 133. The passivation layer 150 includes a first passivation layer 151 and a second passivation layer 153, and they can be formed sequentially. The first passivation layer 151 and the second passivation layer 153 can be formed independently by PVD, CVD, or ALD respectively.

[0105] Since the materials of the first passivation layer 151 and the second passivation layer 153 have been described in detail with reference to FIG. 3, the repeated description is omitted here.

[0106] Referring to FIG. 11H, a photosensitive polymer material film 160m is formed on the passivation layer 150. The photosensitive polymer material film 160m must have photosensitivity applicable to a photolithography process and also have the characteristic of being cured rapidly. Such a photosensitive polymer material film 160m can be, for example, a photoimageable dielectric (PID) material. Specifically, the PID material may include, for example, a polyimide-based photosensitive polymer, a novolak-based photosensitive polymer, polybenzoxazole, a silicone-based polymer, an acrylate-based polymer, or an epoxy-based polymer.

[0107] The photosensitive polymer material film 160m can be formed, for example, by spin coating. Since the viscosity of the photosensitive polymer material film 160m is high, the upper surface of the photosensitive polymer material film 160m can have a relatively high level on the first through electrode structure 131 and the second through electrode structure 133.

[0108] Referring to FIG. 11I, an alignment key pattern 170p can be formed within the photosensitive polymer material film 160m. The formation of the alignment key pattern 170p is performed by selectively exposing the photosensitive polymer material film 160m and developing it.

[0109] In some embodiments, the alignment key pattern 170p is formed to penetrate the photosensitive polymer material film 160m. In some embodiments, the sidewalls of the alignment key pattern 170p may not be completely perpendicular to the first major surface 110A. This is because the time and environment exposed to the etching agent for pattern formation are different depending on the vertical position of the sidewalls of the alignment key pattern 170p. As a result, as shown in FIG. 4, sidewalls 170sw inclined at a predetermined angle α (e.g., about 80° to about 88°) with respect to the first major surface 110A can be formed.

[0110] Thereafter, the photosensitive polymer material film 160m can be cured by annealing at a temperature of about 80°C to about 200°C for about 5 seconds to about 5 minutes.

[0111] Referring to FIG. 11J, anisotropic etching is performed using the alignment key pattern 170p as an etching mask to remove the passivation layer 150 partially or through. Here, an embodiment where the passivation layer 150 is only partially removed is shown.

[0112] In some embodiments, the step of partially removing the passivation layer 150 using the alignment key pattern 170p as an etching mask can be omitted.

[0113] In FIG. 11J, it is illustrated that the photosensitive polymer material film 160m above the first through electrode structure 131 and the second through electrode structure 133 is removed by the anisotropic etching. However, depending on the case, the photosensitive polymer material film 160m can partially remain above the first through electrode structure 131 and the second through electrode structure 133.

[0114] Referring to FIG. 11K, the ends of the first through electrode structure 131 and the second through electrode structure 133 are partially removed to expose them partially from the passivation layer 150.

[0115] The removal of the ends is performed by CMP. By the CMP, the passivation layer 150 on the first through electrode structure 131 and the second through electrode structure 133 is removed. Also, the via dielectric films 131d, 133d and the barrier films 131b, 133b at the upper ends of the first through electrode structure 131 and the second through electrode structure 133 are also partially removed by CMP.

[0116] In some embodiments, the CMP is performed until the upper surface of the photosensitive polymer layer 160, the upper surfaces of the first through electrode structure 131 and the second through electrode structure 133, and the upper surface of the passivation layer surrounding them on the side are substantially in the same plane.

[0117] Also, an alignment key 170 is formed by the CMP.

[0118] Referring to FIG. 11L, a seed metal layer 145m can be formed on the exposed surface. The seed metal layer 145m can be formed, for example, by CVD, ALD, or PVD. The seed metal layer 145m may be made of, for example, Cu, Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu.

[0119] Referring to FIG. 11M, a photoresist material film 180m is formed on the seed metal layer 145m. The photoresist material film 180m can be, for example, a normal photoresist and can be formed to an appropriate thickness, for example, by spin coating.

[0120] Referring to FIG. 11N, a photoresist pattern 180 can be formed by patterning a photoresist material film 180m so that the seed metal layer 145m at the position where the connection terminal structure is to be formed is exposed. The patterning of the photoresist material film 180m can be performed by exposure and development according to a pattern.

[0121] Referring to FIG. 11O, then, the first conductor layer 141 and the solder metal layer 143a can be formed by plating. The plating can be, for example, electroless plating, but is not limited thereto. As shown in FIG. 5, in order to make the first conductor layer 141a of the pillar type, the plating time can be adjusted so that the first conductor layer 141a has a sufficiently large vertical dimension.

[0122] Referring to FIG. 11P, the photoresist pattern 180 can be removed. The removal of the photoresist pattern 180 is performed by a method such as ashing, but is not particularly limited.

[0123] Referring to FIG. 11Q, the exposed portion of the seed metal layer 145m can be removed using the first conductor layer 141 and the solder metal layer 143a as an etching mask. The removal of the exposed portion of the seed metal layer 145m is performed through anisotropic etching or can be accomplished by wet etching using a selective etching solution.

[0124] While removing the exposed portion of the seed metal layer 145m, the exposed surface of the photosensitive polymer layer 160 is also partially removed. In some embodiments, while the exposed portion of the seed metal layer 145m is removed, the upper surface of the photosensitive polymer layer 160 is partially removed. However, since mass transfer is more active in the portion farther from the first conductor layer 141 than in the portion closer to the first conductor layer 141, the photosensitive polymer layer 160 is removed at a relatively faster rate. Thereby, as illustrated in FIG. 4, the thickness of the photosensitive polymer layer 160 decreases as it approaches the alignment keeper pattern 170p, and the upper surface 160u of the photosensitive polymer layer 160 can be inclined with respect to the first main surface 110A.

[0125] Referring to FIG. 11R, the connection terminal structure 140 can be formed by reflowing the solder metal layer 143a. The reflow is performed at a temperature of about 200°C to about 280°C for about 30 seconds to about 10 minutes.

[0126] FIGS. 12A to 12J are side views exemplarily showing a method of manufacturing an interposer according to the embodiment described with reference to FIG. 6.

[0127] The steps prior to the step shown in FIG. 12A are common to the steps shown in FIGS. 11A to 11F, and thus the description thereof is omitted for the sake of brevity. The step shown in FIG. 12A follows the step shown in FIG. 11F.

[0128] Referring to FIG. 12A, a photosensitive polymer material film 160m can be formed on the first main surface 110A, the exposed first through electrode structure 131, and the second through electrode structure 133. The photosensitive polymer material film 160m must have photosensitivity applicable to a photolithography process and must also have the property of being rapidly cured. Since this has been described with reference to FIG. 11H, a detailed description thereof is omitted here.

[0129] Referring to FIG. 12B, an alignment key pattern 170p can be formed within the photosensitive polymer material film 160m. The formation of the alignment key pattern 170p is achieved by performing selective exposure on the photosensitive polymer material film 160m and then developing it.

[0130] In some embodiments, the alignment key pattern 170p can be formed to penetrate through the photosensitive polymer material film 160m.

[0131] Thereafter, the photosensitive polymer material film 160m can be cured by annealing at a temperature of about 80°C to about 200°C for about 5 seconds to about 5 minutes.

[0132] Referring to FIG. 12C, a part of the ends of the first through - electrode structure 131 and the second through - electrode structure 133 is removed, and they are partially exposed from the photosensitive polymer layer 160.

[0133] The removal of the ends can be accomplished by CMP. By this CMP, the upper parts of the first through - electrode structure 131 and the second through - electrode structure 133 can be removed. Further, the via dielectric films 131d, 133d and the barrier films 131b, 133b at the upper ends of the first through - electrode structure 131 and the second through - electrode structure 133 can also be removed by CMP. The alignment key 170 can be formed by this CMP.

[0134] Referring to FIG. 12D, a seed metal layer 145m can be formed on the exposed surface. The seed metal layer 145m is formed, for example, by CVD, ALD, or PVD. The seed metal layer 145m may be composed of, for example, Cu, Cu alloy, Co, Ni, Ru, Co / Cu, or Ru / Cu.

[0135] Referring to FIG. 12E, a photoresist material film 180m can be formed on the seed metal layer 145m. The photoresist material film 180m can be a normal photoresist, for example, and can be formed to an appropriate thickness by spin - coating.

[0136] Referring to FIG. 12F, the photoresist material film 180m can be patterned to form a photoresist pattern 180 such that the seed metal layer 145m at the position where the connection terminal structure is to be formed is exposed. The patterning of the photoresist material film 180m can be performed by exposure and development according to a pattern.

[0137] Referring to FIG. 12G, then, the first conductor layer 141 and the solder metal layer 143a can be formed by plating. The plating can be, for example, electroless plating, but is not limited thereto.

[0138] Referring to FIG. 12H, the photoresist pattern 180 can be removed. The removal of the photoresist pattern 180 can be performed by a method such as ashing, but is not particularly limited.

[0139] Referring to FIG. 12I, the exposed portion of the seed metal layer 145m can be removed using the first conductor layer 141 and the solder metal layer 143a as an etching mask. The removal of the exposed portion of the seed metal layer 145m can be accomplished through anisotropic etching or by wet etching using a selective etching solution.

[0140] Referring to FIG. 12J, the connection terminal structure 140 can be formed by reflowing the solder metal layer 143a. The reflow is performed at a temperature of about 200°C to about 280°C for about 30 seconds to about 10 minutes.

[0141] As described above, the embodiments of the present invention have been described in detail. However, those having ordinary knowledge in the technical field to which the present invention pertains can implement the present invention in various modifications without departing from the spirit and scope of the present invention defined in the claims. Therefore, future modifications of the embodiments of the present invention do not deviate from the technology of the present invention.

Explanation of Reference Numerals

[0142] 100 Interposer 110A First main surface 110B Second main surface 120 Connecting pad 131, 133 Through - electrode structure 140 Connection terminal structure R1 First region R2 Second region 131a First core conductor 131b First barrier film 131d First via dielectric film 131h First via hole 133a Second core conductor 133b Second barrier film 133d Second via dielectric film 141 First conductor layer 143 Solder metal layer 145 Seed metal layer 150 Passivation layer 151 First passivation layer 153 Second passivation layer 156p_1 First upper surface 156p_2 Second upper surface 160 Photosensitive polymer layer 170 Alignment key

Claims

1. An interposer substrate having a first main surface and a second main surface opposite to the first main surface, a first through electrode structure and a second through electrode structure respectively protruding on the first main surface through the interposer substrate, a connection terminal structure in contact with both the first through electrode structure and the second through electrode structure, a photosensitive polymer layer disposed between the connection terminal structure and the interposer substrate between the first through electrode structure and the second through electrode structure, and including, an interposer for a semiconductor package, wherein upper surfaces of protruding portions of the first through electrode structure and the second through electrode structure respectively form a flat surface together with an upper surface of a portion of the photosensitive polymer layer around the protruding portions.

2. further including a passivation layer covering side surfaces of protruding portions of the first through electrode structure and the second through electrode structure and the first main surface, The interposer for a semiconductor package according to claim 1, wherein the photosensitive polymer layer is provided on the passivation layer between the first through electrode structure and the second through electrode structure.

3. The interposer for a semiconductor package according to claim 2, wherein the connection terminal structure is in direct contact with the photosensitive polymer layer between the first through electrode structure and the second through electrode structure.

4. The interposer for a semiconductor package according to claim 3, wherein the connection terminal structure includes a seed metal layer in contact with both the first through electrode structure and the second through electrode structure, a first conductor layer provided on the seed metal layer, and a solder metal layer provided on the first conductor layer.

5. The interposer for a semiconductor package according to claim 3, wherein a lower surface of the connection terminal structure in direct contact with the photosensitive polymer layer is substantially in the same plane as an upper surface of the photosensitive polymer layer.

6. The passivation layer includes a first upper surface that laterally surrounds a protruding portion of the first through electrode structure and is in the same plane as an upper surface of the first through electrode structure, The passivation layer includes a second upper surface that laterally surrounds a protruding portion of the second through electrode structure and is in the same plane as an upper surface of the second through electrode structure, The interposer for a semiconductor package according to claim 5, wherein the connection terminal structure contacts the entire first upper surface and the entire second upper surface.

7. The interposer for a semiconductor package according to claim 1, further comprising an alignment key disposed in the photosensitive polymer layer adjacent to the first through electrode structure.

8. The interposer for a semiconductor package according to claim 2, further comprising an alignment key disposed adjacent to the first through electrode structure, wherein the alignment key penetrates the photosensitive polymer layer and is configured to at least partially penetrate the passivation layer.

9. The interposer for a semiconductor package according to claim 7 or 8, wherein side walls of the alignment key in the photosensitive polymer layer are inclined at an angle of about 80° to about 88° with respect to an upper surface of the interposer substrate.

10. The interposer for a semiconductor package according to claim 7 or 8, wherein the photosensitive polymer layer between the alignment key and the first through electrode structure adjacent thereto has a thickness that decreases closer to the alignment key.

11. The passivation layer includes a first passivation layer located relatively close to the interposer substrate and the first through electrode structure and a second passivation layer located relatively far therefrom, The interposer for a semiconductor package according to claim 2, wherein a Young's modulus of the second passivation layer is higher than a Young's modulus of the first passivation layer.

12. The interposer for a semiconductor package according to claim 11, wherein the Young's modulus of the first passivation layer is about 60 GPa to about 80 GPa, and the Young's modulus of the second passivation layer is about 100 GPa to about 160 GPa.

13. The interposer for a semiconductor package according to claim 11 or 12, wherein the first passivation layer has a thickness of about 1.0 μm to about 3.0 μm, and the second passivation layer has a thickness of about 0.35 μm to about 0.75 μm.

14. A package substrate, an interposer disposed on the package substrate, a first semiconductor device and a second semiconductor device respectively disposed so as to at least partially overlap the interposer, wherein the interposer is An interposer substrate having a first main surface facing the package substrate and a second main surface opposite to the first main surface, A first through electrode structure and a second through electrode structure respectively protruding on the first main surface through the interposer substrate, A passivation layer covering the side surfaces of the protruding portions of the first through electrode structure and the second through electrode structure and the first main surface, A photosensitive polymer layer provided on the passivation layer between the first through electrode structure and the second through electrode structure, A semiconductor package including a connection terminal structure in contact with both the first through electrode structure and the second through electrode structure.

15. The second semiconductor device is a memory device in which a plurality of memory chips are stacked, The semiconductor package according to claim 14, wherein the interposer overlaps the entirety of the first semiconductor device and the entirety of the second semiconductor device.

16. The semiconductor package according to claim 14, wherein the interposer is housed inside the package substrate, and one surface of the package substrate and the second main surface of the interposer substrate are substantially in the same plane.

17. The semiconductor package according to claim 14, wherein the interposer overlaps only a part of the first semiconductor device and a part of the second semiconductor device.

18. The interposer further includes an alignment key disposed in the photosensitive polymer layer adjacent to the first through electrode structure, The semiconductor package according to claim 14, wherein the photosensitive polymer layer has a thickness change of about 0.01 μm to about 0.5 μm between the alignment key and the first through electrode structure adjacent thereto.

19. A package substrate, An interposer disposed on the package substrate, A first semiconductor device and a second semiconductor device respectively disposed so as to at least partially overlap the interposer, Including, The package substrate includes a base layer, an upper surface connection pad provided on the upper surface of the base layer, and a lower surface connection pad provided on the lower surface of the base layer, The interposer is, An interposer substrate having a first main surface facing the package substrate and a second main surface opposite to the first main surface, A first through-electrode structure and a second through-electrode structure that respectively protrude on the first main surface through the interposer substrate; A passivation layer that covers the side surfaces of the protruding portions of the first through-electrode structure and the second through-electrode structure and the first main surface; A photosensitive polymer layer provided on the passivation layer between the first through-electrode structure and the second through-electrode structure; A connection terminal structure that is in contact with both the first through-electrode structure and the second through-electrode structure and is connected to the upper surface connection pad of the package substrate; comprising; The first semiconductor device is a memory device in which a plurality of memory chips are stacked; The second semiconductor device is a memory controller configured to control the memory device, a semiconductor package.

20. The passivation layer surrounds the protruding portion of the first through-electrode structure laterally and includes a first upper surface that is coplanar with the upper surface of the first through-electrode structure; The semiconductor package according to claim 19, wherein the photosensitive polymer layer is located only at the level of the first upper surface or at a level below it.

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