Three-dimensional memory device with a support structure for a gate line slit, and method for forming the three-dimensional memory device

Abstract

To provide a three-dimensional memory device with support structures in gate line slits and methods for forming the same.SOLUTION: Embodiments of a structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having a plurality of conductor layers and a plurality of insulating layers being interleaved and extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into a substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contact the substrate.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of priority to Chinese Patent Application No. 201910522007.2, filed on June 17, 2019, the content of which is incorporated herein by reference in its entirety.

[0002] Embodiments of the present disclosure relate to a three - dimensional (3D) memory device with a support structure in a gate line slit (GLS) and a method for forming a 3D memory device.

Background Art

[0003] Planar memory cells have been scaled down to a smaller size by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the physical dimensions of the memory cells approach the lower limit, planar processes and fabrication techniques become difficult and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0004] 3D memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals that travel to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of a 3D memory device and embodiments of a method for forming a 3D memory device are provided.

[0006] In one example, a 3D memory device comprises a memory stack having a plurality of alternating conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also comprises a plurality of channel structures extending vertically through the memory stack to a substrate, the plurality of channel structures intersecting the plurality of conductor layers to form a plurality of memory cells. The 3D memory device further comprises at least one slit structure extending vertically and laterally in the memory stack, dividing the plurality of memory cells into at least one memory block and comprising a plurality of slit openings and a support structure between adjacent slit openings. The support structure contacts adjacent block structures and contacts the substrate. The 3D memory device further comprises a source structure having insulating spacers at each of the plurality of slit openings and source contacts at respective insulating spacers.

[0007] In another example, a method for forming a 3D memory device is provided. The method includes forming, across a substrate, a dielectric stack comprising a plurality of alternating initial insulating layers and a plurality of initial sacrificial layers, and forming at least one slit structure that extends vertically and laterally in the dielectric stack and divides the dielectric stack into a plurality of block regions. The at least one slit structure each comprises a plurality of slit openings that expose the substrate and an initial support structure between adjacent slit openings. Each of the plurality of block regions may comprise a plurality of alternating insulating layers and a plurality of sacrificial layers, and the initial support structure may comprise a plurality of alternating insulating portions and a plurality of sacrificial portions. Each of the plurality of insulating portions and the plurality of sacrificial portions may contact respective insulating layers and sacrificial layers of the same altitude from adjacent block regions. In some embodiments, the method further includes forming a plurality of channel structures that extend vertically through the dielectric stack, replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions through at least one slit structure, and forming a source structure at each slit structure. The source structure may comprise an insulating spacer at each of the plurality of slit openings and a source contact at each respective insulating spacer.

[0008] In different examples, methods for forming a 3D memory device are provided. The method includes forming, across a substrate, a dielectric stack of alternating plural initial insulating layers and plural initial sacrificial layers; forming a dielectric structure extending along a lateral direction in the dielectric stack, the dielectric structure extending vertically into a first initial insulating layer; patterning the dielectric stack using the dielectric structure as an etching mask to form a slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into pairs of block regions. The slit structure may include plural slit openings exposing the substrate and plural initial support structures between adjacent slit openings. Each of the plural block regions may include alternating plural insulating layers and plural sacrificial layers, and the plural initial support structures may include alternating plural insulating portions and plural sacrificial portions. Each of the plural insulating portions and plural sacrificial portions may contact respective insulating layers and sacrificial layers of the same height from adjacent block regions. The method may also include forming plural channel structures extending vertically through the dielectric stack; replacing the plural sacrificial layers and plural sacrificial portions with plural conductor layers and plural conductor portions through at least one slit structure; and forming a source structure in each slit structure. The source structure may include an insulating spacer at each of the plural slit openings and a source contact at each insulating spacer.

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and to enable one of ordinary skill in the art to make and use the disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0012] Specific configurations and arrangements are considered, but it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in various other applications.

[0013] It should be noted that references herein to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include specific features, structures, or characteristics, but not necessarily all embodiments include the specific features, structures, or characteristics. Further, such language does not necessarily refer to the same embodiment. Further, when a specific feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0014] Generally, technical terms can be understood at least in part from their use in context. For example, as used herein, the term "one or more" can be used, at least in part depending on the context, to describe any feature, structure, or property in a singular sense, or to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a", "an", or "the" can also be understood here, at least in part depending on the context, to convey singular use or plural use. Also, the term "based on" can be understood as not necessarily intended to convey an exclusive collection of factors, but rather, here too, at least in part depending on the context, can allow for the presence of additional factors that are not necessarily explicitly recited.

[0015] As used herein, the term "rated / rationally" refers to the value of a feature or parameter for a component or process step set between aspects of the design of a product or process, along with a range of values above and / or below the desired or target value. The range of values can be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on the specific technology node associated with the subject semiconductor device. Based on the specific technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10 - 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0016] As used herein, a staircase structure refers to a collection of surfaces that includes at least two horizontal planes (e.g., along the x-y plane) and at least two (e.g., first and second) vertical planes (e.g., along the z-axis), such that each horizontal plane is adjacent to a first vertical plane extending upward from a first edge of the horizontal plane and a second vertical plane extending downward from a second edge of the horizontal plane. A "step" or "staircase" refers to a vertical displacement in height between adjacent surface collections. In the present disclosure, the term "staircase" and the term "step" refer to an altitude of a staircase structure and are used interchangeably. In the present disclosure, the horizontal direction can be referred to as a direction parallel to the upper surface of a substrate (e.g., a substrate providing a fabrication platform for forming a structure over itself) (e.g., the x-axis or y-axis), and the vertical direction can be referred to as a direction perpendicular to the upper surface of the structure (e.g., the z-axis).

[0017] NAND flash memory devices, which are widely used in various electronic products, are non-volatile, lightweight, and have low power consumption and good performance. Current planar NAND flash memory devices have reached their storage limits. To further increase the storage capacity and reduce the storage cost per bit, 3D NAND memory devices have been proposed. Processes for forming existing 3D NAND memory devices often include the following steps. First, a stack structure of a plurality of alternating sacrificial layers and insulating layers is formed over a substrate. Channel holes are formed extending in the stack structure. The bottom of the channel holes is etched to form recesses in the substrate. Epitaxial portions are formed at the bottoms of the channel holes by selective epitaxial growth. Semiconductor channels electrically connected to the epitaxial portions are formed in the channel holes. The sacrificial layers can be removed and replaced with conductor layers. The conductor layers function as word lines in the 3D NAND memory device.

[0018] Existing 3D NAND memory devices often include a plurality of memory blocks. Adjacent memory blocks are often separated by GLS, forming an array common source (ACS). In a manufacturing method for forming an existing 3D NAND memory device, the physical dimensions of the GLS are susceptible to vibration and potentially affect the performance of the 3D NAND memory device.

[0019] The present disclosure provides a 3D memory device (e.g., a 3D NAND memory device) with a support structure for a slit structure (e.g., GLS), and a method for forming the 3D memory device. The 3D memory device uses one or more support structures that divide the slit structure into a plurality of slit openings where source contacts are formed. The support structure is in contact with adjacent memory blocks respectively and provides support to the entire structure of the 3D memory device during the formation of the conductor layer / conductor portion and the source contacts. Therefore, the 3D memory device is less susceptible to deformation or damage during the manufacturing process. The support structure includes a split structure and a plurality of alternating conductor portions and insulating portions under the split structure respectively. The split structure extends and connects across adjacent memory blocks in the uppermost part of the memory stack, and the plurality of alternating conductor portions and insulating portions can be in contact with the alternating conductor layers and insulating layers of adjacent memory blocks respectively. In some embodiments, the conductor portion of the support structure and the conductor layers between adjacent memory blocks are formed by the same deposition process. By applying the structure and method of the present disclosure, adjacent memory blocks are connected through the support structure during the formation of the slit structure and the source contacts, and thus the 3D memory device is less likely to deform during the manufacturing process. The physical dimensions of the slit structure are less susceptible to vibration.

[0020] FIG. 1A shows a plan view of an exemplary 3D memory device 150 according to some embodiments. FIG. 1B shows a cross-sectional view of the 3D memory device 150 shown in FIG. 1A along the A-B direction. FIG. 1C shows a cross-sectional view of the 3D memory device 150 shown in FIG. 1A along the C-D direction. As shown in FIG. 1A, the 3D memory device 150 can be divided, for example, along the y direction, into a core region 31 and a staircase region 32. Channel structures and support pillars can be formed in the core region 31. Staircases and electrical connections between the conductor layers and the outer circuits (e.g., contact plugs) can be formed in the staircase region 32. The core region 31 can include one or more first source regions 23, such as a pair, extending along the x direction. First source structures can be formed in each of the first source regions 23. A channel region 41 in which a plurality of channel structures and memory cells are formed is positioned between adjacent first source regions 23. In some embodiments, the channel region 41 can be divided into a plurality of block regions 21 by one or more second source regions 22 extending along the x direction. Memory blocks can be formed in each of the block regions 21, and second source structures can be formed in each of the second source regions 22.

[0021] As shown in FIGS. 1A - 1C, the 3D memory device 150 may include a substrate 100, a buffer oxide layer 101, and a stack structure 11 extending across the buffer oxide layer 101. In the block region 21, the stack structure 11 may include a plurality of conductor layers and a plurality of insulating layers 104 alternating across the buffer oxide layer 101. In some embodiments, the plurality of conductor layers may include a top conductor layer 129 having a plurality of top select conductor layers, a bottom conductor layer 128 having a plurality of bottom select conductor layers, and a control conductor layer 127 between the top conductor layer 129 and the bottom conductor layer 128. The stack structure 11 may also include a dielectric cap layer 105 covering the plurality of conductor layers (i.e., reference numerals 127 - 129) and the insulating layer 104. In the block region 21, the stack structure 11 may also include a plurality of channel structures 140 extending vertically (e.g., in the z - direction) from the top surface of the dielectric cap layer 105 to the substrate 100. Each channel structure 140 may include an epitaxial portion 115 at the bottom portion, a drain structure 120 at the top portion, and a semiconductor channel 119 between the epitaxial portion 115 and the drain structure 120. The semiconductor channel 119 may include a memory film 116, a semiconductor layer 117, and a dielectric core 118. The epitaxial portion 115 may be in conductive contact with the substrate 100, and the semiconductor channel 119 may be in conductive contact with the drain structure 120 and the epitaxial portion 115. A plurality of memory cells may be formed by the semiconductor channel 119 and the control conductor layer 127. In the staircase region 32, the stack structure 11 may include a plurality of contact plugs 131 each in contact with a respective conductor layer (e.g., reference numerals 127, 128, or 129) and a peripheral circuit (not shown) in the insulator 130. The contact plugs 131 may apply a word - line voltage to the connected conductor layer.

[0022] The first source structure may be formed in the first source region 23 so as to extend along the x direction in the core region 31 and the step region 32. The first source structure may include a source contact 126 in the insulating structure 137. The second source structure may be formed in the second source region 22 so as to extend along the x direction in the core region 31 and the step region 32. The second source structure may each include a plurality of source contacts 125 in their respective insulating structures 136. The source contacts 125 formed in one second source region 22 (e.g., of the same second source structure) and their respective insulating structures 136 may be arranged along the x direction. The first and second source structures may each extend vertically through the stack structure 11 and contact the substrate 100, and a source voltage may be applied to the memory cell through the substrate 100. The 3D memory device 150 may include one or more support structures 152 arranged along the x direction and dividing the second source structure into each of the plurality of source contacts 125 in their respective insulating structures 136. In some embodiments, the support structure 152 is a dividing structure 112, and under the dividing structure 112, the support structure 152 includes a dividing structure 112 that connects an adjacent memory block (or block region 21), a plurality of alternating conductor portions (e.g., reference numerals 127-0 and 128-0), and an insulating portion 104-0. The support structure 152 may provide support to the 3D memory device 150 during the formation of the second source structure and the conductor layers (e.g., reference numerals 127 to 129). In some embodiments, one or more cutting structures 111 may be formed in the channel region 41 extending parallel to the first source structure and the second source structure. The cutting structure 111 may divide the top conductor layer 129 into a plurality of top selection conductor layers that function as top selection gate electrodes.

[0023] The substrate 100 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 100 is a thin substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the substrate 100 includes silicon.

[0024] The channel structure 140 can form an array and can each vertically extend above the substrate 100. The channel structure 140 can extend through a plurality of pairs (referred to herein as "conductor / insulator layer pairs") each including a conductor layer (e.g., reference numerals 127, 128, or 129) and the insulating layer 104. In some embodiments, a buffer oxide layer 101 is formed between the substrate 100 and the stack structure 11. On one side along at least the horizontal direction (e.g., the x direction and / or the y direction), the stack structure 11 can include a staircase structure, for example, in the staircase region 32. The number of conductor / insulator layer pairs in the stack structure 11 (e.g., 32, 64, 96, or 128) determines the number of memory cells in the 3D memory device 150. In some embodiments, the conductor layers (e.g., reference numerals 127 to 129) and the insulating layer 104 in the stack structure 11 are alternately arranged along the vertical direction in the block region 21. The conductor layers (e.g., reference numerals 127 to 129) can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The insulating layer 104 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the buffer oxide layer 101 and the dielectric cap layer 105 each include a dielectric material such as silicon oxide. In some embodiments, the top conductor layer 129 includes a plurality of top select conductor layers that function as top select gate electrodes. The control conductor layer 127 can function as a select gate electrode and can form a memory cell with an intersecting channel structure 140. In some embodiments, the bottom conductor layer 128 includes a plurality of bottom select conductor layers that function as bottom select gate electrodes. A desired voltage can be applied to the top select gate electrode and the bottom select gate electrode, respectively, to select a desired memory block / finger / page.

[0025] As shown in FIG. 1B, the channel structure 140 may include a semiconductor channel 119 that extends vertically through the stack structure 11. The semiconductor channel 119 may include channel holes filled with a channel-forming structure, such as, for example, a semiconductor material (e.g., as the semiconductor layer 117) and a dielectric material (e.g., as the memory film 116). In some embodiments, the semiconductor layer 117 includes silicon such as amorphous silicon, polysilicon, or single-crystalline silicon. In some embodiments, the memory film 116 is a composite layer including a tunnel layer, a memory layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of the channel holes of the semiconductor channel 119 may be partially or fully filled with a dielectric core 118 including a dielectric material such as silicon oxide. The semiconductor channel 119 may have a cylindrical shape (e.g., the shape of a pillar). According to some embodiments, the dielectric core 118, the semiconductor layer 117, the tunnel layer, the memory layer, and the blocking layer are arranged in this order radially from the center to the outer surface of the pillar. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory layer may include a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0026] In some embodiments, the channel structure 140 further includes an epitaxial portion 115 (e.g., a semiconductor plug) at a lower portion of the channel structure 140 (e.g., the lower end of the bottom). As used herein, the “upper end” of a component (e.g., the channel structure 140) is the end that is farther away from the substrate 100 in the vertical direction, and the “lower end” of a component (e.g., the channel structure 140) is the end that is closer to the substrate 100 in the vertical direction when the substrate 100 is positioned at the lowest plane of the 3D memory device 150. The epitaxial portion 115 may include a semiconductor material such as silicon that is epitaxially grown from the substrate 100 in any suitable direction. In some embodiments, it is understood that the epitaxial portion 115 includes single-crystalline silicon of the same material as the substrate 100. In other words, the epitaxial portion 115 may include an epitaxial semiconductor layer grown from the substrate 100. The epitaxial portion 115 may include a material different from the substrate 100. In some embodiments, the epitaxial portion 115 includes at least one of silicon, germanium, and silicon germanium. In some embodiments, a part of the epitaxial portion 115 is above the upper surface of the substrate 100 and in contact with the semiconductor channel 119. The epitaxial portion 115 may be conductively connected to the semiconductor channel 119. In some embodiments, the upper surface of the epitaxial portion 115 is positioned between the upper surface and the bottom surface of the lowermost insulating layer 104 (e.g., the insulating layer at the bottom of the stack structure 11).

[0027] In some embodiments, the channel structure 140 further includes a drain structure 120 (e.g., a channel plug) at an upper portion (e.g., the upper end) of the channel structure 140. The drain structure 120 can contact the upper end of the semiconductor channel 119 and can be conductively connected to the semiconductor channel 119. The drain structure 120 can include a semiconductor material (e.g., polysilicon) or a conductive material (e.g., metal). In some embodiments, the drain structure includes an opening filled with Ti / TiN or Ta / TaN as an adhesion layer and tungsten as a conductor material. By covering the upper end of the semiconductor channel 119 during the fabrication of the 3D memory device 150, the drain structure 120 can function as an etching stop layer to prevent the etching of dielectrics filling the semiconductor channel 119, such as silicon oxide and silicon nitride.

[0028] As shown in FIG. 1A, the first source region 23 and the second source region 22 can divide the channel region 41 into a plurality of block regions 21, and these block regions 21 can be further divided by one or more cut structures 111 to form a plurality of memory fingers. A plurality of channel structures 140 (e.g., memory cells) can be formed in each memory block / finger. In some embodiments, the first source region 23, the second source region 22, and the cut structure 111 can extend along the x direction. In some embodiments, the cut structure 111 extends along the x direction in the channel region 41, and the first source region 23 and the second source region 22 can extend laterally in the core region 31 and the step region 32. The number of cut structures 111 in the block region 21 (i.e., the memory block) can range from 0 to n, where n is a suitable positive integer. The number of n should be determined based on the design and / or fabrication of the 3D memory device 150 and should not be limited by the embodiments of the present disclosure. For illustrative purposes, in the present disclosure, n is equal to 1.

[0029] In some embodiments, the cut structure 111 includes a suitable dielectric material such as one or more of silicon oxide, silicon nitride, or silicon oxynitride, and divides each block region 21 (or memory block) into pairs of memory fingers. Specifically, the cut structure 111 can extend vertically (i.e., along the z-direction) into the topmost insulating layer 104 (i.e., the insulating layer 104 under the topmost conductor layer 129). In some embodiments, the bottom surface of the cut structure 111 is between the top and bottom surfaces of the topmost insulating layer 104. In some embodiments, the cut structure 111 divides the topmost conductor layer 129 into a plurality of topmost select conductor layers. A voltage can be applied to one or more of the topmost select conductor layers to select a desired memory finger / page / block.

[0030] In some embodiments, the first source structure includes a source contact 126 that extends along the x-direction in the insulating structure 137. The source contact 126 can make a conductive connection in contact with the substrate 100 to apply a source voltage to the memory cell. In some embodiments, the source contact 126 includes one or more of polysilicon, silicide, germanium, silicon germanium, copper, aluminum, cobalt, and tungsten. In some embodiments, the insulating structure 137 includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the insulator 130 includes a suitable dielectric material such as silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the contact plugs 131 are each conductively connected in contact with their respective conductor layers (e.g., reference numerals 127, 128, or 129). The contact plugs 131 can include one or more of polysilicon, silicide, germanium, silicon germanium, copper, aluminum, cobalt, and tungsten.

[0031] In some embodiments, the second source structure may each include a plurality of source contacts 125 in respective insulating structures 136. Since the materials of the source contacts 125 and the insulating structures 136 can be the same or similar to those of the source contacts 126 and the insulating structures 137, the description will not be repeated here. At least one support structure 152 is formed between pairs of source contacts 125 (and pairs of insulating structures 136) and can contact adjacent block regions 21 (or memory blocks). As shown in FIGS. 1B and 1C, the support structure 152 may include a split structure 112 and a plurality of alternating conductor portions (e.g., reference numerals 127-0 and 128-0) and insulating portions 104-0 below the split structure 112. The conductor portions (e.g., reference numerals 127-0 and 128-0) and the insulating portions 104-0 can each contact (e.g., be connected to) the conductor layers (e.g., reference numerals 127 and 128) and the insulating layer 104 at the same altitude in adjacent block regions 21 (or memory blocks) along the y direction. In some embodiments, the conductor portions (e.g., reference numerals 127-0 and 128-0) and the insulating portions 104-0 are not connected to the conductor layers (e.g., reference numerals 127 and 128) and the insulating layer 104 of any block region 21 (or memory block) in their respective second source regions 22 along the x direction. In some embodiments, the 3D memory device 150 includes one or more support structures 152 arranged along the x direction to divide the second source structure into respective source contacts 125 in the insulating structures 136. As shown in FIGS. 1A-1C, the plurality of support structures 152 can divide the second source structure into a plurality of unconnected source contacts 125 and insulating structures 136 along the x direction. The plurality of support structures 152 can also be connected to the conductor layers (e.g., reference numerals 127 and 128) and the insulating layer 104 of adjacent block regions 21 along the y direction. In some embodiments, the support structure 152 may be formed in the channel region 41.

[0032] In some embodiments, the split structure 112 includes a suitable material having sufficient rigidity and strength and can be used as an etching mask for forming the slit structure before the formation of the second source structure. The material of the split structure 112 can also withstand the gate replacement process for forming the conductor layers (e.g., reference numerals 127-129) and conductor portions (e.g., reference numerals 127-0 and 128-0). In some embodiments, the split structure 112 includes one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the split structure 112 and the cut structure 111 may include the same material, such as silicon oxide. In some embodiments, the conductor portions (e.g., reference numerals 127-0 and 128-0) and the insulating portion 104-0 may include the same material as the respective conductor layers (e.g., reference numerals 127 and 128) and the insulating layer 104 at the same height in the adjacent block region 21 (or memory block). In some embodiments, the bottom surface of the split structure 112 is between the top and bottom surfaces of the topmost insulating layer 104. In some embodiments, the depth of the split structure 112 and the depth of the cut structure 111 may be the same along the z-axis, such as from the top surface of the dielectric cap layer 145 to the same height in the topmost insulating layer 104.

[0033] The width of the split structure 112 along the y direction may be equal to or greater than the width of the second source structure along the y direction. FIG. 13B shows an enlarged plan view 1320 of the split structure 112, the adjacent source contact 125, and the adjacent insulating structure 136. As shown in FIG. 13B, the width d2 of the split structure 112 along the y direction is equal to or greater than the width d1 of the second source structure (or insulating structure 136) along the y direction. In some embodiments, d2 is greater than d1. In some embodiments, the fact that d2 is greater than d1 prevents the support structure 152 (or the alternating conductor portions (e.g., reference numerals 127-0 and 128-0) and the insulating portion 104-0) from being connected to the adjacent memory block. Details are described as follows.

[0034] The 3D memory device 150 can be part of a monolithic 3D memory device. The term "monolithic" means that the components of the 3D memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate. For monolithic 3D memory devices, fabrication faces additional constraints due to the superposition of the processing of peripheral devices and the processing of memory array devices. For example, the fabrication of a memory array device (e.g., a NAND channel structure) is restricted by the thermal budget associated with the peripheral devices formed or to be formed on the same substrate.

[0035] Alternatively, the 3D memory device 150 can be part of a non - monolithic 3D memory device where components (e.g., peripheral devices and memory array devices) are separately formed on different substrates and then joined, for example, in a face - to - face manner. In some embodiments, the memory array device substrate (e.g., substrate 102) remains as the substrate of the joined non - monolithic 3D memory device, and the peripheral devices (e.g., any suitable digital, analog, and / or mixed - signal peripheral circuits used to facilitate the operation of the 3D memory device 150 such as page buffers, decoders, and latches not shown) are flipped and oriented downward toward the memory array device (e.g., a NAND memory string) for hybrid bonding. In some embodiments, it is understood that the memory array device substrate (e.g., substrate 100) is flipped so that the memory array device is above the peripheral devices in the joined non - monolithic 3D memory device and is oriented downward toward the peripheral devices (not shown) for hybrid bonding. The memory array device substrate (e.g., substrate 100) can be a thinned substrate (not the substrate of the joined non - monolithic 3D memory device), and the back - end - of - line (BEOL) interconnects of the non - monolithic 3D memory device can be formed on the back side of the thinned memory array device substrate.

[0036] According to some embodiments, FIGS. 2-4, 7, and 9-12 illustrate a fabrication process for forming a 3D memory device 150, and FIG. 14A shows a flowchart 1400 of the fabrication process.

[0037] At the start of the process, a stack structure of alternating plural initial insulating layers and plural initial sacrificial layers is formed (step 1402). FIGS. 2A-2D illustrate the corresponding structure 200.

[0038] As shown in FIGS. 2A-2D, a stack structure 11 having a dielectric stack of alternating initial insulating layers 104i and initial sacrificial layers 103i is formed across a substrate 100. The initial sacrificial layer 103i can be used for subsequent formation of a control conductor layer 127. The stack structure 11 can also include a top initial sacrificial layer 106i and a bottom initial sacrificial layer 105i for subsequent formation of a top conductor layer 129 and a bottom conductor layer 128, respectively. In some embodiments, the stack structure 11 includes a dielectric cap layer 145 across the initial sacrificial layers (e.g., reference numerals 103i, 105i, and 106i) and the initial insulating layer 104i. The 3D memory device 150 can include a core region 31 for forming a channel structure 140 and support pillars (not shown), and a staircase region 32 for forming a staircase and contact plugs (e.g., reference numeral 131) in the staircase. The core region 31 can include a channel region 41 for forming the channel structure 140. In some embodiments, the channel region 41 can be between first source regions 23. Subsequently, one or more second source regions 22 are formed between the first source regions 23, and block regions 21 can be positioned between the first source region 23 and the second source region 22, or between the second source regions 22, respectively.

[0039] As shown in FIG. 2D, the stack structure 11 may have a staircase structure. The staircase structure can be formed by repeatedly etching a material stack comprising a plurality of alternating sacrificial material layers and insulating material layers using an etching mask such as a patterned PR layer across the material stack. The alternating sacrificial material layers and insulating material layers can be formed by alternately depositing a layer of sacrificial material and a layer of insulating material across the buffer oxide layer 101 until the desired number of layers is reached. In some embodiments, the sacrificial material layer is deposited across the buffer oxide layer 101, the insulating material layer is deposited across the sacrificial material layer, and so on. The sacrificial material layer and the insulating material layer may have the same thickness or different thicknesses. In some embodiments, a sacrificial material layer and the underlying insulating material layer are referred to as a dielectric pair 107. In some embodiments, one or more dielectric pairs 107 can form one level / staircase. During the formation of the staircase structure, the PR layer is cut away (e.g., often etched stepwise inward from the boundaries of the material stack from all directions) and used as an etching mask for etching an exposed portion of the material stack. The amount of PR cut away can be directly related (e.g., can be a determining factor) to the dimensions of the staircase. The cutting away of the PR layer can be obtained using a suitable etching such as isotropic dry etching, e.g., wet etching. One or more PR layers can be continuously formed and cut away for the formation of the staircase structure. Each dielectric pair 107 can be etched after the cutting away of the PR layer using a suitable etching solution to remove a portion of both the sacrificial material layer and the underlying insulating material layer. The etched sacrificial material layer and insulating material layer can form an initial sacrificial layer (e.g., reference numerals 103i, 105i, and 106i) and an initial insulating layer 104i. Next, the PR layer can be removed.

[0040] The insulating material layer and the sacrificial material layer may have different etching selectivities during a subsequent gate replacement process. In some embodiments, the insulating material layer and the sacrificial material layer comprise different materials. In some embodiments, the insulating material layer comprises silicon oxide, and the deposition of the insulating material layer includes one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering. In some embodiments, the sacrificial material layer comprises silicon nitride, and the deposition of the sacrificial material layer includes one or more of CVD, PVD, ALD, and sputtering. In some embodiments, the etching of the sacrificial material layer and the insulating material layer includes one or more suitable anisotropic etching processes, such as dry etching.

[0041] Referring back to FIG. 14A, a plurality of support openings are formed to be arranged along a lateral direction, and the length of the support openings is smaller than the length of the source structure (step 1404). Optionally, a cutting opening extending along the lateral direction is formed. FIGS. 3A-3D show the corresponding structure 300.

[0042] As shown in FIGS. 3A to 3D, at least one support opening 109 is formed in the second source region 22. In some embodiments, a plurality of support openings 109 are formed in respective second source regions 22 along the x-direction, spaced apart from each other. Along the x-direction, the length of the support opening 109 can be smaller than the length of the second source structure to be formed (or the length of the second source region 22, or the length of the slit structure in which the second source structure is formed). The plurality of support openings 109 can have the same or different dimensions. In some embodiments, the plurality of support openings 109 may have the same shape and dimensions along the x-y plane and the same depth along the z-direction. Along the y-direction, the width of the support opening 109 can be equal to or greater than the width of the second source region 22. In some embodiments, the bottom surface of the support opening 109 can be between the top surface and the bottom surface of the topmost initial insulating layer 104i (e.g., the initial insulating layer 104i under the topmost initial sacrificial layer 106i). For example, a suitable patterning process such as an etching process such as dry etching and / or wet etching can be implemented to form the support opening 109.

[0043] In some embodiments, one or more cutting openings 108 extending along the x-direction can be formed by the same patterning / etching process that forms the support opening 110. Along the x-direction, the length of the cutting opening 108 can be the same as the length of the channel region 41 (e.g., or the core region 31) along the x-direction. One or more cutting openings 108 can be formed in one block region 21, for example, depending on the number of memory fingers formed in the memory block. In some embodiments, the bottom surface of the cutting opening 108 can be between the top surface and the bottom surface of the topmost initial insulating layer 104i (e.g., the initial insulating layer 104i under the topmost initial sacrificial layer 106i). In some embodiments, the depth of the support opening 109 is the same as the depth of the cutting opening 108 along the vertical direction. For example, the bottom surfaces of the support opening 109 and the cutting opening 108 are at the same height as the topmost initial insulating layer 104i.

[0044] Referring back to FIG. 14A, the support openings are filled with a dielectric material (step 1406) to form a split structure that connects adjacent block regions. Optionally, any cut openings are filled with a dielectric material to form a cut structure in each block region. FIGS. 4A - 4D illustrate the corresponding structure 400.

[0045] As shown in FIGS. 4A - 4D, the support openings 109 can be filled with a suitable material to form a split structure 112. The split structure 112 can have sufficient rigidity and strength to function as an etching mask for forming a slit structure prior to the formation of the second source structure. The split structure 112 can also withstand a gate replacement process for the formation of conductor layers (e.g., reference numerals 127 - 129) and conductor portions (e.g., reference numerals 127-0 and 128-0). In some embodiments, the split structure 112 can include a material different from the sacrificial layer so that it is hardly or not damaged at all during a gate exchange process in which the sacrificial layer is etched away. In some embodiments, the split structure 112 includes one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. The split structure 112 can be deposited by a suitable deposition process such as CVD, ALD, PVD, sputtering, or a combination thereof. Optionally, the cut openings 108 may be filled with the same material that fills the support openings 109 using the same deposition process. A cut structure 111 extending along the x - direction may be formed.

[0046] Referring back to FIG. 14A, a plurality of channel structures are formed (step 1408). FIGS. 7A and 7B illustrate the corresponding structure 700.

[0047] As shown in FIGS. 7A and 7B, a plurality of channel structures 140 can be formed in the channel regions 41, for example, in each block region 21. A plurality of channel holes extending vertically through the stack structure 11 can be formed. In some embodiments, the plurality of channel holes are formed through alternating initial sacrificial layers (e.g., reference numerals 103i, 105i, and 106i) and the initial insulating layer 104i. The plurality of channel holes can be formed by performing an anisotropic etching process using an etching mask such as a patterned PR layer to remove a portion of the stack structure 11 to expose the substrate 100. In some embodiments, at least one channel hole is formed on each side of the split structure 112 along the y direction. In some embodiments, a plurality of channel holes are formed in each block region 21. A recess region can be formed at the bottom of each channel hole to expose the uppermost portion of the substrate 100 by the same etching process that forms the channel holes above the substrate 100 and / or by another recess etching process. In some embodiments, a semiconductor plug is formed at the bottom of each channel hole, for example, across the recess region. The semiconductor plug can be formed by an epitaxial growth process and / or a deposition process. In some embodiments, the semiconductor plug is formed by epitaxial growth and is referred to as an epitaxial portion 115. Optionally, recess etching (e.g., dry etching and / or wet etching) can be performed to remove excess semiconductor material on the sidewalls of the channel holes and / or to control the upper surface of the epitaxial portion 115 at a desired position. In some embodiments, the upper surface of the epitaxial portion 115 is positioned between the upper and lower surfaces of the lowermost initial insulating layer 104i.

[0048] In some embodiments, the channel hole is formed by performing a suitable etching process, such as, for example, an anisotropic etching process (e.g., dry etching) and / or an isotropic etching process (wet etching). In some embodiments, the epitaxial portion 115 comprises single crystal silicon formed by epitaxial growth from the substrate 100. In some embodiments, the epitaxial portion 115 comprises polysilicon formed by a deposition process. The formation of the epitaxially grown epitaxial portion 115 may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or any combination thereof. The formation of the deposited epitaxial portion 115 may include, but is not limited to, CVD, PVD, and / or ALD.

[0049] In some embodiments, the semiconductor channel 119 is formed across the epitaxial portion 115 in the channel hole and is in contact with the epitaxial portion 115. The semiconductor channel may comprise a channel formation structure having a memory film 116 (e.g., including a block layer, a memory layer, and a tunnel layer), a semiconductor layer 117 formed above the epitaxial portion 115 and connected to the epitaxial portion 115, and a dielectric core 118 filling the remainder of the channel hole. In some embodiments, the memory film 116 is first deposited to cover the sidewalls of the channel hole and the top surface of the epitaxial portion 115, and then the semiconductor layer 117 is deposited over the epitaxial portion 115 across the memory film 116. Subsequently, the block layer, the memory layer, and the tunnel layer may be deposited in this order using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film 116. Next, the semiconductor layer 117 may be deposited on the tunnel layer using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the dielectric core 118 is filled in the remaining space of the channel hole by depositing a dielectric material after the deposition of the semiconductor layer 117, such as silicon oxide.

[0050] In some embodiments, the drain structure 120 is formed above the upper portion of each channel hole. In some embodiments, a portion of the upper surface of the stack structure 11 and the memory film 116, semiconductor layer 117, and dielectric core 118 in the upper portion of each channel hole are removed by CMP, grinding, wet etching, and / or dry etching to form a recess in the upper portion of the channel hole so that the upper surface of the semiconductor channel can be between the upper and bottom surfaces of the dielectric cap layer 105. Next, the drain structure 120 can be formed by depositing a conductive material such as metal into the recess by one or more thin film deposition processes such as CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof. Thereby, the channel structure 140 is formed. Subsequently, a plurality of memory cells can be formed by the intersection of the semiconductor channel 119 and the control conductor layer 127. Optionally, a planarization process such as dry / wet etching and / or CMP is performed to remove excess material on the upper surface of the stack structure 11.

[0051] Referring back to FIG. 14A, a plurality of split structures can be used as an etching mask to form a slit structure with a plurality of slit openings divided by the plurality of split structures (step 1410). FIGS. 9A-9E show the corresponding structure 900.

[0052] As shown in FIGS. 9A to 9E, a slit structure 123 having a plurality of slit openings can be formed in a second source region 22 extending along the x direction. Along the x direction, adjacent slit openings can be separated by a split structure 112 and the remaining portion of the stack structure 11 covered under the split structure 112 by the split structure 112. The slit openings can extend vertically through the stack structure 11 to expose the substrate 100. The patterned / etched initial sacrificial layer forms a plurality of sacrificial layers in the block region 21 and a plurality of sacrificial portions covered under the split structure 112 by the split structure 112. Each sacrificial portion can contact, for example, be connected to, a sacrificial layer of the same height in an adjacent block region 21 along the y direction. The patterned / etched initial insulating layer forms a plurality of insulating layers 104 in the block region 21 and a plurality of insulating portions 104-0 covered under the split structure 112 by the split structure 112. Each insulating portion 104-0 can contact, for example, be connected to, an insulating layer 104 of the same height in an adjacent block region 21 along the y direction. The plurality of insulating portions 104-0 and the plurality of sacrificial portions extending from under each split structure 112 to the substrate 100 can be alternated with each other.

[0053] The width of the split structure 112 along the y direction may be equal to or greater than the width of each slit structure 123 (e.g., adjacent slit openings) along the y direction. FIG. 13A shows an enlarged plan view 1310 of the split structure 112 and adjacent slit openings. As shown in FIG. 13A, the width d2 of the split structure 112 along the y direction is equal to or greater than the width d1 of the slit structure 123 along the y direction. In some embodiments, d2 is greater than d1. In some embodiments, by making d2 greater than d1, during the formation of the slit structure 123, the alternating sacrificial and insulating portions 104-0 are prevented from being connected to the adjacent block regions 21. That is, the split structure 112 can keep adjacent memory blocks connected through the alternating sacrificial and insulating portions 104-0 during the formation of the slit structure 123. In some embodiments, the split structure 112 is used as an etching mask, and an anisotropic etching process, such as dry etching, is performed to remove a portion of the stack structure 11 in the second source region 22 to form the slit structure 123. The remaining portion of the stack structure 11 in the second source region 22 can form alternating sacrificial and insulating portions. The split structure 112 and the underlying alternating sacrificial and insulating portions 104-0 can form an initial support structure.

[0054] Referring back to FIGS. 9A-9E, in some embodiments, one or more other slit structures 124 can be formed in the first source region 23 by the same patterning / etching process that forms the slit openings of the slit structure 123. For example, each other slit structure 124 having a single slit opening can extend through the stack structure 11 along the x direction to expose the substrate 100. In some embodiments, the other slit structures 124 can extend in the core region 31 and the staircase region 32.

[0055] Referring back to FIG. 14A, a plurality of conductor layers, a plurality of memory blocks, and a plurality of support structures connecting adjacent memory blocks are formed (step 1412). FIGS. 9A-9E show corresponding structures.

[0056] As shown in FIGS. 9A to 9E, the sacrificial layer in the block region 21 and the sacrificial portions in the second source region 22 can be removed to form a plurality of horizontal recesses, and a suitable conductor material can be deposited to fill the horizontal recesses, and a plurality of conductor layers (e.g., reference numerals 127 to 129) are formed in the block region 21, and a plurality of conductor portions (e.g., 127-0 and 128-0) are formed in the second source region 22. A support structure 152 having a split structure 112, underlying alternating conductor portions (e.g., reference numerals 127-0 and 128-0), and an insulating portion 104-0 can be formed. The control conductor layer 127 can intersect the semiconductor channel 119, and a plurality of memory cells can be formed in each block region 21 forming a memory block. In some embodiments, the top sacrificial layer in the block region 21 may form the top conductor layer 129, and the bottom sacrificial layer in the block region 21 may form the bottom conductor layer 128. In some embodiments, the initial support structure may form the support structure 152.

[0057] The conductor material can include one or more of tungsten, aluminum, copper, cobalt, silicide, and polysilicon. A suitable isotropic etching process, such as wet etching for example, can be implemented to remove the sacrificial layer and the sacrificial portions, and to form a plurality of horizontal recesses. A suitable deposition process such as CVD, PVD, ALD, and / or sputtering can be implemented to deposit the conductor material into the horizontal recesses to form the conductor layers (e.g., reference numerals 127 to 129) and the conductor portions (e.g., reference numerals 127-0 and 128-0).

[0058] Referring back to FIG. 14A, a source structure is formed in each slit structure (step 1414). FIGS. 10A to 10E show the corresponding structure 1000.

[0059] As shown in FIGS. 10A - 10E, the insulating structure 136 can be formed in each slit opening of the slit structure 123, and the source contact 125 can be formed in each insulating structure 136. The insulating structure 136 and the source contact 125 in each second source region 22 can form a second source structure. The insulating structure 137 can be formed in each other slit structure 124, and the source contact 126 can be formed in each other slit structure 124. The insulating structure 137 and each source contact 126 can form a first source structure. The support structure 152 can separate adjacent source contacts 125 and the insulating structure 136 along the x - axis and can connect adjacent memory blocks along the y - direction. In some embodiments, the insulating structures 136 and 137 include silicon oxide and are deposited by one or more of CVD, PVD, ALD, and sputtering. Reactive ion etching can be performed to remove a portion of the insulating structures 136 and 137 at the bottom of each slit structure to expose the substrate 100. In some embodiments, the source contacts 125 and 126 each include one or more of tungsten, aluminum, copper, cobalt, silicide, and polysilicon, and an appropriate deposition process, such as one or more of CVD, PVD, ALD, and sputtering, is performed to deposit the source contacts 125 and 126 into their respective slit structures.

[0060] Referring back to FIG. 14A, an insulator is formed in the stepped region, and one or more contact plugs are formed in the insulator to contact the conductor layer (step 1416). FIGS. 11 and 12 show the corresponding structures 1100 and 1200.

[0061] As shown in FIGS. 11 and 12, an insulator 130 can be formed in the stepped region 32 to cover the steps (e.g., conductor layers 127-129) and insulate the contact plugs 131 from each other. One or more contact plugs 131 are formed in the insulator 130 to contact the conductor layers 127-129 and form a conductive connection. In some embodiments, the insulator 130 includes silicon oxide and is deposited by one or more of CVD, PVD, ALD, and sputtering. An appropriate anisotropic etching process, such as dry etching, can be performed to form one or more plug openings through the insulator 130 and expose one or more conductor layers (e.g., reference numerals 127, 128, and / or 129). An appropriate conductive material, such as tungsten, is deposited to fill the plug openings. In some embodiments, at least one contact plug is formed in one conductor layer (e.g., reference numerals 127, 128, and / or 129). Optionally, a planarization process, such as CMP and / or recess etching, is performed to remove any excess material from the stack structure 11, e.g., from the formation of various structures.

[0062] In some embodiments, FIGS. 2, 5, 6, and 8-12 illustrate another fabrication process for forming the 3D memory device 150, and FIG. 14B shows a flowchart 1450 of the fabrication process. Different from the fabrication processes shown in FIGS. 2-4, 7, and 9-12, one or more initial split structures are formed and etched to form one or more split structures. For ease of illustration, the same or similar steps shown in FIGS. 2-4, 7, and 9-12 are not described repeatedly.

[0063] At the start of the process, a stack structure of alternating multiple initial insulating layers and multiple initial sacrificial layers is formed (step 1452). FIGS. 2A-2D show the corresponding structure 200. The description of the fabrication process and structure 200 can refer to the description of step 1402 and will not be repeated here.

[0064] Referring back to FIG. 14B, a plurality of support openings extending along the horizontal direction can be formed, and the length of the support openings is equal to the length of the source structure (step 1454). Optionally, a cutting opening extending along the horizontal direction is formed. FIGS. 5A-5C show the corresponding structure 500.

[0065] As shown in FIGS. 5A-5C, the support opening 110 is formed in the second source region 22. Along the x direction, the length of the support opening 110 can be equal to the length of the second source structure to be formed (or the length of the second source region 22, or the length of the slit structure in which the second source structure is formed). Along the y direction, the width of the support opening 109 can be greater than or equal to the width of the second source region 22. In some embodiments, the bottom surface of the support opening 110 can be between the top and bottom surfaces of the first initial insulating layer 104i (e.g., the initial insulating layer 104i) under the topmost initial sacrificial layer 106i. Optionally, one or more cutting openings 108 are formed in the block region 21. The fabrication of the support opening 110 and any cutting openings 108 can refer to the fabrication of the support opening 109 and cutting openings 108 depicted in FIGS. 3A-3D, which will not be repeated here. In some embodiments, the depth of the support opening 110 is the same as the depth of the cutting opening 108 along the vertical direction, e.g., the bottom surfaces of the support opening 110 and the cutting opening 108 are at the same height as the topmost initial insulating layer 104i.

[0066] Referring back to FIG. 14B, the support openings are filled with a dielectric material to form an initial split structure connecting adjacent block regions (step 1456). Optionally, any cutting openings are filled with a dielectric material to form a cutting structure in the block region. FIGS. 6A-6C show the corresponding structure 600.

[0067] As shown in FIGS. 6A-6C, a dielectric material can be deposited to fill the support opening 110 and form an initial split structure 113. In some embodiments, the initial split structure 113 is positioned between adjacent block regions 21. In some embodiments, the length of the initial split structure 113 is equal to the length of the second source structure or the slit structure to be formed. Any cut openings can be filled with a dielectric material to form a cut structure 111 in each block region. The deposition of the dielectric material to form the initial split structure 113 and any cut structures 111 can be referred to the formation of the split structure 112 and cut structures 111 depicted in FIGS. 4A-4C and will not be repeated here.

[0068] Referring back to FIG. 14B, a plurality of channel structures can be formed (step 1458). FIGS. 8A and 8B show the corresponding structure 800.

[0069] As shown in FIGS. 8A and 8B, a plurality of channel structures 140 can be formed in the channel region 41. In some embodiments, at least one channel structure 140 is formed on each side of the initial split structure 113 along the y direction. In some embodiments, a plurality of channel structures 140 are formed in each block region 21. The formation of the channel structures 140 can be referred to the formation of the channel structures 140 depicted in FIGS. 7A and 7B and will not be repeated here.

[0070] Referring back to FIG. 14B, an initial support structure having a split structure is formed (step 1460). A portion of the initial split structure can be removed to form a split structure, and the split structure can be used as an etching mask to remove a portion of the stack structure and to form the initial support structure. FIGS. 9A-9E show the corresponding structure 900.

[0071] As shown in FIGS. 9A - 9E, a portion of the initial split structure 113 can be removed to form one or more split structures 112 arranged along the x - direction and expose a portion of the stack structure 11. In some embodiments, the top - most initial insulating layer 104i is exposed. The split structure 112 can be used as an etching mask to remove a portion of the stack structure 11 that is exposed in the second source region 22 to form a slit structure 123 with a plurality of unconnected slit openings that expose the substrate 100. The initial split structure 113 and the stack structure 11 can be pattern - formed / etched using the same pattern - formation / etching process, or a different pattern - formation / etching process. For example, first, the initial split structure 113 can be pattern - formed to form the split structure 112, and a different etching process can be performed to remove the exposed portion of the stack structure 11 and form the slit openings of the slit structure 123 and one or more initial support structures. Alternatively, the initial split structure 113 and a portion of the stack structure 11 below the initial split structure 113 can be pattern - formed using the same etching process to form the slit openings of the slit structure 123 and one or more initial support structures. In some embodiments, the initial split structure 113 and the stack structure 11 are pattern - formed using the same etching process to reduce the steps and time of the pattern - formation process. The initial split structure 113 and the stack structure 11 can be pattern - formed / etched using one or more suitable etching processes, such as dry etching and / or wet etching. Details of the initial support structure can be referred to the description of the initial support structure depicted in FIGS. 9A - 9E of the flowchart 1400 and will not be repeated here.

[0072] Referring back to FIG. 14B, a plurality of conductor layers, a plurality of memory blocks, and a support structure are formed (step 1462), and a source structure is formed in each slit structure (step 1464). Insulators and contact plugs are formed in the stepped region (step 1466). FIGS. 9 to 12 show the corresponding structures 900 to 1200. The detailed description of steps 1462 to 1466 can refer to the description of steps 1412 to 1416, which will not be repeated here.

[0073] In some embodiments, a 3D memory device comprises a memory stack having a plurality of alternating conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device further comprises a plurality of channel structures extending vertically through the memory stack to a substrate, wherein the plurality of channel structures intersect with the plurality of conductor layers to form a plurality of memory cells. The 3D memory device further comprises at least one slit structure extending vertically and laterally in the memory stack, dividing the plurality of memory cells into at least one memory block, and comprising a plurality of slit openings and a support structure between adjacent slit openings. The support structure contacts adjacent memory blocks and contacts the substrate. The 3D memory device further comprises a source structure having an insulating spacer in each of the plurality of slit openings and a source contact in each respective insulating spacer.

[0074] In some embodiments, the support structure extends vertically through the memory stack to the substrate and is insulated from adjacent source contacts by respective insulating spacers of the adjacent source contacts.

[0075] In some embodiments, the support structure comprises a segmented structure over a plurality of alternating conductor portions and a plurality of insulating portions. The segmented structure can extend laterally to connect adjacent memory blocks and extends vertically to a first insulating layer of the memory stack. The plurality of alternating conductor portions and the plurality of insulating portions each contact corresponding conductor layers and corresponding insulating layers at the same altitude from adjacent memory blocks.

[0076] In some embodiments, the width of the split structure is greater than or equal to the width of each of the adjacent slit openings along another lateral direction perpendicular to the lateral direction along which at least one slit structure extends.

[0077] In some embodiments, the split structure includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0078] In some embodiments, the plurality of conductor portions includes at least one of tungsten, aluminum, copper, cobalt, silicide, or polysilicon. In some embodiments, the plurality of insulating portions includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0079] In some embodiments, the plurality of conductor portions are made of the same material as the conductor layer of the adjacent memory block, and the plurality of insulating portions are made of the same material as the insulating layer of the adjacent memory block.

[0080] In some embodiments, the source contacts each include at least one of tungsten, aluminum, copper, cobalt, silicide, or polysilicon.

[0081] In some embodiments, the 3D memory device further includes a cutting structure that extends horizontally and vertically parallel to the slit structure in at least one memory block and divides the at least one memory block into a plurality of memory fingers.

[0082] In some embodiments, the cutting structure extends vertically into the first insulating layer of the memory stack and includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. The depth of the cutting structure can be the same as the depth of the split structure.

[0083] In some embodiments, the plurality of channel structures each comprise an epitaxial portion, a semiconductor channel, and a drain structure, the epitaxial portion is conductively connected to the substrate, the semiconductor channel is conductively connected to the epitaxial portion and the dielectric cap layer, and the drain structure is conductively connected to the semiconductor channel.

[0084] In some embodiments, the upper surface of the semiconductor channel is between the upper and lower surfaces of the dielectric cap layer across a plurality of alternating conductor layers and a plurality of insulating layers, the upper surface of the epitaxial portion is between the upper and lower surfaces of the lowermost insulating layer, and the semiconductor channel comprises a block layer, a memory layer, a tunnel layer, a semiconductor layer, and a dielectric core arranged inward from the sidewalls of the semiconductor channel toward the center.

[0085] In some embodiments, a method for forming a 3D memory device includes forming a dielectric stack comprising a plurality of alternating initial insulating layers and a plurality of initial sacrificial layers across a substrate, and forming at least one slit structure that extends vertically and horizontally in the dielectric stack and divides the dielectric stack into a plurality of block regions. The at least one slit structure each comprises a plurality of slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each of the plurality of block regions may comprise a plurality of alternating insulating layers and a plurality of sacrificial layers, and the initial support structure may comprise a plurality of alternating insulating portions and a plurality of sacrificial portions. Each of the plurality of insulating portions and the plurality of sacrificial portions may contact respective insulating layers and sacrificial layers at the same height from adjacent block regions. In some embodiments, the method also includes forming a plurality of channel structures extending vertically through the dielectric stack, replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions through the at least one slit structure, and forming a source structure in each of the slit structures. The source structure may comprise an insulating spacer at each of the plurality of slit openings and a source contact at each of the insulating spacers.

[0086] In some embodiments, the step of forming at least one slit structure includes patterning the dielectric stack to form support openings along a lateral direction in which each slit structure extends. The length of the support opening can be less than the length of the slit structure along the lateral direction. The bottom of the support opening can be between the top and bottom surfaces of the first initial insulating layer of the dielectric stack. The step of forming at least one slit structure also includes depositing a dielectric material to fill the support opening and form a split structure.

[0087] In some embodiments, the step of forming at least one slit structure includes removing a portion of the dielectric stack adjacent to the split structure along a lateral direction to form a pair of slit openings that expose the substrate. The width of each of the pair of slit openings can be less than or equal to the width of the split structure along another lateral direction perpendicular to the lateral direction. In some embodiments, the split structure, and the remaining alternating sacrificial and insulating portions below the split structure, form an initial support structure.

[0088] In some embodiments, the step of removing a portion of the dielectric stack includes etching a portion of the dielectric stack adjacent to the split structure and using the split structure as an etch mask to retain the alternating sacrificial and insulating portions below the split structure.

[0089] In some embodiments, the step of forming a plurality of channel structures includes forming at least one channel structure on each side of the split structure along another lateral direction.

[0090] In some embodiments, the step of forming at least one slit structure includes patterning the dielectric stack to form support openings along the lateral direction in which each slit structure extends. The length of the support openings can be equal to the length of the slit structures along the lateral direction. The bottom of the support openings can be between the top and bottom surfaces of the first initial insulating layer of the dielectric stack. In some embodiments, the step of forming at least one slit structure also includes depositing a dielectric material to fill the support openings and form an initial split structure.

[0091] In some embodiments, the step of forming at least one slit structure further includes removing, along the lateral direction of the initial split structure, a pair of second portions adjacent to the first portion to expose a portion of the dielectric stack under the second portions. In some embodiments, the step of forming at least one slit structure also includes removing an exposed portion of the dielectric stack to expose the substrate and to form a pair of slit openings. The width of each of the pair of slit openings can be less than or equal to the width of the initial split structure along another lateral direction perpendicular to the lateral direction. The remaining first portion of the initial split structure can form a split structure. The split structure, together with the remaining alternating sacrificial and insulating portions under the split structure, can form an initial support structure.

[0092] In some embodiments, the step of removing an exposed portion of the dielectric stack includes etching a portion of the dielectric stack adjacent to the split structure and using the split structure as an etching mask to retain the alternating conductor and insulating portions under the split structure.

[0093] In some embodiments, the step of forming a plurality of channel structures includes forming at least one channel structure on both sides of the initial split structure along another lateral direction.

[0094] In some embodiments, the step of replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions through at least one slit structure includes removing the plurality of sacrificial portions of the initial support structure and the plurality of sacrificial layers of the plurality of block regions in the same etching process to form a plurality of lateral recesses. The step of replacing the plurality of sacrificial layers and the plurality of sacrificial portions may also include depositing a conductor material into the plurality of lateral recesses in the same deposition process. The plurality of conductor layers and the plurality of channel structures can form a plurality of memory cells. The plurality of block regions can form a plurality of memory blocks. The split structure and the alternating conductor and insulating portions below can form a support structure.

[0095] In some embodiments, the method further includes forming a cut structure in at least one of the plurality of block regions, the cut structure extending parallel to at least one slit structure and dividing at least one of the plurality of memory blocks into a plurality of memory fingers.

[0096] In some embodiments, the step of forming the cut structure includes forming a cut opening in at least one of the plurality of block regions in the same patterning process as forming the support opening. The cut opening can extend parallel to at least one slit structure. The bottom surface of the cut opening can be between the top and bottom surfaces of the first initial insulating layer. In some embodiments, the step of forming the cut structure also includes depositing a dielectric material to fill the cut opening in the same deposition process as filling the support opening to form the cut structure.

[0097] In some embodiments, the step of forming a plurality of channel structures includes forming a plurality of channel holes that vertically extend from a dielectric cap layer across a dielectric stack to a substrate, and forming an epitaxial portion in each of the plurality of channel holes. The epitaxial portion may be conductively connected to the substrate. In some embodiments, the step of forming a plurality of channel structures also includes forming a semiconductor channel across the epitaxial portion, and forming a drain structure across the semiconductor channel. The drain structure may be conductively connected to the semiconductor channel. The semiconductor may be conductively connected to the epitaxial portion.

[0098] In some embodiments, a method for forming a 3D memory device includes forming, across a substrate, a dielectric stack of alternating pluralities of initial insulating layers and pluralities of initial sacrificial layers; forming a dielectric structure that extends laterally along the dielectric stack, the dielectric structure vertically extending to a first initial insulating layer; patterning the dielectric stack using the dielectric structure as an etch mask to form a slit structure that vertically and laterally extends through the dielectric stack and divides the dielectric stack into pairs of block regions. The slit structure may include a plurality of slit openings that expose the substrate, and a plurality of initial support structures between adjacent slit openings. Each of the plurality of block regions may include alternating pluralities of insulating layers and pluralities of sacrificial layers, and each of the plurality of initial support structures may include alternating pluralities of insulating portions and pluralities of sacrificial portions. Each of the plurality of insulating portions and the plurality of sacrificial portions may contact respective insulating layers and sacrificial layers of the same height from adjacent block regions. The method may also include forming a plurality of channel structures that vertically extend through the dielectric stack, replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions through at least one slit structure, and forming a source structure in each of the slit structures. The source structure may include an insulating spacer in each of the plurality of slit openings, and a source contact in each respective insulating spacer.

[0099] In some embodiments, the dielectric structure comprises a plurality of divided structures that are not connected to each other, and the step of forming the dielectric structure includes patterning a dielectric stack to form a plurality of support openings along a lateral direction. The length of each of the plurality of support openings can be less than the length of the slit structure along the lateral direction. The plurality of support openings may not be connected to each other, and may have a bottom surface between the top and bottom surfaces of the first initial insulating layer. In some embodiments, the step of forming the dielectric structure also includes depositing a dielectric material to fill the plurality of support openings and form the plurality of divided structures.

[0100] In some embodiments, the step of forming at least one slit structure includes removing a portion of the dielectric stack adjacent to each of the plurality of divided structures along a lateral direction to form a plurality of slit openings. The width of each of the plurality of slit openings can be less than or equal to the width of the divided structure along another lateral direction perpendicular to the lateral direction. In some embodiments, the step of forming at least one slit structure also includes a divided structure, and the remaining alternating sacrificial and insulating portions below the divided structure form an initial support structure.

[0101] In some embodiments, the step of removing a portion of the dielectric stack includes etching a portion of the dielectric stack adjacent to the divided structure and using the divided structure as an etching mask to retain the alternating sacrificial and insulating portions below the divided structure.

[0102] In some embodiments, the step of forming a plurality of channel structures includes forming at least one channel structure on both sides of the dielectric structure along another lateral direction.

[0103] In some embodiments, the dielectric structure comprises one initial segmentation structure, and the step of forming the dielectric structure includes patterning a dielectric stack to form a support opening extending along a lateral direction. The length of the support opening can be equal to the length of the slit structure along the lateral direction, and the bottom of the support opening can be between the top surface and the bottom surface of the first initial insulating layer of the dielectric stack. In some embodiments, the step of forming the dielectric structure also includes depositing a dielectric material to fill the support opening and form the initial segmentation structure.

[0104] In some embodiments, the step of forming at least one slit structure further includes removing a pair of second portions adjacent to the first portion along the lateral direction of the initial segmentation structure to expose a portion of the dielectric stack under the second portions. In some embodiments, the step of forming at least one slit structure also includes removing an exposed portion of the dielectric stack to expose the substrate and to form a pair of slit openings. The width of each of the pair of slit openings can be less than or equal to the width of the initial segmentation structure along another lateral direction perpendicular to the lateral direction. The remaining first portion of the initial segmentation structure can form a segmentation structure. The segmentation structure and the remaining alternating sacrificial portions and insulating portions under the segmentation structure can form an initial support structure.

[0105] In some embodiments, the step of removing an exposed portion of the dielectric stack includes etching a portion of the dielectric stack adjacent to the segmentation structure and using the segmentation structure as an etching mask to retain the alternating conductor portions and insulating portions under the segmentation structure.

[0106] In some embodiments, the step of forming a plurality of channel structures includes forming at least one channel structure on both sides of the initial segmentation structure along another lateral direction.

[0107] In some embodiments, the step of replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions includes removing the plurality of sacrificial portions of the initial support structure and the plurality of sacrificial layers of the plurality of block regions in the same etching process to form a plurality of lateral recesses. In some embodiments, the step of replacing the plurality of sacrificial layers and the plurality of sacrificial portions with a plurality of conductor layers and a plurality of conductor portions also includes depositing a conductor material into the plurality of lateral recesses in the same deposition process. The plurality of conductor layers and the plurality of channel structures can form a plurality of memory cells. The plurality of block regions can form a plurality of memory blocks. The divided structure and the alternating conductor portions and insulating portions thereunder can form a support structure.

[0108] In some embodiments, the method further includes forming a cutting structure in at least one of the plurality of block regions. The cutting structure can extend parallel to at least one slit structure and divide at least one of the plurality of memory blocks into a plurality of memory fingers.

[0109] In some embodiments, the step of forming the cutting structure includes forming a cutting opening in at least one of the plurality of block regions in the same patterning process as forming the support opening. The cutting opening can extend parallel to at least one slit structure, and the bottom surface of the cutting opening can be between the top and bottom surfaces of the first initial insulating layer. In some embodiments, the step of forming the cutting structure also includes depositing a dielectric material to fill the cutting opening in the same deposition process as filling the support opening to form the cutting structure.

[0110] In some embodiments, the step of forming a plurality of channel structures includes forming a plurality of channel holes that vertically extend from the dielectric cap layer across the dielectric stack to the substrate, forming an epitaxial portion in each of the plurality of channel holes, wherein the epitaxial portion is conductively connected to the substrate, forming a semiconductor channel across the epitaxial portion, wherein the semiconductor is conductively connected to the epitaxial portion, and forming a drain structure across the semiconductor channel, wherein the drain structure is conductively connected to the semiconductor channel.

[0111] The foregoing description of specific embodiments discloses the general nature of the present disclosure so that others may, by applying the knowledge of those skilled in the art, readily modify and / or adapt such specific embodiments for various applications without departing from the broad concepts of the present disclosure, without undue experimentation. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based upon the teachings and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be understood by those skilled in the art in light of the teachings and guidance herein.

[0112] Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of specific functions and relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined as long as the specified functions and relationships are appropriately implemented.

[0113] The summary and abstract sections can identify one or more exemplary embodiments of the disclosure that are not necessarily all considered by the inventors, and are therefore not intended to limit the disclosure, or the appended claims, in any way.

[0114] The scope and extent of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Description of Reference Numerals

[0115] 11 Stack structure 21 Block region 22 Second source region 23 First source region 31 Core region 32 Staircase region 41 Channel region 100 Substrate 101 Buffer oxide layer 102 Substrate 103i Initial sacrificial layer 104 Insulating layer 104-0 Insulating portion 104i Initial insulating layer 105 Dielectric cap layer 105i Lowermost initial sacrificial layer 106i Uppermost initial sacrificial layer 107 Pair of dielectrics 108 Cut opening 109, 110 Support openings 111 Cut structure 112 Division structure 113 Initial division structure 115 Epitaxial portion 116 Memory film 117 Semiconductor layer 118 Dielectric core 119 Semiconductor channel 120 Drain structure 123, 124 Slit structures 125, 126 Source contacts 127 Control conductor layer 127-0, 128-0 Conductor portions 128 Lowermost conductor layer 129 Uppermost conductor layer 130 Insulator 131 Contact plug 136 and 137 Insulation Structure 140 Channel Structure 145 Dielectric Cap Layer 150 3D Memory Device 152 Support Structure Structures 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200 1310 Enlarged Plan View 1320 Enlarged Plan View 1400 Flow Chart 1450 Flow Chart d1 Width of the Second Source Structure d2 Width of the Split Structure

Claims

1. A stack comprising a plurality of alternating conductor layers and a plurality of insulating layers extending in a lateral direction, a plurality of channel structures extending vertically through the stack, a plurality of first structures extending vertically and laterally in the stack, wherein one of the plurality of first structures includes at least two portions, a split structure between two adjacent portions of the one structure of the plurality of first structures, the split structure extending vertically through a part of the stack, a cut structure extending vertically through only a part of the stack between adjacent first structures, and a three-dimensional (3D) memory device comprising the same.

2. The 3D memory device according to claim 1, wherein one of the two portions of the one structure of the plurality of first structures includes a source contact and an insulating spacer surrounding the source contact.

3. The plurality of conductor layers includes a first conductor layer, the first conductor layer including a first portion and a second portion located on two sides of one of the plurality of first source structures, and a third portion located under the split structure, and the first portion and the second portion are connected by the third portion. The 3D memory device according to claim 1.

4. The 3D memory device according to claim 1, wherein a part of the plurality of alternating conductor layers and the plurality of insulating layers is under the split structure.

5. The 3D memory device according to claim 1, wherein along another lateral direction perpendicular to the lateral direction, the width of the split structure is equal to or greater than the width of one of the two adjacent portions of the one structure of the plurality of first structures.

6. The 3D memory device according to claim 1, further comprising a core region and a stepped region in the lateral direction.

7. The 3D memory device according to claim 6, wherein the first structure extends laterally in the core region and the stepped region, and the cut structure extends laterally in the core region.

8. The 3D memory device according to claim 6, further comprising a second structure extending vertically and laterally in the stack, and two portions of a plurality of conductor layers located on two sides of the second structure are separated.

9. The 3D memory device according to claim 8, wherein the second structure extends laterally in the core region and the stepped region.

10. The 3D memory device according to any one of claims 1 to 9, wherein the plurality of first structures include a plurality of source structures.

11. The 3D memory device according to claim 8, wherein the second structure includes a source structure.

12. The 3D memory device according to claim 6, wherein the dividing structure is in the core region.

13. The 3D memory device according to claim 2, further comprising a substrate located on one side of the stack, wherein the source contact is connected to the substrate.

14. Forming a stack including a plurality of alternating conductor layers and a plurality of insulating layers extending in a lateral direction; Forming a plurality of channel structures extending vertically through the stack; Forming a plurality of first structures each extending vertically and laterally in the stack, wherein one of the plurality of first structures includes at least two portions, the step of forming a plurality of first structures; Forming a dividing structure between two adjacent portions of the one structure among the plurality of first structures, the dividing structure extending vertically through a part of the stack, the step of forming a dividing structure; Forming a cutting structure extending vertically only through a part of the stack between adjacent first structures; A method for forming a three-dimensional (3D) memory device, comprising:

15. The step of forming the stack and the step of forming the first source structure Forming a dielectric stack including a plurality of alternating insulating layers and a plurality of sacrificial layers; Forming at least one slit structure extending vertically and laterally in the dielectric stack, each of the at least one slit structure including a plurality of slit openings and a dividing structure between adjacent slit openings, the dividing structure extending vertically through a part of the dielectric stack, the step of forming at least one slit structure; Forming the first source structure in the plurality of slit openings; Replacing the plurality of sacrificial layers with a plurality of conductive layers through the at least one slit structure; The method according to claim 14, comprising:

16. The step of forming the at least one slit structure includes removing a portion of the dielectric stack adjacent to the split structure along the transverse direction to form a plurality of slit openings, wherein a width of one of the plurality of slit openings is less than or equal to a width of the split structure along another transverse direction perpendicular to the transverse direction. The method according to claim 15.

17. The step of removing the portion of the dielectric stack includes etching the portion of the dielectric stack adjacent to the split structure and using the split structure as an etching mask to hold the plurality of alternating sacrificial portions and the plurality of insulating portions under the split structure. The method according to claim 16.

18. The step of forming the plurality of channel structures includes forming at least one channel structure on two sides of the split structure along the other transverse direction. The method according to claim 14.

19. The step of forming the first source structure in the plurality of slit openings includes forming insulating spacers in the plurality of slit openings and forming source contacts on respective insulating spacers. The method according to claim 15.

20. The step of forming the cut structure includes forming a cut opening extending vertically through a portion of the dielectric stack; and depositing a dielectric material to fill the cut opening and form the cut structure. The method according to claim 15.

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