Transistor

Abstract

To provide a structure in which electric field concentration that may occur in a vicinity of an end of a drain electrode layer (and vicinity of an end of a source electrode) is mitigated when a high gate voltage is applied to a gate electrode layer in a bottom gate type transistor using an oxide semiconductor, deterioration of switching characteristic is suppressed, and consequently reliability is improved.SOLUTION: A cross sectional shape of an insulation layer overlapping on a channel formation region is made in a tapered shape. A film thickness of the insulation layer overlapping on the channel formation region is made 0.3 μm or smaller, preferably not smaller than 5 nm and not larger than 0.1 μm. A taper angle θ of a bottom end section of the insulation layer overlapping on the channel formation region is made 60° or smaller, preferably 45° or smaller, and further preferably 30°or smaller.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor devices have been developed and are used as LSIs, CPUs, and memories. A CPU is a semiconductor integrated circuit (at least transistors and It is an assembly of semiconductor elements having a memory and on which electrodes that serve as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards. It is mounted on a wiring board and used as one of the components in various electronic devices.

[0005] In addition, a technology for manufacturing transistors and the like by using an oxide semiconductor film in a channel formation region is gaining attention. For example, a transistor using zinc oxide (ZnO) as an oxide semiconductor film is , InGaO3(ZnO) m These oxide semiconductor transistors include A transistor using the insulating film is formed on a light-transmitting substrate, and is used as a switch of an image display device. Technologies for use in coupling elements and the like are disclosed in Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] A transistor having a channel formation region formed in an oxide semiconductor has a higher field-effect mobility than a transistor using amorphous silicon. The field-effect mobility of an amorphous silicon transistor is usually about 0.5 cm / Vs, whereas the field-effect mobility of a transistor using an oxide semiconductor is 10 to 20 cm 2 / Vs or higher. / Vs, or a value higher than that can be obtained. In addition, an oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device as in the case of a transistor using polycrystalline silicon. 2 Using such an oxide semiconductor, transistors are formed on a glass substrate or a plastic substrate, and research on applications to liquid crystal display devices, organic EL display devices, electronic paper, etc. is underway.

[0008] On the other hand, display devices having a large display area are becoming popular. In home televisions, televisions with a diagonal display screen of 40 inches to 50 inches are also starting to become popular, and their popularity will accelerate in the future. Since transistors using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of amorphous silicon transistors as described above, they can provide sufficient performance as pixel switching elements even in display devices having a large display area.

[0009] ​​​​​​​​​This is required. In addition, transistors used in display devices are required to have higher breakdown voltages. required.

[0010] One aspect of the present invention is to provide a highly reliable display device and a method for manufacturing the same, using a transistor having good electrical characteristics and high reliability, which uses an oxide semiconductor as a switching element. as a switching element. This is one of the problems.

[0011] In addition, in a bottom-gate type transistor using an oxide semiconductor, when a high gate voltage is applied to the gate electrode layer, the possible electric field concentration near the end of the drain electrode layer (and near the end of the source electrode layer) is alleviated, deterioration of the switching characteristics is suppressed, and improvement of reliability is achieved. This is one of the problems. and a method for manufacturing the same. This is one of the problems.

Means for Solving the Problems

[0012] A bottom-gate type transistor having a structure in which an insulating layer (also called a channel stop layer) overlapping the channel formation region is provided using an oxide semiconductor in the channel formation region. One of the aspects of the present invention is to alleviate the possible electric field concentration near the end of the drain electrode layer (and near the end of the source electrode layer) by devising the cross-sectional shape of the insulating layer overlapping the channel formation region, specifically the cross-sectional shape of the end (such as the taper angle θ and the film thickness), and suppress deterioration of the switching characteristics. This is the present invention. One of the aspects of the present invention is to suppress deterioration of the switching characteristics by devising the cross-sectional shape of the insulating layer overlapping the channel formation region, specifically the cross-sectional shape of the end (such as the taper angle θ and the film thickness), so as to alleviate the possible electric field concentration near the end of the drain electrode layer (and near the end of the source electrode layer). and near the end of the source electrode layer). and suppress deterioration of the switching characteristics.

[0013] Specifically, the cross-sectional shape of the insulating layer overlapping the channel formation region is trapezoidal or triangular, and the taper angle θ at the lower end of the cross-sectional shape is 60° or less, preferably 45° or less, and more preferably 30° or less. By setting such an angle range, when a high gate voltage is applied to the gate electrode layer, the taper angle θ at the lower end of the cross-sectional shape is 60° or less, preferably 45° or less, and more preferably 30° or less. By setting such an angle range, when a high gate voltage is applied to the gate electrode layer, the taper angle θ at the lower end of the cross-sectional shape is 60° or less, preferably 45° or less, and more preferably 30° or less. By setting such an angle range, when a high gate voltage is applied to the gate electrode layer, When applied, it can alleviate the possible electric field concentration occurring near the ends of the drain electrode layer (and near the ends of the source electrode layer). The possible electric field concentration can be alleviated.

[0014] Also, the film thickness of the insulating layer overlapping the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. By setting the film thickness within such a range, the peak of the electric field strength can be made small or the electric field concentration can be dispersed so that there are multiple locations where the electric field concentrates, and as a result, the possible electric field concentration occurring near the ends of the drain electrode layer can be alleviated.

[0015] One aspect of the invention disclosed in this specification is a semiconductor device having a gate electrode layer on an insulating surface, a gate insulating film on the gate electrode layer, an oxide semiconductor film including a channel formation region on the gate insulating film, an insulating layer in contact with the oxide semiconductor film, a source electrode layer having an end on the insulating layer, and a drain electrode layer having an end on the insulating layer. The ends of the source electrode layer and the drain electrode layer overlap the channel formation region via the insulating layer, the end of the insulating layer has a tapered shape, and the film thickness of the insulating layer is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less.

[0016] Another aspect of the present invention is a semiconductor device having a gate electrode layer on an insulating surface, a gate insulating film on the gate electrode layer, an oxide semiconductor film including a channel formation region on the gate insulating film, an insulating layer in contact with the oxide semiconductor film, a source electrode layer having an end on the insulating layer, and a drain electrode layer having an end on the insulating layer. The ends of the source electrode layer and the drain electrode layer overlap the channel formation region via the insulating layer, and the angle formed between the side surface of the end of the insulating layer and the insulating surface is 6 ​​​​​​​​​​It is 0° or less, preferably 45° or less, more preferably 30° or less, and the film thickness of the insulating layer is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less, and it is a semiconductor device characterized by this.

[0017] Also, in the above configuration, the end of the drain electrode layer overlaps the upper surface of the insulating layer. The drain electrode layer also functions as a light-shielding film that blocks external light irradiation to the oxide semiconductor film. When functioning as a light-shielding film, the position of the end of the source electrode layer may be determined within a range where the distance between the end of the source electrode layer and the end of the drain electrode layer does not cause a short circuit.

[0018] Also, when the angle formed by the side surface of the end of the insulating layer and the insulating surface is small, the width of the side surface of the insulating layer (also referred to as the width of the tapered portion) becomes wider, so it is preferable to reduce the parasitic capacitance of the portion where the drain electrode layer overlaps the gate electrode layer. In that case, the end of the drain electrode layer is configured to overlap the side surface of the end of the insulating layer.

[0019] At the end of the insulating layer, the taper angle θ is the angle formed by the side surface of the lower end portion in the cross-sectional shape of the insulating layer and the main plane of the substrate. Note that when the surface of the oxide semiconductor film in the region where the insulating layer is provided is a plane and can be regarded as being substantially parallel to the main plane of the substrate, the taper angle θ refers to the angle formed by the side surface of the lower end portion and the plane of the oxide semiconductor film.

[0020] Also, the cross-sectional shape of the end of the insulating layer overlapping the channel formation region is not particularly limited to a trapezoidal or triangular shape. It can also be a shape having a curved surface on at least a part of the side surface of the insulating layer overlapping the channel formation region. For example, in the cross-sectional shape of the end of the insulating layer, the insulating layer The lower end portion may also have a curved surface determined by the center of the curvature circle located outside the insulating layer. Also, the cross-sectional shape of the end portion of the insulating layer may have a cross-sectional shape that flares out from the upper surface of the insulating layer toward the substrate.

[0021] The insulating layer having the various cross-sectional shapes described above is formed by dry etching or wet etching. As an etching apparatus used for dry etching, an etching apparatus using a reactive ion etching (RIE) method, an etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) can be used. lotron Resonance) or ICP (Inductively Couple d Plasma), etc., can be used. As a dry etching apparatus that can obtain a uniform discharge over a wider area compared to an ICP etching apparatus, an ECCP (Enhanced Capacitively Coupled Plasma) mode etching apparatus in which the upper electrode is grounded, a 13.56 MHz high-frequency power source is connected to the lower electrode, and a 3.2 MHz low-frequency power source is further connected to the lower electrode is available. With this ECCP mode etching apparatus, for example, when using a substrate with a size exceeding 3 m of the 10th generation, it can also be accommodated. For example, when using a substrate with a size exceeding 3 m of the 10th generation, it can also be accommodated. Connect a high-frequency power source of 13.56 MHz to the lower electrode, and further connect a low-frequency power source of 3.2 MHz to the lower electrode. The ECCP (Enhanced Capacitively Coupled Plasma) mode etching apparatus is available. (Enhanced Capacitively Coupled Plasma) mode For this ECCP mode etching apparatus, for example, when using a substrate with a size exceeding 3 m of the 10th generation, it can also be accommodated. For this ECCP mode etching apparatus, for example, when using a substrate with a size exceeding 3 m of the 10th generation, it can also be accommodated.

[0022] Also, when the cross-sectional shape of the insulating layer overlapping the channel formation region is trapezoidal or triangular, the insulating layer is etched while retracting the resist mask to form an insulating layer having a trapezoidal or triangular cross-sectional shape. Etch the insulating layer while retracting the resist mask to form an insulating layer having a trapezoidal or triangular cross-sectional shape. In this specification, the cross-sectional shape refers to the cross-sectional shape obtained by cutting along a plane perpendicular to the main plane of the substrate.

Advantages of the Invention

[0023] By optimizing the cross-sectional shape of the insulating layer, the electric field concentration that may occur near the ends of the drain electrode layer and the source electrode layer can be alleviated, the deterioration of switching characteristics can be suppressed, and a structure with improved reliability can be realized.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that its form and details can be variously changed. Also, the present invention is not construed to be limited to the description content of the embodiments shown below.

[0026] (Embodiment 1) In a transistor having a trapezoidal cross-sectional shape of an insulating layer overlapping a channel formation region, the potential distribution in the vicinity of the drain when a gate bias is applied was calculated. For the calculation, simulation software (Sentaurus Device) manufactured by Synopsys was used.

[0027] A transistor as shown in FIG. 1(A), that is, on a gate insulating film 102 with a thickness of 100 nm provided on a gate electrode layer 101, an oxide semiconductor film 103 with a thickness of 20 nm and a thickness of 10 An insulating layer 104 (channel stop layer) of 0 nm is laminated in order, and is provided on the insulating layer 104 with a source electrode layer and a drain electrode layer 106, and a protective insulating film 107 covering the source electrode layer and the drain electrode layer 106 The bottom gate structure (channel stop type) transistor having is used as a calculation model. The taper angle of the lower end of the insulating layer 104 is 30°.

[0028] -30 V is applied to the gate electrode layer 101, and the drain electrode layer 106 is set to 0 V. The figure showing the equipotential lines is Fig. 1(A). Also, with the vertical axis being the electric field strength at the interface of the oxide semiconductor film 103 on the back channel, that is, in contact with the insulating layer 104, and the horizontal axis being the length in the channel length direction, the graph is Fig. 1(B). Note that the length X in the channel length direction is centered on the center of the channel formation region, and the lower side of the insulating layer 104 having a trapezoidal cross-sectional shape is 3 μm

[0029] Also, for comparison, calculations were performed in the case where the cross-sectional shape of the insulating layer is not a tapered shape, specifically a rectangular shape (the angle formed by the side surface and the main plane of the substrate is 90°). -30 V is applied to the gate electrode layer 101, and the drain electrode layer 106 is set to 0 V. The figure showing the equipotential lines is Fig. 20( A). Also, at the interface of the oxide semiconductor film 103 in contact with the insulating layer 104, with the vertical axis being the electric field strength and the horizontal axis being the length in the channel length direction, the graph is Fig. 20(B). It can be seen that there is electric field concentration in the vicinity of the interface in contact with the lower end of the insulating layer in the oxide semiconductor film, that is, at the position where X = 1.5 μm.

[0030] Compared with the comparative example, the peak of the electric field strength shown in Fig. 1(B) is small. From this, it can be seen that the ​​​​​​​By making the cross-sectional shape of the edge layer tapered compared to a rectangular shape, electric field concentration can be alleviated.

[0031] Also, when -30 V was applied to the gate electrode layer 101 and 20 V was applied to the drain electrode layer 106 , and the source electrode layer was set to 0 V and the electric field strength was calculated, similar results were obtained. It was possible.

[0032] Also, with the taper angles θ being 10°, 30°, 50°, and 70°, the electric field strength at the interface of the oxide semiconductor film in contact with the insulating layer, here the electric field strength at the position where X = 1.5 μm and the electric field strength at the position where X = 1.0 μm were calculated and shown in the graph in Fig. 2(A). In addition, in Fig. 2(A), the electric field strength at the position where X = 1.0 μm when the drain electrode layer was 20 V is indicated by white squares, and the electric field strength at the position where X = 1.5 μm when the drain electrode layer was 20 V is indicated by white circles. The electric field strength at the position where X = 1.0 μm when the drain electrode layer was 0 V is indicated by black squares, and the electric field strength at the position where X = 1.5 μm when the drain electrode layer was 0 V is indicated by black circles.

[0033] Also, with an insulating layer (channel stop layer) having a film thickness of 20 nm and the taper angles θ being 10°, 30 °, 50°, and 70°, the electric field strength at the interface of the oxide semiconductor film in contact with the insulating layer, here the electric field strength at the position where X = 1.5 μm and the electric field strength at the position where X = 1.0 μm were calculated and shown in the graph in Fig. 2(B). In Fig. 2(B), the electric field strength at the position where X = 1.0 μm when the drain electrode layer was 20 V is indicated by white squares, and the electric field strength at the position where X = 1.5 μm when the drain electrode layer was 20 V is indicated by white circles. The electric field strength at the position where X = 1.0 μm when the drain electrode layer was 0 V is indicated by black squares, and the drain electrode​​ The electric field strength at the position of X = 1.5 μm when the polar layer is set to 0 V is indicated by black circles.

[0034] Also, with the cross-sectional shape of the insulating layer being rectangular and the film thickness of the insulating layer being 5 nm, the gate electrode layer 101 is applied with -30 V, the drain electrode layer 106 is set to 0 V, equipotential lines are calculated, and the electric field strength at the interface between the insulating layer and the oxide semiconductor film in contact therewith, and the position where the electric field concentrates are examined. The graph with the electric field strength on the vertical axis and the length in the channel length direction on the horizontal axis is shown in Fig. 3(A). Note that, except for the difference in the film thickness of the insulating layer from the comparative example, the other conditions are the same for the calculation. Compared with the comparative example, by making the film thickness of the insulating layer as thin as 5 nm, peaks of electric field concentration occur at multiple locations and, furthermore, those peaks have smaller values than the peak of the comparative example. From this it can be confirmed that regardless of the cross-sectional shape of the insulating layer, electric field concentration can be alleviated by making the film thickness thinner. Of course, in addition to making the film thickness thinner, it goes without saying that electric field concentration can be further alleviated by making the cross-sectional shape a tapered shape.

[0035] Also, with the cross-sectional shape of the insulating layer being rectangular and the film thickness of the insulating layer being 5 nm, 10 nm, 20 nm, 30 nm, 50 nm, 100 nm, 200 nm, the electric field strength at the position of X = 1.5 μm and the electric field strength at the position of X = 1.0 μm are calculated and shown in Fig. 3(B) as a graph. The graph with the electric field strength on the vertical axis and the length in the channel length direction on the horizontal axis is shown in Fig. 3(A) is shown. In Fig. 3(B), the electric field strength at the position of X = 1.0 μm when the drain electrode layer is 0 V is indicated by black squares, and the electric field strength at the position of X = 1.5 μm when the drain electrode layer is 0 V is indicated by black circles. Also, the film thickness of each part in the cross-sectional structure of Fig. 3(B) is on a logarithmic scale It is shown prominently. Also, with the electric field strength on the vertical axis and the horizontal axis being the length in the channel length direction for each film thickness, when a graph was created, the film thickness range of the insulating layer where peaks of electric field concentration occurred at multiple locations was 5 nm or more and 50 nm or less.

[0036] From the above calculation results, by making the cross-sectional shape of the insulating layer a tapered shape and setting the film thickness of the insulating layer to 5 nm or more and 1 00 nm or less, preferably 5 nm or more and 50 nm or less, it can be said that relaxation of electric field concentration can be achieved. Also, by making it a tapered shape and setting the taper angle to 60° or less, even when the film thickness of the insulating layer is 300 nm, relaxation of electric field concentration can be achieved. Therefore, by setting the taper angle at the end of the insulating layer to 60° or less and the film thickness of the insulating layer to 300 nm or less, it can be said that relaxation of electric field concentration can be achieved.

[0037] (Embodiment 2) In this embodiment, an example of the cross-sectional shape of the insulating layer will be described below.

[0038] The model used in the calculation of Embodiment 1 showed a cross-sectional view near the drain electrode layer 106, but a cross-sectional structural view of the entire transistor including the source electrode layer 105 is shown in FIG. 4(A).

[0039] In FIG. 4(A), since the surface of the oxide semiconductor film 103 in the region where the insulating layer 104 is provided is planar and can be regarded as being substantially parallel to the substrate main plane, the taper angle θ refers to the angle formed by the side surface at the lower end of the insulating layer 104 and the oxide semiconductor film plane as shown. In FIG. 4 (A), since the insulating layer 104 shown is in a line-symmetric shape centered on a line passing through the center of the channel formation region, the taper angles θ at the two lower ends in the cross-sectional shape are substantially the same. Also, the (A), the insulating layer 104 shown is in a line-symmetric shape centered on a line passing through the center of the channel formation region, so the taper angles θ at the two lower ends in the cross-sectional shape are substantially the same. Also, the shape is line-symmetric with respect to the line passing through the center of the channel formation region, so the taper angles θ at the two lower ends in the cross-sectional shape are approximately the same. Also, the ​​The length in the channel length direction is determined with the center of the channel formation region as the origin of the horizontal axis. However the cross-sectional structure of the transistor shown in Fig. 4(A) has the sizes (film thickness, length , width, etc.) of each part set, but is not particularly limited.

[0040] In addition, although Fig. 4(A) shows an example in which the cross-sectional shape of the insulating layer is trapezoidal, as shown in Fig. 4(B) the insulating layer 114 with a triangular cross-sectional shape may also be used. In the cross-sectional shape of the insulating layer 114, the inner angle in contact with the base of the triangle is the taper angle θ. In Fig. 4(B), the end of the drain electrode layer overlaps the side surface of the insulating layer 114. Of course, the end of the source electrode layer also overlaps the side surface of the insulating layer 114. the inner angle in contact with the base of the triangle is the taper angle θ. In Fig. 4(B), the end of the drain electrode layer overlaps the side surface of the insulating layer 114. Of course, the end of the source electrode layer also overlaps the side surface of the insulating layer 114. the end of the drain electrode layer overlaps the side surface of the insulating layer 114. Of course, the end of the source electrode layer also overlaps the side surface of the insulating layer 114.

[0041] In addition, as shown in Fig. 4(C), the insulating layer 124 with a polygonal cross-sectional shape may also be used. As shown in Fig. 4 (C), the insulating layer 124 with a polygonal cross-sectional shape has, in addition to the angle θ1 formed by the side surface at the lower end of the insulating layer 124 and the oxide semiconductor film plane, an angle θ2 formed by the plane indicated by the dotted line (the plane parallel to the main plane of the substrate) and the side surface at the upper end of the insulating layer 104. In this case, at least the angle θ1 is less than 90°, preferably 60° or less, more preferably 30° or less the end of the drain electrode layer overlaps the side surface of the insulating layer 114. Of course, the end of the source electrode layer also overlaps the side surface of the insulating layer 114. to form the insulating layer 124 with a cross-sectional shape. to form the insulating layer 124 with a cross-sectional shape. to form the insulating layer 124 with a cross-sectional shape.

[0042] In addition, as shown in Fig. 4(D), the insulating layer 134 with a shape that flares from the upper surface of the insulating layer to the lower surface of the insulating layer may also be used. The side surface of the insulating layer 134 has a curved surface, and the lower end of the insulating layer also has a curved surface determined by the center of the curvature circle located outside the insulating layer. The side surface of the insulating layer 134 has a curved surface, and the lower end of the insulating layer also has a curved surface determined by the center of the curvature circle located outside the insulating layer. The side surface of the insulating layer 134 has a curved surface, and the lower end of the insulating layer also has a curved surface determined by the center of the curvature circle located outside the insulating layer. Note that the angle (taper angle θ) formed by the plane including the tangent line 133 of the side surface starting from the lower end of the insulating layer and the oxide semiconductor film plane is shown. Note that the angle (taper angle θ) formed by the plane including the tangent line 133 of the side surface starting from the lower end of the insulating layer and the oxide semiconductor film plane is shown. ​

[0043] Alternatively, as shown in FIG. 4(E), the insulating layer 144 may have a cross-sectional shape with a curved side surface. The insulating layer 144 has a curved side surface, and the lower end portion of the insulating layer is located inside the insulating layer. It also has one curved surface determined by the center of the curvature circle. Note that the angle (taper angle θ) formed by the plane of the oxide semiconductor film and the plane including the tangent line 143 of the side surface starting from the lower end of the insulating layer is shown. To realize such an insulating layer 144 with a cross-sectional shape, a plurality of insulating layers with different etching rates may be laminated.

[0044] In addition to the cross-sectional shapes described above, there are various cross-sectional shapes, but it is preferable to use the insulating layers with the shapes shown in FIGS. 4(A) to 4(E) for the transistor. By providing the insulating layers with the shapes shown in FIGS. 4(A) to 4(E) in contact with the oxide semiconductor film, relaxation of electric field concentration can be realized.

[0045] Also, this embodiment can be freely combined with Embodiment 1. For example, by adopting the cross-sectional shape shown in FIG. 4(B), setting the taper angle θ of the end portion of the insulating layer 114 to 60° or less, and setting the film thickness of the insulating layer 114 to 300 nm or less, relaxation of electric field concentration can be achieved.

[0046] (Embodiment 3) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 5 and 6. In this embodiment, a transistor having an oxide semiconductor film is shown as an example of the semiconductor device.

[0047] The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Also , having two gate electrode layers disposed via a gate insulating film above and below the channel formation region It may be a dual gate type.

[0048] The transistor 440 shown in FIGS. 5(A) and 5(B) is an example of a transistor called a bottom gate structure (also referred to as a channel protection type (channel-stopped type)) and is also a reverse staggered type transistor. FIG. 5(A) is a plan view, and the cross section taken along the dashed-dotted line X 1-Y1 in FIG. 5(A) corresponds to FIG. 5(B). As shown in FIG. 5(B), which is a cross-sectional view in the channel length direction, the semiconductor device including the transistor 440 has a gate electrode layer 4

[0049] 01, a gate insulating film 402, an oxide semiconductor film 403, an insulating layer 413, a source electrode layer 405 a, and a drain electrode layer 405b on a substrate 400 having an insulating surface provided with an insulating film 436. 01, a gate insulating film 402, an oxide semiconductor film 403, an insulating layer 413, a source electrode layer 405 a, and a drain electrode layer 405b.

[0050] The insulating layer 413 in contact with the oxide semiconductor film 403 is provided on the channel formation region of the oxide semiconductor film 403 that overlaps with the gate electrode layer 401 and functions as a channel protection film. By devising the cross-sectional shape of the insulating layer 413 overlapping the channel formation region, specifically, the cross-sectional shape of the end portion (such as the taper angle θ and the film thickness of the

[0051] tape), it is possible to relieve the possible electric field concentration in the vicinity of the end portion of the drain electrode layer 405b and suppress the deterioration of the switching characteristics of the transistor 440. Specifically, the cross-sectional shape of the insulating layer 413 overlapping the channel formation region is trapezoidal or triangular shaped, and the taper angle θ of the lower end portion of the cross-sectional shape is 60° or less, preferably 45° or less, more preferably It can be.

[0052] Specifically, the cross-sectional shape of the insulating layer 413 overlapping the channel formation region is trapezoidal or triangular shaped, and the taper angle θ of the lower end portion of the cross-sectional shape is 60° or less, preferably 45° or less, more preferably Preferably, it is 30° or less. By setting the angle range in this way, when a high gate voltage is applied to the gate electrode layer 401, the electric field concentration that may occur near the end of the drain electrode layer 405b can be mitigated.

[0053] In this embodiment, in terms of the cross-sectional shape, the outer ends of the insulating layer 413 outside the central range D are in a tapered shape, which is called the tapered portion. In the cross-sectional shape, the tapered portions of the insulating layer 413 are at both ends, and one of the widths is called the width of the tapered portion. The width of the tapered portion corresponds to about half of the difference between the channel length L and the central range D.

[0054] Also, the film thickness of the insulating layer 413 overlapping the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. By setting the film thickness range in this way, the peak of the electric field strength can be reduced, or the electric field concentration is dispersed and there are multiple locations where the electric field concentrates. As a result, the electric field concentration that may occur near the end of the drain electrode layer 405b can be mitigated.

[0055] As the oxide semiconductor used for the oxide semiconductor film 403, it is preferably to contain at least indium (In) or zinc (Zn). Particularly preferably, it contains In and Zn. Also, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide, it is preferably to have gallium (Ga) in addition to them. Also, it is preferably to have tin (Sn) as a stabilizer. Also, it is preferably to have hafnium (Hf) as a stabilizer. Also, it is preferably to have aluminum (Al) as a stabilizer.

[0056] Also, as other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) may be included, either singly or in combination.

[0057] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides , In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used.

[0058] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, Since it is possible to sufficiently reduce the current and the mobility is high, it is suitable for use in semiconductor devices. It is suitable as a semiconductor material.

[0059] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0060] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0061] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. A de semiconductor is an i-type (intrinsic semiconductor) or is very close to an i-type. Therefore, the off-state current of a transistor including the oxide semiconductor is extremely low. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, the concentration of impurities such as moisture or hydrogen is sufficiently reduced. In addition, an oxide semiconductor film that has been highly purified by reducing oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0062] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current density, which corresponds to the off-state current divided by the transistor channel width, is 100zA. In addition, the capacitance element is connected to a transistor, and the capacitance element A circuit that controls the charge flowing into or out of a capacitance element using the transistor is used. The current density was measured using a highly purified oxide semiconductor. A conductive film is used for the channel formation region, and the charge amount per unit time of the capacitance element is used to determine the channel. The off-current density of the transistor was measured. As a result, the source electrode and drain electrode of the transistor When the voltage between the electrodes is 3 V, an even lower off-current density of several tens of yA / μm is obtained. Therefore, it was found that the highly purified oxide semiconductor film was used for the channel formation region. The off-state current of the transistor is significantly lower than that of a transistor using crystalline silicon. Very low.

[0063] Unless otherwise specified, in this specification, the off-state current is In this case, the drain electrode is set at a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and the gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is less than 0. This refers to the current that flows between the source and drain electrodes when the potential is above the threshold.

[0064] For example, the oxide semiconductor film may be formed using In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When the Zn-based oxide semiconductor film is formed by a sputtering method, the atomic ratio is preferably In :Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or A target of In-Ga-Zn oxide with the atomic ratio of 3:1:4 is used. The oxide semiconductor film is formed by using an In-Ga-Zn oxide target having the above structure. Polycrystals or CAAC (C Axis Aligned Crystal) are formed. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. 0% or less, preferably 95% or more and less than 100%. Use a target with a high filling rate. As a result, the formed oxide semiconductor film becomes a dense film.

[0065] When using an In-Zn-based oxide material as the oxide semiconductor, in the target to be used the atomic ratio of the metal elements is In:Zn = 50:1 to 1:2 (when converted to molar ratio, In2 O3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (when converted to molar ratio, In2O3:ZnO = 10:1 to 1:2), more preferably In:Zn = 1.5:1 to 15:1 (when converted to molar ratio, In2O3:ZnO = 3:4 to 15:2 ). For example, for a target used to form an oxide semiconductor film that is an In-Zn-based oxide when the atomic ratio is In:Zn:O = X:Y:Z, Z > 1.5X + Y. By keeping the ratio of Zn within the above range, improvement in mobility can be achieved.

[0066] The oxide semiconductor film 403 can be in any state of single crystal, polycrystal (also referred to as polycrystalline), or amorphous.

[0067] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr ystalline Oxide Semiconductor) film.

[0068] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed-phase structure with crystal parts in an amorphous phase. Note that the crystal parts are often sized to fit within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM: Transmission Electron Micro scope), the boundary between the amorphous part and the crystal part contained in the CAAC-OS film is not clear. Also, no grain boundaries (grain boundaries ​Therefore, the CAAC-OS film is not characterized by electron transfer caused by grain boundaries. The decrease in mobility is suppressed.

[0069] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0070] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0071] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. It is formed by performing a crystallization treatment such as heat treatment after film formation.

[0072] In a transistor using a CAAC-OS film, the variation in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

[0073] Note that part of the oxygen constituting the oxide semiconductor film may be substituted with nitrogen.

[0074] Also, in an oxide semiconductor having a crystal part such as CAAC-OS, more bulk defects can be reduced, and if the surface flatness is increased, a mobility higher than that of an amorphous oxide semiconductor can be obtained. To increase the surface flatness, it is preferable to form the oxide semiconductor on a flat surface. Specifically, it is preferably formed on a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 .3 nm or less, and more preferably 0.1 nm or less. .3 nm or less, and more preferably 0.1 nm or less.

[0075] Ra is an arithmetic mean roughness defined in JIS B 0601:2001 (ISO4287:1997) extended three-dimensionally so that it can be applied to a curved surface, and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface", and is defined by the following formula. to the specified surface, and the specified surface is a surface to be measured for roughness, and is a rectangular region represented by four points of coordinates (x1, y1, f(x1, y

[0076]

Equation

[0077] Here, the specified surface is the surface to be measured for roughness, and is a rectangular region represented by four points of coordinates (x1, y1, f(x1, y 1)), (x1, y2, f(x1, y2)), (x2, y1, f(x2, y1)), (x 2, y2, f(x2, y2)), and the specified surface is set in the xy plane Let the area of the projected rectangle be S0 and the height of the reference plane (average height of the specified plane) be Z0. Ra can be measured with an atomic force microscope (AFM).

[0078] However, since the transistor 440 described in this embodiment is of the bottom gate type, a substrate 400, a gate electrode layer 401, and a gate insulating film 402 exist below the oxide semiconductor film. Therefore, after forming the gate electrode layer 401 and the gate insulating film 402 to obtain the above flat surface, a planarization process such as CMP processing may be performed. Further, it is not limited to planarizing the entire surface of the substrate, and by sufficiently separating the distance between the side surface of the gate electrode layer 401 and the lower end portion of the insulating layer 413, at least the region that becomes the channel formation region can be brought closer to the above flat surface. Since the transistor 440 is of the channel protection type, the size (L / W) of the channel formation region is determined by the size of the insulating layer 413.

[0079] The film thickness of the oxide semiconductor film 403 is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less), and a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulsed laser deposition method, an ALD (Atomic Layer Deposition) method, etc. can be appropriately used. Further, the oxide semiconductor film 403 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

[0080] Figs. 6(A), 6(B), 6(C), and 6(D) show an example of a method for manufacturing a semiconductor device having the transistor 440. ​​​​​​​​​​​​​

[0081] First, an insulating film 436 is formed on a substrate 400 having an insulating surface.

[0082] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. Also, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied, and those with semiconductor elements provided on these substrates can be used as the substrate 400.

[0083] Also, a semiconductor device may be fabricated using a flexible substrate as the substrate 400. To fabricate a semiconductor device having flexibility, a transistor 440 including an oxide semiconductor film 403 may be directly fabricated on the flexible substrate, or a transistor 440 including an oxide semiconductor film 403 may be fabricated on another fabrication substrate and then peeled off and transferred to the flexible substrate. In addition, in order to peel off and transfer from the fabrication substrate to the flexible substrate, it is advisable to provide a release layer between the fabrication substrate and the transistor 440 including the oxide semiconductor film.

[0084] As the insulating film 436, an oxide insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, a nitride insulating film such as silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, or a mixed material thereof is formed by a plasma CVD method, a sputtering method, or the like. ​​​It is possible.

[0085] The insulating film 436 may be a single layer or a laminate.

[0086] In this embodiment, a silicon nitride film with a thickness of 100 nm and a laminate of a silicon oxide film with a thickness of 150 nm formed by using the plasma CVD method are used as the insulating film 436. of the silicon nitride film and the silicon oxide film with a thickness of 150 nm.

[0087] Next, a conductive film is formed on the insulating film 436, and the conductive film is etched to form the gate electrode layer 401. is formed.

[0088] The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, um, copper, chromium, neodymium, scandium, etc. or an alloy material having these as a main component. In addition, as the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, a silicide film such as nickel silicide, etc. may be used. The gate electrode layer 401 may have a single-layer structure or a laminated structure.

[0089] Furthermore, as the material of the gate electrode layer 401 in contact with the gate insulating film 402, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be applied. Also, a laminated structure of the above conductive material and the above metal material can also be used.

[0090] Also, as the gate electrode layer 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, Specifically, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) can be used. An In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) can be used. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be pulled up, and a so-called normally-off switching element can be realized. In this embodiment, a tungsten film with a thickness of 100 nm is formed by sputtering. Subsequently, a gate insulating film 402 is formed on the gate electrode layer 401.

[0091] In this embodiment, a tungsten film with a thickness of 100 nm is formed by sputtering. .

[0092] Next, a gate insulating film 402 is formed on the gate electrode layer 401.

[0093] In order to improve the coverage of the gate insulating film 402, a planarization treatment may be performed on the surface of the gate electrode layer 401. Especially when an insulating film with a thin thickness is used as the gate insulating film 402, it is preferable that the flatness of the surface of the gate electrode layer 401 is good. In particular, when an insulating film with a thin thickness is used as the gate insulating film 402, it is preferable that the flatness of the surface of the gate electrode layer 401 is good. The thickness of the gate insulating film 402 is set to be 1 nm or more and 20 nm or less, and sputtering, MBE

[0094] methods, CVD methods, pulsed laser deposition methods, ALD methods, etc. can be appropriately used. Further, the gate insulating film 402 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target for film formation. methods, CVD methods, pulsed laser deposition methods, ALD methods, etc. can be appropriately used. Further, the gate insulating film 402 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target for film formation. The thickness of the gate insulating film 402 is set to be 1 nm or more and 20 nm or less, and sputtering, MBE methods, CVD methods, pulsed laser deposition methods, ALD methods, etc. can be appropriately used. Further, the gate insulating film 402 may be formed using a sputtering apparatus in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target for film formation.

[0095] As materials for the gate insulating film 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a nitrided oxide film can be used. It can be formed using a silicon film.

[0096] In addition, as the material of the gate insulating film 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), hafnium silicate with nitrogen added (HfSiO -ate (HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), by using high-k materials such as lanthanum oxide, the gate leakage current can be reduced. Further, the gate insulating film 402 may have a single-layer structure or a stacked structure. -leakage current can be reduced. Further, the gate insulating film 402 may have a single-layer structure or a stacked structure. structure is also acceptable.

[0097] It is preferable that the gate insulating film 402 contains oxygen at the portion in contact with the oxide semiconductor film 403. Preferably, at least an amount of oxygen exceeding the stoichiometric ratio exists in the film (in the bulk). For example, when using a silicon oxide film as the gate insulating film 402, it is set as SiO Preferably, at least an amount of oxygen exceeding the stoichiometric ratio exists in the film (in the bulk). For example, when using a silicon oxide film as the gate insulating film 402, it is set as SiO n (where α>0). 2+α (However, α>0).

[0098] By providing the gate insulating film 402 containing a large amount (excess) of oxygen serving as an oxygen supply source in contact with the oxide semiconductor film 40 3, oxygen can be supplied from the gate insulating film 402 to the oxide semiconductor film 403. Oxygen can also be supplied to the oxide semiconductor film 403 by performing a heat treatment in a state where at least a part of the oxide semiconductor film 403 and the gate insulating film 402 are in contact. can be supplied to the oxide semiconductor film 403. Oxygen can also be supplied to the oxide semiconductor film 403 by performing a heat treatment in a state where at least a part of the oxide semiconductor film 403 and the gate insulating film 402 are in contact. is also acceptable. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled.

[0099] By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be filled. It is cut. Further, the gate insulating film 402 is preferably formed in consideration of the size of the transistor to be fabricated and the step coverage of the gate insulating film 4 02.

[0100] In this embodiment, a silicon oxynitride film with a thickness of 200 nm is formed by a high-density plasma CVD method. is formed.

[0101] Next, an oxide semiconductor film 403 is formed on the gate insulating film 402.

[0102] In the process of forming the oxide semiconductor film 403, in order to prevent hydrogen or water from being contained in the oxide semiconductor film 403, as a pretreatment for forming the oxide semiconductor film 403, the substrate on which the gate insulating film 402 is formed is preheated in the preheating chamber of the sputtering device, and it is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate and the gate insulating film 402. In addition, a cryopump is preferably used as the exhaust means provided in the preheating chamber. and the gate insulating film 402. It is preferable.

[0103] A flattening process may be performed on the region where the oxide semiconductor film 403 is formed in contact with the gate insulating film 402. The flattening process is not particularly limited, but polishing processes (for example, chemical mechanical polishing (Chemical Mechanical Polishing: CMP ))), dry etching processes, and plasma processes can be used. ))

[0104] As the plasma process, for example, reverse sputtering can be performed by introducing argon gas to generate plasma. Reverse sputtering is a method of applying a voltage using an RF power supply to the substrate side in an argon atmosphere to form plasma near the substrate and modify the surface. is. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. Reverse sputtering When performing cleaning, powdery substances (also referred to as particles or dust) adhering to the surface of the gate insulating film 402 can be removed.

[0105] As the planarization process, polishing, dry etching, and plasma treatment may be performed multiple times, or they may be combined. When combined, the process order is not particularly limited and may be appropriately set according to the uneven state of the surface of the gate insulating film 402.

[0106] Note that the oxide semiconductor film 403 is formed under conditions where a large amount of oxygen is contained during film formation (for example, film formation is performed by sputtering in an atmosphere of 100% oxygen), and it is preferably a film containing a large amount of oxygen (preferably, an excessive oxygen content region is included with respect to the stoichiometric composition of the oxide semiconductor in the crystalline state).

[0107] In this embodiment, as the oxide semiconductor film 403, a sputtering method using a sputtering apparatus having an AC power supply is used to form an In-Ga-Zn-based oxide film (IGZO film) with a film thickness of 35 nm. In this embodiment, an In-Ga-Zn-based oxide target with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) is used. The film formation conditions are an oxygen and argon atmosphere (oxygen flow ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C. The film formation rate under these film formation conditions is 16 nm / min.

[0108] Note that the sputtering apparatus used for forming the oxide semiconductor film 403 has a leak rate of the film formation processing chamber of 1×10 Pa·m -10 3Set it to less than [unit] per second. By reducing the leak rate of the film formation processing chamber, the incorporation of impurities into the film formed by the sputtering method can be reduced. In order to reduce the leak rate of the film formation processing chamber, it is necessary to reduce not only external leaks but also internal leaks. External leakage means that gas flows in from outside the vacuum system due to minute holes, seal failures, etc. Internal leakage is caused by leakage from partitions such as valves within the vacuum system or emission gas from internal members. For the sputtering apparatus used for forming the oxide semiconductor film 403, the opening and closing parts of the film formation processing chamber are sealed with a metal gasket. The metal gasket is preferably made of a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion compared to an O-ring and can reduce external leakage. In addition, the adsorbates present inside the film formation processing chamber adhere to the inner wall and thus do not affect the pressure of the film formation processing chamber, but they cause gas emission when the film formation processing chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much as possible the adsorbates present in the film formation processing chamber and evacuate it in advance. Note that in order to promote the desorption of the adsorbates, the film formation processing chamber may be baked. By baking, the desorption rate of the adsorbates can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the removal of the adsorbates is performed while introducing an inert gas, the desorption rate of substances such as water that are difficult to desorb by evacuation alone can be further increased. When forming the oxide semiconductor film 403, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed as the sputtering gas.

[0109] ​​

[0110] The substrate is held in a film forming chamber that is maintained in a reduced pressure state. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above target is used. An oxide semiconductor film 403 is formed over a substrate 400. For this purpose, adsorption type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps, etc. It is preferable to use a displacement pump. Also, a turbo molecular pump is used as the exhaust means. A cold trap may be added. The reaction chamber may be, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H2O), or more preferably, a carbon Since the oxide semiconductor film formed in the film formation chamber is exhausted, The concentration of impurities contained in 403 can be reduced.

[0111] In addition, the gate insulating film 402 and the oxide semiconductor film 403 are successively formed without exposure to the air. It is preferable that the gate insulating film 402 and the oxide semiconductor film 403 be connected without being exposed to air. When the gate insulating film 402 is formed in succession, impurities such as hydrogen and moisture are adsorbed on the surface of the gate insulating film 402. It can be prevented.

[0112] The oxide semiconductor film 403 is formed by forming an island-like oxide semiconductor film into a film-like oxide semiconductor film by a photolithography process. The insulating film can be formed by processing the oxide semiconductor film.

[0113] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0114] Note that the etching of the oxide semiconductor film may be dry etching, wet etching, or both. For example, as the etching solution used for wet etching of the oxide semiconductor film, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, IT-07N (manufactured by Kanto Chemical Co., Inc.) may be used. Further, dry etching by an ICP (Inductively Coupled Plasma) etching method may be performed for etching. Moreover, a heat treatment for removing excessive hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation) may be performed on the oxide semiconductor film 403. The temperature of the heat treatment is 300°C or higher and 700°C or lower, or less than the distortion point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere. In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor film 403 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere and further at 450°C for 1 hour in a nitrogen and oxygen atmosphere. Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus uses a halogen lamp, a metal halide lamp, etc.

[0115]

[0116]

[0117] ​​​​​​​​​​​​​​Lamps such as incandescent lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps irradiate light (electromagnetic waves), and this device heats the object to be processed. It is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as those mentioned above. The GRTA device is a device that performs heat treatment using high-temperature gas. The high-temperature gas includes inert gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed during heat treatment. is used.

[0118] For example, as a heat treatment, the substrate may be placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then GRTA may be performed to take the substrate out of the inert gas.

[0119] In heat treatment, it is preferable that nitrogen or inert gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or inert gases such as helium, neon, and argon introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). is preferable.

[0120] Also, after heating the oxide semiconductor film 403 by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy) method, the moisture content is 20 ppm (dew point conversion of -55°C) or less, preferably 1 ppm or less, more preferably 10 ppb or less of air) may be introduced into the same furnace. It is preferable that oxygen gas or dinitrogen monoxide gas does not contain water, hydrogen, etc. Also, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is preferably 6N or more. preferably is 7N or more (that is, the impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, preferably 0.1 ppm or less). By the action of oxygen gas or nitrous oxide gas, it is simultaneously reduced by the step of removing impurities by dehydration or dehydrogenation treatment, and by supplying oxygen which is the main component material constituting the oxide semiconductor that has has thus decreased, the oxide semiconductor film 403 can be purified to high purity and made into type I (intrinsic).

[0121] Note that the timing of the heat treatment for dehydration or dehydrogenation may be after the formation of the film-like oxide semiconductor film or after the formation of the island-like oxide semiconductor film 403.

[0122] Also, the heat treatment for dehydration or dehydrogenation may be performed multiple times or may be combined with other heat treatments.

[0123] If the heat treatment for dehydration or dehydrogenation is performed in a state where the film-like oxide semiconductor film covers the gate insulating film 402 before the oxide semiconductor film 403 is processed into an island shape, it is preferable because oxygen contained in the gate insulating film 4 02 can be prevented from being released by the heat treatment.

[0124] Also, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor film 403 that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film.

[0125] Also, there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, may be simultaneously desorbed and decreased by dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen deficiency exists at the location where oxygen has desorbed, and this oxygen deficiency causes fluctuations in the electrical characteristics of the transistor. ​ A donor level will occur.

[0126] By introducing oxygen into the oxide semiconductor film 403 that has undergone dehydration or dehydrogenation treatment to supply oxygen into the film, the oxide semiconductor film 403 can be purified and made into type-I (intrinsic). A transistor having the oxide semiconductor film 403 that has been purified and made into type-I (intrinsic) has suppressed fluctuations in electrical characteristics and is electrically stable.

[0127] As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

[0128] In the step of introducing oxygen, when introducing oxygen into the oxide semiconductor film 403, it may be directly introduced into the oxide semiconductor film 403, or may be introduced into the oxide semiconductor film 403 through another film such as the gate insulating film 402. 3. When introducing oxygen through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. may be used. However, when directly introducing oxygen into the exposed oxide semiconductor film 403, a plasma treatment, etc. can also be used.

[0129] The introduction of oxygen into the oxide semiconductor film 403 is preferably performed after the dehydration or dehydrogenation treatment, but is not particularly limited. Also, the introduction of oxygen into the oxide semiconductor film 403 that has undergone the above dehydration or dehydrogenation treatment may be performed multiple times.

[0130] Next, an insulating layer 413 is formed on the channel formation region of the oxide semiconductor film 403 that overlaps with the gate electrode layer 401 (see FIG. 6(A)).

[0131] The insulating layer 413 can be formed by etching an insulating film formed by a plasma CVD method or a sputtering method. As the insulating layer 413, typically, a single layer or a laminate of an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, or a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film can be used.

[0132] When the insulating layer 413 (the film in contact with the oxide semiconductor film 403 when the insulating layer 413 has a laminated structure) in contact with the oxide semiconductor film 403 is in a state containing a large amount of oxygen, it can function suitably as a source for supplying oxygen to the oxide semiconductor film 40 3.

[0133] In this embodiment, as the insulating layer 413, a silicon oxide film with a thickness of 200 nm is formed by a sputtering method. The silicon oxide film is selectively etched to form an insulating layer 413 having a trapezoidal or triangular cross-sectional shape, where the taper angle θ at the lower end of the cross-sectional shape is 60° or less, preferably 45° or less , more preferably 30° or less. Note that the planar shape of the insulating layer 413 is rectangular. In this embodiment, a resist mask is formed on the silicon oxide film by a photolithography process, and selective etching is performed to make the cross-sectional shape of the insulating layer 413 trapezoidal, and the taper angle θ at the lower end of the insulating layer 413 is set to about 30°.

[0134] After forming the insulating layer 413, a heat treatment may be performed. In this embodiment, a heat treatment is performed at 30 0°C for 1 hour in a nitrogen atmosphere.

[0135] Next, the gate electrode layer 401, the gate insulating film 402, the oxide semiconductor film 403, and the insulating layer On 413, a conductive film 445 that forms a source electrode layer and a drain electrode layer (including wirings formed of the same layer) is formed (see FIG. 6(B)). (See FIG. 6(B)).

[0136] The conductive film 445 uses a material that can withstand subsequent heat treatment. As the conductive film 445 used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Also, on one or both of the lower side and the upper side of a metal film such as Al or Cu, a high melting point metal film such as Ti, Mo, or W or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated. Further, the conductive film 445 used for the source electrode layer and the drain electrode layer may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3 - SnO2, abbreviated as ITO), indium zinc oxide (In2O3 - ZnO), or a material in which silicon oxide is included in these metal oxide materials can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. On one or both of the lower side and the upper side of a metal film such as Al or Cu, a high melting point metal film such as Ti, Mo, or W or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated. On one or both of the lower side and the upper side of a metal film such as Al or Cu, a high melting point metal film such as Ti, Mo, or W or their metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated. ) may be laminated. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film having the above-described elements as components (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used.

[0137] Resist masks 448a and 448b are formed on the conductive film 445 by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b (see FIG. 6(C)). After forming the source electrode layer 405a and the drain electrode layer 405b, the resist mask is removed. As a result, the end portion of the drain electrode layer 405b is the insulating layer 4 Resist masks 448a and 448b are formed on the conductive film 445 by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b (see FIG. 6(C)). After forming the source electrode layer 405a and the drain electrode layer 405b, the resist mask is removed. As a result, the end portion of the drain electrode layer 405b is the insulating layer 4 Resist masks 448a and 448b are formed on the conductive film 445 by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b (see FIG. 6(C)). After forming the source electrode layer 405a and the drain electrode layer 405b, the resist mask is removed. As a result, the end portion of the drain electrode layer 405b is the insulating layer 4 After forming the source electrode layer 405a and the drain electrode layer 405b, the resist mask is removed. As a result, the end portion of the drain electrode layer 405b is the insulating layer 4 It is located on the upper surface or side surface of 13, and the end of the source electrode layer 405a is on the upper surface or side surface of the insulating layer 413. or side surface.

[0138] For the etching of the conductive film 445, a gas 447 containing chlorine is used. As the gas 447 containing chlorine, for example, a gas containing chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. can be used. )

[0139] As the etching method, a parallel plate type RIE (Reactive Ion Etching ) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that the desired processed shape can be etched.

[0140] In this embodiment, a laminated film of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by a sputtering method is used as the conductive film 445. The etching of the conductive film 445 is performed by a dry etching method to etch the laminated film of the titanium film, the aluminum film, and the titanium film to form the source electrode layer 405a and the drain electrode layer 405 b. b.

[0141] In this embodiment, after etching the two layers of the titanium film and the aluminum film under the first etching conditions, the remaining single-layer titanium film is removed under the second etching conditions. The first etching ing conditions are that the etching gas (BCl3:Cl2 = 750 sccm:150 sccm) is Use a bias power of 1500 W, an ICP power supply power of 0 W, and a pressure of 2.0 Pa and do so. The second etching condition is to use an etching gas (BCl3:Cl2 = 700 sccm: 100 sccm), set the bias power to 750 W, set the ICP power supply power to 0 W, and set the pressure to 2.0 Pa.

[0142] In the etching process of forming the source electrode layer 405a and the drain electrode layer 405b as described above, a gas 447 containing chlorine is used. However, when the oxide semiconductor film 403 is exposed to the gas 447 containing chlorine, the gas 447 containing chlorine reacts with the oxide semiconductor film 403, and there is a risk that residues will occur between the source electrode layer 405a and the drain electrode layer 405b on the surface of the insulating layer 413 and in the vicinity thereof. Residues existing between the source electrode layer 405a and the drain electrode layer 405 b are factors that cause a deterioration in the electrical characteristics of the transistor 440, such as leakage current. Also, chlorine contained in the gas containing chlorine (in addition to chlorine, elements contained in the gas may also be included) may be mixed into or adhered to the oxide semiconductor film 403, which may have an adverse effect on the transistor characteristics. For example, residues contain compounds containing indium or chlorine. Also, residues may contain other metal elements contained in the oxide semiconductor film (for example, gallium or zinc), other elements used in the gas containing chlorine (for example, boron), and the like. Therefore, after forming the source electrode layer 405a and the drain electrode layer 405b, residues existing between the source electrode layer 405a and the drain electrode layer 405b on the surface of the insulating layer 413 and in the vicinity thereof

[0143]

[0144] Thus, after forming the source electrode layer 405a and the drain electrode layer 405b, on the surface of the insulating layer 413 and in the vicinity thereof, residues existing between the source electrode layer 405a and the drain electrode layer 405b ​​​​​A process to remove the residue is carried out. The process to remove the residue is carried out using plasma treatment using rare gas. For example, a plasma treatment using argon can be suitably used. Note that the step of removing the residue also removes chlorine attached to the oxide semiconductor film 403. By carrying out the process of removing the residue, the surface of the insulating layer 413 is The chlorine concentration is 1×10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 (hereinafter) And the indium concentration is 2×10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 below In addition, the chlorine concentration in the oxide semiconductor film 403 can be set to 1×10 19 / cm 3 It can be as follows:

[0145] Through the above steps, the transistor 440 of this embodiment is manufactured (see FIG. 6D).

[0146] An insulating film serving as a protective insulating film is formed on the source electrode layer 405a and the drain electrode layer 405b. Good too.

[0147] The protective insulating film can be formed using a material and a method similar to those of the insulating layer 413. For example, a silicon oxynitride film is formed to a thickness of 400 nm by the CVD method. After the film is formed, a heat treatment may be performed. For example, the film may be heated at 300° C. for 1 hour in a nitrogen atmosphere. Do the following.

[0148] Furthermore, a highly dense inorganic insulating film may be provided as a protective insulating film. An aluminum oxide film is formed as an insulating film by a sputtering method. High density (film density 3.2g / cm 3 More than 3.6 g / cm, preferably 3.6 g / cm 3 (or more) This allows the transistor 440 to have stable electrical characteristics. Rutherford Backscattering (RBS) Spectrometry and X-Ray Reflectometry (XRR) tion) can be measured.

[0149] An aluminum oxide film that can be used as a protective insulating film provided over the transistor 440 The membrane has a blocking effect that does not allow impurities such as hydrogen and moisture, as well as oxygen, to pass through the membrane. Blocking effect is high.

[0150] Therefore, the aluminum oxide film is free from hydrogen, which is a variable factor during and after the manufacturing process. Impurities such as moisture may be mixed into the oxide semiconductor film 403, and the main components of the oxide semiconductor may be The oxide semiconductor film 403 functions as a protective film for preventing oxygen, which is a material, from being released from the oxide semiconductor film 403.

[0151] In addition, a planarization insulating film may be formed to reduce surface irregularities caused by the transistor 440. The planarizing insulating film is made of polyimide resin, acrylic resin, or benzocyclobutene resin. In addition to the above organic materials, low dielectric constant materials (low In addition, multiple insulating films made of these materials can be stacked. A planarizing insulating film may be formed by performing the above-mentioned process.

[0152] For example, an acrylic resin film having a thickness of 1500 nm may be formed as the planarizing insulating film. After coating the chitosan resin film by the coating method, it can be formed by baking (for example, at 250 ° C for 1 hour in a nitrogen atmosphere). It can be formed.

[0153] After forming the planarizing insulating film, heat treatment may be performed. For example, heat treatment is performed at 250 ° C for 1 hour in a nitrogen atmosphere. Perform heat treatment for 1 hour.

[0154] Thus, after forming the transistor 440, heat treatment may be performed. Further, the heat treatment may be performed multiple times. It may be performed multiple times.

[0155] As described above, an insulating layer 413 having a trapezoidal or triangular cross-sectional shape and a taper angle θ at the lower end of the cross-sectional shape of 60 ° or less, preferably 45 ° or less, and more preferably 30 ° or less is formed, and the end portion of the drain electrode layer and the source electrode layer are formed on the insulating layer 413 overlapping the channel formation region, thereby manufacturing the transistor 440 in which the electric field concentration is alleviated. Form an insulating layer 413 of 60 ° or less, preferably 45 ° or less, and more preferably 30 ° or less, and form the end portion of the drain electrode layer and the end portion of the source electrode layer on the insulating layer 413 overlapping the channel formation region, thereby manufacturing the transistor 440 in which the electric field concentration is alleviated. On the insulating layer 413 overlapping the channel formation region, the end portion of the drain electrode layer and the end portion of the source electrode layer are formed, thereby manufacturing the transistor 440 in which the electric field concentration is alleviated. By forming the end portions of the drain electrode layer and the source electrode layer, the transistor 440 in which the electric field concentration is alleviated is manufactured.

[0156] Therefore, a highly reliable semiconductor device including the transistor 440 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. Further, a highly reliable semiconductor device can be manufactured with high yield and high productivity can be achieved. In addition, a highly reliable semiconductor device can be manufactured with high yield, and high productivity can be achieved. Manufacture with high yield and achieve high productivity.

[0157] Also, according to the above manufacturing method, the transistor 440 is manufactured, a cross-sectional photograph of a sample in which a protective insulating film 460 which is a silicon oxynitride film having a film thickness of 400 nm is formed, and an acrylic resin film having a film thickness of 1500 nm is formed as the planarizing insulating film 461 on the protective insulating film is taken. The acceleration voltage is set to 200 kV with a scanning transmission electron microscope (Hitachi, Ltd. "HD-2300": STEM), and the lower end portion of the insulating layer 413 overlapping the channel formation region (overlapping the drain electrode layer 405b). A cross-sectional photograph of a sample in which a protective insulating film 460 which is a silicon oxynitride film having a film thickness of 400 nm is formed, and an acrylic resin film having a film thickness of 1500 nm is formed as the planarizing insulating film 461 on the protective insulating film is taken. A cross-sectional photograph of a sample in which a protective insulating film 460 which is a silicon oxynitride film having a film thickness of 400 nm is formed, and an acrylic resin film having a film thickness of 1500 nm is formed as the planarizing insulating film 461 on the protective insulating film is taken. Scanning transmission electron microscope (Hitachi, Ltd. "HD-2300": STEM). Acceleration voltage is 200 kV. The lower end of the insulating layer 413 overlapping the channel formation region (overlapping the drain electrode layer 405b). A high-magnification photograph (40,000 times) of the periphery of the lower end portion) is shown in Fig. 7(A). Note that Fig. 7(B) is a schematic diagram of Fig. 7(A). As shown in Fig. 7(A), the angle formed by the main plane of the substrate and the side surface of the insulating layer 413, that is, the taper angle θ is about 30°.

[0158] (Embodiment 4) In this embodiment, another form of the semiconductor device and the method for manufacturing the semiconductor device will be described with reference to Figs. 8 and 9. Parts and processes that are the same as or have the same functions as those in the above embodiment can be performed in the same manner as in the above embodiment, and repeated descriptions will be omitted. Also, detailed descriptions of the same locations will be omitted.

[0159] The transistor 420 shown in Figs. 8(A) and 8(B) is an example of a transistor having a bottom gate structure called a channel protection type (also referred to as a channel-stopped type) and is also a reverse staggered type transistor. Fig. 8(A) is a plan view, and the cross-section taken along the dashed-dotted line X 2 - Y2 in Fig. 8(A) corresponds to Fig. 8(B). As shown in Fig. 8(B), which is a cross-sectional view in the channel length direction, the semiconductor device including the transistor 420 has a gate electrode layer 4 01, a gate insulating film 402, an oxide semiconductor film 403, an insulating layer 423, a source electrode layer 405

[0160] 0a, and a drain electrode layer 405b on a substrate 400 having an insulating surface provided with an insulating film 436. The insulating layer 423 is provided on the oxide semiconductor film 403 including at least the channel formation region of the oxide semiconductor film 403 that overlaps with the gate electrode layer 401, and functions as a channel protection film. Further, the insulating layer 423 reaches the oxide semiconductor film 403 and the source electrode layer 01, a gate insulating film 402, an oxide semiconductor film 403, an insulating layer 423, a source electrode layer 405 a, and a drain electrode layer 405b.

[0161] The insulating layer 423 is provided on the oxide semiconductor film 403 including at least the channel formation region of the oxide semiconductor film 403 that overlaps with the gate electrode layer 401, and functions as a channel protection film. Further, the insulating layer 423 reaches the oxide semiconductor film 403 and the source electrode layer and functions as a channel protection film. Further, the insulating layer 423 reaches the oxide semiconductor film 403 and the source electrode layer 405a. The 405a or the drain electrode layer 405b has an opening provided so as to cover the inner wall. Therefore, the peripheral portion of the oxide semiconductor film 403 is covered with the insulating layer 423 and also functions as an interlayer insulating film. At the intersection of the gate wiring and the source wiring, not only the gate insulating film 402 but also the insulating layer 423 is arranged as an interlayer insulating film, so that the parasitic capacitance can be reduced.

[0162] In the transistor 420, the oxide semiconductor film 403 is configured to be covered with the insulating layer 423, the source electrode layer 405a, and the drain electrode layer 405b.

[0163] By devising the cross-sectional shape of the insulating layer 423 overlapping the channel formation region, specifically the cross-sectional shape of the end portion (such as the taper angle θ and the film thickness), the electric field concentration that may occur near the end portion of the drain electrode layer 405b can be alleviated, and the deterioration of the switching characteristics of the transistor 420 can be suppressed.

[0164] Specifically, the cross-sectional shape of the insulating layer 423 overlapping the channel formation region is trapezoidal or triangular, and the taper angle θ of the lower end portion of the cross-sectional shape is 60° or less, preferably 45° or less, and more preferably 30° or less. By setting such an angle range, when a high gate voltage is applied to the gate electrode layer 401, the electric field concentration that may occur near the end portion of the drain electrode layer 405b can be alleviated.

[0165] Also, the film thickness of the insulating layer 423 overlapping the channel formation region is 0.3 μm or less, preferably 5 nm or more and 0.1 μm or less. By setting such a film thickness range, the peak of the electric field strength can be reduced, or the electric field concentration is dispersed and the locations where the electric field concentrates become plural, and as a result ​​​​​​​​​​​​It is possible to mitigate the possible electric field concentration occurring near the end of the drain electrode layer 405b .

[0166] FIGS. 9(A), 9(B), 9(C), and 9(D) show an example of a method for manufacturing a semiconductor device having a transistor 420 .

[0167] An insulating film 436 is formed on a substrate 400 having an insulating surface. In this embodiment, the insulating film 43 6 is a laminated film of a silicon nitride film with a thickness of 100 nm and a silicon oxide film with a thickness of 150 nm, which are formed using the plasma CVD method

[0168] A conductive film is formed on the insulating film 436, and the conductive film is etched to form a gate electrode layer 401 . In this embodiment, a tungsten film with a thickness of 100 nm is formed by sputtering .

[0169] A gate insulating film 402 is formed on the gate electrode layer 401. In this embodiment, a silicon oxynitride film with a thickness of 200 nm is formed by high-density plasma CVD .

[0170] An oxide semiconductor film 403 is formed on the gate insulating film 402. In this embodiment, as the oxide semiconductor film 403, an In-Ga-Zn-based oxide film (IGZO film) with a thickness of 35 nm is formed using the sputtering method. The film formation conditions are an oxygen and argon atmosphere (oxygen flow rate ratio 50%), a pressure of 0.6 Pa, a power supply power of 5 kW, and a substrate temperature of 170°C .

[0171] The oxide semiconductor film 403 may be subjected to a heat treatment for removing excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). In this embodiment, one of the heat treatment apparatuses is used The substrate is placed in an electric furnace, and the oxide semiconductor film 403 is heated to 450° C. in a nitrogen atmosphere for 1 The heat treatment is then performed for 1 hour at 450° C. in a nitrogen and oxygen atmosphere.

[0172] Next, openings 425 a and 425 b reaching the oxide semiconductor film 403 are formed in the oxide semiconductor film 403. Then, an insulating layer 423 having the above structure is formed (see FIG. 9A).

[0173] The insulating layer 423 is an insulating film formed by plasma CVD or sputtering and then etched. The inner walls of the openings 425a and 425b of the insulating layer 423 are , has a tapered shape.

[0174] The insulating layer 423 is a channel of the oxide semiconductor film 403 overlapping with at least the gate electrode layer 401. The insulating film 403 is provided over the oxide semiconductor film 403 including the channel formation region. It acts as a membrane.

[0175] In this embodiment, a channel formation region of the oxide semiconductor film 403 is covered with an insulating layer 423. In addition, end portions of the oxide semiconductor film 403 are also covered with the insulating layer 423.

[0176] In this embodiment, the insulating layer 423 is a 200 nm thick oxide film formed by sputtering. In this embodiment, the silicon film is formed at the bottom end of the insulating layer 423 in the cross section. The taper angle θ is 30°.

[0177] After the insulating layer 423 is formed, heat treatment may be performed. Heat treatment is carried out at 0°C for 1 hour.

[0178] Next, the oxide semiconductor film 403, the insulating layer 423, and the inner walls of the openings 425a and 425b were covered with a This becomes the source electrode layer and the drain electrode layer (including wirings formed of the same layer). Form the conductive film 445 (see Fig. 9(B)).

[0179] By a photolithography process, form resist masks 448a and 448b on the conductive film 445, perform selective etching to form the source electrode layer 405a and the drain electrode layer 405b (see Fig. 9(C)). After forming the source electrode layer 405a and the drain electrode layer 405b, remove the resist mask.

[0180] For etching the conductive film 445, use a gas 447 containing chlorine. As the gas 447 containing chlorine, for example, a gas containing chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. can be used.

[0181] As the etching method, a parallel plate type RIE (Reactive Ion Etching ) method or an ICP (Inductively Coupled Plasma) etching method can be used. Appropriately adjust the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the temperature of the substrate-side electrode, etc.) so that etching can be performed to the desired processed shape.

[0182] In this embodiment, a laminated film of a titanium film with a thickness of 100 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm formed by a sputtering method is used as the conductive film 445. The etching of the conductive film 445 is performed by a dry etching method to etch the laminated film of the titanium film, the aluminum film, and the titanium film to form the source electrode layer 405a and the drain electrode layer 405 b. ​​​​​​​​Form b.

[0183] In this embodiment, after etching a two-layer film of a titanium film and an aluminum film under a first etching condition, the remaining single-layer titanium film is removed under a second etching condition. Note that the first etching condition uses an etching gas (BCl3:Cl2 = 750 sccm:150 sccm), sets the bias power to 1500 W, sets the ICP power supply power to 0 W, and sets the pressure to 2.0 Pa. The second etching condition uses an etching gas (BCl3:Cl2 = 700 sccm: 100 sccm), sets the bias power to 750 W, sets the ICP power supply power to 0 W, and sets the pressure to 2.0 Pa. 100 sccm), sets the bias power to 750 W, sets the ICP power supply power to 0 W, and sets the pressure to 2.0 Pa.

[0184] In the etching process of forming the source electrode layer 405a and the drain electrode layer 405b as described above, a gas 447 containing chlorine is used. However, when the oxide semiconductor film 403 is exposed to the gas 447 containing chlorine, the gas 447 containing chlorine reacts with the oxide semiconductor film 403, and there is a risk that residues are generated between the source electrode layer 405a and the drain electrode layer 405b on the surface of the insulating layer 423 and in the vicinity thereof. Residues existing between the source electrode layer 405a and the drain electrode layer 405 b cause a decrease in the electrical characteristics of the transistor 420 such as leakage current. Also, chlorine (and other elements contained in the gas may also be included) contained in the gas containing chlorine may be mixed into or adhered to the oxide semiconductor film 403, which may adversely affect the transistor characteristics. b cause a decrease in the electrical characteristics of the transistor 420 such as leakage current. Also, chlorine (and other elements contained in the gas may also be included) contained in the gas containing chlorine may be mixed into or adhered to the oxide semiconductor film 403, which may adversely affect the transistor characteristics. which may adversely affect the transistor characteristics. which may adversely affect the transistor characteristics.

[0185] In this embodiment, during the etching process using the gas 447 containing chlorine, a conductive film 445 is provided to cover the insulating layer 423 and the inner walls of the openings 425a and 425b on the oxide semiconductor film 403. Since it is covered, the oxide semiconductor film 403 is not exposed to the gas 447 containing chlorine.

[0186] In the above process, the transistor 420 of the present embodiment is fabricated (see Fig. 9(D)).

[0187] An insulating film serving as a protective insulating film may be formed on the source electrode layer 405a and the drain electrode layer 405b. This is also acceptable.

[0188] The protective insulating film can be formed using the same materials and methods as the insulating layer 423. For example, a silicon oxynitride film formed by CVD method is formed to a thickness of 400 nm. Further, after the formation of the protective insulating film, a heat treatment may be performed. For example, heat treatment is performed at 300 °C for 1 hour in a nitrogen atmosphere. This is done.

[0189] Also, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistor 420. This is also acceptable.

[0190] For example, an acrylic resin film with a thickness of 1500 nm may be formed as a planarizing insulating film on the protective insulating film. The acrylic resin film can be formed by baking (for example, at 250 °C for 1 hour in a nitrogen atmosphere) after coating by the coating method. This is done.

[0191] After the formation of the planarizing insulating film, a heat treatment may be performed. For example, heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere. This is done.

[0192] As described above, the cross-sectional shape of a part of the insulating layer 423 (the region overlapping with the channel formation region) is trapezoidal. The taper angle θ at the lower end of the cross-sectional shape is 60° or less, preferably 45° or less, and more preferably 30° or less. The insulating layer 423 is formed so that the region overlapping with the channel formation region of the insulating layer 423 By forming the ends of the drain electrode layer and the source electrode layer on the region, a transistor 420 can be fabricated in which the electric field concentration is alleviated.

[0193] Therefore, a highly reliable semiconductor device including a transistor 420 having stable electrical characteristics using the oxide semiconductor film 403 can be provided. Further, a highly reliable semiconductor device can be manufactured with a high yield and high productivity can be achieved.

[0194] Here, the electrical characteristics and the results of the reliability of the transistor 420 actually manufactured according to the above-described process are shown in FIGS. 10, 11, 12, and 13. The size of the transistor is such that the channel length L is 9 μm and the channel width W is 50 μm.

[0195] One of the methods for examining the reliability of a transistor is a bias - thermal stress test (hereinafter referred to as a BT test). The BT test is a type of acceleration test and can evaluate the characteristic changes of a transistor that occur due to long - term use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT test becomes an important index for examining the reliability. The smaller the amount of change in the threshold voltage before and after the BT test, the higher the reliability.

[0196] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is maintained constant, the source and drain of the transistor are set to the same potential, and a potential different from that of the source and drain is applied to the gate for a certain period of time. The substrate temperature may be appropriately set according to the test purpose. Also when the potential applied to the gate is higher than the same potential of the source and drain, it is called a +BT test, and when the potential applied to the gate is lower than the same potential of the source and drain, it is called a -BT test ​ It is called a test.

[0197] The test intensity of the BT test can be determined by the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film is determined by dividing the potential difference between the gate, source, and drain by the film thickness of the gate insulating film. For example, if the electric field strength applied to a gate insulating film with a film thickness of 200 nm is to be 1.5 MV / cm, the potential difference may be set to 3 0 V.

[0198] In general, voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, since the potential difference between the potential at a certain point and the reference potential (e.g., ground potential) is often shown as the potential at that certain point, in this specification when the potential at a certain point is shown as the difference between the potential at that certain point and the reference potential (e.g., ground potential), unless otherwise specified, the potential at that certain point is also referred to as voltage.

[0199] The BT test was conducted for both the +BT test and the -BT test with the substrate temperature at 80 °C, the electric field strength applied to the gate insulating film at 1.5 MV / cm, and the application time at 2000 seconds.

[0200] First, the +BT test will be described. To measure the initial characteristics of the transistor to be subjected to the BT test, the substrate temperature is set to 40 °C, the source-drain voltage (hereinafter referred to as the drain voltage ) is set to 10 V, and the source-gate voltage (hereinafter referred to as the gate voltage ) is set to -30 V to +30 ​​​​The variation characteristics of the source-drain current (hereinafter referred to as the drain current) when it is changed to V , that is, the Vg-Id characteristics were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface. However, if there are no particular problems, it may also be measured at room temperature (25 °C).

[0201] Next, after raising the substrate temperature to 80 °C, the potentials of the source and drain of the transistor were set to 0 V. Subsequently, a voltage was applied to the gate such that the electric field strength applied to the gate insulating film became 1.5 MV / cm . Here, since the thickness of the gate insulating film of the transistor was 200 nm, +30 V was applied to the gate and held for 2000 seconds as it was. Here the application time was set to 2000 seconds, but the time may be changed as appropriate according to the purpose.

[0202] Next, while voltages were applied to the source, drain, and gate, the substrate temperature was lowered to 40 °C . At this time, if the application of the voltage is stopped before the substrate temperature has dropped completely, the damage given to the transistor in the BT test will be recovered due to the influence of the residual heat. Therefore, it is necessary to lower the substrate temperature while the voltage is being applied . After the substrate temperature reached 40 °C, the application of the voltage was terminated .

[0203] Next, the Vg-Id characteristics were measured under the same conditions as the measurement of the initial characteristics, and the Vg-Id characteristics after the +BT test were obtained.

[0204] Subsequently, the -BT test will be described. The -BT test is also performed in the same procedure as the +BT test, but the difference is that the voltage applied to the gate after raising the substrate temperature to 80 °C is -30 V .

[0205] In the BT test, it is important to use a transistor that has never undergone a BT test before for the test. For example, if a -BT test is performed using a transistor that has already undergone a +BT test, the -BT test results cannot be accurately evaluated due to the influence of the previously conducted +BT test. The same applies when a +BT test is performed again using a transistor that has already undergone a +BT test. However, this does not apply in cases where the BT test is deliberately repeated taking these influences into account. Six samples with different substrates were fabricated, and the initial characteristics (threshold value and shift value), the change amount of the threshold voltage after the BT test, and the change amount of the shift value were respectively obtained. The results at 80 °C are shown in the graphs of Fig. 10(A) and Fig. 10(B). Fig. 10(A) shows the data of the +BT test, and Fig. 10(B) shows the data of the -BT test. The shift value (shift 2) indicates the rising voltage value of the Vg-Id characteristic curve when Vd = 10V, and it is the gate voltage at which the current is 1×10 A or less. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. The change amounts of the threshold value and the shift value are important indicators for examining the reliability of the transistor.

[0206] Six samples with different substrates were fabricated, and the initial characteristics (threshold value and shift value), the change amount of the threshold voltage after the BT test, and the change amount of the shift value were respectively obtained. The results at 80 °C are shown in the graphs of Fig. 10(A) and Fig. 10(B). Fig. 10(A) shows the data of the +BT test, and Fig. 10(B) shows the data of the -BT test. Six samples with different substrates were fabricated, and the initial characteristics (threshold value and shift value), the change amount of the threshold voltage after the BT test, and the change amount of the shift value were respectively obtained. The results at 80 °C are shown in the graphs of Fig. 10(A) and Fig. 10(B). Fig. 10(A) shows the data of the +BT test, and Fig. 10(B) shows the data of the -BT test. Six samples with different substrates were fabricated, and the initial characteristics (threshold value and shift value), the change amount of the threshold voltage after the BT test, and the change amount of the shift value were respectively obtained. The results at 80 °C are shown in the graphs of Fig. 10(A) and Fig. 10(B). Fig. 10(A) shows the data of the +BT test, and Fig. 10(B) shows the data of the -BT test. Six samples with different substrates were fabricated, and the initial characteristics (threshold value and shift value), the change amount of the threshold voltage after the BT test, and the change amount of the shift value were respectively obtained. The results at 80 °C are shown in the graphs of Fig. 10(A) and Fig. 10(B). Fig. 10(A) shows the data of the +BT test, and Fig. 10(B) shows the data of the -BT test.

[0207] The shift value (shift 2) indicates the rising voltage value of the Vg-Id characteristic curve when Vd = 10V, and it is the gate voltage at which the current is 1×10 A or less. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. -12 A or less. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated. In this specification, the threshold value (Vth) is defined as the gate voltage at the intersection of the tangent line of the maximum slope of the curve plotted with the gate voltage (Vg [V]) on the horizontal axis and the square root of the drain current (Id1 / 2 [A]) on the vertical axis, when the tangent line is extrapolated. When the drain voltage Vd is set to 10V in this specification, the threshold voltage is calculated.

[0208] The change amounts of the threshold value and the shift value are important indicators for examining the reliability of the transistor. ​It follows that the smaller the changes in the threshold value and the shift value before and after the BT test, the higher the reliability. In Samples 1 to 6, the changes in both the threshold value and the shift value are small.

[0209] Note that for Sample 1 and Sample 2, the film thickness of the insulating layer in contact with the oxide semiconductor film is 100 nm, for Sample 3 and Sample 4, the film thickness of the insulating layer in contact with the oxide semiconductor film is 200 nm, and for Sample 5 and Sample 6, the film thickness of the insulating layer in contact with the oxide semiconductor film is 300 nm. Also, Samples 1, 3, and 5 are silicon oxide films formed by sputtering for the interlayer insulating film (400 nm ) covering the transistor, and Samples 2, 4, and 6 are silicon oxynitride films formed by plasma CVD method.

[0210] Also, the results at 25 °C are shown in the graphs of FIGS. 11(A) and 11(B). For Sample 3, although the threshold voltage has changed in the negative direction compared to the initial characteristics, the change amount ΔVth is 0 .01 V, and Δshift 2 is -0.01 V, showing almost no change and particularly good characteristics so it is difficult to see in FIG. 11(B). Also, for Samples 2 and Sample 1, since the change amount ΔVth is 0.02 V, it is difficult to see in FIG. 11(B) .

[0211] Among the results at 25 °C, since the sample with the smallest changes in the threshold value and the shift value is Sample 3, FIG. 12(A) shows the Vg-Id characteristics of the transistor of Sample 3 before and after the +BT test, and FIG. 12(B) shows the Vg-Id characteristics of the transistor of Sample 3 before and after the -BT test.

[0212] According to Fig. 12(A), the threshold voltage has changed in the positive direction compared to the initial characteristics, but the change amount ΔVth is 0.19V, and Δshift 2 is 0.21V, showing almost no change and good characteristics. Also, according to Fig. 12(B), the threshold voltage has changed in the negative direction compared to the initial characteristics, but the change amount ΔVth is 0.01V, and Δshift 2 is -0.01V, showing almost no change and good characteristics.

[0213] In addition, the BT test was performed while irradiating light. Of course, samples different from the samples on which the above BT test was performed were used. The test method is the same as the above BT test except that the transistor is irradiated with 3000 lux of light from an LED light source. As a result of performing the +BT test while irradiating light, since there is almost no change before and after the +BT test, the experimental results are omitted here.

[0214] Also, the results of the -BT test while irradiating light are shown in Fig. 13. Fig. 13(A) shows the results when the stress condition temperature is 80°C, and Fig. 13(B) shows the results when the stress condition temperature is room temperature (25°C )

[0215] ). Even in the -BT test while irradiating light, in the results when the stress condition temperature is 80°C, the change amount ΔVth of the threshold voltage of the transistor of sample 3 is -0.3 6V compared to the initial characteristics, and Δshift 2 can be -0.65V. Also, in the results when the stress condition temperature is 25°C, the change amount ΔVt h of the threshold voltage of the transistor of sample 3 is -0.36V compared to the initial characteristics, and Δshift 2 is -0.08V, confirming that it is a highly reliable transistor.

[0216] From these reliability results and electrical characteristics, the structure shown in FIG. 8, that is, an insulating layer (film thickness: 100 nm to 300 nm) having a tapered end shape ( taper angle of about 30°) in contact with the oxide semiconductor film shows that the electrical characteristics of the transistor 420 are high and the reliability is also high.

[0217] A transistor using silicon as a semiconductor is different from a transistor using an oxide semiconductor. In the case of a transistor using an oxide semiconductor, when a -Vgs(-GBT) stress is applied, holes are not induced as carriers in the oxide semiconductor film (channel formation region), so an electric field may wrap around to the back channel side and cause deterioration. When the end of the insulating layer provided in contact with the channel formation region has a tapered shape, such a -Vgs(-GBT) stress application can achieve more effective relaxation of the electric field concentration, particularly at the end of the drain electrode layer where the electric field is concentrated.

[0218] (Embodiment 5) A semiconductor device (also referred to as a display device) having a display function can be manufactured using the transistor shown in Embodiment 3 or Embodiment 4. Further, part or all of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0219] In FIG. 14(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In FIG. 1 4(A), in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a single-crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate. A scanned line driving circuit 4004 and a signal line driving circuit 4003 are mounted. Also, separately formed signal line driving circuit 4003 and various signals and potentials supplied to the scanned line driving circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circuit t) 4018a and 4018b.

[0220] In FIGS. 14(B) and 14(C), a sealing material 4005 is provided so as to surround the pixel portion 4 002 and the scanned line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanned line driving circuit 4004 . Therefore, the pixel portion 4002 and the scanned line driving circuit 4004 are sealed together with the display element by the first substrate 400 1, the sealing material 4005, and the second substrate 4006. In FIGS. 14(B) and (C), a signal line driving circuit 4003 formed separately on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The signal line driving circuit 4003 is formed of a single crystal semiconductor film or a poly crystalline semiconductor film. In FIGS. 14(B) and FIG. 14(C), various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanned line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018. In FIGS. 14(B) and FIG. 14(C), an example in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001 is shown, but the present invention is not limited to this configuration. The scanned line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanned line driving circuit may be separately formed and mounted.

[0221] In FIGS. 14(B) and 14(C), an example in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001 is shown, but the present invention is not limited to this configuration. The scanned line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanned line driving circuit may be separately formed and mounted.

[0222] Note that the method of connecting the separately formed drive circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method or the like can be used. FIG. 14(A) is an example of mounting the signal line drive circuit 4003 and the scan line drive circuit 4004 by the COG method, FIG. 14(B) is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 1 4(C) is an example of mounting the signal line drive circuit 4003 by the TAB method.

[0223] In addition, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC or the like including a controller is mounted on the panel.

[0224] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC or a TAB tape or a TCP is attached, a module provided with a printed wiring board at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method is also included in the display device.

[0225] In addition, the pixel portion and the scan line drive circuit provided on the first substrate have a plurality of transistors, and the transistors shown in Embodiment 3 or Embodiment 4 can be applied.

[0226] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element ( also referred to as a light emitting display element) can be used. The light emitting element emits light by current or voltage. The device whose temperature is controlled is included in that category, specifically including inorganic EL (Electro L uminescence), organic EL, etc. Further, a display medium whose contrast changes due to an electrical action, such as electronic ink, can also be applied.

[0227] Next, one form of the semiconductor device will be described with reference to FIGS. 14, 15, and 16. FIG 16 corresponds to a cross-sectional view taken along M-N in FIG. 14(B).

[0228] As shown in FIGS. 14 and 16, the semiconductor device has connection terminal electrodes 4015 and terminal electrode 401 6, and the connection terminal electrodes 4015 and terminal electrode 4016 are electrically connected via an anisotropic conductive film 4019 to the terminals included in the FPC 4018.

[0229] The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode 4 016 is formed of the same conductive film as the gate electrode layers of the transistors 4040 and 4011.

[0230] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 each have a plurality of transistors. In FIG. 16, the transistor 4 040 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are illustrated as examples. In FIG. 16(A), an insulating film 4020 is provided on the transistors 4040 and 4011, and in FIG. 16(B), an insulating film 4021 is further provided. Note that the insulating film 4023 is an insulating film that functions as an underlying film.

[0231] As the transistors 4010, 4011, and 4040, in Embodiment 3 or Embodiment 4 The shown transistor can be applied. In this embodiment, an example of applying a transistor having the same structure as the transistor shown in Embodiment 3 is shown. The transistors 4010 and 4011 are transistors with a bottom gate structure in which an insulating layer that functions as a channel protection film is provided on an oxide semiconductor film.

[0232] The transistors 4010 and 4011 having the same structure as the transistor 440 shown in Embodiment 3 may use the insulating layer shown in Embodiment 1 or Embodiment 2 as the insulating layer provided on the channel formation region. By using the insulating layer shown in Embodiment 1 or Embodiment 2, a transistor in which the end portions of the drain electrode layer and the source electrode layer are formed on the region of the insulating layer overlapping the channel formation region, thereby relaxing the electric field concentration, can be fabricated.

[0233] Also, a structure similar to that of the transistor 420 shown in Embodiment 4 may be applied to the transistors 4010 and 4011. The transistor shown in Embodiment 4 has an insulating layer that functions as a channel protection film provided on an oxide semiconductor film including at least the channel formation region of the oxide semiconductor film overlapping the gate electrode layer, and further reaches the oxide semiconductor film and has an opening provided so that the source electrode layer or the drain electrode layer covers the inner wall. The transistor shown in Embodiment 4 also becomes a transistor in which the electric field concentration is relaxed by forming the end portions of the drain electrode layer and the source electrode layer on the region of the insulating layer overlapping the channel formation region.

[0234] Therefore, a stable electrical characteristic using the oxide semiconductor film of this embodiment shown in FIGS. 14 and 16 ​​​​​​​​​​As a semiconductor device including transistors 4010 and 4011 having the above properties, In addition, it is possible to provide such a highly reliable semiconductor device with a high yield. It is possible to fabricate the semiconductor device and achieve high productivity.

[0235] In addition, the oxide semiconductor film of the driver circuit transistor 4011 overlaps with a channel formation region of the oxide semiconductor film. A conductive layer may be further provided at a position overlapping with a channel formation region of the oxide semiconductor film. By placing it at a position where The amount of change in the threshold voltage of the transistor 4011 can be further reduced. The potential of the gate electrode layer of the transistor 4011 may be the same as or different from that of the gate electrode layer of the transistor 4011. The conductive layer may also function as a second gate electrode layer. V, or may be floating.

[0236] The conductive layer also shields the external electric field, i.e., prevents the external electric field from reaching the internal (including the transistor) It also has a function (particularly an electrostatic shielding function against static electricity) to prevent the electrical resistance of the device from acting on other components (including the circuitry). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0237] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. can be used.

[0238] FIG. 16A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In this case, the liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4 031, and a liquid crystal layer 4008. Note that insulating films 4032 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are configured to be laminated via the liquid crystal layer 4 008.

[0239] Also, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that spherical spacers may be used.

[0240] When a liquid crystal element is used as the display element, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0241] Also, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4030, and the second electrode layer 4031 have a contacting structure. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal is heated and transitions from the cholesteric phase to the isotropic phase. The blue phase can be expressed by using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. Also, in order to widen the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that exhibits the blue phase. It is also possible to form a liquid crystal layer by adding a polymerization initiator or the like and performing a process for polymer stabilization. This can be achieved. A liquid crystal composition that exhibits a blue phase has a short response time and is optically isotropic, so no alignment treatment is required and the viewing angle dependence is small. Also, since there is no need to provide an alignment film, no rubbing treatment is required, so it is possible to prevent electrostatic breakdown caused by the rubbing treatment, and reduce defects and breakage of the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor film may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal composition that exhibits a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor film.

[0242] Also, the specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The value of the specific resistance in this specification is the value measured at 20°C.

[0243] The size of the holding capacitance provided in the liquid crystal display device is set so as to be able to hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current of the transistor or the like. By using the transistor having the oxide semiconductor film disclosed in this specification, it is sufficient to provide a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel.

[0244] ​​​​​​The transistor using the oxide semiconductor film disclosed in this specification can control the current value ( off-state current value) to be low. Therefore, the holding time of an electrical signal such as an image signal can be extended, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and the effect of suppressing power consumption is achieved.

[0245] In addition, the transistor using the oxide semiconductor film disclosed in this specification can obtain a relatively high field-effect mobility, so it can be driven at high speed. For example, by using such a high-speed drivable transistor in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driving circuit portion can be formed on the same substrate. That is, it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driving circuit, so the number of components of the semiconductor device can be reduced. Also, in the pixel portion, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0246] For liquid crystal display devices, TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. ​​​

[0247] In addition, it may be a normally black type liquid crystal display device, for example, one adopting a vertical alignment (VA) mode as a transmissive liquid crystal display device. Examples of the vertical alignment mode include, but are not limited to for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used . It can also be applied to VA type liquid crystal display devices. The VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied . Also, pixels can be divided into several regions (sub-pixels), and a multi-domain or multi-domain design in which the molecules are tilted in different directions can be used, which is called multi-domain or multi-domain design .

[0248] In addition, in the display device, optical members (optical substrates) such as a black matrix (light shielding layer), polarizing member, retardation member, and anti-reflection member are provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, side light, etc. may be used as the light source .

[0249] In addition, the display method in the pixel portion can use a progressive method, an interlace method, etc . Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white) , or one or more colors such as yellow, cyan, and magenta are added to RGB. Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a display device for color display, and can also be applied to a display device for monochrome display.

[0250] In addition, as a display element included in the display device, a light-emitting element that utilizes electroluminescence can be applied. The light-emitting element that utilizes electroluminescence is distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0251] In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, respectively, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. In the present embodiment, an example of using an organic EL element as the light-emitting element is shown.

[0252] For the light-emitting element, at least one of a pair of electrodes may be translucent in order to extract light. Thus, there are light-emitting elements with an upper surface emission structure in which a transistor and a light-emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, a lower surface emission structure in which light is extracted from the surface on the substrate side, and a double-sided emission structure in which light is extracted from the surface on the substrate side and the surface opposite to the substrate, and any of the light-emitting elements with these emission structures can be applied.

[0253] ​​​​​​​​​​​​​Figs. 15(A), 15(B), and 16(B) show examples of a light-emitting device using a light-emitting element as a display element.

[0254] Fig. 15(A) is a plan view of the light-emitting device, and the cross-sections taken along the dashed-dotted lines V1-W1, V2-W2, and V3-W3 in Fig. 15(A) correspond to Fig. 15(B). In the plan view of Fig. 15(A), the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown.

[0255] The light-emitting device shown in Fig. 15 has a transistor 510, a capacitor element 520, and a wiring layer intersection 530 on a substrate 500 provided with an insulating film 501 that functions as an underlayer film, and the transistor 510 is electrically connected to the light-emitting element 540. Note that Fig. 15 shows a bottom-emission type light-emitting device that extracts light from the light-emitting element 540 through the substrate 500.

[0256] As the transistor 510, the transistors shown in Embodiment 3 or Embodiment 4 can be applied. In this embodiment, an example of applying a transistor having the same structure as the transistor 420 shown in Embodiment 4 is shown. The transistor 510 is an inverted staggered type transistor with a bottom gate structure, in which an insulating layer that functions as a channel protection film is provided on an oxide semiconductor film.

[0257] The transistor 510 includes gate electrode layers 511a, 511b, a gate insulating film 502, an oxide semiconductor film 512, an insulating layer 503, and conductive layers 513a, 513b that function as a source electrode layer or a drain electrode layer.

[0258] The transistor 510 having the same structure as the transistor 420 shown in Embodiment 4​​​​​​​​​​​​​ The cross-sectional shape of a part of the insulating layer 503 (the region overlapping with the channel formation region) is trapezoidal, and the cross-sectional taper angle θ of the lower end of the shape is 60° or less, preferably 45° or less, and more preferably 30° or less. Therefore, the insulating layer 503 functioning as a channel protection film includes at least the channel formation region of the oxide semiconductor film 512 overlapping with the gate electrode layers 511a and 511b. The insulating layer 503 is provided on the oxide semiconductor film 512, further reaches the oxide semiconductor film 512, and has an opening provided so as to cover the inner walls of the conductive layers 513a and 513b that function as source electrode layers or drain electrode layers. Also, a structure similar to the transistor 440 shown in Embodiment 3 may be applied to the transistor 510. Further, the cross-sectional shape of a part of the insulating layer 503 (the region overlapping with the channel formation region) may be the same as the cross-sectional shape of the insulating layer shown in Embodiment 1 or Embodiment 2. By using the insulating layer 503 having the same shape as the cross-sectional shape of the insulating layer shown in Embodiment 1 or Embodiment 2, a transistor 510 with alleviated electric field concentration can be manufactured.

[0259] Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 510 having stable electrical characteristics using the oxide semiconductor film 512 of the present embodiment shown in FIG. 15. Also, such a highly reliable semiconductor device can be manufactured with good yield and high productivity can be achieved. The capacitor element 520 includes conductive layers 521a and 521b, a gate insulating film 502, an oxide semiconductor film 5 22, and a conductive layer 523. The conductive layers 521a and 521b and the conductive layer 523 form a gate insulation between them.

[0260] Accordingly, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 510 having stable electrical characteristics using the oxide semiconductor film 512 of the present embodiment shown in FIG. 15. In addition, such a highly reliable semiconductor device can be manufactured with good yield, and high productivity can be achieved. The capacitor element 520 includes conductive layers 521a and 521b, a gate insulating film 502, an oxide semiconductor film 5 22, and a conductive layer 523, and the conductive layers 521a and 521b and the conductive layer 523 form a gate insulation

[0261] The capacitor element 520 includes conductive layers 521a, 521b, a gate insulating film 502, an oxide semiconductor film 5 22, and a conductive layer 523. The conductive layers 521a, 521b and the conductive layer 523 form a gate insulation A capacitor is formed by sandwiching the film 502 and the oxide semiconductor film 522.

[0262] The wiring layer intersection 530 is at the intersection of the gate electrode layers 511a, 511b and the conductive layer 533. There is, and the gate electrode layers 511a, 511b and the conductive layer 533 intersect with each other via the gate insulating film 502 , and the insulating layer 503. With the structure shown in Embodiment 4, the wiring layer intersection 530 can have not only the gate insulating film 50 2 but also the insulating layer 503 disposed between the gate electrode layers 511a, 511b and the conductive layer 533, so that the parasitic capacitance generated between the gate electrode layers 511a, 511b and the conductive

[0263] In this embodiment, a titanium film with a thickness of 30 nm is used as the gate electrode layers 511a and the conductive layer 521a, and a copper thin film with a thickness of 200 nm is used as the gate electrode layers 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

[0264] An IGZO film with a thickness of 25 nm is used as the oxide semiconductor films 512, 522.

[0265] An interlayer insulating film 504 is formed on the transistor 510, the capacitor element 520, and the wiring layer intersection 530, and a color filter layer 505 is provided in a region that overlaps with the light-emitting element 540 on the interlayer insulating film 504. An insulating film 506 that functions as a planarizing insulating film is provided on the interlayer insulating film 504 and the color filter layer 505.

[0266] A light-emitting element 540 including a laminated structure in which the first electrode layer 541, the electroluminescent layer 542, and the second electrode layer 543 are laminated in this order is provided on the insulating film 506. The light-emitting element 540 and the transistor 510 is electrically connected at the openings formed in the insulating film 506 and the interlayer insulating film 504 that reach the conductive layer 513a by the first electrode layer 541 and the conductive layer 513a being in contact with each other. Note that a partition wall 507 is provided so as to cover a part of the first electrode layer 541 and the opening.

[0267] For the interlayer insulating film 504, a silicon oxynitride film with a film thickness of 200 nm or more and 600 nm or less by plasma CVD method can be used. Further, a photosensitive acrylic film with a film thickness of 1500 nm can be used for the insulating film 506, and a photosensitive polyimide film with a film thickness of 1500 nm can be used for the partition wall 507.

[0268] As the color filter layer 505, for example, a colored light-transmissive resin can be used. As the colored light-transmissive resin, photosensitive and non-photosensitive organic resins can be used, but using a photosensitive organic resin layer can reduce the number of resist masks, so the process is simplified and preferable.

[0269] Colored refers to colors excluding achromatic colors such as black, gray, and white, and the color filter layer is formed of a material that transmits only the colored light that has been colored. As the colored light, red, green, blue, etc. can be used. Also, cyan, magenta, yellow, etc. can be used. Transmitting only the colored light that has been colored means that the transmitted light in the color filter layer has a peak at the wavelength of the colored light. The color filter layer may appropriately control the optimum film thickness in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. For example, the film thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

[0270] ​​​​​​​​​​​​​​​ In the light-emitting device shown in FIG. 16(B), the light-emitting element 4513, which is a display element, is electrically connected to the transistor 4010 provided in the pixel portion 4 002. Note that the structure of the light-emitting element 451 3 is a stacked structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light extracted from the light-emitting element 4513 and the like .

[0271] The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, using a photosensitive resin material, an opening is formed on the first electrode layers 4030 and 541, and it is preferably formed such that the side walls of the opening become inclined surfaces formed with a continuous curvature .

[0272] The electroluminescent layers 4511 and 542 may be composed of a single layer or may be composed of a plurality of layers stacked on top of each other .

[0273] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540, a protective film may be formed on the second electrode layers 4031 and 543 and the partition walls 4510 and 507. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed .

[0274] Also, to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting elements 4513 and 540 , a layer containing an organic compound covering the light-emitting elements 4513 and 540 may be formed by a vapor deposition method

[0275] Also, it is sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 The space is filled with a filler 4514 and sealed. In this way, it has high airtightness and is not exposed to the outside air, so that it is preferably packaged (enclosed) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. It is preferably packaged (enclosed) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing so as not to be exposed to the outside air like this. It is preferably packaged (enclosed) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing so as not to be exposed to the outside air like this.

[0276] As the filler 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. As the filler 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. As the filler 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler. As the filler 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler.

[0277] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection.

[0278] In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold In FIGS. 14 to 16, as the first substrates 4001 and 500 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a plastic substrate having light transmissivity can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, if light transmissivity is not required, a metal substrate such as aluminum or stainless steel (gold A film may also be used. For example, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0279] In this embodiment, an aluminum oxide film is used as the insulating film 4020. The insulating film 4020 can be formed by a sputtering method or a plasma CVD method.

[0280] The aluminum oxide film provided as the insulating film 4020 on the oxide semiconductor film has a high blocking effect (blocking effect) that does not allow the film to permeate impurities such as hydrogen and moisture and oxygen.

[0281] Therefore, the aluminum oxide film functions as a protective film that prevents the incorporation of impurities such as hydrogen and moisture, which are factors of variation, into the oxide semiconductor film during and after the manufacturing process, and the release of oxygen, which is the main component material constituting the oxide semiconductor, from the oxide semiconductor film.

[0282] In addition, the insulating films 4021 and 506 that function as planarization insulating films can be made of heat-resistant organic materials such as acrylic resin, polyimide resin, benzocyclobutene-based resin, polyamide resin, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that an insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0283] The method for forming the insulating films 4021 and 506 is not particularly limited, and depending on the material, a sputtering method, an SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet Methods such as screen printing and offset printing can be used.

[0284] The display device performs display by transmitting light from a light source or a display element. Therefore, thin films such as a substrate, an insulating film, and a conductive film provided in the pixel portion where light passes through all have light transmittance in the wavelength region of visible light. Be made light transmissive.

[0285] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, light transmittance and reflectivity may be selected according to the direction of light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0286] The first electrode layers 4030, 541 and the second electrode layers 4031, 543 can use conductive materials having light transmittance such as indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and graphene.

[0287] In addition, the first electrode layers 4030, 541 and the second electrode layers 4031, 543 are made of tungsten ( W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium ( V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver ( Ag), etc., or an alloy thereof, or one or more kinds of metal nitrides thereof can be used for formation.

[0288] ​​​​In this embodiment, since the light-emitting device shown in FIG. 15 is a bottom emission type, the first electrode layer 54 1 has translucency and the second electrode layer 543 has reflectivity. Therefore, when a metal film is used for the first electrode layer 541, the film thickness is made thin enough to maintain translucency, and when a conductive film having translucency is used for the second electrode layer 543, a conductive film having reflectivity may be laminated.

[0289] Also, as the first electrode layers 4030, 541 and the second electrode layers 4031, 543, a conductive composition containing a high-conductivity molecule (also referred to as a conductive polymer) can be used to form them. As the conductive polymer, so-called π-electron conjugated system conductive polymers can be used. For example, , polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers composed of two or more of aniline, pyrrole and thiophene or their derivatives and the like can be mentioned.

[0290] Also, since the transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0291] By applying the transistor shown in Embodiment 1 or Embodiment 2 as described above, a semiconductor device having various functions can be provided.

[0292] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0293] (Embodiment 6) Using the transistor shown in Embodiment 3 or Embodiment 4, information on an object is read A semiconductor device having an image sensor function can be manufactured.

[0294] Fig. 17(A) shows an example of a semiconductor device having an image sensor function. Fig. 17(A) is an equivalent circuit of a photosensor, and Fig. 17(B) is a cross-sectional view showing a part of the photosensor. .

[0295] One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the gate of the transistor 640. One of the source or drain of the transistor 640 is electrically connected to the photosensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source or drain is electrically connected to the photosensor output signal line 671.

[0296] In the circuit diagrams in this specification, as can be clearly identified as a transistor using an oxide semiconductor film, the symbol of the transistor using an oxide semiconductor film is described as "OS". In Fig. 17(A), the transistors 640 and 656 can be applied with the transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4, and are transistors using an oxide semiconductor film. In this embodiment, an example of applying a transistor having the same structure as the transistor 440 shown in Embodiment 3 is shown. The transistor 640 is a bottom gate structure transistor provided with an insulating layer that functions as a channel protection film on an oxide semiconductor film.

[0297] FIG. 17(B) shows a cross-sectional view of a photodiode 602 and a transistor 640 in a photosensor on a substrate 601 (TFT substrate) having an insulating surface, where a photodiode 602 and a transistor 640 that function as sensors are provided . A substrate 613 is provided on the photodiode 602 and the transistor 640 using an adhesive layer 608 .

[0298] An insulating film 631, an interlayer insulating film 633, and an interlayer insulating film 634 are provided on the transistor 640 . The photodiode 602 is provided on the interlayer insulating film 633, and between electrode layers 641a and 641b formed on the interlayer insulating film 633 and an electrode layer 642 provided on the interlayer insulating film 634 , a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c are laminated in this order from the side of the interlayer insulating film 633 .

[0299] The electrode layer 641b is electrically connected to a conductive layer 643 formed in the interlayer insulating film 634, and the electrode layer 642 is electrically connected to a conductive layer 645 via the electrode layer 641a . The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640 .

[0300] Here, a pin-type photodiode is exemplified in which a semiconductor film having a p-type conductivity type as the first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) as the second semiconductor film 606b, and a semiconductor film having an n-type conductivity type as the third semiconductor film 606c are laminated .

[0301] The first semiconductor film 606a is a p-type semiconductor film and contains an impurity element that imparts a p-type ​​​​It can be formed by an amorphous silicon film. For the formation of the first semiconductor film 606a, a semiconductor material gas containing a group 13 impurity element (e.g., boron (B)) is used, and it is formed by plasma CVD method . Silane (SiH4) may be used as the semiconductor material gas. Or, S i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Also, after forming an amorphous silicon film without impurity elements, impurity elements may be introduced into the amorphous silicon film by diffusion method or ion implantation method. After introducing impurity elements by ion implantation method or the like , heating or the like may be performed to diffuse the impurity elements. In this case, as a method for forming the amorphous silicon film, LPCVD method, vapor growth method, or sputtering method, etc. may be used. The film thickness of the first semiconductor film 606a is preferably formed to be 10 nm or more and 5 0 nm or less.

[0302] The second semiconductor film 606b is a type I semiconductor film (intrinsic semiconductor film), and is formed by an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH4) may be used. Or, Si2H6, SiH2Cl2, SiHCl3, S iCl4, SiF4, etc. may also be used. The formation of the second semiconductor film 606b may be performed by LPCVD method, vapor growth method, sputtering method, etc. The film thickness of the second semiconductor film 606b is preferably formed to be 2 00 nm or more and 1000 nm or less.

[0303] The third semiconductor film 606c is an n-type semiconductor film, and is an amorphous containing an impurity element that imparts n-type It is formed of a fast silicon film. For the formation of the third semiconductor film 606c, a semiconductor material gas containing a Group 15 impurity element (e.g., phosphorus (P)) is used to form it by plasma CVD method. Silane (SiH4) may be used as the semiconductor material gas. Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. Also, after forming an amorphous silicon film that does not contain an impurity element, an impurity element may be introduced into the amorphous silicon film using a diffusion method or an ion implantation method. After introducing an impurity element by an ion implantation method or the like, heating or the like may be performed to diffuse the impurity element. In this case, as a method for forming an amorphous silicon film, an LPCVD method, a vapor phase growth method, or a sputtering method may be used. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less. The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi Amorphous Semiconductor: SAS) semiconductor. Also, since the mobility of holes generated by the photoelectric effect is smaller than that of electrons, a pin-type photodiode exhibits better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, an example of converting the light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed into an electrical signal is shown. Also, since the light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film side used as the light-receiving surface becomes disturbing light, the electrode layer uses a conductive film having light-shielding properties. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less.

[0304] Also, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi Amorphous Semiconductor: SAS) semiconductor. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less.

[0305] Also, since the mobility of holes generated by the photoelectric effect is smaller than that of electrons, a pin-type photodiode exhibits better characteristics when the p-type semiconductor film side is the light-receiving surface. Here, an example of converting the light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed into an electrical signal is shown. Also, since the light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film side used as the light-receiving surface becomes disturbing light, the electrode layer uses a conductive film having light-shielding properties. Here, an example of converting the light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed into an electrical signal is shown. Here, an example of converting the light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed into an electrical signal is shown. It is preferable that it be present. Also, the n-type semiconductor film side can be used as the light-receiving surface.

[0306] As the insulating film 631, the interlayer insulating film 633, and the interlayer insulating film 634, an insulating material is used, and depending on the material, it can be formed by a sputtering method, a plasma CVD method, a SOG method, spin coating, dip coating, spray coating, a droplet discharge method (inkjet method), screen printing, offset printing, etc.

[0307] As the insulating film 631, as the inorganic insulating material, an oxide insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, a silicon nitride film a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc. nitride insulating film single layer or laminate can be used.

[0308] In this embodiment, an aluminum oxide film is used as the insulating film 631. The insulating film 631 can be formed by a sputtering method or a plasma CVD method.

[0309] The aluminum oxide film provided as the insulating film 631 on the oxide semiconductor film has a high blocking effect (blocking effect) that does not allow the film to permeate hydrogen, moisture, any impurities, and both oxygen. .

[0310] Therefore, the aluminum oxide film functions as a protective film that prevents the mixing of impurities such as hydrogen and moisture, which are factors of variation, into the oxide semiconductor film during and after the manufacturing process, and the release of oxygen, which is the main component material constituting the oxide semiconductor, from the oxide semiconductor film.

[0311] As the interlayer insulating films 633 and 634, an insulating film that functions as a planarizing insulating film to reduce surface irregularities is preferable. As the interlayer insulating films 633 and 634, for example, organic insulating materials having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide resin, and epoxy resin can be used. In addition to the above organic insulating materials, single layers or laminates such as low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can be used. By detecting the light incident on the photodiode 602, information on the object to be detected can be read. Note that a light source such as a backlight can be used when reading information on the object to be detected.

[0312]

[0313] The transistor 640 having the same structure as the transistor 440 shown in Embodiment 3 may use the insulating layer shown in Embodiment 1 or Embodiment 2 as the insulating layer provided over the channel formation region. By using the insulating layer shown in Embodiment 1 or Embodiment 2, a transistor in which electric field concentration is alleviated can be manufactured by forming the ends of the drain electrode layer and the source electrode layer over a region of the insulating layer overlapping with the channel formation region.

[0314] Alternatively, a structure similar to that of the transistor 420 shown in Embodiment 4 may be applied to the transistor 640. In the transistor shown in Embodiment 4, an insulating layer that functions as a channel protection film is provided over an oxide semiconductor film including at least a channel formation region of an oxide semiconductor film overlapping with a gate electrode layer, and further reaches the oxide semiconductor film and the source electrode layer or The drain electrode layer has an opening provided so as to cover the inner wall. The transistor shown in Embodiment 4 also has the end portions of the drain electrode layer and the source electrode layer formed on the region overlapping with the channel formation region of the insulating layer, resulting in a transistor in which the electric field concentration is alleviated.

[0315] Therefore, a highly reliable semiconductor device including a transistor having stable electrical characteristics using the oxide semiconductor film of the present embodiment can be provided. In addition, a highly reliable semiconductor device can be manufactured with a high yield, achieving high productivity. 640

[0316] The configurations, methods, etc. shown in the present embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0317] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, gaming machines (pachinko machines, slot machines, etc.), and game cabinets. Specific examples of these electronic devices are shown in FIG. 18. (Pachinko machines, slot machines, etc.), and game cabinets.

[0318] FIG. 18(A) shows a table 9000 having a display unit. The table 9000 has a display unit 9003 incorporated in a housing 9001, and the display unit 9003 can display an image. A configuration in which the housing 9001 is supported by four legs 9002 is shown. The housing 9001 also has a power cord 9005 for power supply. ​​​​​​​​​​​

[0319] The semiconductor device shown in any one of Embodiments 1 to 6 can be used for the display unit 9003 and can impart high reliability to the electronic device.

[0320] The display unit 9003 has a touch input function, and by touching the display button 9004 displayed on the display unit 9003 of the table 9000 with a finger or the like, screen operations and information input can be performed, and communication with other household appliances or control can be enabled, so that other household appliances can be controlled as a control device by screen operations. For example, if a semiconductor device having the image sensor function shown in Embodiment 3 is used, the display unit 9003 can be provided with a touch input function.

[0321] Also, the screen of the display unit 9003 can be set perpendicular to the floor by a hinge provided on the housing 9001, and it can also be used as a television device. In a narrow room, installing a television device with a large screen will narrow the free space, but if a display unit is built into the table, the space in the room can be effectively utilized.

[0322] FIG. 18(B) shows a television device 9100. The television device 9100 has a display unit 9103 incorporated in a housing 9101, and the display unit 9103 can display an image. Here, a configuration in which the housing 9101 is supported by a stand 9105 is shown.

[0323] The operation of the television device 9100 is performed by an operation switch provided in the housing 9101 or a separate remote It can be performed by the remote control unit 9110. The operation keys provided in the remote control unit 9110 9109 can be used to operate channels and volume, and can also operate the video displayed on the display unit 9103 In addition, the remote control unit 9110 may be configured to include a display unit 9107 for displaying information output from the remote control unit 9110.

[0324] The television apparatus 9100 shown in FIG. 18(B) includes a receiver, a modem, etc. The television apparatus 9100 can receive general television broadcasts by the receiver, and can further connect to a wired or wireless communication network via the modem, enabling one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers, etc.) information communication to be performed.

[0325] The semiconductor device shown in any of Embodiments 1 to 6 can be used for the display units 9103 and 9107 and can provide high reliability to the television apparatus and the remote control unit .

[0326] FIG. 18(C) is a computer, including a main body 9201, a housing 9202, a display unit 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, etc. The computer is manufactured by using the semiconductor device according to one aspect of the present invention for its display unit 9203 . By using the semiconductor device shown in the previous embodiments, a highly reliable computer can be obtained .

[0327] FIGS. 19(A) and 19(B) are foldable tablet terminals. FIG. 19(A) ​is in an open state, and the tablet terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, a fastener 9033, and an operation switch 9038.

[0328] The semiconductor device according to any one of Embodiments 1 to 6 can be used for the display unit 9631a and the display unit 9631 b, and a highly reliable tablet terminal can be obtained.

[0329] A part of the display unit 9631a can be set as a touch panel area 9632a, and data can be input by touching the displayed operation keys 9638. Note that in the display unit 963 1a, as an example, a configuration in which half of the area has only a display function and the other half of the area has a touch panel function is shown, but the present invention is not limited to this configuration. All areas of the display unit 963 1a may have a touch panel function. For example, the entire surface of the display unit 96 31a can be used as a keyboard button display to form a touch panel, and the display unit 9631b can be used as a display screen.

[0330] Similarly, in the display unit 9631b, a part of the display unit 9631b can be set as a touch panel area 9632b. Further, when a finger or a stylus touches the position where the keyboard display switching button 9639 of the touch panel is displayed, the keyboard buttons can be displayed on the display unit 9631b. Moreover, touch input can be simultaneously performed on the touch panel area 9632a and the touch panel area 9632b.

[0331]

[0332] In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor. In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor. In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor. In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor. In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor. In addition, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built in the tablet terminal during use. The tablet terminal may incorporate other detection devices such as sensors that detect inclination, such as a gyro and an acceleration sensor, in addition to the optical sensor.

[0333] In addition, in FIG. 19(A), an example in which the display areas of the display unit 9631b and the display unit 9631a are the same is shown, but it is not particularly limited, and the size of one may be different from that of the other, and the display quality may also be different. For example, one may be a display panel that can perform higher-definition display than the other. In addition, in FIG. 19(A), an example in which the display areas of the display unit 9631b and the display unit 9631a are the same is shown, but it is not particularly limited, and the size of one may be different from that of the other, and the display quality may also be different. For example, one may be a display panel that can perform higher-definition display than the other. In addition, in FIG. 19(A), an example in which the display areas of the display unit 9631b and the display unit 9631a are the same is shown, but it is not particularly limited, and the size of one may be different from that of the other, and the display quality may also be different. For example, one may be a display panel that can perform higher-definition display than the other. In addition, in FIG. 19(A), an example in which the display areas of the display unit 9631b and the display unit 9631a are the same is shown, but it is not particularly limited, and the size of one may be different from that of the other, and the display quality may also be different. For example, one may be a display panel that can perform higher-definition display than the other.

[0334] FIG. 19(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that in FIG. 19(B), a configuration including a battery 9635 and a DCDC converter 9636 is shown as an example of the charge / discharge control circuit 9634. FIG. 19(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that in FIG. 19(B), a configuration including a battery 9635 and a DCDC converter 9636 is shown as an example of the charge / discharge control circuit 9634. FIG. 19(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that in FIG. 19(B), a configuration including a battery 9635 and a DCDC converter 9636 is shown as an example of the charge / discharge control circuit 9634. FIG. 19(B) shows a closed state, and the tablet terminal includes a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. Note that in FIG. 19(B), a configuration including a battery 9635 and a DCDC converter 9636 is shown as an example of the charge / discharge control circuit 9634.

[0335] Since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, the display unit 9631a and the display unit 9631b can be protected, and a tablet terminal with excellent durability and reliability from the viewpoint of long-term use can be provided. Since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, the display unit 9631a and the display unit 9631b can be protected, and a tablet terminal with excellent durability and reliability from the viewpoint of long-term use can be provided. Since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, the display unit 9631a and the display unit 9631b can be protected, and a tablet terminal with excellent durability and reliability from the viewpoint of long-term use can be provided.

[0336] In addition, the tablet terminal shown in FIGS. 19(A) and 19(B) can also be used in various situations. A function for displaying reports (such as still images, moving images, text images, etc.), a calendar, a date, or a time, etc. A function for displaying on a display unit, a touch input function for touch input operation or editing of the information displayed on the display unit, A function for controlling processing by various software (programs), etc., and the like can be achieved. And so on.

[0337] Power can be supplied to a touch panel, a display unit, or a video signal processing unit, etc. by a solar cell 9633 mounted on the surface of the tablet-type terminal. Note that the solar cell 9633 can be provided on one side or both sides of the housing 9630, and can be configured to efficiently charge the battery 9635. As the battery 9635, using a lithium-ion battery has advantages such as being able to achieve miniaturization. And so on.

[0338] Also, the configuration and operation of the charge and discharge control circuit 9634 shown in Fig. 19(B) will be described with reference to the block diagram in Fig. 19(C ). In Fig. 19(C), the solar cell 9633, the battery 96 35, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display unit 9631 are shown, and the battery 9635, the DCDC converter 9636 , the converter 9637, and the switches SW1 to SW3 correspond to the locations in the charge and discharge control circuit 9634 shown in Fig. 19(B).

[0339] First, an example of the operation when power is generated by the solar cell 9633 due to external light will be described. The power generated by the solar cell is stepped up or down by the DCD C converter 9636 to become a voltage for charging the battery 9635. Then, the operation of the display unit 9631 is powered by the sun When the power from the battery 9633 is used, the switch SW1 is turned on, and the converter 96 37 will step up or step down the voltage to the required voltage for the display unit 9631. Also, when the display on the display unit 96 31 is not performed, SW1 is turned off and SW2 is turned on to charge the battery 96 35.

[0340] Note that the solar cell 9633 is shown as an example of a power generation means, but it is not particularly limited, and the battery can be charged by other power generation means such as a piezoelectric element (piezoelectric element) or a thermoelectric conversion element (Peltier element). 9635 may be configured to be charged. For example, a contactless power transmission module that wirelessly (non-contact) transmits and receives power for charging, or a configuration that combines other charging means may also be used.

[0341] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

Explanation of Reference Numerals

[0342] 101: Gate electrode layer 102: Gate insulating film 103: Oxide semiconductor film 104: Insulating layer 105: Source electrode layer 106: Drain electrode layer 107: Protective insulating film

Claims

1. An oxide semiconductor film having a channel formation region, an insulating layer having a region on the oxide semiconductor film, a first conductive layer having a region in contact with the upper surface of the oxide semiconductor film, a second conductive layer having a region in contact with the upper surface of the oxide semiconductor film, a transistor comprising: In a cross-sectional view in the channel length direction of the transistor, the angle formed by the tangent of the side surface of the insulating layer and the surface of the oxide semiconductor film is 60° or less at the lower end of the insulating layer, and the contact point of the tangent changes continuously so as to become smaller as it goes from the lower end of the insulating layer to the upper surface of the insulating layer, having a region that varies, The transistor, wherein the film thickness of the insulating layer is 0.3 μm or less.

2. An oxide semiconductor film having a channel formation region, an insulating layer having a region on the oxide semiconductor film, a first conductive layer having a region in contact with the upper surface of the oxide semiconductor film, a second conductive layer having a region in contact with the upper surface of the oxide semiconductor film, a transistor comprising: The oxide semiconductor film has a first region, and a second region and a third region disposed with the first region interposed therebetween, The insulating layer is in contact with the upper surface of the oxide semiconductor film in the first region, The first conductive layer is in contact with the upper surface of the oxide semiconductor film in the second region, The second conductive layer is in contact with the upper surface of the oxide semiconductor film in the third region, In a cross-sectional view in the channel length direction of the transistor, the angle formed by the tangent of the side surface of the insulating layer and the surface of the oxide semiconductor film is 60° or less at the lower end of the insulating layer, and the contact point of the tangent changes continuously so as to become smaller as it goes from the lower end of the insulating layer to the upper surface of the insulating layer, having a region that varies, The transistor, wherein the film thickness of the insulating layer is 0.3 μm or less.

3. The transistor according to claim 1 or claim 2, wherein the film thickness of the insulating layer is 5 nm or more and 0.1 μm or less.

4. The transistor according to any one of claims 1 to 3, wherein the insulating layer has silicon oxide.

5. The transistor according to any one of claims 1 to 4, wherein the oxide semiconductor film has In, Ga, and Zn.

Images