Representation device

Abstract

To manufacture a semiconductor device and a display device with fewer steps.SOLUTION: A semiconductor device includes a transistor 100 and a pixel electrode 110. The transistor includes a first gate electrode 101, a first insulating layer 102 on the first gate electrode, a semiconductor layer 103 on the first insulating layer, a second insulating layer 105 on the semiconductor layer, and a second gate electrode 106 on the second insulating layer. The first gate electrode includes a region overlapping with the semiconductor layer through the first insulating layer. The second gate electrode includes a region overlapping with the semiconductor layer through the second insulating layer. The pixel electrode is provided on the second insulating layer. In the first region 121, at least part of the second gate electrode corresponds to at least a part of the region overlapping with at least part of the semiconductor layer. The second region 122 is at least part of the region where the pixel electrode is provided. The second insulating layer in the first region is thinner than the second insulating layer in the second region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a display device, a light-emitting device, and methods for manufacturing them. In particular, it relates to a semiconductor device, a display device, a light-emitting device using a transistor, and methods for manufacturing them. Or, it relates to an electronic device using a semiconductor device, a display device, or a light-emitting device.

Background Art

[0002] In a transistor having gate electrodes above and below a semiconductor layer, it is known that the on-current can be increased or the threshold can be controlled to reduce the off-current. A transistor having such a configuration is called a double-gate transistor or a dual-gate transistor. Hereinafter, a transistor having such a configuration may also be referred to as a bottom-gate transistor having a back gate electrode.

[0003] A bottom-gate transistor having a back gate electrode can be used, for example, in a display device. (See FIG. 7 etc. of Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the display device described in Patent Document 1, in order to increase the aperture ratio or reduce the noise to the pixel electrode, an insulating layer for planarization is formed on the transistor, and the planarization ​​​​​​​A pixel electrode is formed on an insulating layer for use. Here, the back gate electrode of the transistor is , which is the lower layer of the insulating layer for planarization and is disposed at a position close to the semiconductor layer (the semiconductor layer in which a channel is formed ) of the transistor.

[0006] In the display device described in Patent Document 1, since the back gate electrode is formed in a layer different from the pixel electrode , there is a problem that the manufacturing process increases compared to a display device using a transistor having a configuration without a back gate electrode.

[0007] In order to reduce the increase in the manufacturing process of the display device, when the back gate electrode and the pixel electrode are formed in the same layer , there is an insulating layer for planarization between the back gate electrode and the semiconductor layer of the transistor . Since the insulating layer for planarization generally has a large thickness, there is a problem that the back gate electrode cannot sufficiently perform its function.

[0008] One aspect of the present invention is to fabricate a semiconductor device using a bottom gate type transistor having a back gate electrode in fewer processes. Or, one aspect of the present invention is to provide a semiconductor device using a bottom gate type transistor having a back gate electrode that can be fabricated in fewer processes. Or, one aspect of the present invention is to provide a semiconductor device using a bottom gate type transistor having a back gate electrode that can apply a strong electric field to the semiconductor layer by the back gate electrode. Or, one aspect of the present invention is to provide a semiconductor device in which the threshold voltage is controlled. Or, one aspect of the present invention is to provide a semiconductor device that easily becomes in a normally-off state. Or, one aspect of the present invention is ​​​​One aspect aims to provide a semiconductor device using a transistor with a large on-current as one of the problems. Or, one aspect of the present invention aims to provide a semiconductor device having a transistor capable of suppressing light from entering a channel or the like as one of the problems. Or, one aspect of the present invention aims to provide a semiconductor device having a transistor that is less likely to deteriorate as one of the problems. Or, one aspect of the present invention aims to provide a semiconductor device in which the thickness of an insulating layer provided over a channel of a transistor is made different using a halftone mask or a grayscale mask as one of the problems. Or, one aspect of the present invention aims to provide a better semiconductor device while suppressing an increase in the number of processes as one of the problems. Or, one aspect of the present invention aims to provide a semiconductor device in which an increase in cost is suppressed by suppressing an increase in the number of processes as one of the problems. Or, one aspect of the present invention aims to provide a display device capable of performing accurate display using a transistor with a small off-current as one of the problems. Or, one aspect of the present invention aims to provide a display device with a high aperture ratio as one of the problems. Or, one aspect of the present invention aims to provide a semiconductor device with less noise to a pixel electrode as one of the problems. Also, one aspect of the present invention aims to provide a semiconductor device in which an insulating layer provided under a pixel electrode is thicker than an insulating layer provided under a back gate electrode as one of the problems. Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification,

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, drawings, Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and the specification, It is possible to extract problems other than these from the descriptions of the drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention has a transistor and a pixel electrode. The transistor has a first gate electrode, a first insulating layer on the first gate electrode, a semiconductor layer on the first insulating layer, and a semiconductor layer having a second insulating layer on the layer and a second gate electrode on the second insulating layer. The first gate electrode has a region overlapping the semiconductor layer via the first insulating layer, and the second gate electrode has a second region overlapping the semiconductor layer via the insulating layer. The pixel electrode is provided on the second insulating layer and the first region is at least a part of the region where at least a part of the second gate electrode overlaps with at least a part of the semiconductor layer. The second region is at least a part of the region where the pixel electrode is provided. The second insulating layer in the first region is thinner than the second insulating layer in the second region. It is a semiconductor device characterized by this. region. The second insulating layer in the first region is thinner than the second insulating layer in the second region. It is a semiconductor device characterized by this.

[0011] The transistor further has a first electrode and a second electrode, and one of the first electrode and the second electrode can be used as the source electrode and the other as the drain electrode. The pixel electrode may be electrically connected to the transistor at an opening provided in the second insulating layer. The transistor further has a first electrode and a second electrode, and one of the first electrode and the second electrode can be used as the source electrode and the other as the drain electrode. The pixel electrode may be electrically connected to the transistor at an opening provided in the second insulating layer. layer.

[0012] The second insulating layer may include either one or both of a color filter and a black matrix. both of a color filter and a black matrix.

[0013] One aspect of the present invention forms a first gate electrode on an insulating surface, forms a first insulating layer on the first gate electrode, and on the first insulating layer, via the first insulating layer, of the first gate electrode. forms a first insulating layer on the first gate electrode, and on the first insulating layer, via the first insulating layer, of the first gate electrode. Form a semiconductor layer in which at least a part overlaps with at least a part, and on the semiconductor layer, a first region and a second region are provided, and form a second insulating layer in which the first region is thinner than the second region, and on the second insulating layer, a second gate electrode in which at least a part of the semiconductor layer overlaps with at least a part through the first region of the second insulating layer, and on at least a part of the second region of the second insulating layer, form at least a part of a pixel electrode. A method for manufacturing a semiconductor device is characterized by this.

[0014] In one aspect of the present invention, a first gate electrode is formed on an insulating surface, and on the first gate electrode a first insulating layer is formed, and on the first insulating layer, a semiconductor layer in which at least a part overlaps with at least a part of the first gate electrode through the first insulating layer is formed, and on the semiconductor layer, a first region and a second region are provided, the first region is thinner than the second region, and a second insulating layer having a penetrating opening is formed, and on the second insulating layer, a second gate electrode in which at least a part of the semiconductor layer overlaps with at least a part through the first region of the second insulating layer, and on at least a part of the second region of the second insulating layer, at least a part overlaps, and in the penetrating opening, a pixel electrode in contact with a lower wiring or an electrode is formed. A method for manufacturing a semiconductor device is characterized by this.

[0015] The second insulating layer may be formed by using a halftone mask, a grayscale mask, a phase shift mask, or a multi-tone mask.

Advantages of the Invention

[0016] According to one aspect of the present invention, a semiconductor device using a bottom gate type transistor having a back gate electrode can be manufactured with fewer steps. Or, with fewer steps ​​​​​​A semiconductor using a bottom gate type transistor having a back gate electrode that can be manufactured. An apparatus can be provided. Or, a semiconductor apparatus that can apply a strong electric field to a semiconductor layer by a back gate electrode can be provided. Or, a semiconductor apparatus whose threshold voltage can be controlled can be provided. Or, a semiconductor apparatus that easily becomes in a normally-off state can be provided. Or, a semiconductor apparatus using a transistor with a large on-current can be provided. Or, using a halftone mask, a grayscale mask, a phase shift mask, or a multi-tone mask, etc., a semiconductor apparatus that makes the thickness of the insulating layer provided on the channel of the transistor different can be provided. Or, while suppressing an increase in the number of processes, a better semiconductor apparatus can be provided. Or, by suppressing an increase in the number of processes, a semiconductor apparatus with a suppressed increase in cost can be provided. Or, a display device that can perform accurate display using a transistor with a small off-current can be provided. Or, a display device with a high aperture ratio can be provided. Or, a display device with less noise to a pixel electrode can be provided. Or, a display device in which the insulating layer provided under the pixel electrode is thicker than the insulating layer provided under the back gate electrode can be provided.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present The present invention is not construed as being limited to the description of the embodiments shown below. In the following description of the configurations, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repeated description thereof will be omitted.

[0019] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with the content described in another part (even part of the content) in that embodiment, and / or the content described in one or more other embodiments (even part of the content). That is, combinations, replacements, etc. can be made.

[0020] Note that the configuration of a figure (even part of it) described in one embodiment can be combined with the configuration of another part of that figure, the configuration of another figure (even part of it) described in that embodiment, and / or the configuration of a figure (even part of it) described in one or more other embodiments. That is, combinations can be made.

[0021] Note that in the figures, the size, thickness, or area may be exaggerated for clarity. Therefore, one aspect of the embodiments of the present invention is not necessarily limited to its scale. Or, the figures schematically show ideal examples. Therefore, one aspect of the embodiments of the present invention is not limited to the shapes shown in the figures. For example, it can include variations in shape due to manufacturing techniques, variations in shape due to errors, etc. That is, it is possible.

[0022] Note that when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. including the case where it is. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and includes those other than the connection relationship shown in the figure or the text. As an example of the case where X and Y are electrically connected, one or more elements (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between X and Y can be connected between X and Y. not limited to the connection relationship shown in the figure or the text, and includes those other than the connection relationship shown in the figure or the text.

[0023] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y can be connected between X and Y. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected. For example, elements (such as switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between X and Y can be connected between X and Y.

[0024] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y can be connected between X and Y. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y X and Y are considered to be functionally connected.

[0025] In addition, when it is explicitly described that X and Y are electrically connected, it is considered to include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. including the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected.

[0026] In addition, even if components that are independent on the circuit diagram are shown to be electrically connected, actually, for example, when a part of the wiring also functions as an electrode, etc. ​​​The conductive layer may also have the functions of a plurality of components such as wirings and electrodes. In this specification, electrical connection includes such a case where one conductive layer has the functions of a plurality of components even when it has them combined.

[0027] (Embodiment 1) In this embodiment, one aspect of a semiconductor device (such as a display device, a light-emitting device, etc.) of the present invention will be described with reference to the drawings.

[0028] A cross-sectional view of a semiconductor device according to one aspect of the present invention is shown in Fig. 1(A). The semiconductor device has a transistor 100 and an electrode 110 on an insulating surface ( or an insulating substrate) 200. The transistor 100 has an electrode 101, an insulating layer 102 on the electrode 101, a semiconductor layer 103 on the insulating layer 102, an insulating layer 105 on the semiconductor layer 103, and an electrode 106 on the insulating layer 105. The electrode 101 has a region overlapping the semiconductor layer 103 via the insulating layer 102. The electrode 106 has a region overlapping the semiconductor layer 103 via the insulating layer 105. The electrode 110 is provided on the insulating layer 105. The region 121 is at least a part of the region where at least a part of the electrode 106 overlaps with at least a part of the semiconductor layer 103. The region 1 22 is at least a part of the region where the electrode 110 is provided. The insulating layer 105 in the region 12 1 is thinner than the insulating layer 105 in the region 122. The insulating layer 105 has a region 122 that is thicker than the region 121, and the region 121 is at least a part of the region where the electrode 106 overlaps with the semiconductor layer 103, and it can also be said that the region 122 overlaps with at least a part of the electrode 110.

[0029] Here, electrode 101 functions as the first gate electrode of transistor 100, and electrode 106 can function as the second gate electrode (back gate electrode) of transistor 100. Also, electrode 110 can function as a pixel electrode. Since electrode 106 overlaps with semiconductor layer 103 through the thin region (region 121) of insulating layer 105, electrode 106 functions sufficiently as a back gate electrode. Electrodes 110 and 106 may be formed by etching the same conductive film. In this case, electrodes 110 and 106 have the same material and generally have the same film thickness. Also, electrodes 110 and 106 may be formed by etching different conductive films. When etching the same conductive film, the number of process steps can be reduced.

[0030] Note that it is desirable for the transistor to have both a first gate electrode and a second gate electrode (back gate electrode). However, one aspect of the embodiment of the present invention is not limited to this, and it is also possible to have only one of the first gate electrode or the second gate electrode (back gate electrode) and not have the other. For example, as shown in FIG. 66(C), a configuration without electrode 106 may be used. Even in such a case, it can function as a transistor.

[0031] In FIG. 1(A), transistor 100 further has electrodes 104a and 104b. One of electrodes 104a and 104b can be used as a source electrode, and the other can be used as a drain electrode. In FIG. 1(A), electrodes 104a and 104b are above semiconductor layer 103 (for example, electrodes 104a and 104b are in contact with the upper surface and side surface of semiconductor layer 103)​​​​​​ It is provided in the sea urchin). The lower surface of the semiconductor layer 103 and the electrodes 104a and 104b are not in contact.

[0032] Note that it is desirable for the transistor to have both a source electrode and a drain electrode. However, one aspect of the embodiment of the present invention is not limited to this, and the transistor may have only one of the source electrode or the drain electrode and not have the other, and it is also possible not to have both. Even in such a case, if the transistor is connected to another element (for example, another transistor) using the semiconductor layer 10 3, a transistor in which a channel is formed in the semiconductor layer 103 can function normally.

[0033] Note that a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. Here, since the source and the drain change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the part that functions as the source and the part that functions as the drain may not be called the source or the drain. In that case, as an example, one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other of the source and the drain may be denoted as the second terminal, the second electrode, or the second region.

[0034] ​​​The electrode 110 is electrically connected to the transistor 100 through an opening provided in the insulating layer 105. can be connected to

[0035] In addition, when explicitly stating "Y on top of X" or "Y on top of X", X It is not limited to Y being directly on top of X. This also includes cases where there is another object between X and Y. Here, X and Y are objects (e.g. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.

[0036] Thus, for example, if a description explicitly states "layer Y on (or on) layer X," In this case, layer Y is directly above layer X, and layer X is directly above another layer (e.g. This includes cases where there is a layer (e.g. layer Z) and layer Y is directly on top of it. The other layer (eg, layer Z) may be a single layer or multiple layers (laminate).

[0037] Furthermore, the same applies when it is explicitly stated that "Y is above X." It is not limited to Y being directly on top of X, but may also be the case where another object is between X and Y. For example, if we say "above layer X, layer Y is located," we mean the layer X. There is layer Y directly above and there is another layer (say layer Z) directly above and in contact with layer X. This includes the case where layer Y is directly on top of it. Z, etc.) may be a single layer or a multi-layer (laminate).

[0038] The same applies to the case where there is a Y below an X, or a Y below an X.

[0039] Note that, as shown in FIG. 9(A), even if the thickness of the region of the semiconductor layer 103 that does not overlap with the electrode 104a and the electrode 104 b is reduced. For example, when performing the etching process for forming the electrodes 104a and 104 b, a part of the surface of the semiconductor layer 103 existing under the layers that will become the electrodes 104a and 104b may be etched. In this way, a transistor in which at least a part of the channel region in the semiconductor layer 103 becomes thin (or a transistor without a channel protection film between the upper part of the channel and the electrodes 104a and 104b) may be referred to as a channel etching type transistor. The semiconductor layer 103 is etched. In this way, a transistor in which at least a part of the channel region in the semiconductor layer 103 becomes thin (or a transistor without a channel protection film between the upper part of the channel and the electrodes 104a and 104b) may be referred to as a channel etching type transistor. conductor layer 103 may be etched. In this way, a transistor in which at least a part of the channel region in the semiconductor layer 103 becomes thin (or a transistor without a channel protection film between the upper part of the channel and the electrodes 104a and 104b) may be referred to as a channel etching type transistor. For example, a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced).

[0040] One aspect of the semiconductor device of the present invention is not limited to FIG. 1(A). Examples of other configurations of the semiconductor device of the present invention are shown below. Note that the same parts as those in FIG. 1(A) are denoted by the same reference numerals, and the description thereof is omitted. One aspect of the semiconductor device of the present invention is not limited to FIG. 1(A). Examples of other configurations of the semiconductor device of the present invention are shown below. Note that the same parts as those in FIG. 1(A) are denoted by the same reference numerals, and the description thereof is omitted. For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced).

[0041] For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced). For example, as shown in FIG. 1(B), a configuration in which an insulating layer 107 is provided between the semiconductor layer 103 and the electrodes 104a and 104b can also be adopted. The insulating layer 107 has a function as a protective film (channel protection film) for preventing the semiconductor layer 103 (particularly, the channel region of the semiconductor layer 103) from being etched when performing the etching process for forming the electrodes 104a and 104b. A transistor provided with a channel protection film may be referred to as a channel protection type transistor. In this case, since the semiconductor layer 103 can be made thinner, the S value of the transistor 100 can be improved (reduced).

[0042] Note that when a channel protection type transistor is used, as shown in FIG. 65(D), region 1 In 21, it is possible to remove the insulating layer 105. In that case, the electrode 106 and the insulating layer 107 are in a structure where they are in direct contact in part. By doing so, the electrode 106 can apply a stronger electric field to the semiconductor layer 103 as a back gate electrode. Also, for example, as shown in Fig. 2(A), the electrodes 104a and 104b may be formed below the semiconductor layer 103 (for example, such that a part of the upper surfaces and end faces of the electrodes 104a and 104b are in contact with the lower surface of the semiconductor layer 103). By doing so, the semiconductor layer 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). In 21, it is possible to remove the insulating layer 105. In that case, the electrode 106 and the insulating layer 107 are in a structure where they are in direct contact in part. By doing so, the electrode 106 can apply a stronger electric field to the semiconductor layer 103 as a back gate electrode. .

[0043] Or, for example, as shown in Fig. 2(A), the electrodes 104a and 104b may be formed below the semiconductor layer 103 (for example, such that a part of the upper surfaces and end faces of the electrodes 104a and 104b are in contact with the lower surface of the semiconductor layer 103). By doing so, the semiconductor layer 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). Also, for example, as shown in Fig. 2(A), the electrodes 104a and 104b may be formed below the semiconductor layer 103 (for example, such that a part of the upper surfaces and end faces of the electrodes 104a and 104b are in contact with the lower surface of the semiconductor layer 103). By doing so, the semiconductor layer 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). Or, for example, as shown in Fig. 2(A), the electrodes 104a and 104b may be formed below the semiconductor layer 103 (for example, such that a part of the upper surfaces and end faces of the electrodes 104a and 104b are in contact with the lower surface of the semiconductor layer 103). By doing so, the semiconductor layer 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller). Or, for example, as shown in Fig. 2(A), the electrodes 104a and 104b may be formed below the semiconductor layer 103 (for example, such that a part of the upper surfaces and end faces of the electrodes 104a and 104b are in contact with the lower surface of the semiconductor layer 103). By doing so, the semiconductor layer 103 can be prevented from being damaged when the electrodes 104a and 104b are etched. Or, the semiconductor layer 103 can be made thinner, and the S value can be improved (the S value can be made smaller).

[0044] Or, for example, as shown in Fig. 3(A), the end portions 131a and 131b of the semiconductor layer 103 and the end portions 132a and 132b of the electrodes 104a and 104b can be made to have a substantially aligned shape. Such a semiconductor layer 103 and electrodes 104a and 104b can be formed by etching a laminated film of a semiconductor film and a conductive film on the semiconductor film using the same mask. As the mask, a photomask having three or more regions with different light transmittances for exposure (hereinafter referred to as a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask) can be used. Or, for example, as shown in Fig. 3(A), the end portions 131a and 131b of the semiconductor layer 103 and the end portions 132a and 132b of the electrodes 104a and 104b can be made to have a substantially aligned shape. Such a semiconductor layer 103 and electrodes 104a and 104b can be formed by etching a laminated film of a semiconductor film and a conductive film on the semiconductor film using the same mask. As the mask, a photomask having three or more regions with different light transmittances for exposure (hereinafter referred to as a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask) can be used. Or, for example, as shown in Fig. 3(A), the end portions 131a and 131b of the semiconductor layer 103 and the end portions 132a and 132b of the electrodes 104a and 104b can be made to have a substantially aligned shape. Such a semiconductor layer 103 and electrodes 104a and 104b can be formed by etching a laminated film of a semiconductor film and a conductive film on the semiconductor film using the same mask. As the mask, a photomask having three or more regions with different light transmittances for exposure (hereinafter referred to as a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask) can be used. b can be formed by etching a laminated film of a semiconductor film and a conductive film on the semiconductor film using the same mask. As the mask, a photomask having three or more regions with different light transmittances for exposure (hereinafter referred to as a halftone mask, a gray tone mask, a phase shift mask, or a multi-tone mask) can be used. By using a halftone mask, a region where the semiconductor layer 103 is exposed and a region where the semiconductor layer 103 is removed can be formed by an etching process using a single mask. By using a halftone mask, a region where the semiconductor layer 103 is exposed and a region where the semiconductor layer 103 is removed can be formed by an etching process using a single mask. By using a halftone mask, a region where the semiconductor layer 103 is exposed and a region where the semiconductor layer 103 is removed can be formed by an etching process using a single mask. By using a halftone mask, a region where the semiconductor layer 103 is exposed and a region where the semiconductor layer 103 is removed can be formed by an etching process using a single mask. 103 and a region where the semiconductor layer 103 is removed can be formed by an etching process using a single mask. This makes it possible to further reduce the manufacturing process of the transistor 100 and achieve further cost reduction of the semiconductor device. When the semiconductor layer 10 3, the electrode 104a, and the electrode 104b are formed using a halftone mask, the semiconductor layer 103 will necessarily exist under the electrode 104a and the electrode 104b. Note that the end portions 132a and / or the end portions 132b may be stepped.

[0045] Alternatively, as shown in Fig. 3(B), an insulating layer 107 that functions as a channel protection film can be provided in the configuration shown in Fig. 3(A). Thus, even in cases other than Fig. 3(B), a channel protection film can be additionally provided in various transistors where the channel protection film is not provided.

[0046] Alternatively, for example, as shown in Fig. 9(A), a configuration can be adopted in which conductive layers 108a and 108b are provided between the semiconductor layer 103, the electrode 104a, and the electrode 10 4b. The conductive layers 108a and 108b can be formed using, for example, a semiconductor layer doped with an impurity element that imparts conductivity. Alternatively, for example, the conductive layers 108a and 108 b can be formed using a conductive metal oxide. Alternatively, for example, the conductive layers 108a and 108b can be formed using a conductive metal oxide doped with an impurity element that imparts conductivity. In the case of Fig. 1(A) etc., an impurity element that imparts conductivity may be added to a part of the region of the semiconductor layer 103. Examples of impurity elements that impart conductivity include phosphorus, arsenic, boron, hydrogen, tin, etc.

[0047] ​​​​​​​​​​​Here, in FIG. 9(A), among the semiconductor layer 103, the electrodes 104a and 104b , and in the regions that do not overlap with the conductive layers 108a and 108b, the thickness becomes thinner . This is because when performing the etching process for forming the electrodes 104a and 104b, and the conductive layers 108a and 108b, a part of the surface of the semiconductor layer 103 existing in the lower layer of the layers that will become the electrodes 104a and 104b, as well as the layers that will become the conductive layers 108a and 108b, is etched (channel etching type transistor). Also, by providing a channel protection film between the semiconductor layer 103 and the conductive layers 108a and 108b, it is possible to prevent the semiconductor layer 103 from being etched (channel protection type transistor).

[0048] Note that in the above, the electrodes 110 and 106 are shown with a configuration formed using the same layer, but it is not limited to this, and the electrodes 110 and 106 may be formed using different layers.

[0049] Or, an insulating layer can be provided between the electrodes 104a and 104b and the semiconductor layer 103, or between the electrodes 104a and 104b and the conductive layers 108a and 108b. And an opening is provided in the insulating layer to connect the electrodes 104a and 104b to the semiconductor layer 103, or to connect the electrodes 104a and 104b to the conductive layers 108a and 108b.

[0050] Note that as the substrate having the insulating surface 200, various substrates can be used. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, For example, a single crystal substrate or a silicon substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film, etc. are available. Further, the transistor 100 may be formed on a substrate and then the transistor 100 may be disposed on another substrate by transposing the transistor 100 to the other substrate. As described above, in the transistor 100 shown in FIGS. 1(A), 1(B), 2(A), 3(A), 3(B), 9(A), etc., the threshold voltage can be effectively controlled by the back gate electrode. Therefore, it is possible to make it easier to be in the normally-off state. Or, the on-current can be effectively increased by the back gate electrode. Or, the off-current can be effectively decreased by the back gate electrode. Or, the on-off ratio can be increased by the back gate electrode. Therefore, by adopting the above configuration in a display device, the display device can perform accurate display. Or, by adopting the above configuration in a display device or a light-emitting device and making the insulating layer 105 function also as a planarization film, the aperture ratio can be increased. This embodiment is one of the basic examples among the configuration examples which are one aspect of the present invention. Therefore, for a part or all of it, changes, additions, modifications, deletions, applications, generalization to a higher concept, or

[0051]

[0052]

[0053] ​​​​​​​​​​​​​​It can be implemented in free combination with other embodiments corresponding to the sub-conceptualized ones. It is possible.

[0054] (Embodiment 2) In this embodiment, one aspect of the semiconductor device (such as a display device, a light-emitting device, etc.) of the present invention will be described with reference to the drawings. It will be described with reference to the drawings.

[0055] In Embodiment 1, in the configurations shown using FIGS. 1(A), 1(B), 2(A), 3(A), 3(B ), 9(A), etc., the insulating layer 105 in the region 122 or a part thereof can be a stack of a plurality of layers. The insulating layer 105 in the region 122 or a part thereof has a stack of m (m is a natural number of 2 or more) layers. The insulating layer 105 in the region 121 or a part thereof may have a stack of the same number or fewer layers than m or a single layer. Or, the insulating layer 105 may include an organic insulating layer. The insulating layer 10 5 may include a stack of an organic insulating layer and an inorganic insulating layer. For example, in the configurations shown in FIGS. 1(A), 1(B), 2(A), 3(A), 3(B),

[0056] 9(A), etc. described above, the insulating layer 105 in the region 122 has a stack of the layer 105a and the layer 105b, and the insulating layer 105 in the region 121 may have a single layer of the layer 105a. The layer 105b is formed above the layer 105a. Such a configuration is shown in FIGS. 1( C), 1(D), 2(B), 3(C), 3(D), 9(B). By adopting such a configuration, by utilizing the difference in etchability (selectivity ratio), only the necessary parts are etched, and a stack of the layer 105a and the layer 105b can be formed. It can be formed. As a result, it becomes easier to control the film thickness in each region of the insulating layer 105. Alternatively, depending on the film quality, different functions (for example, a planarization function, a function of blocking impurities, a light-shielding function, etc.) can be appropriately provided in each region. Or, by forming some of the layers using a photosensitive material, the number of process steps can be reduced.

[0057] Here, layer 105a may be an inorganic insulating layer and layer 105b may be an organic insulating layer. In that case, since an organic material is used, it is possible to make layer 105b thicker than layer 105a. By making layer 105a an inorganic insulating layer (more preferably, a silicon nitride film), for example, it is possible to prevent impurities in layer 105b from entering the transistor 100. Also, by making layer 105b an organic insulating layer, since the organic insulating layer can function as a planarization layer, it is possible to mitigate the unevenness caused by the transistor 100 or the like. In this way, the surface on which the electrode 110 is formed can be made flat. Therefore, for example, when the electrode 110 is used as a pixel electrode, display defects can be reduced. Or, since the film thickness of layer 105b can be increased, noise to the pixel electrode can be reduced. Or, since the etching selectivity is different due to the different film qualities, only the necessary parts can be selectively etched to form a stack of layer 105a and layer 105b having a predetermined shape.

[0058] Alternatively, layer 105a and / or layer 105b (or a part thereof) (more preferably layer 105b) may be made into a color filter and / or a black matrix. By forming a color filter and / or a black matrix, the bonding margin between the substrate provided with the transistor 1 00 (substrate having an insulating surface 200) and another substrate (e.g., a counter substrate in a display device etc.) can be increased. Or, by using a black matrix in the layer 105a and / or layer 105b (or a part thereof) near the transistor 100, light can be made less likely to enter the transistor 100. By making light less likely to enter, the off-current of the transistor 100 and the deterioration of the transistor 100 can be reduced. For example, as shown in FIG. 65(A), a black matrix 652 can be provided in a part of the layer 1 05b. Note that, as the black matrix, a configuration in which a plurality of color filters having different colors are stacked can also be used.

[0059] Note that, since it is desirable to form the color filter and / or the black matrix using an organic material, it is desirable to form it in the layer 105b. However, it is not limited to this, and as the black matrix, a conductive film having light-shielding properties can also be used.

[0060] Or, the film thickness of the layer 105a may be made thinner than the film thickness of the layer 105b. By making the film thickness of the layer 105a thinner, the electric field by the electrode 106 can be sufficiently supplied to the channel. Or, by making the film thickness of the layer 105b thicker, the unevenness caused by the transistor 100 etc. can be sufficiently alleviated.

[0061] Or, for example, in FIGS. 1(A), 1(B), 2(A), 3(A), 3( B), in the configuration shown in FIG. 9(A) etc., the insulating layer 105 in the region 122 has a laminate of layer 10 5b and layer 105c, and the insulating layer 105 in the region 121 may have a single layer of layer 105c. Layer 105c is formed above layer 105b. Such a configuration is , shown in FIGS. 26(A), 26(B), 27(A), 28(A), 28(B), 34( A). By adopting such a configuration, by utilizing the difference in etchability (selectivity ratio) and etching only the necessary portions, a laminate of layer 105b and layer 105c can be formed. As a result, it becomes easy to control the film thickness in each region of the insulating layer 105. Or, depending on the film quality, different functions (for example, planarization function, impurity blocking function, light shielding function, etc.) can be appropriately provided in each region. Also since some layers can be formed using a photosensitive material, the number of process steps can be reduced.

[0062] Here, layer 105b may be an organic insulating layer and layer 105c may be an inorganic insulating layer. In that case, since an organic material is used, it is possible to make layer 105b thicker than layer 105c. By making layer 105c an inorganic insulating layer (more preferably, a silicon nitride film), impurities in layer 1 05b can be prevented from entering the electrode 106 and the layers provided on the electrode 106 (for example, liquid crystal layer, alignment film , organic EL layer, etc.). Or, by making layer 105b an organic insulating layer, the organic insulating layer can be used as a planarization layer to relieve the unevenness caused by the transistor 100 etc. In this way, the surface on which the electrode 110 is formed can be made flat. Therefore, for example, when the electrode 110 is used as a pixel electrode, display irregularities can be reduced. Noise can be reduced. Or, since the film thickness of layer 105b can be increased, noise to the pixel electrode can be reduced. Or, due to the different film qualities, the etching selection ratio is different, so only the necessary parts can be selectively etched to form a stack of layer 105b and layer 105c with a predetermined shape.

[0063] Or, layer 105b, and / or, layer 105c (or a part thereof) can be (more preferably layer 105b) used as a color filter and / or a black matrix. By using a color filter and / or a black matrix, the bonding margin between the substrate (substrate having the insulating surface 200) on which the transistor 1 00 is provided and another substrate (for example, a counter substrate in a display device etc.) can be increased. Or, by using a black matrix in layer 105b and / or layer 105c (or a part thereof) near the transistor 1 00, light can be made less likely to enter the transistor 100. By making light less likely to enter, the off-current of the transistor 100 can be reduced and / or the degradation of the transistor 100 can be reduced. For example, as shown in FIG. 65(B), a black matrix 652 can be provided in a part of layer 105b. It should be noted that as the black matrix, a configuration in which a plurality of color filters with different colors are stacked can also be used.

[0064] It should be noted that since it is desirable to form the color filter and / or the black matrix using an organic material, it is desirable to form it in layer 105b. However, it is not limited to this, and a conductive film having light-shielding properties can also be used as the black matrix. ​

[0065] Alternatively, the thickness of the layer 105c may be smaller than the thickness of the layer 105b. By reducing the thickness, the electric field from the electrode 106 can be sufficiently supplied to the channel. Alternatively, by increasing the thickness of the layer 105b, the transistor 100 etc. The unevenness can be sufficiently reduced.

[0066] Alternatively, for example, the above-mentioned Figs. 1(A), 1(B), 2(A), 3(A), and 3( 9(A) and the like, the insulating layer 105 in the region 122 is the layer 10 5a, layer 105b and layer 105c are stacked, and the insulating layer 105 in the region 121 is layer 105a. Such a structure may be a laminate of layers 105a and 105c. D), Fig. 27(B), Fig. 28(C), Fig. 28(D), and Fig. 34(B). By using the difference in the ease of etching (selectivity), the necessary parts can be etched. By etching only the layer 105a, the layer 105b, and the layer 105c are formed as a stack. As a result, it becomes easier to control the film thickness of the insulating layer 105 in each region. Or, depending on the film quality, different functions (e.g., flattening function, blocking impurities) can be performed. Each area can be given an appropriate function (such as a function to block light, a function to block light, etc.). The layers can be formed using photosensitive materials, reducing the number of process steps. is possible.

[0067] Here, the layer 105a is an inorganic insulating layer, the layer 105b is an organic insulating layer, and the layer 105c is an inorganic insulating layer. In this case, since an organic material is used, the layers 105a and 105c are It is possible to make layer 105b thicker than layer 105a. By making layer 105a an inorganic insulating layer (more preferably, a silicon nitride film), for example, impurities in layer 105b can be prevented from entering the transistor 100. Alternatively, by making layer 105c an inorganic insulating layer (more preferably, a silicon nitride film), impurities in layer 105b can be prevented from entering the electrode 106 or the layer provided on the electrode 106. By making layer 105b an organic insulating layer, the organic insulating layer can be used as a planarizing layer to mitigate unevenness caused by the transistor 100 or the like. Thus, the surface on which the electrode 110 is formed can be made flat. Therefore, for example, when the electrode 110 is used as a pixel electrode, display defects can be reduced. Or, since the film thickness of layer 105b can be increased, noise to the pixel electrode can be reduced. Or, the film qualities of layer 105a and layer 105b, or layer 105b and layer 105c can be made different. Then, by utilizing the different etching selectivity due to the different film qualities, only the necessary portions can be selectively etched to form a laminate of layer 105a, layer 105b, and layer 105c having a predetermined shape. For example, impurities in layer 105b can be prevented from entering the transistor 100 by making layer 105a an inorganic insulating layer (more preferably, a silicon nitride film). Alternatively, by making layer 105c an inorganic insulating layer (more preferably, a silicon nitride film), impurities in layer 105b can be prevented from entering the electrode 106 or the layer provided on the electrode 106. For example, impurities in layer 105b can be prevented from entering the electrode 106 or the layer provided on the electrode 106 by making layer 105c an inorganic insulating layer (more preferably, a silicon nitride film). By making layer 105b an organic insulating layer, the organic insulating layer can be used as a planarizing layer to mitigate unevenness caused by the transistor 100 or the like. Thus, the surface on which the electrode 110 is formed can be made flat. Therefore, for example, when the electrode 110 is used as a pixel electrode, display defects can be reduced. Or, since the film thickness of layer 105b can be increased, noise to the pixel electrode can be reduced. Or, since the film thickness of layer 105b can be increased, noise to the pixel electrode can be reduced. Or, the film qualities of layer 105a and layer 105b, or layer 105b and layer 105c can be made different. Then, by utilizing the different etching selectivity due to the different film qualities, only the necessary portions can be selectively etched to form a laminate of layer 105a, layer 105b, and layer 105c having a predetermined shape. Then, by utilizing the different etching selectivity due to the different film qualities, only the necessary portions can be selectively etched to form a laminate of layer 105a, layer 105b, and layer 105c having a predetermined shape. Then, by utilizing the different etching selectivity due to the different film qualities, only the necessary portions can be selectively etched to form a laminate of layer 105a, layer 105b, and layer 105c having a predetermined shape.

[0068] Or, layer 105a, layer 105b, and / or layer 105c (or a part thereof) (more preferably layer 105b) may be used as a color filter and / or a black matrix. By using it as a color filter and / or a black matrix, the bonding margin between the substrate on which the transistor 100 is provided (the substrate having the insulating surface 200) and another substrate (for example, the counter substrate in a display device, etc.) can be increased. For example, when the electrode 110 is used as a pixel electrode, display defects can be reduced. Alternatively, by using a black matrix on layer 105a, layer 105b, and / or layer 105c ( or a part thereof) in the vicinity of transistor 100, light can be made difficult to enter transistor 100. By making it difficult for light to enter, it becomes possible to reduce the off-current of transistor 100 and / or reduce the deterioration of transistor 100. For example, as shown in FIG. 65(C), a black matrix 652 can be provided in a part of layer 105b. Note that, as the black matrix, a configuration in which a plurality of color filters with different colors are stacked can also be used.

[0069] Note that since it is desirable that the color filter and / or the black matrix be formed using an organic material, it is desirable that they be formed in layer 105b. However, it is not limited to this, and as the black matrix, a conductive film having light-shielding properties can also be used.

[0070] Note that layer 105a, layer 105b, and layer 105c may each be a single layer or a stack of a plurality of layers.

[0071] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiment 1. Therefore, it can be freely combined with any other embodiment of Embodiment 1 or implemented by replacement.

[0072] (Embodiment 3) In this embodiment, an aspect of a semiconductor device (such as a display device or a light-emitting device) of the present invention will be described with reference to the drawings.

[0073] In Embodiment 1, in the configurations shown using FIGS. 1(A), 1(B), 2(A), 3(A), 3(B ), 9(A), etc., a configuration in which the insulating layer 105 is thinned in the vicinity of the channel of the transistor 100 was shown. However, the range of the region ( region 121) where the insulating layer 105 is thinned is not limited to this. The range of the region 121 may be a part of the vicinity of the channel. For example, the configuration shown in FIG. 1(A) can be changed to the configuration shown in FIG. 66(A). In FIG. 66(A), the range of the region 121 is a part of the vicinity of the channel (a range narrower than the region 121 in FIG. 1(A)). The configurations of the figures other than FIG. 1(A) can be changed in the same way. Or, the range of the region 121 may be in the vicinity of the entire transistor 100, or may be a wider range. For example, in the vicinity of the transistor 100 (for example, the region where the electrode 106 overlaps with the electrode 104a and / or the electrode 104b), a configuration in which the insulating layer 1 05 is thinned may be used.

[0074] Also, in Embodiment 2, in the configurations shown in FIGS. 1(C), 1(D), 2(B), 3(C), 3(D), 9(B), 26(A), 26(B), 27(A), 28(A), 28(B), 34(A), 26(C), 26(D), 27(B), 28(C) , 28(D), 34(B), 65(A), 65(B), 65(C), etc., a configuration in which the layer 105b in the vicinity of the channel of the transistor 100 is removed to thin the insulating layer 105 was shown. However, the region where the layer 105b is removed is not limited to this. The region where the layer 105b is removed may be a part of the vicinity of the channel. For example, the configuration shown in FIG. 1( C) can be changed to the configuration shown in FIG. 66(B). In FIG. 66(B), ​ The range of the region 121 is a part near the channel (narrower than the region 121 in FIG. 1(C)). The configurations of the figures other than FIG. 1(C) can be changed in the same way. Alternatively, the range of the region 1 21 may be in the vicinity of the entire transistor 100, or may be a wider range. For example, in the configurations shown in FIG. 1(C), FIG. 1(D), FIG. 2(B), FIG. 3(C), FIG. 3(D), FIG. 9(B), FIG. 26(C), FIG. 26(D), FIG. 27(B), FIG. 28(C), FIG. 28(D), in the configuration shown in FIG. 34(B), the layer 105b near the transistor 100 can be removed and the insulating layer 105 can be thinned. For example, in the region where the electrode 106 overlaps with the electrode 104a and / or the electrode 104b, the layer 105b can be removed. This configuration is shown in FIG. 1(E) , FIG. 2(D), FIG. 2(C), FIG. 3(E), FIG. 2(E), FIG. 9(C), FIG. 26(E), FIG. 2 7(D), FIG. 27(C), FIG. 28(E), FIG. 27(E), FIG. 34(C).

[0075] Note that in the configurations shown in FIG. 26(E), FIG. 27(D), FIG. 27(C), FIG. 28(E), FIG. 27(E), FIG. 34(C), in part or all of the region where the layer 105b is removed, either the layer 105a or the layer 105c can be further removed.

[0076] In the vicinity of the transistor 100 (for example, the region where the electrode 106 overlaps with the electrode 104a and / or the electrode 10 4b), in the configuration where the insulating layer 105 is thinned, the capacitance value of the parasitic capacitance formed by the electrode 106 overlapping with the electrode 1 04a and / or the electrode 104b can be increased. Therefore, the parasitic capacitance can also be positively used as a holding capacitance. For example, the holding capacitance can be used as the holding capacitance of a pixel. In this way, the transistor Even if the insulating layer 105 is made thinner in the vicinity of the transistor 100, when a constant potential is applied to the electrode 106, that potential does not affect the potential of the electrode 104a and / or the electrode 104b. However, one aspect of the embodiment of the present invention is not limited to this.

[0077] On the other hand, when a varying potential (such as a pulse potential) is applied to the electrode 106 (for example, when a signal similar to the signal input to the electrode 101 is input to the electrode 106), in order to reduce the influence of the change in the potential applied to the electrode 106 on the potential of the electrode 104a and / or the electrode 104b, it is desirable to increase the thickness of the insulating layer 105 between the electrode 106 and the electrode 104a and / or the electrode 104b. For example, it is desirable that a layer 105b exists between the electrode 106 and the electrode 104a and / or the electrode 104b. In this way, the influence of the change in the potential applied to the electrode 106 on the potential of the electrode 104a and / or the electrode 104b can be reduced, and for example, noise can be prevented from entering the signal input to the electrode 110 connected to the electrode 104b. Therefore, when the electrode 110 is used as a pixel electrode, the display quality of the display device can be improved. However, one aspect of the embodiment of the present invention is not limited to this.

[0078] Note that the electrode 106 may be formed over the entire region 121, or may be formed at least in a part of the region 121. When the electrode 106 is small, the overlap between the electrode 104 a and / or the electrode 104b and the electrode 106 becomes small, so the influence of the change in the potential applied to the electrode 106 on the potential of the electrode 104a and / or the electrode 104b can be reduced.

[0079] ​​​​​​​​ Alternatively, when forming a drive circuit (e.g., a scanning line that inputs a signal to a pixel) using the transistor 100 or a signal line drive circuit), the entire drive circuit may be defined as the region 121. For example, the entire layer 105b on the drive circuit may be removed. This is because there is no need to provide a display element for image display on the drive circuit, so flattening by the layer 105b is not necessary. Alternatively, by removing the entire layer 105b on the drive circuit, the capacitance element (parasitic capacitance) formed by electrodes and wirings can be increased. In this way, the capacitance element (parasitic capacitance) for performing a bootstrap operation and the capacitance element (parasitic capacitance) for a dynamic circuit can be increased. Alternatively, when removing the entire layer 105b on the drive circuit, since there is no need for a margin to leave a part of the layer 105b, the layout area of the entire drive circuit can be reduced. In this case, the electrodes 106 of a plurality of the transistors 100 included in the drive circuit may be electrically connected to each other. Alternatively, among a plurality of the transistors 100 included in the drive circuit, the electrodes 106 may be separated from each other or may not be separated.

[0080] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 2. Therefore, it can be freely combined with other embodiments such as Embodiments 1 to 2 or implemented by replacement.

[0081] (Embodiment 4) In this embodiment, one aspect of the semiconductor device (such as a display device, a light-emitting device, etc.) of the present invention This will be described with reference to the drawings.

[0082] In the configuration examples of the semiconductor device or the like shown in the first to third embodiments, An example of the configuration of the connection portion between 110 and electrode 104b is shown.

[0083] Electrode 110 and electrode 104 when insulating layer 105 has a laminate of layers 105a and 105b An example of the configuration of the connection portion b will be described with reference to FIGS.

[0084] FIG. 4A shows the configuration shown in FIG. 1C and the electrode 110 and the electrode 104 in the configuration. In the enlarged view of FIG. 4(A), the edge of the opening of layer 105a is The ends of the openings in the layer 105b and the layer 105c are generally aligned. After forming a laminated film of film A which becomes layer 105a and film B which becomes layer 105b, the same photomask is used. It can be formed by etching film A and film B using a mask.

[0085] The shape of the connection between the electrode 110 and the electrode 104b is not limited to the configuration shown in the enlarged view of FIG. For example, the structure shown in FIG. 4B may be used. In FIG. 4B, the layer 105a The edge of the opening in layer 105a is not aligned with the edge of the opening in layer 105b, and the diameter of the opening in layer 105b is The diameter of the opening is larger than that of 05a (the difference in the diameter of the opening is shown as Δx1 in the figure). For example, the opening is formed by fabricating the structure shown in the enlarged view of FIG. 4(A) and then assembling the layer 105b. When layer 105b is ashed, layer 1 The insulating layer 05b is made of an organic insulating layer. Chemically reacting reactive oxygen molecules, ozone molecules, or oxygen atoms, etc., with the organic layer. by ashing to remove a part of the layer. Or, the film A that becomes the layer 105a After forming a laminated film of the film A that becomes the layer 105a and the film B that becomes the layer 105b, the films A and B are etched using a photomask. After that, the etched film B is further etched using another photomask to form it. Or, after forming a laminated film of the film A that becomes the layer 105a and the film B that becomes the layer 105b, the film B is etched using a photomask, and then the film A is etched using another photomask to form it as well. When etching the films A and B using another photomask, for example, as shown in FIG. 5(B), the diameter of the opening of the layer 105b can be made larger than the diameter of the opening of the layer 105a from the configuration shown in FIG. 4(B) (the difference in the diameter of the opening is indicated by Δx3 in the figure ). Or, when etching the films A and B using another photomask, for example, as shown in FIG. 5(A), the diameter of the opening of the layer 105a can be made larger than the diameter of the opening of the layer 105b (the difference in the diameter of the opening is indicated by Δx2 in the figure).

[0086] In FIGS. 4 and 5, a configuration example of the connection portion between the electrode 1 10 and the electrode 104b when the insulating layer 105 is not a laminate of the layer 105a and the layer 105b is shown. However, since the laminated structure of the insulating layer 105 is not limited to this, the connection portion between the electrode 110 and the electrode 104b can have various configurations according to the laminated structure .

[0087] For example, a configuration example of the connection portion between the electrode 110 and the electrode 104b when the insulating layer 105 is a laminate of the layer 105b and the layer 105c is shown in FIG. 29. FIG. 29(A) is shown in FIG. 26(A) FIG. 13 is a diagram showing a configuration in which the electrode 110 and the electrode 104b are connected to each other in an enlarged manner. In FIG. 29(A), the edge of the opening in layer 105b is not aligned with the edge of the opening in layer 105c. In FIG. 29(B), the diameter of the opening in layer 105b is larger than the diameter of the opening in layer 105c. The edge of the opening of layer 105b is not aligned with the edge of the opening of layer 105c. is larger than the diameter of the opening in layer 105b.

[0088] The openings having the shapes shown in FIG. 29(A) and FIG. 29(B) are formed by, for example, forming the film B which becomes the layer 105b. After the film B is etched using a photomask, the film C that will become the layer 105c is formed. The film C is then etched using another photomask to form the film. The opening having the shape shown in FIG. 29(B) can be formed, for example, by the film B which becomes the layer 105b and the layer 105 After forming a laminated film of film C, which becomes c, films B and C are etched using a photomask. Then, the etched film C is further etched using another photomask. The insulating layer can be formed by:

[0089] Although not shown in FIG. 29, the edge of the opening of the layer 105b and the edge of the opening of the layer 105c may be of generally uniform shape.

[0090] For example, when the insulating layer 105 is a laminate of the layers 105a, 105b, and 105c, An example of the configuration of the connection between the electrode 110 and the electrode 104b is shown in FIG. The configuration shown in FIG. 26(C) and the connection part between the electrode 110 and the electrode 104b in the configuration In FIG. 30(A), the edge of the opening in layer 105a and the edge of the opening in layer 105b are shown. The parts are generally aligned. The end of the opening of layer 105a and the end of the opening of layer 105b are not aligned with the end of the opening of layer 105 c, and the diameters of the openings of layer 105a and layer 105b are larger than the diameter of the opening of layer 105c . In FIG. 30(B), the end of the opening of layer 105a and the end of the opening of layer 105c are generally aligned . The end of the opening of layer 105a and the end of the opening of layer 105c are not aligned with the end of the opening of layer 105b, and the diameter of the opening of layer 105b is larger than the diameters of the openings of layer 105a and layer 1 05c

[0091] The opening having the shape shown in FIG. 30(A) can be formed, for example, by forming a laminated film of film A which becomes layer 105a and film B which becomes layer 105b, etching film B and film A with a photomask, then forming film C which becomes layer 105 c, and etching film C with another photomask .

[0092] The opening having the shape shown in FIG. 30(B) can be formed, for example, by forming a laminated film of film A which becomes layer 105a and film B which becomes layer 105b, etching film B with a photomask, then forming film C which becomes layer 105 c, and etching film C and film A with another photomask .

[0093] Although not shown in FIG. 30, the ends of the openings of layer 105a, layer 105b, and layer 105c may have an aligned shape .

[0094] Alternatively, the ends of the openings of layer 105a, layer 105b, and layer 105c may all have a non-aligned shape . In that case, the end of layer 105a is layer 105 ​​It may be configured to cover b. The end of layer 105b may or may not be covered by layer 105c. It may not be covered.

[0095] In addition, in the configurations shown in FIGS. 4 and 5, the taper angle (indicated by θ2 in the figure) of the end of the opening of layer 105a and the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b may be substantially the same or different from each other. In the configuration shown in FIG. 29, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may be substantially the same or different from each other. In the configuration shown in FIG. 30, the taper angle (indicated by θ2 in the figure) of the end of the opening of layer 105a, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b, and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may all be substantially the same, or two of the angles may be substantially the same, or the three angles may be different from each other. It is sufficient that they are approximately the same or different from each other. In the configuration shown in FIG. 29, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may be substantially the same or different from each other. In the configuration shown in FIG. 30, the taper angle (indicated by θ2 in the figure) of the end of the opening of layer 105a, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b, and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may all be substantially the same, or two of the angles may be substantially the same, or the three angles may be different from each other. The taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may be substantially the same or different from each other. It is sufficient that they are approximately the same or different from each other. In the configuration shown in FIG. 30, the taper angle (indicated by θ2 in the figure) of the end of the opening of layer 105a, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b, and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may all be substantially the same, or two of the angles may be substantially the same, or the three angles may be different from each other. The taper angle (indicated by θ2 in the figure) of the end of the opening of layer 105a, the taper angle (indicated by θ1 in the figure) of the end of the opening of layer 105b, and the taper angle (indicated by θ3 in the figure) of the end of the opening of layer 105c may all be substantially the same, or two of the angles may be substantially the same, or the three angles may be different from each other. It is sufficient that all three angles are substantially the same, or two of the angles are substantially the same, or the three angles are different from each other. It is sufficient that all three angles are substantially the same, or two of the angles are substantially the same, or the three angles are different from each other. That is, it is not limited to this.

[0096] As an example, when the film thickness of layer 105b is thick, it is desirable that θ1 is small in order to make the end of layer 105b as smooth as possible. For example, it is desirable that θ2 is larger than θ1. Also, for example, it is desirable that θ3 is larger than θ1. However, one aspect of the embodiments of the present invention is not limited to this. That is, it is desirable that θ2 is larger than θ1. Also, for example, it is desirable that θ3 is larger than θ1. However, one aspect of the embodiments of the present invention is not limited to this. Also, for example, it is desirable that θ3 is larger than θ1. However, one aspect of the embodiments of the present invention is not limited to this. That is, it is not limited to this.

[0097] Here, the taper angle of the end of the layer refers to the angle formed by the side surface (the tangent at the lower end of the end) of the end of the layer and the bottom surface of the layer when observed in the cross-sectional direction. By controlling the thickness and material of each layer, the etching conditions when forming openings in each layer, etc., the taper of each layer can be controlled. (The tangent at the lower end of the end) and the bottom surface of the layer. By controlling the thickness and material of each layer, the etching conditions when forming openings in each layer, etc., the taper of each layer can be controlled. And the taper of each layer can be controlled by controlling the thickness and material of each layer, the etching conditions when forming openings in each layer, etc. The corner can be controlled.

[0098] In addition, FIGS. 4, 5, 29, and 30 show configuration examples of the connection portion between the electrode 110 and the electrode 104b in the configuration shown in FIGS. 1(C), 26(A), and 26(C). However, in the semiconductor devices having other configurations shown in Embodiments 1 to 3, the same configuration can be applied to the connection portion between the electrode 110 and the electrode 104b.

[0099] In addition, the configuration examples of the connection portion between the electrode 110 and the electrode 104b shown in FIGS. 4, 5, 29, and 30 can be applied to the configuration of a connection portion that electrically connects any electrode provided under the insulating layer 105 and any electrode provided on the insulating layer 105 at an opening provided in the insulating layer 105. For example, it can also be applied to the configuration of a connection portion between an electrode formed in the same layer as the electrode 110 and an electrode formed in the same layer as the electrode 104b. For example, it can also be applied to the configuration of a connection portion between the electrode 110 or an electrode formed in the same layer as the electrode 110 and the electrode 101 or an electrode formed in the same layer as the electrode 101. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 101 or an electrode formed in the same layer as the electrode 101. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 104b or an electrode formed in the same layer as the electrode 104b. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 104b or an electrode formed in the same layer as the electrode 104b. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 104b or an electrode formed in the same layer as the electrode 104b. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 104b or an electrode formed in the same layer as the electrode 104b. For example, it can also be applied to the configuration of a connection portion between the electrode 106 or an electrode formed in the same layer as the electrode 106 and the electrode 104b or an electrode formed in the same layer as the electrode 104b.

[0100] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 3. Therefore, It can be implemented by freely combining with other embodiments such as Embodiment 1 to Embodiment 3. This is possible.

[0101] (Embodiment 5) In this embodiment, an example of the electrical connection between the electrode 106 of the transistor 100 and other electrodes or wirings will be described. In the drawings used for the description, the same parts as those in the drawings described in the previous embodiments are denoted by the same reference numerals, and the description thereof will be omitted. For example, the electrode 106 can be electrically connected to the electrode 101. By connecting in this way, the same potential as that of the electrode 101 can be supplied to the electrode 106. Therefore, the on-current of the transistor 100 can be increased. Examples of electrically connecting the electrode 106 to the electrode 101 are shown in FIGS. 6(A) to 6(E), FIGS. 7(A) to 7(E), FIGS. 8(A) to 8(E), FIGS. 9(D), FIGS. 9(E), FIGS. 31(A) to 31(E), FIGS. 32(A) to 32(E), FIGS. 33(A) to 33(E), FIGS. 34(D), FIGS. 34(E). Note that, for the various figures described in Embodiment 1 to Embodiment 4, similarly to these figures, the electrode 106 and the electrode 101 can be electrically connected, and the figures can be described in the same way. That is, it can come.

[0102] For example, the electrode 106 can be electrically connected to the electrode 101. By connecting in this way, the same potential as that of the electrode 101 can be supplied to the electrode 106. Therefore, the on-current of the transistor 100 can be increased. By connecting in this way, the same potential as that of the electrode 101 can be supplied to the electrode 106. Therefore, the on-current of the transistor 100 can be increased. Therefore, the on-current of the transistor 100 can be increased. Examples of electrically connecting the electrode 106 to the electrode 101 are shown in FIGS. 6(A) to 6(E), FIGS. 7(A) to 7(E), FIGS. 8(A) to 8(E), FIGS. 9(D), FIGS. 9(E), FIGS. 31(A) to 31(E), FIGS. 32(A) to 32(E), FIGS. 33(A) to 33(E), FIGS. 34(D), FIGS. 34(E). ~FIGS. 8(E), FIGS. 9(D), FIGS. 9(E), FIGS. 31(A) to 31(E), FIGS. 32(A) to FIGS. 32(E), FIGS. 33(A) to 33(E), FIGS. 34(D), FIGS. 34(E). Note that For the various figures described in Embodiment 1 to Embodiment 4, similarly to these figures, the electrode 106 and the electrode 101 can be electrically connected, and the figures can be described in the same way. come. That is, it can come.

[0103] Note that when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels, an opening may be formed for each pixel to electrically connect the electrode 106 to the electrode 101. As a result, the contact resistance and the wiring resistance can be reduced. Or, an opening may be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 101. As a result, the layout When forming a pixel matrix composed of a plurality of pixels by arranging the transistor 100 in each pixel, an opening may be formed for each pixel to electrically connect the electrode 106 to the electrode 101. This is possible. As a result, the contact resistance and the wiring resistance can be reduced. Or, an opening may be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 101. As a result, the layout The outer area can be reduced. Alternatively, the electrical connection between the electrode 106 and the electrode 101 may be made within the pixel matrix region or may be made outside the pixel matrix region. By making the connection outside the pixel matrix region, the layout area within the pixel matrix region can be reduced. As a result, the aperture ratio can be improved. Incidentally, when a drive circuit is provided outside the pixel matrix region, it is preferable that the electrical connection between the electrode 106 and the electrode 101 be made in the region between the drive circuit and the pixel matrix region.

[0104] Alternatively, for example, the electrode 106 can be electrically connected to the electrode 104a or the electrode 104b. By making the connection in this way, the same potential as that of the electrode 104a or the electrode 104b can be supplied to the electrode 106. An example in which the electrode 106 is connected to the electrode 104b is shown in FIGS. 13(A) to 13(E), FIGS. 14(A) to 14(E), FIGS. 15(A) to 15( E), FIGS. 38(A) to 38(E), FIGS. 39(A) to 39(E), FIGS. 40(A) to 4 0(E). Incidentally, for the various figures described in Embodiments 1 to 4 as well, similarly to these figures, the electrode 106 and the electrode 104a or the electrode 104b can be electrically connected, and the figures can be described similarly.

[0105] Incidentally, when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels, an opening may be formed for each pixel to electrically connect the electrode 106 to the electrode 104b, or an opening may be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 104b. Also, the electrical connection between the electrode 106 and the electrode 104b is made within the pixel matrix region. This may be performed outside the pixel matrix region. By these means, similar to the above-described case, it is possible to reduce contact resistance and wiring resistance and / or reduce the layout area. Similarly, it is possible to reduce contact resistance and wiring resistance and / or reduce the layout area. It can be done.

[0106] Also, for example, the electrode 106 can be electrically connected to the electrode 104b and the electrode 110. By connecting in this way, the same potential as that of the electrode 104b and the electrode 110 can be supplied to the electrode 106. Examples of connecting the electrode 106 to the electrode 104b and the electrode 110 are shown in FIGS. 16(A) to 16(E), FIGS. 17(A) to 17(E), FIGS. 18(A) to 18(E), FIGS. 41(A) to 41(E), FIGS. 42(A) to 42(E), and FIGS. 43(A) to 43(E). Note that the configurations shown in these figures are examples in which the electrode 110 and the electrode 106 are integrally formed from the same conductive film, and the electrode 110 and the electrode 106 are collectively referred to as the electrode 110. Note that although an example in which the electrode 110 and the electrode 106 are formed from the same conductive film is shown, the present invention is not limited to this. The electrode 110 and the electrode 106 may be formed by etching different conductive films. Also, the electrode 110 and the electrode 106 may be electrically connected by contacting each other. Note that, similarly to these figures, for the various figures described in Embodiments 1 to 4, the electrode 106 can be electrically connected to the electrode 104b and the electrode 110, and the figures can be described in the same manner. By connecting in this way, the same potential as that of the electrode 104b and the electrode 110 can be supplied to the electrode 106. The electrode 106 is connected to the electrode 104b and the electrode 110. Examples are shown in FIGS. 16(A) to 16(E), FIGS. 17(A) to 17(E), FIGS. 18(A) to 18(E), FIGS. 41(A) to 41(E), FIGS. 42(A) to 42(E), and FIGS. 43(A) to 43(E). Similarly, for the various figures described in Embodiments 1 to 4, the electrode 106 can be electrically connected to the electrode 104b and the electrode 110, and the figures can be described in the same manner. The configurations shown in these figures are examples in which the electrode 110 and the electrode 106 are integrally formed from the same conductive film, and the electrode 110 and the electrode 106 are collectively referred to as the electrode 110. Note that the configurations shown in these figures are examples in which the electrode 110 and the electrode 106 are integrally formed from the same conductive film, and the electrode 110 and the electrode 106 are collectively referred to as the electrode 110. Note that although an example in which the electrode 110 and the electrode 106 are formed from the same conductive film is shown, the present invention is not limited to this. The electrode 110 and the electrode 106 may be formed by etching different conductive films. Also, the electrode 110 and the electrode 106 may be electrically connected by contacting each other. Note that, similarly to these figures, for the various figures described in Embodiments 1 to 4, the electrode 106 can be electrically connected to the electrode 104b and the electrode 110, and the figures can be described in the same manner. Similarly, for the various figures described in Embodiments 1 to 4, the electrode 106 can be electrically connected to the electrode 104b and the electrode 110, and the figures can be described in the same manner. It is possible to connect them, and the figures can be described in the same manner.

[0107] Also, for example, the electrode 106 can be electrically connected to the electrode 101a formed using the same layer as the electrode 101. Here, the electrode 101 and the electrode 101a can be formed by etching the same conductive film using the same mask (reticle). That is, Also, for example, the electrode 106 can be electrically connected to the electrode 101a formed using the same layer as the electrode 101. Here, the electrode 101 and the electrode 101a can be formed by etching the same conductive film using the same mask (reticle). The electrode 101 and the electrode 101a can be formed by etching the same conductive film using the same mask (reticle). and are simultaneously patterned. Therefore, the electrode 101 and the electrode 101a are generally equal in terms of material , thickness, etc. An example of connecting the electrode 106 to the electrode 101a is shown in FIGS. 10(A) to FIGS. 10(E), FIGS. 11(A) to 11(E), FIGS. 12(A) to 12(E), FIGS. 35(A ) to FIGS. 35(E), FIGS. 36(A) to 36(E), FIGS. 37(A) to 37(E). Note that for the various figures described in Embodiments 1 to 4, similarly to these figures , an electrode formed using the same layer as the electrode 106 and the electrode 101 can be electrically connected, and the figures can be described similarly.

[0108] Note that when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels , an opening may be formed for each pixel to electrically connect the electrode 106 to the electrode 101a, or an opening may be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 101a. Also, the electrical connection between the electrode 106 and the electrode 101a may be made within the pixel matrix region or outside the pixel matrix region. For example, the electrode 101a can be a capacitance line arranged in the pixel matrix. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 101a can be a gate signal line arranged in another pixel, or a different gate signal line within the same pixel.

[0109] Also, for example, the electrode 106 can be electrically connected to an electrode 104c formed using the same layer as the electrode 104a or the electrode 104b. Here, the electrode 104a and the electrode 104b The electrode 104c can be formed by etching the same conductive film using the same mask (reticle). That is, they are patterned simultaneously. Therefore, the electrode 104a, the electrode 104b, and the electrode 104c are generally equal in terms of material, thickness, etc. An example in which the electrode 106 is connected to the electrode 104c is shown in FIGS. 23(A) to 23(E), FIGS. 24(A) to 24(E), FIGS. 25(A) to 25(E), FIGS. 49(A) to 49(E), FIGS. 50(A) to 50(E), and FIGS. 51(A) to 51(E). Note that in FIGS. 25(A) to 25(E) and FIGS. 51(A) to 51(E), there is a semiconductor layer 103a formed in the same layer as the semiconductor layer 103 under the electrode 104c. In addition, for the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. This can be achieved by patterning them simultaneously. Therefore, the electrode 104a, the electrode 104b, and the electrode 104c are generally equal in terms of material, thickness, etc. The electrode 104a, the electrode 104b, and the electrode 104c are generally equal in terms of material, thickness, etc. An example in which the electrode 106 is connected to the electrode 104c is shown in FIGS. 23(A) to 23(E), FIGS. 24(A) to 24(E), FIGS. 25(A) to 25(E), FIGS. 49(A) to 49(E), FIGS. 50(A) to 50(E), and FIGS. 51(A) to 51(E). Note that in FIGS. 25(A) to 25(E) and FIGS. 51(A) to 51(E), there is a semiconductor layer 103a formed in the same layer as the semiconductor layer 103 under the electrode 104c. In addition, for the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. shown in FIGS. 25(A) to 25(E), FIGS. 49(A) to 49(E), FIGS. 50(A) to 50(E), and FIGS. 51(A) to 51(E). Note that in FIGS. 25(A) to 25(E) and FIGS. 51(A) to 51(E), there is a semiconductor layer 103a formed in the same layer as the semiconductor layer 103 under the electrode 104c. In addition, for the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. In FIGS. 25(A) to 25(E) and FIGS. 51(A) to 51(E), there is a semiconductor layer 103a formed in the same layer as the semiconductor layer 103 under the electrode 104c. In addition, for the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. For the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. For the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described. For the various figures described in Embodiments 1 to 4, similarly to these figures, the electrode 106 and an electrode formed using the same layer as the electrode 104a or the electrode 104b can be electrically connected, and the figures can be similarly described.

[0110] In addition, when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel to electrically connect the electrode 106 to the electrode 104c, or an opening can be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 104c. In addition, when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel to electrically connect the electrode 106 to the electrode 104c, or an opening can be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 104c. In addition, when the transistor 100 is arranged in each pixel to form a pixel matrix composed of a plurality of pixels, an opening can be formed for each pixel to electrically connect the electrode 106 to the electrode 104c, or an opening can be formed for every plurality of pixels to electrically connect the electrode 106 to the electrode 104c. In addition, the electrical connection between the electrode 106 and the electrode 104c can be performed within the pixel matrix region or outside the pixel matrix region. For example, the electrode 104c can be a capacitance line arranged in the pixel matrix. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 104c can be a signal line, a power supply line arranged in another pixel, or another signal within the same pixel. In addition, the electrical connection between the electrode 106 and the electrode 104c can be performed within the pixel matrix region or outside the pixel matrix region. For example, the electrode 104c can be a capacitance line arranged in the pixel matrix. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 104c can be a signal line, a power supply line arranged in another pixel, or another signal within the same pixel. In addition, the electrical connection between the electrode 106 and the electrode 104c can be performed within the pixel matrix region or outside the pixel matrix region. For example, the electrode 104c can be a capacitance line arranged in the pixel matrix. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 104c can be a signal line, a power supply line arranged in another pixel, or another signal within the same pixel. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 104c can be a signal line, a power supply line arranged in another pixel, or another signal within the same pixel. The capacitance line forms a capacitance such as a holding capacitance by overlapping with other wirings, electrodes, conductive layers, etc. via an insulating layer. Or, the electrode 104c can be a signal line, a power supply line arranged in another pixel, or another signal within the same pixel. It can be a signal line or a power line.

[0111] Here, when the electrode 101a or the electrode 104c is used as a capacitance line, the following configuration is applied. This can be done.

[0112] A capacitance line is provided for each pixel row (or each pixel column) of the pixel matrix. The electrode 106 of the transistor 100 of the pixel row (or pixel column) is provided in the pixel row (or pixel column). Alternatively, each pixel row of the pixel matrix may be electrically connected to a capacitance line. (or each pixel column), and a capacitance line is provided for each pixel row (or each pixel column), and the transistor 100 The electrode 106 is provided in the pixel row (or pixel column) adjacent to the pixel row (or pixel column). The capacitance line may be electrically connected to the capacitance line.

[0113] In addition, when one pixel of the pixel matrix has multiple sub-pixels, each sub-pixel row (or A capacitance line is provided for each subpixel row (or each subpixel column), and a transistor for each subpixel row (or each subpixel column) is provided for each The electrode 106 of the capacitor 100 is connected to a capacitance line provided in the corresponding subpixel row (or the corresponding subpixel column). Alternatively, one pixel of the pixel matrix may be electrically connected to a plurality of sub-pixels. In the case where pixels are provided, a capacitance line is provided for each pixel row (or each pixel column), and a capacitance line is provided for each sub-pixel row (or The electrode 106 of the transistor 100 of each pixel row (or each subpixel column) is connected to the Alternatively, the pixel matrix may be electrically connected to a capacitance line provided in the pixel matrix. When a pixel in the array has multiple sub-pixels, each sub-pixel row (or each sub-pixel column) A capacitance line is provided, and the electrode 106 of the transistor 100 of each subpixel row (or each subpixel column) is in the subpixel row (or subpixel column) adjacent to the subpixel row (or subpixel column) It may be configured to be electrically connected to the provided capacitance line.

[0114] The plurality of capacitance lines can also be shared with each other. For example, in adjacent pixels (or sub-pixels ), the capacitance lines can be shared. As a result, the number of capacitance lines can be reduced.

[0115] In addition, when the electrode 106 of the transistor 100 is electrically connected to the capacitance line, a constant potential (preferably, the lowest potential among the potentials applied to the electrode 101, or a potential lower than that) can be applied to the capacitance line. By this, the threshold voltage of the transistor 100 can be controlled to be normally-off. Further, noise caused by capacitive coupling with the electrode 101, the electrode 104a, etc. can be prevented from entering the electrode 110.

[0116] In addition, when the electrode 106 of the transistor 100 is electrically connected to the capacitance line, a pulse signal can be supplied to the capacitance line. For example, in the case of performing common inversion driving, the potentials of the counter electrode and the capacitance line may change with the same amplitude value. Even in such a case, by supplying a low potential to the electrode 106 such that the transistor 100 is in an off state, the threshold voltage of the transistor 100 can be controlled to be normally-off.

[0117] In addition, when the electrode 106 of the transistor 100 is electrically connected to the capacitance line, it is preferable that the semiconductor layer 103 is not sandwiched between the pair of electrodes of the capacitance element formed with the capacitance line as one of the electrodes. However, one aspect of the embodiment of the present invention is not limited to this.

[0118] Note that the electrodes 101a and 104c are not limited to capacitance lines and can be other wirings. For example, they can be power supply lines, initialization wirings, etc. For example, they may be wirings provided in a pixel circuit in a display device using an EL element (organic light emitting element). Or, they may be wirings provided in a drive circuit (for example, a scanning line drive circuit or a signal line drive circuit in a display device).

[0119] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 4. Therefore, it can be implemented in free combination with other embodiments such as Embodiments 1 to 4.

[0120] (Embodiment 6) In this embodiment, an example of the electrical connection between the electrode 101 of the transistor 100 (or an electrode formed in the same layer as the electrode 101) and the electrode 104a or 104b of the transistor 100 (or an electrode formed in the same layer as the electrodes 104a and 104b) will be described. For the description, FIGS. 19, 44, and 45 will be used. In the drawings used for the description, the same parts as those in the drawings used in the previous embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0121] In FIG. 19, in the case where the insulating layer 105 is provided with the layers 105a and 105b, an example of the electrical connection between the electrode 101a formed in the same layer as the electrode 101 of the transistor 100 and the electrode 104c formed in the same layer as the electrodes 104a and 104b is shown.

[0122] In the configuration shown in Fig. 19(A), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 191 provided in the layer 105a and the layer 105 b, and the openings 192 provided in the insulating layer 102, the layer 105a, and the layer 105b. In the configuration shown in Fig. 19(B), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 193 provided in the layer 105a and the opening 194 provided in the insulating layer 102 and the layer 105a. That is, in the connection portion 109 of the electrode 104c and the electrode 101a, the layer 105b is removed.

[0123] In the configuration shown in Fig. 19(B), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 193 provided in the layer 105a and the opening 194 provided in the insulating layer 102 and the layer 105a. That is, in the connection portion 109 of the electrode 104c and the electrode 101a, the layer 105b is removed. In the configuration shown in Fig. 19(B), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 193 provided in the layer 105a and the opening 194 provided in the insulating layer 102 and the layer 105a. That is, in the connection portion 109 of the electrode 104c and the electrode 101a, the layer 105b is removed. That is, in the connection portion 109 of the electrode 104c and the electrode 101a, the layer 105b is removed. In the connection portion 109 of the electrode 104c and the electrode 101a, the layer 105b is removed.

[0124] Note that the configuration is not limited to removing the layer 105b throughout the entire connection portion of the electrode 104c and the electrode 101a. For example, as in the configurations shown in Fig. 19(C) and Fig. 19(D), the layer 105b may remain in a part of the connection portion 109 of the electrode 104c and the electrode 101a. Note that the configuration is not limited to removing the layer 105b throughout the entire connection portion of the electrode 104c and the electrode 101a. For example, as in the configurations shown in Fig. 19(C) and Fig. 19(D), the layer 105b may remain in a part of the connection portion 109 of the electrode 104c and the electrode 101a. Note that the configuration is not limited to removing the layer 105b throughout the entire connection portion of the electrode 104c and the electrode 101a. For example, as in the configurations shown in Fig. 19(C) and Fig. 19(D), the layer 105b may remain in a part of the connection portion 109 of the electrode 104c and the electrode 101a. .

[0125] In the configuration shown in Fig. 19(C), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 195 provided in the layer 105a and the opening 196 provided in the insulating layer 102, the layer 105a, and the layer 105b. In the configuration shown in Fig. 19(C), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 195 provided in the layer 105a and the opening 196 provided in the insulating layer 102, the layer 105a, and the layer 105b. In the configuration shown in Fig. 19(C), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 195 provided in the layer 105a and the opening 196 provided in the insulating layer 102, the layer 105a, and the layer 105b.

[0126] In the configuration shown in Fig. 19(D), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 197 provided in the layer 105a and the layer 105 b and the opening 198 provided in the insulating layer 102 and the layer 105a. In the configuration shown in Fig. 19(D), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 197 provided in the layer 105a and the layer 105b and the opening 198 provided in the insulating layer 102 and the layer 105a.

[0127] Next, in Fig. 44, when the layers 105b and 105c are provided as the insulating layer 105 Here, an example of the electrical connection between electrode 101a formed in the same layer as electrode 101 of transistor 100, and electrode 104c formed in the same layer as electrode 104a or electrode 104b is shown.

[0128] In the configuration shown in FIG. 44(A), electrode 104c and electrode 101a are electrically connected by electrode 110b at opening 441 provided in layer 105b and layer 105c, and opening 442 provided in insulating layer 102, layer 105b, and layer 105c.

[0129] In the configuration shown in FIG. 44(B), electrode 104c and electrode 101a are electrically connected by electrode 110b at opening 443 provided in layer 105c, and opening 444 provided in insulating layer 102 and layer 105c. That is, layer 105b is removed at connection portion 109 between electrode 104c and electrode 101a.

[0130] Note that the configuration is not limited to removing layer 105b throughout the connection portion between electrode 104c and electrode 101a. For example, as in the configurations shown in FIGS. 44(C) and 44(D), layer 105b may remain in a part of connection portion 109 between electrode 104c and electrode 101a.

[0131] In the configuration shown in FIG. 44(C), electrode 104c and electrode 101a are electrically connected by electrode 110b at opening 445 provided in layer 105c, and opening 446 provided in insulating layer 102, layer 105b, and layer 105c.

[0132] In the configuration shown in FIG. 44(D), electrode 104c and electrode 101a are electrically connected by electrode 110b at opening 447 provided in layer 105b and layer 105c, and opening 448 provided in insulating layer 102 and layer 105c. It is electrically connected by the electrode 110b.

[0133] Next, in FIG. 45, when the insulating layers 105 are provided with the layer 105a, the layer 105b, and the layer 105c, an example of the electrical connection between the electrode 101a formed in the same layer as the electrode 101 of the transistor 100 and the electrode 104c formed in the same layer as the electrode 104a or the electrode 104b is shown. is shown.

[0134] In the configuration shown in FIG. 45(A), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 451 provided in the layer 105a, the layer 105b, and the layer 105c, and at the opening 452 provided in the insulating layer 102, the layer 105a, the layer 105b, and the layer 105c. are electrically connected by the electrode 110b. are.

[0135] In the configuration shown in FIG. 45(B), the electrode 104c and the electrode 101a are electrically connected by the electrode 110b at the opening 453 provided in the layer 105a and the layer 105c, and at the opening 454 provided in the insulating layer 102, the layer 105a, and the layer 105c. That is, at the connection portion 109 between the electrode 104c and the electrode 101a, the layer 105b is removed. is removed.

[0136] Note that the configuration is not limited to removing the layer 105b throughout the connection portion between the electrode 104c and the electrode 101a. For example, as in the configurations shown in FIG. 45(C) and FIG. 45(D), the layer 105b may remain in a part of the connection portion 109 between the electrode 104c and the electrode 101a. is also good. is.

[0137] In the configuration shown in FIG. 45(C), the electrode 104c and the electrode 101a are at the opening 455 provided in the layer 105a and the layer 105c, and at the insulating layer 102, the layer 105a, the layer 105b, and the layer 105c provided In the formed opening 456, it is electrically connected by the electrode 110b.

[0138] In the configuration shown in FIG. 45(D), the electrode 104c and the electrode 101a are connected to the opening 457 provided in the layer 105a, the layer 105b, and the layer 105c, and the opening 458 provided in the insulating layer 102, the layer 105a, and the layer 105c, and are electrically connected by the electrode 110b. In the formed opening 457 provided in the layer 105a, the layer 105b, and the layer 105c, and the opening 458 provided in the insulating layer 102, the layer 105a, and the layer 105c, they are electrically connected by the electrode 110b. In the formed opening 457 provided in the layer 105a, the layer 105b, and the layer 105c, and the opening 458 provided in the insulating layer 102, the layer 105a, and the layer 105c, they are electrically connected by the electrode 110b.

[0139] The connection configuration between the electrode 104c and the electrode 101a shown in this embodiment can be applied to the connection configuration between the electrode 104b and the electrode 101 when, for example, connecting the transistor 100 in diode connection. The diode-connected transistor can be used, for example, in a protection circuit or a drive circuit. Alternatively, the connection configuration between the electrode 104c and the electrode 101a can also be applied when connecting a gate electrode to a source electrode or a drain electrode. For example, in a pixel circuit or a drive circuit configured by providing a plurality of transistors in one pixel, it is used when connecting a gate electrode to a source electrode or a drain electrode. For example, in a pixel circuit having an EL element (organic light-emitting element) in a pixel, a plurality of transistors are provided, and there may be a case of connecting a gate electrode to a source electrode or a drain electrode. Alternatively, in a circuit for driving a gate line, a plurality of transistors are provided. In the case of connecting the transistor 100 in diode connection, the connection configuration between the electrode 104b and the electrode 101. The diode-connected transistor can be used, for example, in a protection circuit or a drive circuit. Or, the connection configuration between the electrode 104c and the electrode 101a. Can also be applied when connecting a gate electrode to a source electrode or a drain electrode. For example, in a pixel circuit or a drive circuit configured by providing a plurality of transistors in one pixel. When connecting a gate electrode to a source electrode or a drain electrode. For example, in a pixel circuit having an EL element (organic light-emitting element) in a pixel. A plurality of transistors are provided, and there may be a case of connecting a gate electrode to a source electrode or a drain electrode. Or, in a circuit for driving a gate line, a plurality of transistors are provided.

[0140] Also, the shapes of the openings 191 to 198 in FIG. 19, the openings 441 to 448 in FIG. 44, and the openings 451 to 458 in FIG. 45 can be applied with the same configuration as the opening configuration shown using FIGS. 4, 5, 29, and 30 in Embodiment 4. In FIG. 45, the openings 451 to 458. Can be applied with the same configuration as the opening configuration shown using FIGS. 4, 5, 29, and 30 in Embodiment 4. ​

[0141] Note that, as a connection configuration between the electrode 104c and the electrode 101a, it is also possible to make the connection without using the electrode 110b. For example, it is also possible to provide a contact hole in the insulating layer 102 and directly connect the electrode 10 4c and the electrode 101a.

[0142] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization to a higher concept, or specialization to a lower concept of part or all of Embodiments 1 to 5. Therefore , it can be implemented in free combination with other embodiments such as Embodiments 1 to 5.

[0143] (Embodiment 7) In this embodiment, a configuration for increasing the parasitic capacitance of the transistor 100 or a configuration for increasing the capacitance value of a capacitive element electrically connected to the transistor 100 will be described by way of an example. FIGS. 20, 21, 46, and 47 will be used for the description. Note that in the drawings used for the description, the same parts as those in the drawings used for the description in the previous embodiments are denoted by the same reference numerals and the description thereof is omitted.

[0144] Note that FIGS. 20(A) to 20(D) and FIGS. 21(A) to 21(D) are examples when a laminate of the layer 105a and the layer 105b is used as the insulating layer 105 , and FIGS. 46(A), 46( C), 47(B), and 47(C) are examples when a laminate of the layer 105b and the layer 105c is used as the insulating layer 105 , and FIGS. 46(B), 46(D), 47(A), and 47(D) are examples when a laminate of the layer 105a, the layer 105b, and the layer 105c is used as the insulating layer 105 .

[0145] In FIGS. 20, 21, 46, and 47, all or most of the layer 105b on the electrode 104b is removed, and the capacitance value (or the capacitance value of the capacitive element) of the parasitic capacitance between the electrode 104b and the electrode 106 is large. In the figure, for example, a parasitic capacitance occurs in the portion 281 surrounded by the dashed line, and / or a capacitive element is formed. By appropriately determining the shapes of the electrodes 104b and 106 and the range for removing the layer 105b on the electrode 104b, etc., the value of this capacitance can be adjusted. Note that in FIGS. 20, 21, 46, and 47, a parasitic capacitance may also occur between the electrode 104b and the electrode 101, and / or a capacitive element may be formed. By appropriately determining the shapes of the electrodes 104b and 101, the value of this capacitance can be adjusted. In this way, the capacitance between the gate and the source of the transistor 100 can be increased. Or, a capacitive element with a large capacitance value can be formed. For example, when the transistor 100 is used in a circuit that performs a bootstrap operation, it is preferable to increase the capacitance between the gate and the source. Or, in a dynamic circuit, when a signal is stored in a capacitive element, it is desirable for the capacitive element to be large. Therefore, it is preferable to use the transistor 100 having the configuration shown in FIGS. 20, 21, 46, 47, etc. This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 6. Therefore, it can be implemented in free combination with other embodiments such as Embodiments 1 to 6.

[0146]

[0147]

[0148]

[0149] (Embodiment 8) In this embodiment, an example of the structure of a capacitive element included in a semiconductor device (such as a display device or a light-emitting device) will be described. FIGS. 22 and 48 will be used for the description. In the drawings used for the description, the same parts as those in the drawings used in the previous embodiments are denoted by the same reference numerals, and the description thereof will be omitted. Note that FIGS. 22(A) to 22(E) show an example in which a stack of layer 105a and layer 105b is used as the insulating layer 105, FIGS. 48(A) and 48(C) show an example in which a stack of layer 105b and layer 105c is used as the insulating layer 105, and FIGS. 48(B), 48(D), and 48(E) show an example in which a stack of layer 105a, layer 105b, and layer 105c is used as the insulating layer 105. An electrode 101a formed in the same layer as the electrode 101 is used as one electrode, and an electrode 104c formed in the same layer as the electrode 104a or the electrode 104b is used as the other electrode to form a capacitive element. This example is shown in FIGS. 22(A) and 22(B). In the figure, for example, a capacitive element is formed in a portion 282 surrounded by a broken line. Note that the electrode 106a is an electrode formed in the same layer as the electrode 106. In FIGS. 22(A) and 22(B), an example in which the electrode 106a is electrically connected to the electrode 104c is shown, but one aspect of the embodiment of the present invention is not limited thereto. The electrode 106a may not be electrically connected to the electrode 104c, may be electrically connected to the electrode 101a, may be electrically connected to both the electrode 101a and the electrode 104c, or may not be provided on the portion 282.

[0150] Note that FIGS. 22(A) to 22(E) are examples in the case where a stack of layer 105a and layer 105b is used as the insulating layer 105, FIGS. 48(A) and 48(C) are examples in the case where a stack of layer 105b and layer 105c is used as the insulating layer 105, and FIGS. 48(B), 48(D), and 48(E) are examples in the case where a stack of layer 105a, layer 105b, and layer 105c is used as the insulating layer 105.

[0151] An electrode 101a formed in the same layer as the electrode 101 is used as one electrode, and an electrode 104c formed in the same layer as the electrode 104a or the electrode 104b is used as the other electrode to form a capacitive element. This example is shown in FIGS. 22(A) and 22(B). In the figure, for example, a capacitive element is formed in a portion 282 surrounded by a broken line. Note that the electrode 106a is an electrode formed in the same layer as the electrode 106. In FIGS. 22(A) and 22(B), an example in which the electrode 106a is electrically connected to the electrode 104c is shown, but one aspect of the embodiment of the present invention is not limited thereto. The electrode 106a may not be electrically connected to the electrode 104c, may be electrically connected to the electrode 101a, may be electrically connected to both the electrode 101a and the electrode 104c, or may not be provided on the portion 282.

[0152] Using electrode 101a formed in the same layer as electrode 101 as one electrode and electrode 106a as the other electrode, a capacitive element can be formed. An example of this is shown in FIGS. 22(C), 22( D), 22(E), 48(A), 48(B), 48(C), 48(D), and 4 8(E). In the figures, for example, a capacitive element is formed in the portion 283 surrounded by a dashed line.

[0153] Note that in FIG. 22(C), the configuration in which a part of layer 105b is removed is shown in FIG. 22(D). In the configuration shown in FIG. 22(D), layer 105b in region 121c has been removed. Further , in FIG. 22(D), the configuration in which layer 105b is removed with a width wider than the width (in the left - right direction of the paper surface) where electrode 101a is provided is shown in FIG. 22(E). Also, in FIGS. 48(C) and 48(D ), FIGS. 48(A) and 48(B) show the configuration in which a part of layer 105b is removed. ) In the configuration shown in FIGS. 48(C) and 48(D), layer 105b in region 121c has been removed. Further, in FIG. 48(D), the configuration in which layer 105b is removed with a width wider than the width (in the left - right direction of the paper surface) where electrode 101a is provided is shown in FIG. 48(E).

[0154] Note that in FIGS. 22 and 48, electrode 106a may be an electrode formed in the same layer as electrode 106, electrode 110, or electrode 110 . Electrode 101a may be electrode 101. Electrode 104c may be electrode 104.

[0155] The capacitive element shown in FIGS. 22 and 48 can be used as a capacitive element provided between the gate and source of transistor 100. Alternatively, for example, it can be used as a holding capacitor provided in a pixel. Alternatively, in a driving circuit, it can be used as a capacitive element for holding a signal.​ can be used as

[0156] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 7. Therefore , it can be implemented in any combination with other embodiments such as Embodiments 1 to 7.

[0157] (Embodiment 9) In this embodiment, an example of the material of the insulating layer, electrode, semiconductor layer, etc. in the configurations shown in Embodiments 1 to 8 will be described.

[0158] The material of the semiconductor layer 103 of the transistor 100 will be described below. Note that the semiconductor layer formed in the same layer as the semiconductor layer 103 can also use the same material.

[0159] The semiconductor layer 103 of the transistor 100 may include a layer made of an oxide semiconductor (oxide semiconductor layer). Examples of the oxide semiconductor include, for example, In-Sn-Ga-Zn-O-based oxide semiconductor which is a quaternary metal oxide, In-Ga-Zn-O-based oxide semiconductor which is a ternary metal oxide, In-Sn-Zn-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, Sn-Al-Zn-O-based oxide semiconductor, Hf-In-Zn-O-based oxide semiconductor, and In-Zn-O-based oxide semiconductor which is a binary metal oxide, Sn-Zn-O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, Sn-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, and a unary metal oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, semiconductor, In-Mg-O-based oxide semiconductor, In-Ga-O-based oxide semiconductor, and a unary metal In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, In addition, the above oxide semiconductor may contain elements other than In, Ga, Sn, and Zn. It may also contain elements such as SiO2.

[0160] For example, an In-Sn-Zn-O oxide semiconductor is a semiconductor that contains indium (In), tin (Sn) It means an oxide semiconductor containing zinc (Zn), regardless of its composition ratio. For example, an In-Ga-Zn-O oxide semiconductor is a semiconductor that contains indium (In), gallium (G a) It means an oxide semiconductor containing zinc (Zn), regardless of its composition ratio. The In-Ga-Zn-O oxide semiconductor can be called IGZO.

[0161] The oxide semiconductor layer can be formed using an oxide semiconductor film. When a Zn-O-based oxide semiconductor film is formed by a sputtering method, the composition of the target is The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or For example, 20:45:35 is used.

[0162] In addition, when an In-Zn-O-based oxide semiconductor film is formed by a sputtering method, The composition ratio of the target is In:Zn=50:1 to 1:2 in atomic ratio (converted to molar ratio). and In2O3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (In terms of molar ratio, In2O3:ZnO=10:1 to 1:2), and more preferably I n:Zn = 1.5:1 to 15:1 (converted to molar ratio: In2O3:ZnO = 3:4 to For example, the target has an atomic ratio of In:Zn:O=X:Y:Z. Then, Z>1.5X+Y.

[0163] In addition, when an In-Ga-Zn-O-based oxide semiconductor film is formed by a sputtering method, In this case, the composition ratio of the target is In:Ga:Zn=1:1:0.5, In:G It can be a:Zn=1:1:1, or In:Ga:Zn=1:1:2.

[0164] In addition, by setting the purity of the target to 99.99% or more, the amount of the target that is mixed into the oxide semiconductor film can be reduced. It is possible to reduce the amount of alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. In addition, by using the target, lithium, sodium, and the like can be easily formed in the oxide semiconductor film. The concentrations of alkali metals such as thorium and potassium can be reduced.

[0165] In addition, oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem even if it is used in a cheap product that contains a large amount of alkali metals such as sodium (Na). It has been pointed out that soda-lime glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide "Physical properties of semiconductors and the current status of device development," Solid State Physics, September 2009, Vol. 44, pp.621-633.) However, this is not a proper indication. Alkali metals are oxidized. Alkaline earth metals are also impurities because they are not elements that make up oxide semiconductors. When an element is not a component of the body, it becomes an impurity. In particular, Na When the insulating film in contact with the oxide semiconductor layer is an oxide, Na diffuses into the insulating film. + In addition, Na reacts with the metals and oxygen that constitute the oxide semiconductor in the oxide semiconductor layer. This breaks the coupling or interrupts the coupling, resulting in, for example, a threshold voltage The shift in the negative direction leads to transistor characteristics such as normally on and reduced mobility. This impurity causes deterioration of the properties and also causes variation in the characteristics. The deterioration and variation in the characteristics of the transistor occur when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. Therefore, this phenomenon is remarkable when the hydrogen concentration in the oxide semiconductor layer is 1×10 18 / c m 3 Less than or equal to 1×10 17 / cm 3 If the concentration of the impurity is less than or equal to Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is , 5×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 More preferably, 1 ×10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / c m 3 Less than or equal to 1×10 15 / cm 3 Similarly, the measured value of K concentration should be less than 0. is 5 x 10 15 / cm 3 Less than or equal to 1×10 15 / cm 3 The following should be used.

[0166] Note that the oxide semiconductor layer may be amorphous or may have crystallinity. The conductor layer may be single crystal or non-single crystal. If it is non-single crystal, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. The oxide semiconductor layer may be a layer having a c-axis orientation and a triaxial structure as viewed from a direction perpendicular to the ab plane. having an atomic arrangement of a triangle, hexagon, equilateral triangle, or regular hexagon, and in a direction perpendicular to the c-axis direction when viewed from also referred to as CAAC: C Axis Aligned Crystal.) An oxide containing a crystal containing a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers can be used.

[0167] CAAC will be described in detail with reference to FIGS. 69 to 71. Unless otherwise specified in FIGS. 69 to 71, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab-plane. Note that when simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary. In FIG. 69, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms.

[0168] FIG. 69(A) shows a structure having one 6-coordinate In atom and six 4-coordinate oxygen atoms (hereinafter 4-coordinate O atoms) adjacent to the In atom The structure showing only the adjacent oxygen atoms with respect to one In atom is herein referred to as a subunit. The structure of FIG. 69(A) has an octahedral structure, but is shown as a planar structure for simplicity. Note that there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 69(A). The subunit shown in FIG. 69(A) has a charge of 0.

[0169] FIG. 69(B) shows a structure having one 5-coordinate Ga atom, three 3-coordinate oxygen atoms (hereinafter 3-coordinate O atoms) adjacent to the Ga atom and two 4-coordinate O atoms adjacent to the Ga atom. All of the 3-coordinate O atoms are present in the ab-plane. There is one 4-coordinate O atom each in the upper half and the lower half of FIG. 69(B). Also, since the In atom also has a 5-coordination ​​​​It can take the structure shown in Fig. 69(B). The subunit shown in Fig. 69(B) has a charge of 0 .

[0170] Fig. 69(C) shows a structure composed of one 4-coordinate Zn atom and four 4-coordinate O atoms adjacent to the Zn atom . There is one 4-coordinate O atom in the upper half of Fig. 69(C) and three 4-coordinate O atoms in the lower half . Alternatively, there may be three 4-coordinate O atoms in the upper half of Fig. 69(C) and one 4-coordinate O atom in the lower half. The subunit shown in Fig. 69(C) has a charge of 0 .

[0171] Fig. 69(D) shows a structure having one 6-coordinate Sn atom and six 4-coordinate O atoms adjacent to the Sn atom . There are three 4-coordinate O atoms in the upper half of Fig. 69(D) and three 4-coordinate O atoms in the lower half. The subunit shown in Fig. 69(D) has a charge of +1 .

[0172] Fig. 69(E) shows a subunit containing two Zn atoms. There is one 4-coordinate O atom in the upper half of Fig. 69(E) and one 4-coordinate O atom in the lower half. The subunit shown in Fig. 69(E) has a charge of -1 .

[0173] Here, several aggregates of subunits are called one group, and several aggregates of groups are called one unit .

[0174] Here, the rules for bonding these subunits to each other will be described. The three O atoms in the upper half of the 6-coordinate In atom shown in Fig. 69(A) each have three adjacent In atoms downward , and the three O atoms in the lower half each have three adjacent In atoms upward. Fig. 69(B ​) One of the O atoms in the upper half of the 5 - coordinated Ga atom shown in has one neighboring Ga atom downward, and one of the O atoms in the lower half has one neighboring Ga atom upward. As shown in Fig. 69(C), one of the O atoms in the upper half of the 4 - coordinated Zn atom shown in has one neighboring Zn atom downward, and the three O atoms in the lower half each have three neighboring Zn atoms upward. Thus, the number of 4 - coordinated O atoms above the metal atom and the number of neighboring metal atoms below that O atom are equal, and similarly, the number of 4 - coordinated O atoms below the metal atom and the number of neighboring metal atoms above that O atom are equal. Since the O atom is 4 - coordinated, the sum of the number of neighboring metal atoms below and the number of neighboring metal atoms above is 4. Therefore, when the sum of the number of 4 - coordinated O atoms above one metal atom and the number of 4 - coordinated O atoms below another metal atom is 4, the two types of sub - units having metal atoms can bond to each other. For example, when a 6 - coordinated metal atom (In or Sn) bonds through the 4 - coordinated O atoms in the lower half, since there are three 4 - coordinated O atoms, it will bond with either a 5 - coordinated metal atom (Ga or In) or a 4 - coordinated metal atom (Zn). These metal atoms with these coordination numbers bond through 4 - coordinated O atoms in the c - axis direction. In addition, the sub - units bond to form a group so that the total charge of the layer structure is 0. Fig. 70(A) shows a model diagram of one group constituting the layer structure of the In - Sn - Zn - O system. Fig. 70(B) shows a unit composed of three groups. Note that Fig. 70(C ) shows the atomic arrangement when observing the layer structure of Fig. 70(B) from the c - axis direction.

[0175]

[0176]

[0177] In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown. In Fig. 70(A), for simplicity, the 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are three 4 - coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the round frame. Similarly, in Fig. 70(A), there is one 4 - coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the round frame. Also, similarly, in Fig. 70(A), there is one 4 - coordinated O atom in the lower half, and a Zn atom with three 4 - coordinated O atoms in the upper half and a Zn atom with one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half are shown.

[0178] In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit. In Fig. 70(A), the groups constituting the layer structure of the In - Sn - Zn - O system are, in order from the top, Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with one 4 - coordinated O atom each in the upper and lower halves. The In atoms are bonded to Zn atoms with three 4 - coordinated O atoms in the upper half. Through the one 4 - coordinated O atom in the lower half of the Zn atom, they are bonded to In atoms with three 4 - coordinated O atoms each in the upper and lower halves. The In atoms are bonded to a subunit consisting of two Zn atoms with one 4 - coordinated O atom each in the upper half. Through the one 4 - coordinated O atom in the lower half of this subunit, they are bonded to Sn atoms with three 4 - coordinated O atoms each in the upper and lower halves. Several groups are combined to form one unit.

[0179] Here, for 3 - coordinated O atoms and 4 - coordinated O atoms, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, In (6 - coordinated or 5 - coordinated) Here, for 3 - coordinated O atoms and 4 - coordinated O atoms, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, In (6 - coordinated or 5 - coordinated) The charges of the atoms, Zn (4 - coordinated) atoms, and Sn (5 - or 6 - coordinated) atoms are +3, +2, and +4 respectively. Therefore, the subunit containing Sn atoms has a charge of +1. Thus, in order to form a layer structure containing Sn atoms, a charge of - 1 is required to cancel out the charge of +1. As a structure with a charge of - 1, as shown in Fig. 69(E), a subunit containing 2 Zn atoms can be cited. For example, if there is 1 subunit containing Sn atoms and 1 subunit containing 2 Zn atoms, the charges will be cancelled out, so the total charge of the layer structure can be made 0.

[0180] Also, assume that In atoms can take both 5 - coordination and 6 - coordination. Specifically, by using the unit shown in Fig. 70(B), a crystal of the In - Sn - Zn - O system (I n2SnZn3O8) can be obtained. Note that the obtained layer structure of the In - Sn - Zn - O system can be represented by the composition formula In2SnZn2O7(ZnO) m (m is 0 or a natural number).

[0181] In addition to this, there are also quaternary metal oxides such as In - Sn - Ga - Zn - O system oxides and ternary metal oxides such as In - Ga - Zn - O system oxides (also denoted as IGZO). )、In - Al - Zn - O system oxides、Sn - Ga - Zn - O system oxides、Al - Ga - Zn - O system oxides、Sn - Al - Zn - O system oxides、and binary metal oxides such as In - Zn - O system oxides、Sn - Zn - O system oxides、Al - Zn - O system oxides、Zn - Mg - O system acid oxides、Sn - Mg - O system oxides、In - Mg - O system oxides、and In - Ga - O system oxides、 unary metal oxides such as In - O system oxides、Sn - O system oxides、Zn - O system oxides, etc.​​​ The same applies when using

[0182] For example, Fig. 71(A) shows a model diagram of one group constituting the layer structure of the In-Ga-Zn-O system.

[0183] In Fig. 71(A), the group constituting the layer structure of the In-Ga-Zn-O system has, from the top, In atoms with three 4-coordinate O atoms each in the upper and lower halves, bonded to a Zn atom with one 4-coordinate O atom in the upper half, and the three 4-coordinate O atoms in the lower half of the Zn atom bonded to Ga atoms with one 4-coordinate O atom each in the upper and lower halves through the three 4-coordinate O atoms in the lower half of the Zn atom, and the In atoms with three 4-coordinate O atoms each in the upper and lower halves are bonded through one 4-coordinate O atom in the lower half of the Ga atom. Some of the groups are combined to form one unit.

[0184] Fig. 71(B) shows a unit composed of three groups. Note that Fig. 71(C) shows the atomic arrangement when observing the layer structure of Fig. 71(B) from the c-axis direction.

[0185] Here, since the charges of In (6-coordinate or 5-coordinate) atoms, Zn (4-coordinate) atoms, and Ga (5-coordinate) atoms are +3, +2, and +3 respectively, the subunit composed of In atoms, Zn atoms, and Ga atoms has a charge of 0. Therefore, for these combinations, the total charge of the layer structure is always 0.

[0186] Here, since the charges of In (6-coordinate or 5-coordinate) atoms, Zn (4-coordinate) atoms, and Ga (5-coordinate) atoms are +3, +2, and +3 respectively, the charges of In atoms, Zn atoms, and Ga atoms Subunits containing either of these have a zero charge. When combined, the total charge of the group is always zero.

[0187] An oxide semiconductor film containing CAAC (hereinafter also referred to as a CAAC film) can be formed by a sputtering method. The target can be made of the above-mentioned materials. When forming a CAAC film by sputtering, the oxygen gas ratio in the atmosphere is For example, when a sputtering method is performed in a mixed gas atmosphere of argon and oxygen, When performing this, the oxygen gas ratio is preferably 30% or more, and more preferably 40% or more. This is more preferable because the crystallization of CAAC is promoted by the supplementation of oxygen from the atmosphere. It is.

[0188] In addition, when the CAAC film is formed by the sputtering method, It is preferable to heat the substrate to be treated to 150° C. or higher, and it is preferable to heat the substrate to 170° C. or higher. This is because the crystallization of CAAC is promoted with an increase in the substrate temperature. .

[0189] In addition, after the CAAC film is heat-treated in a nitrogen atmosphere or in a vacuum, It is preferable to carry out the heat treatment in an oxygen atmosphere or in a mixed atmosphere of oxygen and other gases. The oxygen deficiency caused by the previous heat treatment is restored by the supply of oxygen from the atmosphere in the subsequent heat treatment. This is because it can be restored.

[0190] In addition, it is preferable that the film surface (film-forming surface) on which the CAAC film is formed is flat. Since the AC film has a c-axis that is approximately perpendicular to the surface on which the film is formed, the concave portions on the surface on which the film is formed are This is because the convexity induces the generation of crystal grain boundaries in the CAAC film. Therefore, C Before the CAAC film is formed, it is preferable to perform a planarization treatment such as Chemical M echanical Polishing (CMP) on the surface to be coated. Further, the average roughness of the surface to be coated is preferably 0.5 nm or less, and more preferably 0 .3 nm or less.

[0191] In addition, the oxide semiconductor film formed by sputtering or the like may contain moisture or hydrogen (including hydroxyl groups) as impurities. In one aspect of the present invention, moisture or hydrogen in the oxide semiconductor film (or the oxide semiconductor layer formed by the oxide semiconductor film) and other impurities are reduced (dehydrated or dehydrogenated) by performing a heat treatment on the oxide semiconductor film (oxide semiconductor layer) in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air (when measured using a dew point meter of the CRDS (cavity ringdown laser spectroscopy) method, the moisture content is 20 ppm (dew point equivalent to -55 °C) or less, preferably 1 ppm or less, preferably 10 ppb or less of air) atmosphere. The heat treatment is performed on the oxide semiconductor film (oxide semiconductor layer).

[0192] By performing a heat treatment on the oxide semiconductor film (oxide semiconductor layer), moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) can be desorbed. Specifically, the heat treatment may be performed at a temperature of 250 °C or higher and 75 0 °C or lower, preferably 400 °C or higher and lower than the strain point of the substrate. For example , it may be performed at 500 °C for 3 minutes or more and 6 minutes or less. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the strain point of the glass substrate.

[0193] After thus desorbing moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer), oxygen is added. Thus, oxygen vacancies in the oxide semiconductor film (oxide semiconductor layer) are reduced , and the oxide semiconductor film (oxide semiconductor layer) can be made into an i-type or brought as close as possible to the i-type. .

[0194] The addition of oxygen can be performed, for example, by forming an insulating film having a region with an oxygen content higher than the stoichiometric composition ratio in contact with the oxide semiconductor film (oxide semiconductor layer) and then heating it. In this way, excess oxygen in the insulating film can be supplied to the oxide semiconductor film (oxide semiconductor layer). In this way, the oxide semiconductor film (oxide semiconductor layer) can be brought into a state of containing excess oxygen. The excess oxygen is present, for example, between the lattices of the crystals constituting the oxide semiconductor film (oxide semiconductor layer).

[0195] Note that the insulating film having a region with an oxygen content higher than the stoichiometric composition ratio may be either the upper insulating film or the lower insulating film among the insulating films in contact with the oxide semiconductor film (oxide semiconductor layer), but it is preferable to use both. By using the insulating film having a region with an oxygen content higher than the stoichiometric composition ratio for the upper and lower insulating films in contact with the oxide semiconductor film (oxide semiconductor layer) and sandwiching the oxide semiconductor film (oxide semiconductor layer), the above effects can be enhanced more.

[0196] Here, the insulating film having a region with an oxygen content higher than the stoichiometric composition ratio may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. Note that the insulating film is water It is desirable to minimize the amount of impurities such as hydrogen and other chemicals contained in the insulating film. The hydrogen penetrates into the oxide semiconductor film (oxide semiconductor layer) or This removes oxygen from the oxide semiconductor layer, causing the oxide semiconductor film to have a low resistance (become n-type). Therefore, the insulating film should be one that contains as little hydrogen as possible. It is important not to use hydrogen in the film formation process so that the insulating film is not damaged. For example, a silicon nitride film or a silicon nitride film is used as an insulating film having a high barrier property. Silicon nitride oxide film, aluminum nitride film, aluminum oxide film, or aluminum nitride oxide film When a plurality of laminated insulating films are used, the nitrogen content ratio is The insulating film such as a silicon oxide film or a silicon oxynitride film having a low barrier property is preferably used as the insulating film having a high barrier property. The insulating layer is formed on the side close to the oxide semiconductor film (the nitride semiconductor layer). The insulating film is sandwiched between the oxide semiconductor film (oxide semiconductor layer) and the insulating film with high barrier properties. By using an insulating film with high barrier properties, the oxide semiconductor film (oxide semiconductor Prevents impurities such as moisture or hydrogen from entering the insulating film (interlayer) and the interface with other insulating films and their vicinity. In addition, the ratio of nitrogen to the oxide semiconductor film (oxide semiconductor layer) can be adjusted so that the oxide semiconductor film (oxide semiconductor layer) is in contact with the oxide semiconductor film. By forming insulating films such as low-temperature silicon oxide films and silicon oxynitride films, materials with high barrier properties can be used. This can prevent the insulating film used from being in direct contact with the oxide semiconductor film (oxide semiconductor layer).

[0197] In addition, oxygen is added after moisture or hydrogen is removed from the oxide semiconductor film (oxide semiconductor layer). The oxide semiconductor film (oxide semiconductor layer) is subjected to heat treatment in an oxygen atmosphere. It may be achieved. The temperature of the heat treatment is, for example, 100°C or higher and less than 350°C, preferably 15 0°C or higher and less than 250°C. It is preferable that the oxygen gas used for the heat treatment in the oxygen atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, ( that is, the impurity concentration in oxygen is 1 ppm or less, preferably 0.1 ppm or less), which is preferable. That is, the impurity concentration in oxygen is 1 ppm or less, preferably 0.1 ppm or less), which is preferable. That is preferable.

[0198] Alternatively, oxygen addition after desorbing moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) may be performed using an ion implantation method, an ion doping method, or the like. For example, oxygen plasma generated by microwaves of 2.45 GHz may be added to the oxide semiconductor film (oxide semiconductor layer). GHz may be added to the oxide semiconductor film (oxide semiconductor layer). That's all right.

[0199] The oxide semiconductor layer formed in this way can be used as the semiconductor layer 103 of the transistor 100. In this way, a transistor 100 with a significantly reduced off-current can be obtained. In this way, a transistor 100 with a significantly reduced off-current can be obtained.

[0200] The semiconductor layer 103 of the transistor 100 may contain microcrystalline silicon. Microcrystalline silicon is a semiconductor with an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystalline). Microcrystalline silicon has a crystal grain size of 2 nm or more and 200 nm or less, preferably 10 nm or more 80 nm or less, more preferably 20 nm or more and 50 nm or less, and even more preferably 25 nm or more 33 nm or less, and columnar crystals or acicular crystals are growing in the normal direction to the substrate surface. Therefore, grain boundaries may be formed at the interfaces of the columnar crystals or acicular crystals.

[0201] As a representative example, the Raman spectrum of microcrystalline silicon is shifted to a lower wavenumber side than 52 0 cm -1 which indicates that of single-crystalline silicon. That is, between 520 cm -1 indicating single-crystalline silicon and 480 cm -1 indicating amorphous silicon, there is a peak in the Raman spectrum of microcrystalline silicon. Also, it contains at least 1 atomic % or more of hydrogen or halogen in order to terminate dangling bonds. Furthermore, by including noble gas elements such as helium, argon , krypton, or neon to further promote lattice strain, more stable and better microcrystalline silicon can be obtained. A description of such microcrystalline silicon is disclosed, for example, in U.S. Patent No. 4,409,134.

[0202] The semiconductor layer 103 of the transistor 100 may contain amorphous silicon. The semiconductor layer 103 of the transistor 100 may contain polycrystalline silicon. Or, the semiconductor layer 103 of the transistor 100 may contain an organic semiconductor, carbon nanotubes and the like.

[0203] The material of the electrode 110 will be described below. Electrodes formed in the same layer as the electrode 110 can also use the same material.

[0204] The electrode 110 can be formed using a light-transmissive conductive material. Examples of light-transmissive conductive materials include indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO ), organoindium, organotin, zinc oxide, indium zinc oxide, and the like. Note that the electrode 110 includes both a light-transmissive region and a reflective region. ) and can be used. ​This is also acceptable. By doing so, a transflective display device can be configured. Also, the electrode 110 may be formed using a conductive material having reflectivity. By doing so, a reflective display device can be configured. Alternatively, a light-emitting device with a configuration that emits light on the side opposite to the substrate on which the pixels are formed (top emission) can be configured.

[0205] In particular, when using a conductive material having reflectivity as the electrode 110, by providing the electrode 110 above the transistor 100 so as to overlap with the transistor 10 0, the aperture ratio can be improved.

[0206] The material of the electrode 106 will be described below. Note that electrodes formed in the same layer as the electrode 106 can also use the same material.

[0207] The electrode 106 can be formed using a translucent conductive material. Examples of the translucent conductive material include indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO ), organoindium, organotin, zinc oxide, indium zinc oxide, and the like can be used.

[0208] The material of the insulating layer 105 will be described below.

[0209] The insulating layer 105 may include an organic insulating layer. The insulating layer 105 may include an inorganic insulating layer. The insulating layer 105 may include a laminate of an inorganic insulating layer and an organic insulating layer. For example , the layers 105a and 105c can be inorganic insulating layers. The layer 105b can be an organic insulating layer.

[0210] When the insulating layer 105 or the layer 105b is used as a color filter, the insulating layer 105 or As the layer 105b, a green organic insulating layer, a blue organic insulating layer, a red organic insulating layer, etc. are used. When the insulating layer 105 or the layer 105b is used as a black matrix, A black organic insulating layer can be used as the insulating layer 105 or the layer 105b.

[0211] The organic insulating layer may be made of acrylic resin, polyimide, polyamide, or the like. By using polyimide, the light-emitting element formed on the insulating layer 105 or layer 105b can be It is also possible to reduce the deterioration of the organic insulating layer by using a photosensitive material. In the case of a film using a photosensitive material, the film can be etched without forming a resist mask. The organic insulating layer can be formed by a droplet discharge method such as an ink jet method. Alternatively, the ink jet method or other droplet ejection method may be used. The layer may be etched after it is formed. For example, the layer may be formed by a liquid method such as an ink-jet method. A layer formed by a droplet discharge method is etched using a resist mask. Good too.

[0212] As the inorganic insulating layer, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used. do.

[0213] In this embodiment, some or all of the first to eighth embodiments are modified or added. It corresponds to addition, modification, deletion, application, superordinate conception, or subordinate conception. The present invention may be freely combined with other embodiments such as the first to eighth embodiments. This can be done.

[0214] (Embodiment 10) In this embodiment, one aspect of a method for manufacturing a semiconductor device is shown.

[0215] An example of a method for manufacturing a semiconductor device having the configuration shown in FIG. 1(A) is shown in FIG. 59.

[0216] An electrode 101 is formed on the insulating surface 200, and an insulating layer 102 is formed on the electrode 101. On the insulating layer 102, a semiconductor layer 103 is formed such that at least a part of the semiconductor layer 103 overlaps at least a part of the electrode 101 through the insulating layer 102 (FIG. 59(A)).

[0217] Electrodes 104a and 104b are formed on the semiconductor layer 103. An insulating film 591 is formed on the electrodes 104a and 104b. It is assumed that the insulating film 591 is formed of a positive photosensitive material (FIG. 59(B)).

[0218] Next, the insulating film 591 is exposed by using a halftone mask 592. Here, the halftone mask 592 has regions 592a, 592b, and 592c, and the transmittance of light used for exposure is different for each region. Here, (transmittance of region 592c) > (transmittance of region 592b) > (transmittance of region 592a) (FIG. 59(C)).

[0219] By exposing the insulating film 591 using such a halftone mask 592, an insulating layer 105 having regions 121 and 122 can be formed, where region 121 is thinner than region 122 and has a penetrating opening 123 (FIG. 59(D)).

[0220] Thereafter, on the insulating layer 105, an electrode 106 that overlaps at least a part of the semiconductor layer 103 through region 121, and on at least a part of region 122, an electrode 110 ​​​​​​​​forming at least a part of it (FIG. 59(E)).

[0221] In this way, a semiconductor device can be formed.

[0222] In the above description, an example in which a positive photosensitive material is used as the insulating film 591 is shown, but this is not limited thereto. A negative photosensitive material may be used. Also, without using a photosensitive material as the insulating film 591, a resist is formed on the insulating film 591, and the resist is exposed using a half-tone mask to form a resist mask, and the insulating layer 105 may be formed by etching the insulating film 591 using the resist mask.

[0223] An example of a method for manufacturing a semiconductor device having the configuration shown in FIG. 1(C) is shown in FIG. 60.

[0224] An electrode 101 is formed on an insulating surface 200, and an insulating layer 102, a semiconductor layer 103, electrodes 10 4a and an electrode 104b are formed. The manufacturing steps up to this point are the same as those in FIG. 59. On the electrodes 10 4a and the electrode 104b, an insulating film 601a is formed, and an insulating film 601 b is formed on the insulating film 601a (FIG. 60(A)).

[0225] Next, a resist 602 is formed on the insulating film 601b. The resist 602 is a positive type. The resist 602 is exposed by using a half-tone mask 603. Here the half-tone mask 603 has regions 603a, 603b, and 603c, and the light transmittance used for exposure is different for each of them. Here, (transmittance of region 603c) > (transmittance of region 6 03b) > (transmittance of region 603a) (FIG. 60(B)).

[0226] ​By exposing the resist 602 using such a half-tone mask 603, Thus, a resist mask 604 having three regions with different thicknesses is formed (FIG. 60( C).

[0227] The insulating film 601a and the insulating film 601b are etched using the resist mask 604. By this, it has a region 121 and a region 122, and the region 121 is thinner than the region 122, In addition, an insulating layer (a laminate of layers 105a and 105b) having an opening 123 penetrating therethrough is formed. This can be done (Figure 60(D)).

[0228] Then, a thin film is formed on the layer 105b, which is connected to at least a part of the semiconductor layer 103 through the region 121. At least a portion of the electrode 110 is disposed on at least a portion of the region 122 and at least a portion of the electrode 106 overlapping the region 122. At least a part of the slit is formed (Figure 60(E)).

[0229] In this manner, a semiconductor device can be formed.

[0230] In the manufacturing process shown in FIG. 60, a positive type resist 602 is used. However, the present invention is not limited to this. A negative photosensitive material may be used. First, the insulating film 601b is formed using a photosensitive material, and the insulating film 601b is subjected to half-tone masking. By exposing the layer to light, an insulating layer (a laminate of layers 105a and 105b) is formed. Good too.

[0231] In addition, in the manufacturing process shown in FIG. 60, an example using a half-tone mask is shown, but this is not limited to this. For example, a manufacturing process as shown in FIG.

[0232] The manufacturing process up to FIG. 61(A) is the same as that of FIG.

[0233] In the manufacturing process shown in FIG. 61, the insulating film 601b is etched to form the region 121 and the opening 1 24. Thus, the layer 105b is formed (FIG. 61(B)).

[0234] Thereafter, the insulating film 601a exposed at the opening 124 is etched to form the penetrating opening 123. At this time, a part of the layer 105b may be further etched. Thus, an insulating layer having the region 121 and the region 122, where the region 121 is thinner than the region 122 and has a penetrating opening 123 (a laminate of the layers 105a and 105b) can be formed (FIG. 61(C)). FIG. 61(D)).

[0235] Thereafter, on the layer 105b, an electrode 106 that overlaps at least a part of the semiconductor layer 103 through the region 121, and at least a part of the electrode 110 is formed on at least a part of the region 122 (

[0236] Thus, a semiconductor device can be formed.

[0237] Note that, in the manufacturing process shown in FIG. 61, a configuration in which the insulating film 601a and the insulating film 601b are laminated and then the etching process of these films is performed is shown, but the present invention is not limited to this. For example, a manufacturing process as shown in FIG. 62 can be employed.

[0238] Up to the formation of the insulating film 601a (FIG. 62(A)), the manufacturing process is the same as that shown in FIG. 61 .

[0239] After forming the insulating film 601a, the insulating film 601a is etched to form the layer 105a having the opening 125 (FIG. 62(B)).

[0240] ​​​​Thereafter, an insulating film 601b is formed to cover the layer 105a (FIG. 62(C)).

[0241] Next, the insulating film 601b is etched. At this time, a part of the layer 105a is further etched. Thus, if we have region 121 and region 122, and region 121 is region 12 2 and has an opening 123 therethrough (a stack of layers 105a and 105b). ) can be formed (Figure 62(D)).

[0242] Then, a thin film is formed on the layer 105b, which is connected to at least a part of the semiconductor layer 103 through the region 121. At least a portion of the electrode 110 is disposed on at least a portion of the region 122 and at least a portion of the electrode 106 overlapping the region 122. At least a part of the porosity (Figure 62(E)).

[0243] In this manner, a semiconductor device can be formed.

[0244] In the manufacturing process shown in FIGS. 60, 61, and 62, the insulating layer 105 is formed into two films (insulating A manufacturing process in which only one of the films is selectively formed. In this example, the regions 121 and 122 are formed by removing the However, the present invention is not limited to the above, and may be applied to a manufacturing process in which the insulating layer 105 is formed from m (m is a natural number) films, By selectively removing only n films (n is a natural number smaller than m) out of m films, In this way, the regions 121 and 122 may be formed.

[0245] For example, a manufacturing process for forming the insulating layer 105 from three films is shown in FIG. The process corresponds to a manufacturing process of a semiconductor device having the structure shown in FIG.

[0246] The manufacturing process up to the step shown in FIG. 63(A) is the same as that shown in FIG.

[0247] After the insulating film 601b is formed, the insulating film 601b is etched to form the openings 126 and A layer 105b having an opening 127 is formed (Figure 63(B)).

[0248] Thereafter, an insulating film 601c is formed to cover the layer 105b (FIG. 63(C)).

[0249] Next, the insulating film 601a and the insulating film 601c are etched to form a through hole. Thus, an opening 123 is formed through the region 121 and the region 122. An insulating layer (layer 105a and layer 105b) is formed on the insulating layer 105a and has an opening 123 therethrough, the opening 123 being thinner than the region 122. A layer 105c and a layer 105b can be formed (FIG. 63(D)).

[0250] Then, a thin film is formed on the layer 105c, which is connected to at least a part of the semiconductor layer 103 through the region 121. At least a portion of the electrode 110 is disposed on at least a portion of the region 122 and at least a portion of the electrode 106 overlapping the region 122. At least a part of it (Figure 63(E)).

[0251] In this manner, a semiconductor device can be formed.

[0252] In addition, the manufacturing process for forming the insulating layer 105 from three films is the same as the process shown in FIG. An example of a different process is shown in FIG. 64. The process shown in FIG. 64 is performed in the configuration shown in FIG. This corresponds to the manufacturing process of a semiconductor device in which the end of the layer 105a is covered with the layer 105b. .

[0253] First, the insulating film is etched to form a layer 105a having an opening 128a. After this, an insulating film 601b is formed (FIG. 64(A)).

[0254] Etch the insulating film 601b to form layer 105b having openings 127 and 128 (Fig. 64(B)). Here, opening 128 is formed at opening 128a and has a diameter smaller than that of opening 128a.

[0255] Subsequently, form an insulating film 601c to cover layer 105b (Fig. 64(C)).

[0256] Next, by etching the insulating film 601c, form a penetrating opening 123. In this way, an insulating layer (a laminate of layer 105a, layer 105b, and layer 105c) having regions 121 and 122, where region 121 is thinner than region 122 and has a penetrating opening 123, can be formed (Fig. 64(D)).

[0257] Thereafter, on layer 105c, form an electrode 106 such that at least a part of the semiconductor layer 103 overlaps through region 121, and on at least a part of region 122, form at least a part of electrode 110 (Fig. 64(E)).

[0258] In this way, a semiconductor device can be formed.

[0259] Note that in Figs. 59 to 64, a method for manufacturing a semiconductor device having a configuration shown in a figure obtained by deforming a part of Figs. 1(A), 1(C), and 26(C) is shown. However, a semiconductor device having other configurations shown in the above embodiments can be manufactured in the same manner.

[0260] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 9. Therefore, it can be implemented in any combination with other embodiments such as Embodiments 1 to 9.​​​​​​​​ It can be formed into a shape with a protrusion.

[0261] (Embodiment 11) In this embodiment, an example of applying the semiconductor device shown in Embodiments 1 to 10 to a display device will be described. will be described.

[0262] The semiconductor devices shown in Embodiments 1 to 10 can be used for pixels of a liquid crystal display device or the like. It can be used.

[0263] An example of a cross-sectional view of a pixel of a liquid crystal display device is shown in FIG. 52. FIGS. 52(A) and 52(B) are cross-sectional views of a pixel when the semiconductor device having the configuration shown in FIG. 1(C) is used in a liquid crystal display device. In FIG. 52, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 52, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted.

[0264] In FIG. 52, the transistor 100 can be a transistor provided in a pixel. The electrode 110 can be a pixel electrode. The layer 105b can be a color filter and / or a black matrix. or a black matrix.

[0265] In FIG. 52(A), a protrusion 510 is provided on the region 122. The protrusion 510 can function as a spacer. Therefore, the protrusion 510 can control the distance between the substrate on which the transistor 100 is formed (hereinafter referred to as a pixel substrate) and the substrate for sealing the liquid crystal layer (hereinafter referred to as a counter substrate). Note that a black matrix may be formed by the protrusion 510. Alternatively, the protrusion 510 can function as a rib for controlling the alignment of liquid crystal molecules. By the protrusion 510, the direction in which the liquid crystal molecules fall can be controlled. It can function as a spacer. Therefore, the protrusion 510 can control the distance between the substrate on which the transistor 100 is formed (hereinafter referred to as a pixel substrate) and the substrate for sealing the liquid crystal layer (hereinafter referred to as a counter substrate). Note that a black matrix may be formed by the protrusion 510. Alternatively, the protrusion 510 can function as a rib for controlling the alignment of liquid crystal molecules. By the protrusion 510, the direction in which the liquid crystal molecules fall can be controlled. the substrate on which the transistor 100 is formed (hereinafter referred to as a pixel substrate) and the substrate for sealing the liquid crystal layer (hereinafter referred to as a counter substrate). (hereinafter referred to as a counter substrate). The distance therebetween can be controlled. Note that a black matrix may be formed by the protrusion 510. Alternatively, the protrusion 510 can function as a rib for controlling the alignment of liquid crystal molecules. By the protrusion 510, the direction in which the liquid crystal molecules fall can be controlled. Note that a black matrix may be formed by the protrusion 510. Alternatively, the protrusion 510 can function as a rib for controlling the alignment of liquid crystal molecules. By the protrusion 510, the direction in which the liquid crystal molecules fall can be controlled. can function as a rib for controlling the alignment of liquid crystal molecules. By the protrusion 510, the direction in which the liquid crystal molecules fall can be controlled. The direction in which the liquid crystal molecules fall can be controlled.

[0266] In FIG. 52, a liquid crystal layer, an electrode paired with a pixel electrode (hereinafter referred to as a counter electrode), The counter substrate is not shown. The counter electrode may be provided on the pixel substrate or on the counter substrate. Also, although the alignment film is not shown, an alignment film may or may not be provided.

[0267] In the configuration shown in FIG. 52(A), as shown in FIG. 52(B), layers 510a and 510b are provided so as to fill a region where the insulating layer 105 is thin or non-existent (for example, a region where layer 105b is removed). Thus, unevenness on the portion of the pixel substrate facing the liquid crystal layer can be alleviated. Layers 510a and 510b may be formed using a material different from that of the protrusions 510, or may be formed using the same material. The black matrix may be formed by any one or all of layers 510a, 510b, and the protrusions 510. In FIG. 52(B), a configuration in which one of layers 510a and 510b is not provided may also be adopted. For example, a configuration in which only layer 510a is provided may be adopted.

[0268] In FIG. 52, the protrusions 510, layers 510a, and 510b can be formed by processing the insulating layer through a photolithography process. Alternatively, they can be formed using a photosensitive material. They may also be formed by a droplet ejection method such as inkjet. In FIG. 52, an example of providing the protrusions 510 on the pixel substrate is shown, but the present invention is not limited thereto. Protrusions may be provided on the counter substrate.

[0269] In FIG. 52, the protrusions 510 are shown in a configuration where they overlap the electrode 110, but the present invention is not limited thereto. The protrusions 510 can also be provided so as not to overlap the electrode 110.​​​​​ Yes. In addition, the protrusion 510 can be provided so as to overlap a part of the electrode 110 and not overlap another part. Moreover, the protrusion 510 may be provided for each pixel, or may be provided for every plurality of pixels. The protrusion 510 may be provided so as to overlap a part of the pixel wiring, or may be provided so as to overlap a part of the black matrix.

[0270] In FIG. 52, a configuration in which the semiconductor device shown in FIG. 1(C) is applied to a liquid crystal display device is shown, but it is not limited thereto. The semiconductor devices shown in Embodiments 1 to 10 can be applied to a liquid crystal display device. For example, when the semiconductor devices shown in Embodiments 1 to 10 are applied to a liquid crystal display device, similar to FIG. 52, any one of the protrusion 510, the layer 510a, and the layer 510b can be provided.

[0271] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 10. Therefore, it can be implemented in free combination with other embodiments such as Embodiments 1 to 10.

[0272] (Embodiment 12) In this embodiment, an example in which the semiconductor device shown in Embodiments 1 to 10 is applied to a display device will be described.

[0273] As an example, the semiconductor devices shown in Embodiments 1 to 10 can be used for pixels such as a liquid crystal display device

[0274] FIGS. 55(A) to 55(F) show an example of a circuit diagram of one pixel of a pixel portion of a liquid crystal display device. . The pixel has a transistor, a capacitive element, and a liquid crystal element. Further, it also has a gate signal line 5 51, a source signal line 552, a capacitive line 553, etc. The source signal line 552 can also be referred to as a video signal line. In the pixel having the configuration shown in FIGS. 55(A) to 55(F), there is a sub-pixel in one pixel. As the transistor, the transistor 100 shown in Embodiments 1 to 10 can be used. FIG. 55(G) is a transistor symbol used in FIGS. 55( A) to 55(F). In FIG. 55(G), the correspondence between the transistor symbol and the configuration of the transistor 100 shown in Embodiments 1 to 10 is shown. FIG. 55(H) shows only the liquid crystal element shown in FIGS. 55(A) to 55(F). As shown in FIG. 55(H), the liquid crystal element has an electrode 110 (corresponding to a pixel electrode) and an electrode 550 (corresponding to a counter electrode). Further, there is a liquid crystal layer between the electrode 110 and the electrode 550.

[0275] (corresponding to a counter electrode). Further, there is a liquid crystal layer between the electrode 110 and the electrode 550.

[0276] As the capacitive element shown in FIGS. 55(A) to 55(F), the parasitic capacitance and the capacitive element shown in Embodiment 7 or Embodiment 8 can be used.

[0277] The semiconductor devices shown in Embodiments 1 to 10 can also be used for the pixels of a display device (hereinafter referred to as an EL display device) or a light-emitting device using an EL element (organic light-emitting element). FIGS. 56(A) to 56(C) show an example of a circuit diagram of a pixel of an EL display device. The pixel shown in FIGS. 56(A ) to 56(C) has an EL element 560, a transistor 562, a transistor

[0278] 562, a transistor ) to 56(C) has an EL element 560, a transistor 562, a transistor ​​​It has a transistor 563 and a capacitor element 564. Furthermore, it also has a gate signal line 551, a source signal line 5 52, a capacitor line 553, a current supply line 561, etc. The source signal line 552 is also called a video signal line. The transistor 562 has a function of controlling whether or not to supply a video signal to the gate of the transistor 563 The transistor 563 has a function of controlling the current supplied to the EL element 560 As such a transistor, the transistor 100 shown in Embodiments 1 to 10 can be used The correspondence between the transistor symbol and the configuration of the transistor 100 shown in Embodiments 1 to 10 is as shown in FIG. 55(G) as follows

[0279] Also, the semiconductor devices shown in Embodiments 1 to 10 can be used in drive circuits such as liquid crystal display devices and EL display devices. As the drive circuit, for example, it can be used in a scanning line drive circuit or a signal line drive circuit that outputs signals to pixels FIGS. 57(A) and 5 7(B) show an example of a part of the drive circuit. The transistors (transistors 701, transistor 702, transistor 703, transistor 704, transistor 705, transistor 706, transistor 707, transistor 708, transistor 709, transistor 710, transistor 711, transistor 712, transistor 713, transistor 715, transistor 801, transistor 802, transistor 803, transistor 804, transistor 805, transistor 806, transistor 807, transistor 808, transistor 809, transistor 810, transistor 811, transistor 812, transistor 813, transistor 814, transistor For some or all of the Ta815, transistor 816, and transistor 817, the transistor 100 shown in Embodiments 1 to 10 can be used.

[0280] Also, as the capacitive element 714 in FIG. 57(A), parasitic capacitances or capacitive elements shown in Embodiment 7 or Embodiment 8 can be used.

[0281] This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of some or all of Embodiments 1 to 11. Therefore, it can be implemented in free combination with other embodiments such as Embodiments 1 to 11.

[0282] (Embodiment 13) In this embodiment, an example in which the semiconductor device shown in Embodiments 1 to 10 is applied to a display device such as a liquid crystal display device will be described.

[0283] One aspect of the configuration of the pixels of the liquid crystal display device is shown in FIGS. 53, 58(A), and 58(B). Also, the cross-sectional views of A1 to A2 in the top view of FIG. 53 are shown in FIG. 58(A) or FIG. 58(B).

[0284] In FIGS. 53, 58(A), and 58(B), the pixel 530 includes a transistor 100, a capacitive element 531, and a liquid crystal element (or display element). Note that the pixel 530 may be a sub-pixel. In FIGS. 53 and 58, only the electrode 110 corresponding to the pixel electrode of the liquid crystal element (or display element) is shown, and the counter electrode (common electrode) is not shown.

[0285] The configuration of the transistor 100 can adopt various configurations shown in Embodiments 1 to 10. Therefore, since the configuration of the transistor 100 is the same as the configuration shown in Embodiments 1 to 10, the same parts are denoted by the same reference numerals and the description thereof is omitted. Note that FIG. 58(A) is an example in which the transistor 100 having the configuration shown in FIG. 1(A) is applied, and FIG. 58(B) is an example in which the transistor 100 having the configuration shown in FIG. 1(C) is applied.

[0286] The capacitive element 531 can use parasitic capacitances and capacitive elements shown in Embodiments 7 and 8. Note that in FIG. 58(A), an example of forming the capacitive element 531 in the region 121c where the insulating layer 105 is made thin is shown. In FIG. 58(B), an example of forming the capacitive element 531 in the region 121c where the layer 105b is removed is shown. The configuration of the capacitive element 531 shown in FIG. 58(B) corresponds to the configuration of the capacitive element shown in FIG. 22(D).

[0287] The electrode 106 of the transistor 100 is electrically connected to the electrode 101a at the opening 501a. The electrode 101 of the transistor 100 serves as a gate electrode of the transistor and also functions as a gate wiring. An electrode 101a is provided in parallel with the electrode 101. The electrode 101a functions as a wiring for applying a potential to the electrode 106 of the transistor 100 and also functions as a capacitance line for pixels (or sub-pixels) in adjacent rows. The electrode 104a of the transistor 100 serves as one of a source electrode or a drain electrode and also functions as a source wiring. The source wiring is provided so as to cross the gate wiring. The electrode 104b of the transistor 100 serves as the other of the source electrode or the drain electrode and the opening 50 ​ In 1b, it is electrically connected to the electrode 110. One of the pair of electrodes of the capacitive element 531 is the electrode 110, and the other is the electrode 101a.

[0288] Note that the electrode 101a can be formed of the same material in the same layer as the electrode 101, for example. Note that the electrode 101a and the electrode 101 may be formed of different materials.

[0289] Another aspect of the pixel configuration of the liquid crystal display device is shown in FIGS. 54, 58(C), and 58(D). Also, the cross-sectional views of A1 to A2 in the top view of FIG. 54 are FIGS. 58(C) or 58 (D).

[0290] In FIGS. 54, 58(C), and 58(D), the pixel 530 includes a transistor 100, a capacitive element 532, and a liquid crystal element (or display element). Note that the pixel 530 may be a sub-pixel.

[0291] The configuration of the transistor 100 is the same as the configurations shown in Embodiments 1 to 10. Therefore, the same parts are denoted by the same reference numerals and the description thereof is omitted. Note that FIG. 58(C) is an example in which the transistor 100 having the configuration shown in FIG. 1( A) is applied, and FIG. 58(D) is an example in which the transistor 100 having the configuration shown in FIG. 1(C ) is applied. Thus, as the transistor 1 00, various configurations shown in Embodiments 1 to 10 can be adopted.

[0292] As the capacitive element 532, the parasitic capacitance and the capacitive element shown in Embodiments 7 and 8 can be used. Note that in FIG. 58(C), in the region 121c where the insulating layer 105 is made thin, ​​, an example of forming the capacitor element 532. In the region 1 where the layer 105b is removed in FIG. 58(D) 21c, it is an example of forming the capacitor element 532. The configuration of the capacitor element 5 31 shown in FIG. 58(D) corresponds to the configuration of the capacitor element shown in FIG. 22(E).

[0293] The electrode 106 of the transistor 100 is electrically connected to the electrode 101 at the opening 502a. The electrode 101 of the transistor 100 serves as the gate electrode of the transistor and also functions as a gate wiring. An electrode 101b is provided in parallel with the electrode 101. The electrode 101b functions as a capacitor line. The electrode 104a of the transistor 100 is either a source electrode or one of the drain electrodes and also functions as a source wiring. The source wiring is provided so as to cross the gate wiring. The electrode 104b of the transistor 100 is the other of the source electrode or the drain electrode and is electrically connected to the electrode 110 at the opening 502b. One of the pair of electrodes of the capacitor element 532 is the electrode 110, and the other is the electrode 101b.

[0294] Note that the electrode 101b can be formed of the same material in the same layer as the electrode 101, for example. Note that the electrode 101b and the electrode 101 may be formed of different materials.

[0295] Note that in FIG. 54, a configuration having a plurality of openings is shown as the electrode 110, but it is not limited to this. Also, in the configuration shown in FIG. 53, the electrode 110 may have a configuration having a plurality of openings. The electrode 110 can have an arbitrary shape.

[0296] In FIGS. 53, 54, and 58, the electrode 110 is a light-transmissive electrode. Alternatively, the electrode may include both a reflective region and a light-transmitting region. The electrode 110 may have both a reflective region and a light-transmitting region. When an electrode including the above is used, the liquid crystal display device can be made semi-transmissive.

[0297] The electrode 110 is an electrode including both a reflective region and a light-transmitting region. In the case where the reflective electrode is formed in the region having the reflectivity, the same layer as the layer in which the reflective electrode is formed is provided. The material can be used to form the electrode 106. Thus, the semiconductor of the transistor 100 The layer 103 can be light-shielding. The electrodes including both the transparent film and the reflective film are laminated by etching using a halftone mask. It can also be formed by etching.

[0298] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a A light-emitting device, which is a device for displaying light, can have various forms or elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an EL (electroluminescence) device. luminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements) , LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors ( current-dependent light-emitting transistors), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices child, electrowetting element, grating light valve (GLV), plasma Display panels (PDP), digital micromirror devices (DMD), piezoelectric ceramics Contrast displays, carbon nanotubes, etc., are created by electro-magnetic effects. There are those having a display medium in which brightness, reflectance, transmittance, etc. change. Using an EL element Examples of display devices using an EL element include an EL display. Examples of display devices using an electron-emitting element include a field emission display (FED) or a surface-conduction electron-emitter display (SED) flat panel display (SED). Examples of display devices using a liquid crystal element include a liquid crystal display (transmission type liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). Examples of display devices using an electronic ink or an electrophoretic element include an electronic paper. This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 12. Therefore, it can be freely combined with other embodiments such as Embodiments 1 to 12 and implemented.

[0299]

[0300] (Embodiment 14) In this embodiment, an example of applying a display device to a display module will be described.

[0301] FIG. 72 is a diagram showing a display module. The display module shown in FIG. 72 has a housing 901, a display device 902, a backlight unit 903, and a housing 904. The display device 902 is electrically connected to a driver IC 905. Further, a power supply voltage and a signal are supplied to the backlight unit 903 through a terminal 906.

[0302] Note that the present invention is not limited to the display module shown in FIG. 72, and may be a display module having a touch panel. Further, the display module may have a flexible printed circuit (FPC). In FIG. 72, the driver IC 905 may be electrically connected to the display device 902 by a flexible printed circuit (FPC). Further, the display module may have an optical film such as a polarizing plate or a retardation plate. This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 13. Therefore, it can be implemented in any combination with other embodiments such as Embodiments 1 to 13. (Embodiment 15) In this embodiment, an example of an electronic device will be described. FIGS. 67(A) to 67(H) and FIGS. 68(A) to 68(D) are diagrams showing an electronic device. These electronic devices can include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 5008, and the like. FIG. 67(A) shows a mobile computer, which, in addition to the above-described components, may include a switch 5009

[0303] This embodiment is not limited to the display module shown in FIG. 72 and may be a display module having a touch panel. Further, the display module may have a flexible printed circuit (FPC). In FIG. 72, the driver IC 905 may be electrically connected to the display device 902 by a flexible printed circuit (FPC). Further, the display module may have an optical film such as a polarizing plate or a retardation plate. This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 13. Therefore, it can be implemented in any combination with other embodiments such as Embodiments 1 to 13. (Embodiment 15) In this embodiment, an example of an electronic device will be described. FIGS. 67(A) to 67(H) and FIGS. 68(A) to 68(D) are diagrams showing an electronic device. These electronic devices can include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 5008, and the like.

[0304] (Embodiment 15) In this embodiment, an example of an electronic device will be described.

[0305] FIGS. 67(A) to 67(H), FIGS. 68(A) to 68(D) are diagrams showing an electronic device. These electronic devices can have a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 5008, etc. FIG. 67(A) is a mobile computer, and in addition to the above, it may have a switch 5009 Note that the present invention is not limited to the display module shown in FIG. 72, and may be a display module having a touch panel. Further, the display module may have a flexible printed circuit (FPC). In FIG. 72, the driver IC 905 may be electrically connected to the display device 902 by a flexible printed circuit (FPC). Further, the display module may have an optical film such as a polarizing plate or a retardation plate. This embodiment corresponds to a modification, addition, correction, deletion, application, generalization, or specialization of part or all of Embodiments 1 to 13. Therefore, it can be implemented in any combination with other embodiments such as Embodiments 1 to 13. (Embodiment 15) In this embodiment, an example of an electronic device will be described. FIGS. 67(A) to 67(H) and FIGS. 68(A) to 68(D) are diagrams showing an electronic device. These electronic devices can include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 5008, and the like.

[0306] FIG. 67(A) is a mobile computer, and in addition to the above, it may have a switch 5009 and can have an infrared port 5010, etc. Fig. 67(B) is a portable type image playback device (for example, a DVD playback device), and in addition to the above, it can have a second display unit 5002, a recording medium reading unit 5011, etc. Fig. 67(C) is a go ogle type display, and in addition to the above, it can have a second display unit 5002, a support unit 5012 , earphones 5013, etc. Fig. 67(D) is a portable game machine, and in addition to the above, it can have a recording medium reading unit 5011, etc. Fig. 67(E) is a digital camera with a TV receiving function, and in addition to the above, it can have an antenna 5014, a shutter button 5015, an imaging unit 5016, etc. Fig. 67(F) is a portable type game machine, and in addition to the above, it can have a second display unit 5002, a recording medium reading unit 5011 , etc. Fig. 67(G) is a TV receiver, and in addition to the above, it can have a tuner, an image processing unit, etc. Fig. 67(H) is a portable TV receiver device, and in addition to the above, it can have a charger 5017 capable of sending and receiving signals, etc. Fig. 68(A) is a display, and in addition to the above, it can have a support stand 5018, etc. Fig. 68(B) is a camera, and in addition to the above, it can have an external connection port 5019, a shutter button 5015, an imaging unit 5016, etc. Fig. 68(C) is a computer, and in addition to the above, it can have a pointing device 5 020, an external connection port 5019, a reader / writer 5021, etc. Fig. 68(D) is a mobile phone, and in addition to the above, it can have a transmitting unit, a receiving unit, a mobile phone / mobile . Fig. 68(D) is a mobile phone, and in addition to the above, it can have a transmitting unit, a receiving unit, a mobile phone / mobile phone transceiver, etc. Fig. 68(D) is a mobile phone, and in addition to the above, it can have a transmitting unit, a receiving unit, a mobile phone / mobile It can have a tuner for a one-segment partial reception service for mobile terminals, etc.

[0307] The electronic devices shown in FIGS. 67(A) to 67(H) and FIGS. 68(A) to 68(D) can have various functions. For example, functions such as displaying various information (such as still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be included. Further, in an electronic device having a plurality of display units, it can have a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or a function of displaying a stereoscopic image by displaying an image considering parallax on a plurality of display units, etc. Further, in an electronic device having an imaging unit, it can have a function of taking a still image, a function of taking a moving image, a function of automatically or manually correcting the taken image, a function of saving the taken image on a recording medium (external or built into the camera), a function of displaying the taken image on the display unit, etc. Note that the functions that the electronic devices shown in FIGS. 67(A) to 67(H) and FIGS. 68(A) to 68(D) can have are not limited to these, and they can have various functions. The electronic devices described in this embodiment are characterized by having a display unit for displaying some kind of information.

[0308]

[0309] Next, application examples of the semiconductor device will be described.

[0310] Fig. 68(E) shows an example in which the semiconductor device is provided integrally with a building. Fig. 68( E) includes a housing 5022, a display unit 5023, a remote control device 5024 which is an operation unit, a speaker 5025, etc. The semiconductor device is wall-mounted and integrated with the building, and can be installed without requiring a large installation space.

[0311] Fig. 68(F) shows another example in which the semiconductor device is provided integrally with a building inside the building. The display panel 5026 is attached integrally with the unit bus 5027, and a bather can view the display panel 5026.

[0312] Note that, in this embodiment, a wall and a unit bus are taken as examples of the building, but this embodiment is not limited thereto, and the semiconductor device can be installed in various buildings.

[0313] Next, an example in which the semiconductor device is provided integrally with a moving body will be shown.

[0314] Fig. 68(G) is a diagram showing an example in which the semiconductor device is provided in an automobile. The display panel 5028 is attached to the vehicle body 5029 of the automobile, and can display, on demand, the operation of the vehicle body or information input from inside or outside the vehicle body. Note that it may have a navigation function.

[0315] Fig. 68(H) is a diagram showing an example in which the semiconductor device is provided integrally with a passenger aircraft. Fig. 68(H) is a diagram showing the shape during use when a display panel 5031 is provided on the ceiling 5030 above the seat of a passenger aircraft. The display panel 5031 is provided on the ceiling 5 ​It is integrally attached via 030 and the hinge portion 5032, and the telescopic movement of the hinge portion 5032 enables the passenger to view the display panel 5031. The display panel 5031 has a function of displaying information by being operated by the passenger.

[0316] In addition, in the present embodiment, examples of the moving body include an automobile body and an airplane body but are not limited thereto, and it can be installed on various things such as motorcycles, four-wheel vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0317] In addition, in this specification, etc., in the figures or sentences described in a certain embodiment, it is possible to extract a part thereof and form an aspect of the invention. Therefore when a figure or sentence describing a certain part is described, the content obtained by extracting a part of the figure or sentence thereof is also disclosed as an aspect of the invention and is assumed to be able to form an aspect of the invention. For this reason, for example, in the drawings or sentences in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is assumed that a part thereof can be extracted and form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) and form an aspect of the invention. As another example from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers and form an aspect of the invention. It is possible to extract and constitute one aspect of the invention. As yet another example, from a flowchart composed of N elements (N is an integer), it is possible to extract M elements (M is an integer and M < N) (N is an integer) and constitute one aspect of the invention. )

[0318] In this specification and the like, when at least one specific example is described in the figure or text described in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, when at least one specific example is described in the figure or text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention.

[0319] In this specification and the like, at least the content described in the figure (which may be a part of the figure) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, for a certain content, if it is described in the figure, even if it is not described using text, the content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention.

Explanation of Reference Numerals

[0320] 100 Transistor 101 Electrode 102 Insulating Layer 103 Semiconductor Layer 104 Electrode 105 Insulating Layer 106 Electrode 107 Insulating layer 110 Electrode 121 Region 122 Region 123 Opening 124 Opening 125 Opening 126 Opening 127 Opening 128 Opening 191 Opening 192 Opening 193 Opening 194 Opening 195 Opening 196 Opening 197 Opening 198 Opening 200 Insulating surface 281 Portion 282 Portion 283 Portion 441 Opening 442 Opening 443 Opening 444 Opening 445 Opening 446 Opening 447 Opening 448 Opening 451 Opening 452 Opening 453 Opening 454 Opening 455 Opening 456 Opening 457 Opening 458 Opening 510 Protrusion 530 Pixel 531 Capacitor element 532 Capacitor element 550 Electrode 551 Gate signal line 552 Source signal line 553 Capacitance line 560 EL element 561 Current supply line 562 Transistor 563 Transistor 564 Capacitor element 591 Insulating film 592 Halftone mask 602 Resist 603 Halftone mask 604 Resist mask 652 Black matrix 701 Transistor 702 Transistor 703 Transistor 704 Transistor 705 Transistor 706 Transistor 707 Transistor 708 Transistor 709 Transistor 710 Transistor 711 Transistor 712 Transistor 713 Transistor 714 Capacitor element 715 Transistor 801 Transistor 802 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 Transistor 808 Transistor 809 Transistor 810 Transistor 811 Transistor 812 Transistor 813 Transistor 814 Transistor 815 Transistor 816 Transistor 817 Transistor 901 Housing 902 Display device 903 Backlight unit 904 Housing 905 Driver IC 906 Terminal Electrode 101a Electrode 101b Semiconductor layer 103a Electrode 104a Electrode 104b Electrode 104c Layer 105a Layer 105b Layer 105c Electrode 106a Conductive layer 108a Conductive layer 108b Connection part 109 Electrode 110b Region 121c Opening 128a End 131a End 131b End 132a End 132b Housing 5000 Display part 5001 Display part 5002 Speaker 5003 LED lamp 5004 Operation key 5005 Connection terminal 5006 Sensor 5007 Microphone 5008 Switch 5009 Infrared port 5010 Recording medium reading part 5011 Support part 5012 Earphone 5013 Antenna 5014 Shutter button 5015 Image receiving part 5016 Charger 5017 Support stand 5018 External connection port 5019 Opening 501a Opening 501b Pointing device 5020 Reader / writer 5021 Housing 5022 Display part 5023 5024 Remote control device 5025 Speaker 5026 Display panel 5027 Unit bus 5028 Display panel 5029 Vehicle body 502a Opening 502b Opening 5030 Ceiling 5031 Display panel 5032 Hinge part 510a Layer 510b Layer 592a Region 592b Region 592c Region 601a Insulating film 601b Insulating film 601c Insulating film 603a Region 603b Region 603c Region

Claims

1. A display device having, in a pixel, an EL element, a first transistor having a function of controlling a current supplied to the EL element, and a second transistor having a function of controlling whether to supply a video signal to a gate of the first transistor, a first conductive layer, a first insulating layer having a region above the first conductive layer, an oxide semiconductor layer having a region above the first insulating layer, a second conductive layer having a region above the oxide semiconductor layer, a second insulating layer having a region above the second conductive layer, a third insulating layer having a region above the second insulating layer, a fourth insulating layer having a region above the third insulating layer, and a third conductive layer having a region above the fourth insulating layer, wherein the first conductive layer has a region overlapping the oxide semiconductor layer via the first insulating layer, the oxide semiconductor layer has a region functioning as a channel formation region of the first transistor, the first conductive layer has a region functioning as a gate electrode of the first transistor, the second conductive layer has a region functioning as a source electrode or a drain electrode of the first transistor, the third conductive layer has a first region, a second region, and a third region, the first region overlaps the second insulating layer, the third insulating layer, and the fourth insulating layer, the first region functions as a pixel electrode of the EL element, the second region does not overlap the third insulating layer and overlaps the channel formation region via the second insulating layer and the fourth insulating layer, the third region does not overlap the fourth insulating layer, does not overlap the third insulating layer, and does not overlap the second insulating layer, in the third region, the third conductive layer has a region in contact with the second conductive layer, the third insulating layer functions as a color filter, a display device, wherein an upper surface of the second insulating layer and a lower surface of the fourth insulating layer are in contact with each other in a region below the second region and overlapping the channel formation region.

2. A display device having, in a pixel, an EL element, a first transistor having a function of controlling a current supplied to the EL element, and a second transistor having a function of controlling whether to supply a video signal to a gate of the first transistor, a first conductive layer, a first insulating layer having a region above the first conductive layer, An oxide semiconductor layer having a region above the first insulating layer, A second conductive layer having a region above the oxide semiconductor layer, A second insulating layer having a region above the second conductive layer, A third insulating layer having a region above the second insulating layer, A fourth insulating layer having a region above the third insulating layer, A third conductive layer having a region above the fourth insulating layer, and having, The first conductive layer has a region overlapping the oxide semiconductor layer via the first insulating layer, The oxide semiconductor layer has a region functioning as a channel formation region of the first transistor, The first conductive layer has a region functioning as a gate electrode of the first transistor, The second conductive layer has a region functioning as a source electrode or a drain electrode of the first transistor, The third conductive layer has a first region, a second region, and a third region, The first region overlaps with the second insulating layer, the third insulating layer, and the fourth insulating layer, The first region functions as a pixel electrode of the EL element, The second region does not overlap with the third insulating layer and overlaps with the channel formation region via the second insulating layer and the fourth insulating layer, The third region does not overlap with the fourth insulating layer, does not overlap with the third insulating layer, and does not overlap with the second insulating layer, In the third region, the third conductive layer has a region in contact with the second conductive layer, The third insulating layer functions as a color filter, Below the second region and in a region overlapping the channel formation region, the upper surface of the second insulating layer and the lower surface of the fourth insulating layer are in contact, The oxide semiconductor layer has an In—O based oxide semiconductor, a display device.

3. In claim 1 or claim 2, A display device, wherein the upper surface of the second insulating layer and the lower surface of the fourth insulating layer are in contact at a periphery of the third region.

4. In any one of claims 1 to 3, The third conductive layer has a fourth region, The fourth region has a region overlapping with a fifth insulating layer, The fifth insulating layer has a region functioning as a color filter, A display device, wherein the fifth insulating layer has a color different from that of the third insulating layer.

Images