Semiconductor device

Abstract

To provide a semiconductor device that combine power supply stabilization with improved heat dissipation performance.SOLUTION: The semiconductor device has a substrate and a semiconductor chip disposed on the substrate, the substrate has a groove opening on the semiconductor chip side, a wiring section of a predetermined pattern is provided inside the groove via an insulating layer, the substrate is connected to the ground wiring of the semiconductor chip, the wiring section is connected to the power wiring of the semiconductor chip, and the wiring section is not exposed from the rear side of the substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In semiconductor devices, generally, as the generations progress, the integration degree increases, and accordingly, the power consumption per circuit scale decreases due to the reduction of the load capacitance and the decrease of the power supply voltage. On the other hand, when the integration degree increases, the heat generation density does not necessarily decrease, but rather tends to increase. For future semiconductor devices, power supply stabilization and improvement of heat dissipation performance are required.

[0003] As a conventional semiconductor device, for example, a structure is known in which a silicon substrate is processed from the back side, a metal wiring for power supply is formed on the back side of the silicon substrate, and the lower surface of the metal wiring is exposed from the back of the silicon substrate. This power supply metal wiring is connected to other wirings by through-wirings provided in the silicon substrate (see, for example, Non-Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a semiconductor device having the above structure, although a certain degree of power supply stabilization is possible, since it does not have a heat dissipation mechanism, the heat dissipation effect cannot be expected much.

[0006] The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device that achieves both power supply stabilization and improvement of heat dissipation performance.

Means for Solving the Problems

[0007] This semiconductor device has a power ground layer and a semiconductor chip disposed on the power ground layer. The power ground layer includes a substrate having a groove that opens to the semiconductor chip side, and a wiring portion of a predetermined pattern disposed inside the groove via an insulating layer. The substrate is connected to the ground wiring of the semiconductor chip, and the wiring portion is connected to the power wiring of the semiconductor chip. The substrate and the wiring portion are directly connected to a through electrode provided on the semiconductor chip. The wiring portion is not exposed from the back surface of the substrate.

Advantages of the Invention

[0008] According to the disclosed technology, a semiconductor device that achieves both power supply stabilization and improved heat dissipation performance can be provided.

Brief Description of the Drawings

[0009]

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Best Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and redundant descriptions may be omitted.

[0011] 〈First Embodiment〉 [Structure of Semiconductor Device] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to the first embodiment. Referring to FIG. 1, a semiconductor device 1 according to the first embodiment includes a power ground layer 10, and semiconductor chips 301 and 302 sequentially stacked on the power ground layer 10 with an insulating layer 20 therebetween. The semiconductor chips 301 and 302 are stacked with their main surfaces (the surfaces on the electrode pad formation side) facing the same direction. In the semiconductor device 1, semiconductor chips in different layers can transmit signals and supply power by connecting through the through electrodes 36. More than three semiconductor chips may be stacked on the power ground layer 10. Also, the semiconductor chips arranged on the power ground layer 10 are not limited to a stacked body and may be a single layer. Alternatively, in a plan view, a plurality of semiconductor chips may be arranged at different positions on the power ground layer 10. In this case as well, the semiconductor chips may be a stacked body, a single layer, or a mixture of a stacked body of semiconductor chips and a single semiconductor chip.

[0012] FIG. 2 is a plan view illustrating the power ground layer. FIG. 3 is a perspective view illustrating the power ground layer, schematically showing the substrate connected to the ground wiring of the semiconductor chip and the wiring portion connected to the power supply wiring of the semiconductor chip separately. Note that in FIG. 1, the power ground layer is drawn in a more simplified manner than in FIGS. 2 and 3.

[0013] Referring to FIGS. 1 to 3, the power ground layer 10 includes a substrate 11 and a wiring portion 12. The substrate 11 has a structure in which a groove 115 that opens toward the semiconductor chip 301 side is formed in a conductive plate-like body. The substrate 11 has a bottom portion 111, a frame-shaped side wall portion 112 that surrounds the bottom portion 111, and a plurality of columnar portions 113 that are spaced apart from each other in a region surrounded by the side wall portion 112 on the bottom portion 111.

[0014] Each columnar portion 113 is, for example, arranged vertically and horizontally and spaced apart from each other. The planar shape of each columnar portion 113 is, for example, a square, but can be any shape such as a rectangle or a circle. The upper surface of each columnar portion 113 is substantially on the same plane as the upper surface of the side wall portion 112. The gaps between each columnar portion 113 and the side wall portion 112, and the gaps between adjacent columnar portions 113 are the groove 115.

[0015] As the material of the substrate 11, for example, a semiconductor material with relatively high hardness such as silicon or diamond is preferably used in terms of ensuring strength. The thickness T1 of the substrate 11 is, for example, 100 μm or more and 300 μm or less. The thickness T2 of the bottom portion 111 is, for example, 10 μm or more and 30 μm or less. The interval S1 between adjacent columnar portions 113 is, for example, 10 μm or more and 30 μm or less.

[0016] When the substrate 11 is formed of silicon, the volume of silicon is preferably 60% or less with respect to the total volume of silicon and the wiring portion 12. Thereby, high thermal conductivity by the conductor portion can be obtained.

[0017] The wiring portion 12 is disposed inside the groove 115 of the substrate 11 via an insulating layer (not shown). That is, the wiring portion 12 is insulated from the substrate 11 by the insulating layer. Note that an insulating layer and a barrier layer may be provided between the substrate 11 and the wiring portion 12. A decoupling capacitor is formed between the substrate 11, the insulating layer, and the wiring portion 12. Thereby, the power supply of the semiconductor device 1 can be stabilized.

[0018] The wiring portion 12 is a pattern formed vertically and horizontally with a plurality of openings 125, and the columnar portions 113 of the substrate 11 are arranged in each of the openings 125. The upper surface of the wiring portion 12 is substantially on the same plane as the upper surface of the side wall portion 112 of the substrate 11 and the upper surfaces of the respective columnar portions 113. The wiring portion 12 is not exposed from the back surface of the substrate 11. That is, the back surface of the semiconductor device 1 consists only of the bottom portion 111 of the substrate 11.

[0019] The pattern having the plurality of openings 125 of the wiring portion 12 is, for example, a mesh-shaped pattern in plan view. Here, the mesh shape refers to a shape in which a plurality of openings 125 are formed by intersecting wirings. The intersecting wirings do not necessarily have to be straight lines. Also, the intersecting wirings do not necessarily have to be orthogonal to each other. In the present application, the case where the intersecting wirings are straight lines and orthogonal to each other is particularly referred to as a lattice shape.

[0020] The planar shape of the opening 125 can be any shape such as a square, a rectangle, a circle, etc., according to the planar shape of the columnar portion 113. In the example of FIG. 2, the wiring portion 12 is formed in a lattice shape in which a plurality of linearly arranged wirings in the left-right direction intersect a plurality of linearly arranged wirings in the up-down direction, and the planar shape of each opening 125 is substantially square.

[0021] As the material of the wiring portion 12, it is preferable in terms of ensuring electrical characteristics and heat dissipation performance to include, for example, a metal material such as copper that has relatively high electrical conductivity and thermal conductivity. In addition to copper, metals such as silver (Ag) and aluminum (Al) may be used as the material of the wiring portion 12. The thickness of the wiring portion 12 is the same as the depth of the groove 115 of the substrate 11. The width of the portion sandwiched between adjacent columnar portions 113 is the same as the interval S1 between adjacent columnar portions 113, and is, for example, 10 μm or more and 30 μm or less.

[0022] Returning to the description of FIG. 1, the semiconductor chip 301 is stacked on the power ground layer 10 via the insulating layer 20. Further, the semiconductor chip 302 is stacked on the semiconductor chip 301. As the material of the insulating layer 20, for example, SiO2, SiON, Si3N4, etc. or a high-k dielectric material such as a hafnium oxide film can be used. The thickness of the insulating layer 20 can be, for example, about 0.05 μm to 0.5 μm.

[0023] Each of the semiconductor chips 301 and 302 has a substrate 31, an insulating layer 32, a wiring layer 33, an electrode pad 34, an insulating layer 35, and a through electrode 36. The substrate 31 of each of the semiconductor chips 301 and 302 is thinned, and the thickness of each substrate 31 is, for example, 0.2 μm or more and 5 μm or less.

[0024] In the semiconductor chips 301 and 302, the substrate 31 is made of, for example, silicon, gallium nitride, silicon carbide, etc. A semiconductor integrated circuit (not shown) is formed on the main surface side of the substrate 31. The semiconductor integrated circuit includes, for example, a plurality of field-effect transistors having a drain, a gate, and a source, and each field-effect transistor is separated by an element isolation layer.

[0025] The insulating layer 32 is formed on one surface of the substrate 31. Although simplified in FIG. 1 and the like, a wiring layer 33 including a plurality of layers of horizontal wiring and vertical wiring is formed of copper or the like in the insulating layer 32. The horizontal wirings in different layers are connected to each other by vertical wiring as appropriate. The electrode pad 34 is located on the uppermost layer of the wiring layer 33 and is electrically connected to the lower wiring layer 33.

[0026] In the semiconductor chips 301 and 302, a part of the through electrode 36 is formed on the upper surface of the electrode pad 34, and the upper surface of the through electrode 36 is exposed on the surface of the insulating layer 32. Note that the electrode pad 34 and the portion of the through electrode 36 formed on the upper surface of the electrode pad 34 may be simply referred to as an electrode pad.

[0027] The planar shape of the electrode pad 34 and the planar shape of the through electrode 36 formed on the upper surface of the electrode pad 34 can be, for example, rectangular, circular, or the like. When the planar shape of the electrode pad 34 is circular, the diameter of the electrode pad 34 can be, for example, about 3 μm to 10 μm. The planar shape of the through electrode 36 formed on the upper surface of the electrode pad 34 is slightly smaller than the planar shape of the electrode pad 34.

[0028] The material of the electrode pad 34 is, for example, copper. The electrode pad 34 may have a structure in which a plurality of metals are laminated. Specifically, for example, as the electrode pad 34, a laminate in which an Au layer, an Al layer, a Cu layer, etc. are laminated on a Ti layer or a TiN layer can be used. As the electrode pad 34, a laminate in which an Au layer is laminated on a Ni layer, a laminate in which a Pd layer and an Au layer are sequentially laminated on a Ni layer, a layer made of a high melting point metal such as Co, Ta, Ti, TiN, etc. is used instead of Ni, and a Cu layer or an Al layer is laminated on the same layer. A laminate or a damascene structure wiring can also be used.

[0029] In the semiconductor chips 301 and 302, an insulating layer serving as a barrier layer may be provided on the back surface of the substrate 31. In this case, as the material of the insulating layer, for example, SiO2, SiON, Si3N4, etc. can be used. The thickness of the insulating layer can be, for example, about 0.05 μm to 0.5 μm. By forming an insulating layer (barrier layer) on the back surface side of the substrate 31 in the semiconductor chips 301 and 302, the risk of the semiconductor chip being contaminated by metal impurities from the back surface side can be reduced, and when a semiconductor chip is disposed in the lower layer, it can be insulated from the lower semiconductor chip.

[0030] The semiconductor chips adjacent to each other vertically are directly joined, for example, without using an adhesive layer or the like, but when necessary (for example, when the surface of the semiconductor integrated circuit is not flat), they may be joined via an adhesive layer or the like.

[0031] In the semiconductor chip 301, via holes are formed that penetrate the substrate 31 and the insulating layer 32, further penetrate the insulating layer 20, and expose the upper surface of the substrate 11 or the wiring portion 12 of the power ground layer 10. An insulating layer 35 is provided on the inner wall (side wall) of the via hole. In the semiconductor chip 302, via holes are formed that penetrate the substrate 31 and the insulating layer 32 and expose the upper surface of the through electrode 36 of the semiconductor chip 301. An insulating layer 35 is provided on the inner wall (side wall) of the via hole. As the material of the insulating layer 35, for example, SiO2, SiON, Si3N4, etc. can be used. The thickness of the insulating layer 35 can be, for example, about 0.05 μm to 0.5 μm.

[0032] The inside of the insulating layer 35 is filled with the through electrode 36. The electrode pads 34 of each semiconductor chip are directly electrically connected via the through electrode 36. The planar shape of the through electrode 36, excluding the portion formed on the upper surface of the electrode pad 34, is, for example, circular or polygonal. When the planar shape of the through electrode 36, excluding the portion formed on the upper surface of the electrode pad 34, is circular, its diameter can be, for example, about 0.3 μm to 5 μm.

[0033] In the semiconductor chip 301, at least a part of the through electrode 36 connected to the ground wiring of the semiconductor chip 301 penetrates the insulating layer 20 and the end face is electrically connected to the substrate 11 of the power ground layer 10. Also, at least a part of the through electrode 36 connected to the power wiring of the semiconductor chip 301 penetrates the insulating layer 20 and the end face is electrically connected to the wiring portion 12 of the power ground layer 10.

[0034] Preferably, the total area of the end faces of the through electrodes 36 connected to the substrate 11 or the wiring portion 12 is 2% or more of the area of the back surface of the semiconductor chip 301. Thereby, heat from the semiconductor chip 301 can be sufficiently transmitted to the power ground layer 10. Also, the connection between the substrate 11 and the ground wiring of the semiconductor chip 301 and the connection between the wiring portion 12 and the power wiring of the semiconductor chip 301 can be reliably made with low resistance.

[0035] The material of the through electrode 36 is, for example, copper. The through electrode 36 may have a structure in which a plurality of metals are laminated. Specifically, for example, as the through electrode 36, a laminate in which an Au layer, an Al layer, a Cu layer, etc. are laminated on a Ti layer or a TiN layer can be used. As the through electrode 36, a laminate in which an Au layer is laminated on a Ni layer, a laminate in which a Pd layer and an Au layer are sequentially laminated on a Ni layer, a layer made of a refractory metal such as Co, Ta, Ti, TiN, etc. is used instead of Ni, and a Cu layer or an Al layer is laminated on the same layer A laminate or a damascene structure wiring or the like may be used.

[0036] [Manufacturing process of semiconductor device] Next, the manufacturing process of the semiconductor device according to the first embodiment will be described. FIGS. 4 to 16 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. Here, an example using the so-called wafer-on-wafer method for laminating semiconductor chips is shown, but the so-called chip-on-wafer method may also be used. However, as described above, the semiconductor chips arranged on the power supply ground layer are not limited to the laminate, and may be a single layer. Alternatively, in a plan view, a plurality of semiconductor chips may be arranged at different positions on the power supply ground layer. Also in this case, the semiconductor chips may be a laminate, a single layer, or a mixture of a laminate of semiconductor chips and a single semiconductor chip.

[0037] First, in the process shown in FIG. 4, the substrate 11 is prepared. Here, as an example, the substrate 11 is a silicon wafer. The silicon wafer is, for example, circular, and the diameter is, for example, 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm), etc. The thickness of the substrate 11 is, for example, 0.625 mm (in the case of a 6-inch diameter), 0.725 mm (in the case of an 8-inch diameter), 0.775 mm (in the case of a 12-inch diameter), etc.

[0038] Since the surface of the substrate 11 finally contacts the through electrode, it is particularly preferable that the impurity concentration on the surface of the substrate 11 is high, 10 20 cm -3It is preferably as described above. Ion implantation may be performed on the surface of the substrate 11. The substrate 11 may be doped with a P-type impurity such as boron, but doping with phosphorus as an N-type impurity is preferable from the viewpoint of capacitance formation described later.

[0039] Next, in the process shown in FIG. 5, a groove 115 is formed in the substrate 11. The groove 115 can be formed by, for example, dry etching or the like. Here, as an example, a mesh-shaped groove 115 as shown in FIG. 3 is formed. The width of the groove 115 is, for example, 20 μm, and the depth is, for example, 180 μm.

[0040] Next, in the process shown in FIG. 6, a wiring portion 12 is formed in the groove 115 of the substrate 11. Specifically, first, an insulating layer covering the bottom surface and the inner wall surface of the groove 115 is formed to a thickness of about 200 nm with a silicon oxide film or the like by a plasma CVD method or the like. Then, a barrier metal layer is formed of copper or the like so as to cover the insulating layer, and a seed layer is further formed of a laminated film of tantalum nitride and copper or the like. The barrier metal layer and the seed layer can be formed by, for example, a sputtering method or the like. Then, an electrolytic plating layer made of copper or the like is formed on the seed layer so as to protrude from the upper surface of the substrate 11 by an electrolytic plating method that supplies power from the seed layer. Thereafter, the electrolytic plating layer protruding from the upper surface of the substrate 11 is removed by CMP or the like. The upper surface of the substrate 11 and the upper surface of the wiring portion 12 can be, for example, flush. Thereafter, annealing is preferably performed under appropriate conditions for sintering. As described above, a power supply ground layer 10A having a wiring portion 12 in the groove 115 of the substrate 11 and having a plurality of regions that become the power supply ground layer 10 when singulated is manufactured.

[0041] Next, in the process shown in FIG. 7, an unthinned substrate 31 is prepared. Here, as an example, the substrate 31 is a silicon wafer. The substrate 31 is defined with a plurality of product regions A and scribe regions B that separate the respective product regions A. The product regions A are arranged, for example, vertically and horizontally. C in the scribe region B indicates a position (hereinafter referred to as "cutting position C") where a dicing blade or the like cuts the substrate 31.

[0042] Next, in the process shown in FIG. 8, a semiconductor integrated circuit, an insulating layer 32, a wiring layer 33, and electrode pads 34 are formed on a substrate 31 by a well-known method. Thereby, a semiconductor device 30A having a plurality of product regions A that will become semiconductor chips 301 when singulated is fabricated. In FIG. 8, illustration of the semiconductor integrated circuit, the wiring layer 33, and the electrode pads 34 is omitted.

[0043] Next, in the process shown in FIG. 9, a support substrate 510 is bonded to the electrode pad formation side of the semiconductor device 30A via an adhesive layer 520. As the support substrate 510, it is preferable to use a substrate through which light can pass during alignment. For example, a substrate such as a quartz glass substrate can be used. As the adhesive layer 520, for example, an adhesive that softens at the temperature to be heated in the process shown in FIG. 12 described later (an adhesive that softens at about 200° C. or lower) can be used. The adhesive layer 520 can be formed on one surface of the support substrate 510 by, for example, a spin coating method. Alternatively, the adhesive layer 520 may be formed on the element surface of the semiconductor device 30A. The adhesive layer 520 may be formed on at least one of one surface of the support substrate 510 and the element surface of the semiconductor device 30A using a method such as attaching a film-shaped adhesive instead of the spin coating method.

[0044] Next, in the process shown in FIG. 10, the structure shown in FIG. 9 is inverted upside down. Then, using a grinder or the like, the back surface (the surface opposite to the main surface) of the substrate 31 of the semiconductor device 30A is mechanically ground, and further polished for finishing by CMP or the like to thin the back surface side of the substrate 31. An insulating layer may be formed on the thinned back surface side of the substrate 31 by a plasma CVD method or the like.

[0045] The thickness of the thinned substrate 31 is, for example, 0.2 μm or more and 5 μm or less. By setting the thickness of the substrate 31 to 0.2 μm or more and 5 μm or less, the processing time of the via hole is significantly shortened, the aspect ratio is relaxed by thinning, and the embedding property and coverage are improved. In addition, the thermal conductivity from the substrate 31 to the power supply ground layer 10 can be improved.

[0046] Next, in the process shown in FIG. 11, an insulating layer 20 is formed on the wiring portion 12 side of the power ground layer 10A fabricated in FIG. 6 by a method such as plasma CVD. Then, with the back side of the semiconductor device 30A facing the insulating layer 20, the semiconductor device 30A bonded to the support substrate 510 is laminated on the power ground layer 10A via the insulating layer 20.

[0047] Next, in the process shown in FIG. 12, the support substrate 510 and the adhesive layer 520 shown in FIG. 11 are removed. As described above, it is preferable to use, as the adhesive layer 520, an adhesive that softens at the temperature at which heating is performed in the process shown in FIG. 12 (an adhesive that softens at about 200° C. or lower). Thereby, a laminate is formed on the power ground layer 10A, in which the thinned semiconductor device 30A is laminated via the insulating layer 20.

[0048] In FIGS. 13 to 16 that follow, the description will be made with reference to one cross-section of the product region A (the region between adjacent cutting positions C) shown in FIG. 7.

[0049] Next, in the process shown in FIG. 13, via holes 30x are formed in the semiconductor device 30A. The via holes 30x penetrate through the electrode pads 34, the insulating layer 32, and the substrate 31 of the semiconductor device 30A, and further penetrate through the insulating layer 20 so that the upper surface of the substrate 11 or the wiring portion 12 of the power ground layer 10A is exposed. The via holes 30x can be formed, for example, by dry etching or the like. The via holes 30x are, for example, circular in plan view, and their diameter can be, for example, about 0.3 μm to 5 μm.

[0050] Next, in the process shown in FIG. 14, an insulating layer 35 that coats the inner wall surface of the via holes 30x is formed, and a through electrode 36 is further formed inside the insulating layer 35. To form the insulating layer 35, first, for example, by a method such as plasma CVD, an insulating layer that continuously coats the inner wall surface of the via holes 30x and the upper surface of the substrate 11 or the wiring portion 12 exposed inside the via holes 30x is formed. Then, portions other than the portion that coats the inner wall surface of the via holes 30x are removed by RIE (Reactive Ion Etching) or the like.

[0051] The through electrode 36 can be formed in the via hole 30x, for example, by combining a sputtering method and a plating method. Specifically, for example, a metal such as Cu is deposited by sputtering to a thickness of about 50 nm to 500 nm so as to continuously coat the inner wall surface of the via hole 30x and the upper surface of the substrate 11 or the wiring portion 12 exposed in the via hole 30x, thereby forming a power supply layer. Then, the inside of the via hole 30x is filled with a metal such as Cu by an electrolytic plating method that supplies power through the power supply layer, and an electrolytic plating layer protruding from the upper surface of the insulating layer 32 is formed. Then, the electrolytic plating layer protruding from the upper surface of the insulating layer 32 is removed by CMP or the like. The upper surface of the electrolytic plating layer filled in the via hole 30x and the upper surface of the insulating layer 32 can be flush, for example. Thereby, the through electrode 36 in which the electrolytic plating layer is laminated on the power supply layer can be formed.

[0052] Next, in the process shown in FIG. 15, a semiconductor device 30B having a plurality of product regions A that will become semiconductor chips 302 when individualized is manufactured by the same process as in FIGS. 7 and 8. The semiconductor device 30B has the same structure as the semiconductor device 30A. Next, the semiconductor device 30B is laminated on the semiconductor device 30A by the same process as in FIGS. 9 to 12. Then, a via hole 30x, an insulating layer 35, and a through electrode 36 are formed in the semiconductor device 30B by the same process as in FIGS. 13 and 14. The electrode pad 34 of the semiconductor device 30B is electrically connected to the through electrode 36 of the semiconductor device 30A through the through electrode 36 of the semiconductor device 30B.

[0053] Next, in the process shown in FIG. 16, the back side of the substrate 11 of the power supply ground layer 10A is mechanically ground using a grinder or the like, and further polished for finishing by CMP or the like to thin the back side of the substrate 11. The thickness of the substrate 11 becomes, for example, 200 μm.

[0054] Next, the structure shown in FIG. 16 is cut at the cutting position C to individualize each product area. As a result, a plurality of semiconductor chips 301 are formed from the semiconductor device 30A, and a plurality of semiconductor chips 302 are formed from the semiconductor device 30B. Further, a plurality of power ground layers 10 having a substrate 11 and a wiring portion 12 are formed from the power ground layer 10A. That is, a plurality of semiconductor devices 1 (see FIG. 1) in which semiconductor chips 301 and 302 are sequentially stacked on the power ground layer 10 via the insulating layer 20 are completed.

[0055] Thus, the semiconductor device 1 has a power ground layer 10 including a substrate 11 having a groove 115 opening to the semiconductor chip 301 side and a wiring portion 12 of a predetermined pattern disposed inside the groove 115 via an insulating layer, and the wiring portion 12 is not exposed from the back surface of the substrate 11. The substrate 11 is connected to the ground wiring of the semiconductor chip 301, and the wiring portion 12 is connected to the power wiring of the semiconductor chip 301.

[0056] In the semiconductor device 1, power supply stabilization can be achieved by using a metal such as copper, which is a good conductor, for the wiring portion 12, and a reduction in voltage (≒ reduction in power) due to power supply stabilization can be realized. Further, since a metal such as copper is also a good heat conductor, heat generation of the entire semiconductor device 1 can be made uniform. Further, the back surface of the semiconductor device 1 is formed only of the substrate 11, and the wiring portion 12 is not exposed from the back surface of the substrate 11. Therefore, since heat can be efficiently exhausted from the back surface of the substrate 11, the heat dissipation performance of the semiconductor device 1 can be improved. That is, a semiconductor device 1 that achieves both power supply stabilization and improvement in heat dissipation performance can be realized.

[0057] Further, since the back surface of the semiconductor device 1 is formed only of the substrate 11 and the wiring portion 12 is not exposed from the back surface of the substrate 11, a metal heat sink or the like can be easily attached to the back surface of the substrate 11.

[0058] In FIG. 2 and the like, an example in which the wiring portion 12 is formed integrally with the groove 115 of the substrate 11 is shown, but the present invention is not limited thereto. For example, the wiring portion 12 may be divided into a plurality of systems insulated from each other in a plan view (see, for example, FIG. 26 and the like described later). In this case, the wiring portions of the respective systems can be connected to power supply wirings of different systems of the semiconductor chip (for example, power supply wirings having different power supply voltages from each other).

[0059] <Modification Example 1 of the First Embodiment> In Modification Example 1 of the first embodiment, an example of a semiconductor device having a power supply ground layer with a different wiring portion structure is shown. In Modification Example 1 of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0060] FIG. 17 is a cross-sectional view illustrating a semiconductor device according to Modification Example 1 of the first embodiment. Referring to FIG. 17, the semiconductor device 1A according to Modification Example 1 of the first embodiment is different from the semiconductor device 1 (see FIG. 1 and the like) in that the power supply ground layer 10 is replaced with the power supply ground layer 40.

[0061] The power supply ground layer 40 includes a substrate 11 and a wiring portion 42. The substrate 11 is as described above. The wiring portion 42 is disposed in the groove 115 of the substrate 11 via an insulating layer or a barrier layer (not shown). The wiring portion 42 including the opening 145 can have, for example, the same pattern as that in FIG. 2. The dimensional relationship between the substrate 11 and the wiring portion 42 can be the same as the dimensional relationship between the substrate 11 and the wiring portion 12.

[0062] The wiring portion 42 has a laminated structure in which a second layer 42B is laminated on a first layer 42A. The first layer 42A is formed of a material that transmits heat more easily than the second layer 42B. The first layer 42A is, for example, a carbon layer including carbon nanotubes, graphene flakes, or the like. The second layer 42B is, for example, a metal layer such as a copper layer. In other words, the wiring portion 42 includes a metal layer disposed on the semiconductor chip 301 side and a carbon layer located under the metal layer.

[0063] For example, when the first layer 42A is a carbon layer and the second layer 42B is a copper layer, since the carbon layer conducts heat more easily than the copper layer, the heat dissipation performance can be improved compared to the case where the wiring portion 42 is formed only of the copper layer. However, in order to reduce the resistance value and contact resistance of the wiring portion 42, not all of them are made of the carbon layer, and a copper layer is also required. That is, by having the wiring portion 42 include both the carbon layer and the copper layer, it is possible to reduce the thermal resistance and the electrical resistance. In addition, by providing the carbon layer, it is possible to relieve the thermal strain of copper.

[0064] From the viewpoint of sufficiently enhancing the heat dissipation performance, in a longitudinal sectional view as shown in the cross-sectional view of FIG. 17, the area of the first layer 42A (for example, a carbon layer) is preferably 10% or more with respect to the area of the wiring portion 42 (for example, the total area of the carbon layer and the metal layer).

[0065] To form the power ground layer 40, for example, in the same manner as in FIGS. 4 and 5, a substrate 11 having a groove 115 is fabricated as shown in FIG. 18, and the first layer 42A is formed in the groove 115 of the substrate 11 as shown in FIG. 19. Specifically, first, an insulating layer covering the bottom surface and the inner wall surface of the groove 115 is formed. Then, a barrier metal layer and a seed layer are sequentially formed so as to cover the insulating layer. Then, a solution containing carbon nanotubes, graphene flakes, etc. is poured into the bottom side in the groove 115, the solution adhering outside the groove 115 is wiped off, and then the solvent is evaporated. Thereby, the first layer 42A is formed.

[0066] Next, as shown in FIG. 20, a second layer 42B is formed on the first layer 42A within the groove 115. Specifically, an electrolytic plating layer made of copper or the like is formed on the seed layer so as to protrude from the upper surface of the substrate 11 by an electrolytic plating method that supplies power from the seed layer formed in the process of FIG. 19. Thereafter, the electrolytic plating layer protruding from the upper surface of the substrate 11 is removed by CMP or the like. The upper surface of the substrate 11 and the upper surface of the second layer 42B can be flush, for example. Thereafter, annealing is preferably performed under appropriate conditions for sintering. As described above, a power supply ground layer 40A having a wiring portion 42 in which the first layer 42A and the second layer 42B are sequentially laminated within the groove 115 of the substrate 11 and having a plurality of regions that become the power supply ground layer 40 when individualized is manufactured.

[0067] In the process shown in FIG. 19, a metal nanopaste may be mixed with a solution containing carbon nanotubes, graphene flakes, or the like. Examples of the metal nanopaste include copper nanopaste. Thereafter, when sintering is performed in the process of FIG. 20, for example, the copper particles in the copper nanopaste are sintered with the copper of the seed layer, and the contact resistance with the carbon material can be improved.

[0068] Also, a metal nanopaste may be used for forming the second layer 42B in the process shown in FIG. 20. Examples of the metal nanopaste include copper nanopaste. Since the second layer 42B formed from the metal nanopaste has a porous shape, it is possible to relieve the thermal stress of a metal such as copper. When the surface flatness is lost by sintering, plating or CMP may be added for the purpose of compensation.

[0069] <Modification Example 2 of the First Embodiment> Modification Example 2 of the first embodiment shows an example of a semiconductor device in which a connection wiring portion is disposed between the power supply ground layer and the semiconductor chip. In Modification Example 2 of the first embodiment, the description of the same components as those in the embodiments already described may be omitted.

[0070] FIG. 21 is a cross-sectional view illustrating a semiconductor device according to Modification 2 of the first embodiment. Referring to FIG. 21, a semiconductor device 1B according to Modification 2 of the first embodiment is different from the semiconductor device 1 (see FIG. 1 etc.) in that a connection wiring portion 50 is disposed between a power ground layer 10 and a semiconductor chip 301.

[0071] The connection wiring portion 50 includes an insulating layer 51 and a wiring layer 52. The insulating layer 51 is formed of, for example, a silicon oxide film, and the wiring layer 52 is formed of, for example, copper. The wiring layer 52 includes a wiring formed on the upper surface side of the insulating layer 51 and a through-wiring connected to this wiring and penetrating the insulating layer 51. The wiring layer 52 can be formed, for example, by a dual damascene method. A part of the through-wiring of the wiring layer 52 is electrically connected to the substrate 11 of the power ground layer 10, and the other part of the through-wiring is electrically connected to the wiring portion 12 of the power ground layer 10.

[0072] In FIG. 21, although the wiring layer 52 is depicted in a simplified manner, the wiring layer 52 has a higher density of wiring than the wiring of the wiring portion 12. For example, when the wiring width of the wiring portion 12 is about 20 μm, if the minimum wiring width of the wiring layer 52 is formed to be about 1 / 40 of that, even when it is difficult to directly connect the semiconductor chip 301 and the power ground layer 10, the two can be easily connected through the connection wiring portion 50. Note that the connection wiring portion 50 may have a multilayer wiring structure.

[0073] <Comparison with the Conventional Structure>

[0074]

Table 1

[0075] The semiconductor devices of the conventional structure 1 and the conventional structure 2 are structured such that the silicon substrate is processed from the back side, copper wiring is formed on the back side of the silicon substrate, and the lower surface of the copper wiring is exposed from the back of the silicon substrate. The specifications of the copper wiring are as shown in Table 1. That is, the semiconductor devices of the conventional structure 1 and the conventional structure 2 have a significantly thinner wiring thickness compared to the semiconductor devices of the first embodiment and the second embodiment, and do not have a portion corresponding to the bottom 111 of the semiconductor devices of the first embodiment and the second embodiment. Note that the insulating layer in Table 1 is an insulating layer formed between the silicon substrate and the wiring.

[0076] The semiconductor device of the first embodiment shown in Table 1 has the structure shown in FIG. 1 etc. Here, the material of the substrate 11 is silicon, the thickness of the substrate 11 is 200 μm, and the thickness of the bottom 111 is 20 μm. Also, the wiring portion 12 is only a copper layer, the wiring width and the wiring pitch of the wiring portion 12 are each 20 μm, and the wiring thickness is 180 μm. Also, the insulating layer thickness is 0.2 μm. Also, the volume of silicon is 60% or less with respect to the total volume of silicon and the wiring portion. Also, the total area of the end faces of the through electrodes connected to silicon or the wiring portion is 2% or more of the area of the back surface of the semiconductor chip.

[0077] The semiconductor device of the second embodiment shown in Table 1 has the structure shown in FIG. 17 etc. Here, the material of the substrate 11 is silicon, the thickness of the substrate 11 is 200 μm, and the thickness of the bottom 111 is 20 μm. Also, the wiring portion 12 is a copper layer and a carbon layer, the wiring width and the wiring pitch of the wiring portion 12 are each 20 μm, and the wiring thickness is 180 μm. Also, the insulating layer thickness is 0.2 μm. Also, the volume of silicon is 60% or less with respect to the total volume of silicon and the wiring portion. Also, the total area of the end faces of the through electrodes connected to silicon or the wiring portion is 2% or more of the area of the back surface of the semiconductor chip. Also, in a longitudinal sectional view as shown in the cross-sectional view of FIG. 17, the area of the carbon layer is 10% or more with respect to the total area of the carbon layer and the copper layer.

[0078]

Table 2

[0079] The in-plane temperature difference in Table 2 is calculated for the case where the semiconductor device of the conventional structure 1 has an in-plane temperature difference of 20°C, to find out the in-plane temperature differences of the semiconductor devices of the conventional structure 2, the first embodiment, and the second embodiment. The semiconductor device of the first embodiment can suppress the in-plane temperature difference to about half that of the semiconductor device of the conventional structure 1. That is, due to the effects of the thick copper wiring and the bottom left on the silicon, the in-plane temperature difference can be significantly suppressed. In the semiconductor device of the second embodiment, where the wiring portion has a copper layer and a carbon layer, the in-plane temperature difference can be suppressed to about half that of the semiconductor device of the first embodiment. That is, the effect of the wiring portion including the carbon layer is very large. When the in-plane temperature difference is about 10°C, if the semiconductor device is a DRAM, the time standard of the data retention time of the DRAM can be maintained, and no special measures such as changing the refresh cycle are required.

[0080] 〈Application Example of the First Embodiment〉 In the application example of the first embodiment, an example of a semiconductor device in which a plurality of stacked bodies in which a power ground layer and a semiconductor chip are stacked are thermally bonded is shown. In the application example of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0081] FIG. 22 is a perspective view illustrating a semiconductor device according to Application Example 1 of the first embodiment. Referring to FIG. 22, the semiconductor device 1C according to Application Example 1 of the first embodiment has a stacked body 601 in which a power ground layer 101 and a semiconductor chip 301 are stacked, and a stacked body 602 in which a power ground layer 102 and a semiconductor chip 302 are stacked.

[0082] In laminate 601, in a plan view, semiconductor chip 301 is larger than power supply ground layer 101, and a part of semiconductor chip 301 protrudes from the end of power supply ground layer 101. Also, in laminate 602, semiconductor chip 302 is larger than power supply ground layer 102, and a part of semiconductor chip 302 protrudes from the end of power supply ground layer 102.

[0083] Laminate 601 and laminate 602 are arranged such that power supply ground layer 101 and power supply ground layer 102 face opposite sides, and the protruding portion of semiconductor chip 301 and the protruding portion of semiconductor chip 302 are in contact. In the region where the protruding portion of semiconductor chip 301 and the protruding portion of semiconductor chip 302 are in contact, semiconductor chip 301 and semiconductor chip 302 are electrically connected. The connection between semiconductor chip 301 and semiconductor chip 302 may be face-to-face or face-to-back.

[0084] The semiconductor chip 301 of laminate 601 is, for example, a logic chip with a relatively low power supply voltage. Also, the semiconductor chip 302 of laminate 602 is, for example, a SRAM (Static RAM) chip with a relatively high power supply voltage.

[0085] In semiconductor device 1C, the area of the non-overlapping portion is larger than the area of the overlapping portion of semiconductor chip 301 and semiconductor chip 302, and a power supply ground layer is arranged in the non-overlapping portion. Therefore, it is possible to suppress the occurrence of a local high temperature portion (hot spot) in semiconductor device 1C and make the heat generation of the entire semiconductor device 1C uniform. Also, since the area of each power supply ground layer is increased, the problem of insufficient heat dissipation area is solved, and it is possible to efficiently dissipate heat from each power supply ground layer.

[0086] FIG. 23 is a plan view illustrating a semiconductor device according to Application Example 2 of the first embodiment. Referring to FIG. 23, semiconductor device 1D according to Application Example 2 of the first embodiment includes one laminate 603 in which five power supply ground layers 103 and semiconductor chip 303 are laminated, and four laminates 604 in which power supply ground layer 104 and semiconductor chip 304 are laminated.

[0087] As shown above the arrow in FIG. 23, in laminate 603, five power ground layers 103 are provided. One power ground layer 103 is laminated at the center of one surface of semiconductor chip 303, and the outer peripheral portion of one surface of semiconductor chip 303 is exposed around the power ground layer 103. At four corner portions of one surface of semiconductor chip 303 exposed from the power ground layer 103 arranged at the center, power ground layers 103 are respectively arranged so as to protrude from semiconductor chip 303.

[0088] Also, as shown above the arrow in FIG. 23, in laminate 604, in plan view, semiconductor chip 304 is larger than power ground layer 104, and a part of semiconductor chip 304 protrudes from the end of power ground layer 104. Four laminates 604 are prepared.

[0089] When the four laminates 604 are arranged as above the arrow in FIG. 23, turned upside down, and laminated on laminate 603, semiconductor device 1D shown below the arrow in FIG. 23 is obtained. In semiconductor device 1D, one surface of semiconductor chip 303 exposed from each power ground layer 103 and the protruding portions of semiconductor chips 304 in each laminate 604 are arranged to be in contact with each other. In the region where the exposed portion of semiconductor chip 303 and the protruding portions of each semiconductor chip 304 are in contact with each other, semiconductor chip 303 and each semiconductor chip 304 are electrically connected. The connection between semiconductor chip 303 and semiconductor chip 304 may be face-to-face or face-to-back.

[0090] The semiconductor chip 303 of laminate 603 is, for example, an MPU (Micro Processing Unit) chip or a GPU (Graphics Processing Unit) chip. Also, the semiconductor chip 304 of laminate 604 is, for example, an SRAM chip. That is, in semiconductor device 1D, for example, an MPU chip or a GPU chip is arranged at the center, and four SRAM chips are arranged around it. Conversely, an SRAM chip may be arranged at the center, and various processor chips may be arranged around it.

[0091] Even in the 1D semiconductor device, similar to the 1C semiconductor device, the area of the non-overlapping portion is larger than the area of the overlapping portion between the semiconductor chip 303 and the semiconductor chip 304, and a power ground layer is disposed in the non-overlapping portion. Therefore, it is possible to suppress the occurrence of a local high-temperature portion (hot spot) in the semiconductor device 1D and to equalize the heat generation of the entire semiconductor device 1D. Further, since the area of each power ground layer is increased, the insufficient heat dissipation area is eliminated, and it is possible to efficiently dissipate heat from each power ground layer.

[0092] FIG. 24 is a plan view illustrating a semiconductor device according to Application Example 3 of the first embodiment. Referring to FIG. 24, the semiconductor device 1E according to Application Example 3 of the first embodiment includes one laminate 605 in which a power ground layer 105 and a semiconductor chip 305 are laminated, and two laminates 606 in which a power ground layer 106 and a semiconductor chip 306 are laminated.

[0093] As shown above the arrow in FIG. 24, in the laminate 605, the power ground layer 105 is laminated at the central portion of one surface of the semiconductor chip 305, and both ends of one surface of the semiconductor chip 305 are exposed on both sides of the power ground layer 105.

[0094] Also, as shown above the arrow in FIG. 24, in the laminate 606, in a plan view, the semiconductor chip 306 is larger than the power ground layer 106, and a part of the semiconductor chip 306 protrudes from the end of the power ground layer 106. Two laminates 606 are provided.

[0095] When two laminates 606 are arranged as shown above the arrow in FIG. 24, turned upside down, and laminated on the laminate 605, the semiconductor device 1E shown below the arrow in FIG. 24 is obtained. In the semiconductor device 1E, one surface of the semiconductor chip 305 exposed from the power supply ground layer 105 is arranged to be in contact with the protruding portion of the semiconductor chip 306 in each laminate 606. In the region where the exposed portion of the semiconductor chip 305 is in contact with the protruding portion of each semiconductor chip 306, the semiconductor chip 305 and each semiconductor chip 306 are electrically connected. The connection between the semiconductor chip 305 and the semiconductor chip 306 may be face-to-face or face-to-back.

[0096] The semiconductor chip 305 of the laminate 605 is, for example, an MPU chip or a GPU chip. Also, the semiconductor chip 306 of the laminate 606 is, for example, an SRAM chip. That is, in the semiconductor device 1E, for example, an MPU chip or a GPU chip is arranged at the center, and two SRAM chips are arranged on both sides thereof. Conversely, an SRAM chip may be arranged at the center, and various processor chips may be arranged on both sides thereof.

[0097] In the semiconductor device 1E as well, similar to the semiconductor device 1C, the area of the non-overlapping portion of the semiconductor chip 305 and the semiconductor chip 306 is larger than the area of the overlapping portion, and a power supply ground layer is arranged in the non-overlapping portion. Therefore, it is possible to suppress the occurrence of a local high-temperature portion (hot spot) in the semiconductor device 1E and to equalize the heat generation of the entire semiconductor device 1E. Also, since the area of each power supply ground layer is increased, the problem of insufficient heat dissipation area is solved, and it is possible to efficiently dissipate heat from each power supply ground layer.

[0098] FIG. 25 is a plan view illustrating a semiconductor device according to Application Example 4 of the first embodiment. Referring to FIG. 25, the semiconductor device 1F according to Application Example 4 of the first embodiment includes one laminate 607 in which a power supply ground layer 107 and a semiconductor chip 307 are laminated, and four laminates 608 in which a power supply ground layer 108 and a semiconductor chip 308 are laminated.

[0099] As shown above the arrow in FIG. 25, in laminate 607, power ground layer 107 is laminated at the center of one surface of semiconductor chip 307, and the outer peripheral portion of one surface of semiconductor chip 307 is exposed around power ground layer 107.

[0100] Also, as shown above the arrow in FIG. 25, in laminate 608, in plan view, semiconductor chip 308 is larger than power ground layer 108, and a part of semiconductor chip 308 protrudes from the end of power ground layer 108. Four laminates 608 are prepared.

[0101] When the four laminates 608 are arranged as above the arrow in FIG. 25, turned upside down, and laminated on laminate 607, semiconductor device 1F shown below the arrow in FIG. 25 is obtained. In semiconductor device 1F, one surface of semiconductor chip 307 exposed from power ground layer 107 and the protruding portions of semiconductor chips 308 in each laminate 608 are arranged to be in contact. In the region where the exposed portion of semiconductor chip 307 and the protruding portions of each semiconductor chip 308 are in contact, semiconductor chip 307 and each semiconductor chip 308 are electrically connected. The connection between semiconductor chip 307 and semiconductor chip 308 may be face-to-face or face-to-back.

[0102] The semiconductor chip 307 of laminate 607 is, for example, an MPU chip or a GPU chip. Also, the semiconductor chip 308 of laminate 608 is, for example, an SRAM chip. That is, in semiconductor device 1F, for example, an MPU chip or a GPU chip is arranged at the center, and four SRAM chips are arranged around it. Conversely, an SRAM chip may be arranged at the center, and various processor chips may be arranged around it.

[0103] Even in the semiconductor device 1F, similar to the semiconductor device 1C, the area of the non-overlapping portion between the semiconductor chip 307 and the semiconductor chip 308 is larger than the area of the overlapping portion, and a power ground layer is disposed in the non-overlapping portion. Therefore, it is possible to suppress the occurrence of a local high-temperature portion (hot spot) in the semiconductor device 1F and to equalize the heat generation of the entire semiconductor device 1F. In addition, since the area of each power ground layer is increased, the shortage of the heat radiation area is eliminated, and it is possible to efficiently radiate heat from each power ground layer.

[0104] FIG. 26 is a plan view illustrating a semiconductor device according to Application Example 5 of the first embodiment. Referring to FIG. 26, a semiconductor device 1G according to Application Example 5 of the first embodiment includes one power ground layer 109, one semiconductor chip 309, and six semiconductor chips 30 10 and.

[0105] In the semiconductor device 1G, the power ground layer 109 has four systems of wiring portions insulated from each other. In this case, each system of wiring portions can be connected to power wirings of different systems of the semiconductor chip 309 and the semiconductor chip 30 10 .

[0106] The four wiring portions are arranged in two rows and two columns, and the semiconductor chip 309 is arranged across one surface of each of the two wiring portions arranged in the left column. Also, the six semiconductor chips 30 10 are arranged across one surface of each of the two wiring portions arranged in the right column.

[0107] In a plan view, since the semiconductor chip 309 and the six semiconductor chips 30 10 are smaller than the power ground layer 109, a part of the power ground layer 109 is exposed from the semiconductor chip 309 or the semiconductor chip 30 10 . The semiconductor chip 309 is, for example, a logic chip with a relatively low power supply voltage. Also, the semiconductor chip 30 10 is, for example, a SRAM chip with a relatively high power supply voltage.

[0108] Thus, the power ground layer may be larger than the semiconductor chip to be mounted in plan view. By adopting such a structure, the heat dissipation efficiency from the power ground layer can be improved. When the semiconductor device has a connection wiring portion 50 as shown in FIG. 21, the connection between different semiconductor chips may be made using the wiring of the connection wiring portion 50. In this case, the capacitance of the connection wiring is smaller than that when the connection between semiconductor chips is made through the wiring of the package or the silicon interposer, and there is an effect of reducing the power consumption of the entire device. Further, the portion of the power ground layer exposed from the semiconductor chip may be used as a contact for supplying power to the semiconductor device.

[0109] Note that, in the application example of the first embodiment, the semiconductor chips arranged on the power ground layer are not limited to one layer and may be a laminate. Alternatively, a laminate of semiconductor chips and a single layer of semiconductor chips may be mixed.

[0110] Although the preferred embodiments etc. have been described in detail above, the present invention is not limited to the above-described embodiments etc., and various modifications and substitutions can be made to the above-described embodiments etc. without departing from the scope described in the claims.

[0111] For example, in the above embodiment, the case where a semiconductor substrate (silicon wafer) having a circular shape in plan view is used has been described as an example, but the semiconductor substrate is not limited to a circular shape in plan view, and for example, a panel-shaped one such as a rectangular shape in plan view may be used.

Description of Reference Numerals

[0112] 1, 1A to 1G Semiconductor device 10, 10A, 101 to 109, 40, 40A Power ground layer 11 Substrate 12 Wiring portion 301 to 30 10 Semiconductor chip 30A, 30B Semiconductor device 30x Via hole 31 Substrate 32 Insulating layer 33 Wiring layer 34 Electrode pad 35 Insulating layer 36 Through electrode 42A First layer 42B Second layer 50 Connection wiring part 51 Insulating layer 52 Wiring layer 601 - 608 Laminated body 111 Bottom 112 Side wall part 113 Columnar part 115 Groove 125, 145 Opening 510 Support substrate 520 Adhesive layer

Claims

1. A power ground layer, and a semiconductor chip disposed on the power ground layer, wherein the power ground layer includes: a substrate having a groove that opens to the semiconductor chip side, and a wiring portion having a predetermined pattern disposed inside the groove via an insulating layer, the substrate is connected to the ground wiring of the semiconductor chip, the wiring portion is connected to the power wiring of the semiconductor chip, the substrate and the wiring portion are directly connected to a through electrode provided in the semiconductor chip, and the wiring portion is not exposed from the back surface of the substrate. A semiconductor device.

2. A power ground layer, and a semiconductor chip disposed on the power ground layer, wherein the power ground layer includes: a substrate having a groove that opens to the semiconductor chip side, and a wiring portion having a predetermined pattern disposed inside the groove via an insulating layer, the substrate is connected to the ground wiring of the semiconductor chip, the wiring portion is connected to the power wiring of the semiconductor chip, the wiring portion is not exposed from the back surface of the substrate, and the predetermined pattern is a mesh-shaped pattern in plan view. A semiconductor device.

3. A power ground layer, and a semiconductor chip disposed on the power ground layer, wherein the power ground layer includes: a substrate having a groove that opens to the semiconductor chip side, and a wiring portion having a predetermined pattern disposed inside the groove via an insulating layer, the substrate is connected to the ground wiring of the semiconductor chip, the wiring portion is connected to the power wiring of the semiconductor chip, the wiring portion is not exposed from the back surface of the substrate, the connection between the substrate and the ground wiring of the semiconductor chip and the connection between the wiring portion and the power wiring of the semiconductor chip are performed by a through electrode provided in the semiconductor chip, and the total area of the end faces of the through electrodes connected to the substrate or the wiring portion is 2% or more of the area of the back surface of the semiconductor chip. A semiconductor device.

4. A power ground layer, and a semiconductor chip disposed on the power ground layer, wherein the power ground layer includes: a substrate having a groove that opens to the semiconductor chip side, and a wiring portion having a predetermined pattern disposed inside the groove via an insulating layer, the substrate is connected to the ground wiring of the semiconductor chip, the wiring portion is connected to the power wiring of the semiconductor chip, the wiring portion is not exposed from the back surface of the substrate, and the substrate is formed of silicon. A semiconductor device in which the volume of the silicon is 60% or less of the total volume of the silicon and the wiring portion.

5. The substrate has a bottom portion, a side wall portion surrounding the bottom portion, and a plurality of columnar portions disposed apart from each other in a region surrounded by the side wall portion on the bottom portion. The semiconductor device according to claim 2, wherein each of the columnar portions is disposed within an opening of the mesh-like pattern.

6. The semiconductor device according to any one of claims 1 to 5, wherein a decoupling capacitor is formed between the substrate, the insulating layer, and the wiring portion.

7. The semiconductor device according to claim 4, wherein the wiring portion includes a metal layer.

8. The semiconductor device according to claim 7, wherein the metal layer is porous.

9. The semiconductor device according to claim 4, wherein the wiring portion includes a metal layer located on the semiconductor chip side and a carbon layer located under the metal layer.

10. The semiconductor device according to claim 9, wherein in a longitudinal cross-sectional view, the area of the carbon layer is 10% or more of the total area of the carbon layer and the metal layer.

11. The semiconductor device according to claim 9 or 10, wherein the carbon layer includes carbon nanotubes or graphene flakes, and the metal layer includes copper.

12. The semiconductor device according to any one of claims 1 to 11, wherein a connection wiring portion having a higher wiring density than the wiring of the wiring portion is disposed between the power ground layer and the semiconductor chip.

13. In a plan view, a plurality of semiconductor chips are disposed at different positions on the power ground layer. A connection wiring portion having a higher wiring density than the wiring of the wiring portion is disposed between the power ground layer and each of the semiconductor chips. The semiconductor device according to any one of claims 1 to 11, wherein each of the semiconductor chips is connected by the connection wiring portion.

14. The wiring portion is divided into a plurality of systems insulated from each other in a plan view. The semiconductor device according to any one of claims 1 to 13, wherein the wiring portion of each system is connected to a power supply wiring of a different system of the semiconductor chip.

15. The semiconductor device according to any one of claims 1 to 14, wherein the power ground layer is larger than the semiconductor chip in a plan view.

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