Common adjustment circuit

Abstract

This common adjustment circuit (10) comprises: a first comparator (151) that compares a reference voltage with the voltage between a first transistor (111) and a first resistor (121), and outputs the result; a current mirror circuit (161) that includes a second transistor (112) that passes an input current, and a third transistor (113) that passes an output current; a replica circuit (20) that mimics a differential amplifier; and a second comparator (19) in which one input is connected to the connection node between the third transistor (113) and a second resistor (122), and the other input is connected to the replica output node of the replica circuit (20), the second comparator (19) comparing the two inputs and outputting a bias voltage.

Description

Technical Field

[0001] The present invention relates to a common adjustment circuit for adjusting an output common voltage in a differential amplifier.

Background Art

[0002] A differential amplifier is a circuit that amplifies and outputs two input signals with a certain differential gain, and is used, for example, in a high-speed serial interface that performs high-speed operation.

[0003] In recent years, in semiconductor integrated circuits, the miniaturization of the manufacturing process has advanced, and circuit design for stable operation has become difficult due to the accompanying reduction in power supply voltage.

[0004] In a differential amplifier, it is important to stabilize the output voltage (output common voltage) at the output terminal when the voltage difference at the differential input terminals is 0, and the potential difference (voltage head room) between the power supply voltage and the output common voltage. For example, when the output common voltage is unstable, the voltage head room becomes insufficient, and problems such as unstable circuit operation occur.

[0005] Therefore, a common adjustment circuit for stabilizing the output common voltage is used. For example, Patent Document 1 shows a common adjustment circuit using a replica circuit and a comparator.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In Patent Document 1, regarding the method of generating the reference voltage of a comparator in a common adjustment circuit, a configuration by resistance division and a configuration using a resistor and a constant current source are disclosed. However, when variations in elements occur due to the manufacturing process, in the configuration as shown in Patent Document 1 above, sufficient voltage headroom cannot be ensured, and there is a risk that the operation may become unstable. Specifically, for example, when process variations or fluctuations in the power supply voltage occur, if a deviation occurs in the above reference voltage, the voltage headroom may become small.

[0008] In particular, in a circuit such as a high-speed serial interface where performance in a high-speed operating environment is required, the effects of noise and fluctuations in the output common voltage caused by deviations in the reference voltage are likely to occur, and the effects of insufficient voltage headroom become more prominent.

[0009] The present disclosure aims to solve the above problems and provide a common adjustment circuit that acts so that the voltage headroom of the differential amplifier does not vary even in the presence of process variations or power supply voltage fluctuations.

Means for Solving the Problems

[0010] A common adjustment circuit according to one aspect of the present disclosure relates to a common adjustment circuit that outputs a first bias voltage for applying to the gate of an output load transistor of a differential amplifier. The common adjustment circuit includes a first comparator having one input connected to a reference voltage, the other input connected to a first node, and comparing and outputting the two inputs; a first transistor having a gate connected to the output of the first comparator, a source connected to the first node, and a drain connected to a second node; a first resistor having one terminal connected to the first node and the other terminal connected to a first power supply; a current mirror circuit including a second transistor having a gate and a drain connected to the second node and passing an input current, and a third transistor having a gate connected to the second node and passing an output current; a second resistor having one terminal connected to the source of the third transistor via a third node; a second comparator having one input connected to the third node, the other input connected to a fourth node, and comparing and outputting the two inputs to output the bias voltage; and a replica circuit including a replica transistor corresponding to the output load transistor of the differential amplifier, the gate of the replica transistor being connected to the output of the second comparator, and a replica output node corresponding to the output node of the differential amplifier being connected to the fourth node.

[0011] A common adjustment circuit according to another aspect of the present disclosure relates to a common adjustment circuit that outputs a first bias voltage for applying to the gate of an output load transistor of a differential amplifier. The common adjustment circuit includes a first comparator having one input connected to a reference voltage, the other input connected to a first node, and comparing and outputting the two inputs; a first transistor having a gate connected to the output of the first comparator, a source connected to the first node, and a drain connected to a second node; a first resistor having one terminal connected to the first node and the other terminal connected to a first power supply; a second resistor having one terminal connected to the second node and the other terminal connected to a second power supply having a potential different from that of the first power supply; a second comparator having one input connected to the third node, the other input connected to a fourth node, and comparing the two inputs and outputting the bias voltage; and a replica circuit including a replica transistor corresponding to the output load transistor of the differential amplifier, the gate of the replica transistor being connected to the output of the second comparator, and a replica output node corresponding to the output node of the differential amplifier being connected to the fourth node.

Effects of the Invention

[0012] In the present disclosure, a common adjustment circuit can be provided that acts so that the voltage headroom of a differential amplifier does not vary even in the presence of process variations and power supply voltage fluctuations.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described with reference to the drawings. Note that the specific numerical values and the like shown in the following embodiments are merely examples for facilitating the understanding of the invention and are not intended to limit the scope of the invention.

[0015] The common adjustment circuit is a circuit aimed at stabilizing the output common voltage of the differential amplifier by applying a bias voltage to the gate of the output load transistor of the differential amplifier described later. In other words, the common adjustment circuit is a circuit that generates a bias voltage for obtaining a predetermined output common voltage in the differential amplifier and supplies it to the gate of the output load transistor of the differential amplifier. The output common voltage is, as described above, the output voltage at the output terminal when the voltage difference between the differential input terminals is 0.

[0016] The common adjustment circuit according to the present disclosure is configured to act so that the voltage headroom of the differential amplifier does not vary even in the presence of process variations and power supply voltage fluctuations. In the following description, first, the voltage headroom of the differential amplifier will be described, and then a specific circuit example will be shown to describe the common adjustment circuit of the present disclosure.

[0017] -Voltage Headroom- First, the voltage headroom will be described.

[0018] (Differential Amplifier) FIG. 2 shows an example of a differential amplifier 50 to which the common adjustment circuit 10 of the present disclosure is connected.

[0019] The differential amplifier 50 amplifies the differential input signal Vi (Vip, Vin) input from the pair of input terminals 501 and 502, and outputs it as a differential output signal Vo (Vop, Von) from the pair of output terminals 503 and 504. In the following description, the same reference numerals may be used for the signal names and the voltage values of the signals. Also, for the power supply VDD described later, the same reference numerals may be used for the name and the voltage value.

[0020] The differential amplifier 50 includes a pair of differential transistors (N-type transistors 511 and 512), a pair of output load circuits 560 and 570, and an N-type transistor 515 that operates as a tail current source.

[0021] The N-type transistor 511 has its gate connected to the input terminal 501, its source connected to the drain of the transistor 515, and its drain connected to one of the output load circuits 560 and one of the output terminals 504, respectively. The N-type transistor 512 has its gate connected to the input terminal 502, its source connected to the drain of the transistor 515, and its drain connected to the other output load circuit 570 and the other output terminal 503, respectively. The transistor 511 and the transistor 512 are configured to have the same electrical characteristics. Also, the output load circuit 560 and the output load circuit 570 are configured to have the same electrical characteristics.

[0022] The output load circuit 560 includes P-type transistors 561 and 562 provided in parallel between the power supply VDD and the output terminal 504 The drains of the transistors 561 and 562 are connected to the output terminal 504 via the node 581. The gate of the transistor 562 is connected to the node 581. A bias voltage Vpc output from the second comparator 19 is applied to the gate of the transistor 561 via the input terminal 506.

[0023] The output load circuit 570 is between the power supply VDD and the output terminal 503It includes P-type transistors 571 and 572 provided in parallel therewith. The drains of transistors 571 and 572 are connected to the output terminal 503 via the node 582. The gate of transistor 572 is connected to the node 582. A bias voltage Vpc is applied to the gate of transistor 571 via the input terminal 506.

[0024] A bias voltage Vb is applied to the gate of transistor 515 via the input terminal 505. By applying a voltage equal to or higher than the threshold voltage of transistor 515 as the bias voltage Vb to the gate of transistor 515, transistor 515 operates as a constant current source (hereinafter referred to as a tail current source).

[0025] Figure 3 takes the difference between the input signal Vip and the input signal Vin, "Vip - Vin", on the horizontal axis and shows the changes in the respective output signals Vop and Von. Figure 4(a) shows the change of the differential input signal Vi over time, and Figure 4(b) shows the change of the differential output signal Vo over time.

[0026] In Figure 3, the output common voltage Vcm of the differential output signal Vo is represented by the following equation (1).

[0027]

Equation

[0028] Here, VDD is the power supply voltage of the differential amplifier 50, Rd is the combined impedance of the output load circuit 560 or the combined impedance of the output load circuit 570, and Is is the current flowing through the tail current source (transistor 515). From the above equation (1), it can be seen that the output common voltage Vcm of the differential amplifier 50 is determined by the voltage drop of the current Is flowing from the power supply voltage VDD and the combined impedance Rd of the output load 560 (570).

[0029] Further, the relationship between the fluctuation component vin of the differential input signal Vi (obtained by removing the DC component of the input signal from the voltage of the differential input signal Vi) and the fluctuation component vout of the differential output signal Vo (obtained by removing the output common voltage Vcm from the voltage value of the differential output signal Vo) is represented by the following formula (2).

[0030]

Number

[0031] Here, gm is the transconductance of the differential pair transistors (N-type transistors 511 and 512).

[0032] Also, the voltage headroom Vh of the differential amplifier 50 is represented by the following formula (3).

[0033]

Number

[0034] As shown in the above formula (3), the voltage headroom Vh is the potential difference between the power supply voltage and the output common voltage Vcm, and is the margin of the voltage amplitude that can extract the signal without distortion as the differential output signal Vo. Therefore, when the voltage headroom Vh becomes small and a sufficient voltage amplitude margin cannot be ensured, problems such as distortion of the differential output signal Vo occur. For example, when the differential amplifier 50 is used in a high-speed interface, there is a risk that the signal quality cannot be sufficiently ensured with respect to the standard, and the common adjustment circuit of the present disclosure is made to solve this problem.

[0035] <First Embodiment> -Common Adjustment Circuit- Hereinafter, the common adjustment circuit according to this embodiment will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of the common adjustment circuit according to the first embodiment.

[0036] As shown in FIG. 1, the common adjustment circuit 10 includes a reference voltage generation circuit 11 for generating a reference voltage Vrf, a second comparator 19, and a replica circuit 20.

[0037] -Reference Voltage Generation Circuit- The reference voltage generation circuit 11 includes a first comparator 151, a first transistor 111, a first resistor 121, a second resistor 122, and a current mirror circuit 161.

[0038] The first comparator 151 has a reference voltage Vid applied to one input via an input terminal 101 and the source of an N-type first transistor 111 connected to the other input via a first node 181. The first comparator 151 compares the reference voltage Vid with the source voltage of the first transistor 111 and outputs the comparison result to the gate of the first transistor 111. As a result, the voltage of the first node 181 is adjusted to the reference voltage Vid.

[0039] The reference voltage Vid is supplied from a circuit that reduces voltage fluctuations due to variations in the manufacturing process, changes in the operating environment such as power supply voltage fluctuations and temperature fluctuations. The reference voltage Vid is supplied, for example, from a conventionally known bandgap reference circuit.

[0040] The first resistor 121 is provided between the first node 181 and the ground VSS (corresponding to the first power supply). As a result, a current I1 shown in the following equation (4) flows through the first transistor 111.

[0041]

Equation

[0042] Here, R1 is the resistance value of the first resistor 121.

[0043] The current mirror circuit 161 includes a P-type second transistor 112 that conducts the above-described current I1 (hereinafter referred to as the input current I1) as an input current, and a P-type third transistor 113 that conducts an output current I2. The output current I2 can be adjusted, for example, by changing the ratio of the sizes of the second transistor 112 and the third transistor 113, or by changing the reference voltage Vid or the resistance value R1 of the first resistor 121.

[0044] The gate and drain of the second transistor 112 are connected to the drain of the first transistor 111 via the second node 182. The source of the second transistor 112 is connected to the power supply VDD (corresponding to the second power supply) via the third resistor 123.

[0045] The gate of the third transistor 113 is connected to the second node 182. That is, the gates of the second transistor 112 and the third transistor 113 are connected to each other. The drain of the third transistor 113 is connected to the ground VSS. The source of the third transistor 113 is connected to the power supply VDD via the second resistor 122. For the sake of convenience of explanation, the node connecting the source of the third transistor 113 and the second resistor 122 is referred to as the "third node 183". The third node 183 is connected to one input of the second comparator 19. Thereby, a reference voltage Vrf shown in the following formula (5) is applied to one input of the second comparator 19.

[0046]

Equation

[0047] Here, R2 is the resistance value of the second resistor 122.

[0048] -Second Comparator- The second comparator 19 has the reference voltage Vrf applied to one input as described above, and the output node 282 (corresponding to the replica output node) of the replica circuit 20 connected to the other input. The second comparator 19 compares the reference voltage Vrf with the output of the replica circuit 20 and outputs the comparison result to node 281. Connected to node 281 are the output terminal 102 and the gate of the replica transistor 261 of the replica circuit 20 described later.

[0049] - Replica Circuit - The replica circuit 20 is a circuit configured to mimic the circuit configuration of the differential amplifier 50 to which the common adjustment circuit 10 is connected. That is, the replica circuit 20 is a circuit whose configuration changes with the differential amplifier 50 to which the common adjustment circuit 10 is connected. FIG. 1 shows the replica circuit 20 in the case where the common adjustment circuit 10 is connected to the differential amplifier 50 shown in FIG. 2 described above.

[0050] The replica circuit 20 includes a replica load circuit 260 that mimics the output load circuit 560, and a replica current source 215 that mimics the transistor 515 operating as a tail current source. The replica load circuit 260 is configured to have the same electrical characteristics as the output load circuit 560. The replica current source 215 is configured such that a current that is half of the current flowing through the transistor 515 flows through it.

[0051] The replica load circuit 260 includes P-type replica transistors 261 and 262 provided in parallel between the power supply VDD and the output node 282. The gate of the replica transistor 261 is connected to the output of the second comparator 19 via the node 281. That is, the same voltage as the gate of the transistor 561 of the output load circuit 560 is applied to the gate of the replica transistor 261. The drains of the replica transistor 261 and the replica transistor 262 are connected to the other input of the second comparator 19 via the output node 282. The gate of the replica transistor 262 is connected to the output node 282. The replica transistor 261 is configured to have the same electrical characteristics as the transistor 561, and the replica transistor 262 is configured to have the same electrical characteristics as the transistor 562.

[0052] Thereby, the voltage of the output node 282 of the replica circuit 20 is adjusted to the reference voltage Vrf. The output node 282 of the replica circuit 20 corresponds to the output nodes connected to the output terminals 503 and 504 of the differential amplifier 50. Then, the output common voltage Vcm at the output terminals 503 and 504 of the differential amplifier 50 is adjusted to the reference voltage Vrf.

[0053] Therefore, the output common voltage Vcm of the differential amplifier 50 is expressed by the following formula (6) from the above formula (5), and the voltage headroom Vh of the differential amplifier 50 is expressed by the following formula (7) from formula (6) and formula (3).

[0054]

Equation

[0055]

Equation

[0056] As shown in the above formula (7), in the common adjustment circuit 10 of the present embodiment, the voltage headroom Vh does not depend on the power supply VDD, and depends only on the resistance ratio between the first resistor 121 and the second resistor 122, and the current ratio between the input current I1 and the output current I2. Generally, the process variations of the resistance elements in the same circuit have the same tendency. Therefore, the resistance ratio between the first resistor 121 and the second resistor 122 is substantially not affected by manufacturing variations. Further, the current mirror circuit 161 is configured so as to be substantially not affected even when there are variations in the power supply voltage or temperature changes such as the ambient temperature, and is a circuit capable of obtaining a highly accurate I2 / I1. Similarly, the reference voltage Vid can also be made substantially not affected by variations in the power supply voltage or the like. Therefore, the common adjustment circuit 10 acts so that the voltage headroom Vh of the differential amplifier 50 does not vary even in the presence of process variations or power supply voltage fluctuations, and the problems of the prior art are solved. Specifically, it will be described in the following "Comparative Example".

[0057] Furthermore, the common adjustment circuit 10 of the present embodiment can easily change the voltage headroom Vh by changing the mirror ratio I2 / I1 of the current mirror circuit 161 and the resistance ratio R2 / R1.

[0058] <Comparative Example 1> In Comparative Example 1, as shown in FIG. 10 of Patent Document 1, a common voltage generation circuit is configured such that a load element (resistance value Rx) and a constant current source (current value Ix) are provided in series between the power supply voltage and the ground potential, and the output thereof is output to a differential amplifier via a comparator. Then, the reference voltage Vx input to the comparator corresponding to the second comparator 19 of the present disclosure and the voltage headroom Vhx of the differential amplifier at the connection destination are expressed by the following formulas (8) and (9).

[0059]

Equation

[0060]

Equation

[0061] In the case of the configuration of Comparative Example 1, since the resistance value Rx of the load element varies due to variations in the manufacturing process, the voltage headroom Vhx of the differential amplifier at the connection destination varies due to this variation, and the operation of the circuit may become unstable. The same applies when a transistor element is used as a resistor instead of the resistance element, but since it is affected by variations in the manufacturing process, the configuration of the present embodiment is not affected by such Manufacturing variations of resistive elements and transistor elements influences.

[0062] <Comparative Example 2> In Comparative Example 2, as shown in FIG. 11 of Patent Document 1, the common voltage generation circuit is configured by a resistance voltage division circuit of a resistance ratio Ry1 / Ry2, and its output is output to the differential amplifier via a comparator. Then, the reference voltage Vy input to the comparator corresponding to the second comparator 19 of the present disclosure and the voltage headroom Vhy of the differential amplifier at the connection destination are expressed by the following formulas (10) and (11).

[0063]

Equation

[0064]

Equation

[0065] As shown in formula (11), in the case of the configuration of Comparative Example 2, when the power supply voltage VDD varies, the voltage headroom Vhy of the differential amplifier at the connection destination varies, and the operation of the circuit may become unstable. However, the configuration of the present embodiment is not affected by such Power supply voltage fluctuations influences.

[0066] <Modification Example 1 of the First Embodiment> FIG. 5 is a circuit diagram showing a configuration of a differential amplifier circuit including a common adjustment circuit 10 and a differential amplifier 60 according to Modification 1 of the first embodiment. In the following description, the description will focus on the differences from the above-described first embodiment (FIGS. 1 and 2), and the description of the common configuration may be omitted.

[0067] In the common adjustment circuit 10 of FIG. 5, the current mirror circuit 161 is a cascode type circuit. Specifically, in this modification, a fourth transistor 114 is provided between the second transistor 112 and the first transistor 111, and a fifth transistor 115 is provided between the third transistor 113 and the ground VSS. That is, the fourth transistor 114 and the fifth transistor 115 are cascode-connected to the second transistor 112 and the third transistor 113. Thereby, the accuracy of the mirror ratio of the current mirror circuit 161 is further improved, and the accuracy of the reference voltage Vrf (output common voltage Vcm) and the voltage headroom Vh can be further improved.

[0068] FIG. 5 shows an example in which the configuration of the differential amplifier 60 is different, and thereby the configuration of the replica circuit 20 is different from that in FIG. 1. The differential amplifier in FIG. 5 is used, for example, as a continuous-time linear equalizer for the front end of a high-speed interface.

[0069] In FIG. 5, the differential amplifier circuit includes a plurality of differential amplifiers 60 having the same configuration and electrical characteristics. Each differential amplifier 60 amplifies the differential input signal Vi input from the pair of input terminals 601 and 602 and outputs it as a differential output signal Vo from the pair of output terminals 603 and 604.

[0070] The differential amplifier 60 includes a differential pair of transistors (N-type transistors 611, 612), paired output load circuits 640, 650, a source load 660, and tail current sources 665, 666. The source of transistor 611 is connected to ground VSS via tail current source 665, and the source of transistor 612 is connected to ground VSS via tail current source 666. The source load 660 has a configuration in which a resistor 661 and a capacitor 662 are connected in parallel between the sources of transistor 611 and transistor 612. In the differential amplifier 60, transistor 611 and transistor 612, and output load circuit 640 and output load circuit 650 are each configured to have the same electrical characteristics. Also, tail current source 665 and tail current source 666 are configured to supply the same current.

[0071] The output load circuit 640 corresponds to the output load circuit 560 in FIG. 2 and is different from FIG. 2 in that it is a parallel circuit of a P-type transistor 641 and a resistor 642. Also, in FIG. 5, a resistor 621 and a peaking inductor 631 connected in series are provided between the output load circuit 640 and the output terminal 603. The output load circuit 650 corresponds to the output load circuit 570 in FIG. 2 and is different from FIG. 2 in that it is a parallel circuit of a P-type transistor 651 and a resistor 652. Also, in FIG. 5, a resistor 622 and a peaking inductor 632 connected in series are provided between the output load circuit 650 and the output terminal 604. The P-type transistor 641 and the P-type transistor 651 are configured to have the same electrical characteristics, and the resistor 642 and the resistor 652 are configured to have the same electrical characteristics. Furthermore, the resistor 621 and the resistor 622 are configured to have the same electrical characteristics, and the peaking inductor 631 and the peaking inductor 632 are configured to have the same electrical characteristics.

[0072] In FIG. 5, the replica circuit 20 is different from FIG. 1 in that it is configured to imitate the circuit configuration of the differential amplifier 60. The replica circuit 20 includes a replica load circuit 340 imitating the output load circuit 640, a replica resistor 321 imitating the resistor 621, a replica inductor 331 imitating the peaking inductor 631, and a replica current source 365 imitating the tail current source 665. The replica load circuit 340 is a parallel circuit of a replica transistor 341 imitating the P-type transistor 641 and a replica resistor 342 imitating the resistor 642. The replica load circuit 340 is configured to have the same electrical characteristics as the output load circuit 640, that is, the replica transistor 341 has the same electrical characteristics as the transistor 641, and the replica resistor 342 has the same electrical characteristics as the resistor 642. The replica current source 365 is configured to have the same current flowing through it as the current flowing through the current source 665.

[0073] With such a configuration, similar to the embodiment, the output common voltage Vcm of the differential amplifier 60 is represented by the aforementioned formula (6), and the voltage headroom Vh of the differential amplifier 60 is represented by the aforementioned formula (7). That is, by using the common adjustment circuit 10 of this modified example, the voltage headroom Vh of the differential amplifier 60 does not depend on the power supply VDD, but only depends on the resistance ratio of the first resistor 121 and the second resistor 122, and the current ratio of the input current I1 and the output current I2. Thereby, the common adjustment circuit 10 acts so that the voltage headroom Vh of the differential amplifier 60 does not fluctuate even with process variations and power supply voltage fluctuations, and the problems of the prior art are solved. Also, the voltage headroom Vh can be easily changed.

[0074] Furthermore, in the differential amplifier circuit according to this modification example, a plurality of differential amplifiers 60 with the same configuration of the output load circuit 640 are provided, and a bias voltage Vpc is supplied from a common adjustment circuit 10 common to them. Thereby, while suppressing an increase in area, for a plurality of differential amplifiers 60, it is possible to act so that the voltage headroom Vh of the differential amplifier 60 does not fluctuate even in the case of process variations or power supply voltage fluctuations. Although not shown, for example, since a high gain can be obtained by cascading a plurality of stages of differential amplifiers 60, the configuration of this modification example can be preferably used in such a case.

[0075] <Modification Example 2 of the First Embodiment> FIG. 6 is a circuit diagram showing a configuration of a differential amplifier circuit including a common adjustment circuit 10 and differential amplifiers 60 and 70 according to Modification Example 2 of the first embodiment. In the following description, the description will focus on the differences from the aforementioned Modification Example 1 (FIG. 5), and the description of the common configuration may be omitted.

[0076] The differential amplifier circuit in FIG. 6 includes a plurality of differential amplifiers 60 and 70 having different configurations from each other. Here, for the sake of convenience, two differential amplifiers 60 and 70 are exemplified. One differential amplifier 60 has the same configuration as that of Modification Example 1, but the number of differential amplifiers is not limited to two, and a combination of differential amplifiers different from FIG. 6 may be used.

[0077] In FIG. 6, as a comparator corresponding to the second comparator 19 in FIG. 5, it includes a third comparator 191 provided corresponding to the first replica circuit 201 and a third comparator 192 provided corresponding to the first replica circuit 202.

[0078] The third comparator 191 has one input connected to the third node 183 to which the reference voltage Vrf is applied, and the other input connected to the output node 282 (corresponding to the replica output node) of the first replica circuit 201. The third comparator 191 compares the reference voltage Vrf with the output of the first replica circuit 201 and outputs the comparison result (bias voltage Vpc1) to the node 281. Connected to the node 281 are the output terminal 102 and the gate of the replica transistor 341 of the first replica circuit 201 described later. The output terminal 102 is connected to the input terminal 605 of the differential amplifier 60. The third comparator 191 applies the bias voltage Vpc1 to the gates of the transistors 641 and 651 described later.

[0079] The third comparator 192 has one input connected to the third node 183 to which the reference voltage Vrf is applied, and the other input connected to the output node 284 (corresponding to the replica output node) of the first replica circuit 202. The third comparator 192 compares the reference voltage Vrf with the output of the first replica circuit 202 and outputs the comparison result (bias voltage Vpc2) to the node 283. Connected to the node 283 are the output terminal 103 and the gate of the replica transistor 441 of the first replica circuit 202 described later. The output terminal 103 is connected to the input terminal 705 of the differential amplifier 70. The third comparator 192 applies the bias voltage Vpc2 to the gates of the transistors 741 and 751 of the differential amplifier 70.

[0080] The differential amplifier 70 amplifies the differential input signal Vi input from the paired input terminals 701 and 702, and outputs it as the differential output signal Vo from the paired output terminals 703 and 704. The circuit configuration of the differential amplifier 70 is such that the peaking inductors 631 and 632 are omitted from the differential amplifier 60. In FIG. 6, in the differential amplifier 60 and the differential amplifier 70, the lower two digits of the symbols correspond to the same configurations, and the detailed description thereof is omitted here. In the differential amplifier 70, the transistor 711, the transistor 712, the output load circuit 740, the output load circuit 750, the resistor 721, and the resistor 722 are each configured to have the same electrical characteristics. Also, the tail current source 765 and the tail current source 766 are configured to supply the same current.

[0081] In FIG. 6, the replica circuit 20 includes a first replica circuit 201 configured by mimicking the circuit configuration of the differential amplifier 60, and a first replica circuit 202 configured by mimicking the circuit configuration of the differential amplifier 70.

[0082] The first replica circuit 201 has the same configuration as the replica circuit 20 in FIG. 5. The first replica circuit 202 includes a replica load circuit 440 mimicking the output load circuit 740, a replica resistor 421 mimicking the resistor 721, and a replica current source 465 mimicking the tail current source 765.

[0083] The replica load circuit 440 is a parallel circuit of a replica transistor 441 mimicking the P-type transistor 741 and a replica resistor 442 mimicking the resistor 742. The replica load circuit 440 is configured to have the same electrical characteristics as the output load circuit 740, that is, the replica transistor 441 has the same electrical characteristics as the transistor 741, and the replica resistor 442 has the same electrical characteristics as the resistor 742. Further, the replica resistor 421 is configured to have the same electrical characteristics as the resistor 721. The replica current source 465 is configured such that the same current flows as the current flowing through the tail current source 765.

[0084] By adopting such a configuration, similar to the embodiment, the output common voltage Vcm of the differential amplifier 60 and the output common voltage Vcm of the differential amplifier 70 are each represented by the aforementioned formula (6). Also, the voltage headroom Vh of the differential amplifier 60 and the voltage headroom Vh of the differential amplifier 70 are each represented by the aforementioned formula (7).

[0085] That is, by using the common adjustment circuit 10 of this modified example, the voltage headroom Vh of the differential amplifier 60 is independent of the power supply VDD and depends only on the resistance ratio between the first resistor 121 and the second resistor 122 and the current ratio between the input current I1 and the output current I2. Thereby, the common adjustment circuit 10 acts so that the voltage headroom Vh of the differential amplifier 60 does not vary even with process variations or power supply voltage fluctuations, and the problems of the prior art are solved. Also, the voltage headroom Vh can be easily changed. The same applies to the differential amplifier 70.

[0086] Furthermore, in this modified example, even when there are a plurality of types of differential amplifiers 60 and 70 having different configurations, bias voltages Vpc1 and Vpc2 can be supplied so that the voltage headroom Vh does not vary for each of the differential amplifiers 60 and 70 while suppressing the increase in the circuit.

[0087] <Modification Example 3 of the First Embodiment> FIG. 7 is a circuit diagram showing the configuration of a differential amplifier circuit including the common adjustment circuit 10 according to Modification Example 3 of the first embodiment and differential amplifiers 50 and 80. In the following description, the description will focus on the differences from the aforementioned first embodiment (FIGS. 1 and 2), and the description of the common configurations may be omitted. The configuration of the differential amplifier 50 and the corresponding common adjustment circuit 10 is the same as that in FIG. 1, and here, the configuration of the differential amplifier 80 and the corresponding common adjustment circuit 10 will be described.

[0088] In FIG. 7, the gate of the sixth transistor 116 is connected to the second node 182, and the gates of the second transistor 112 and the sixth transistor 116 are connected to each other. As a result, an output current I3 flows through the sixth transistor 116. The output current I3 can be adjusted, for example, by changing the size ratio of the second transistor 112 and the sixth transistor 116, or by changing the reference voltage Vid or the resistance value R1 of the first resistor 121.

[0089] The drain of the sixth transistor 116 is connected to the ground VSS. The source of the sixth transistor 116 is connected to the power supply VDD via the fourth resistor 124. For convenience of explanation, the node connecting the source of the sixth transistor 116 and the fourth resistor 124 is referred to as the "fifth node 185". The fifth node 185 is connected to one input of the third comparator 193. As a result, a reference voltage Vrf2 shown in the following formula (12) is applied to one input of the third comparator 193.

[0090]

Equation

[0091] Here, R4 is the resistance value of the fourth resistor 124.

[0092] As described above, the third comparator 193 has a reference voltage Vrf2 applied to one input and the output node 286 (corresponding to the replica output node) of the second replica circuit 203 connected to the other input. The third comparator 193 compares the reference voltage Vrf2 with the output of the second replica circuit 203 and outputs the comparison result to the node 285. The output terminal 104 and the gate of the replica transistor 271 of the second replica circuit 203 described later are connected to the node 285. The output terminal 104 is connected to the input terminal 806 of the differential amplifier 80. The third comparator 193 applies a bias voltage Vpc3 to the gates of the transistors 861 and 871 of the differential amplifier 80.

[0093] The differential amplifier 80 amplifies the differential input signal Vi2 (Vip2, Vin2) input from the paired input terminals 801 and 802, and outputs it as a differential output signal Vo2 (Vop2, Von2) from the paired output terminals 803 and 804. The circuit configuration of the differential amplifier 80 is different in that, in addition to the differential amplifier 50, a series circuit in which a resistor 821, a switch 822, and a resistor 823 are connected in series is connected between the output terminal 803 and the output terminal 804. Also, a variable current source 866 is connected as a tail current source. By adding such a configuration, the gain can be changed without changing the common voltage Vcm, and the output amplitude can be changed without relying on the common adjustment circuit 10. In FIG. 7, in the differential amplifier 50 and the differential amplifier 80, the configurations with the same last two digits of the symbols correspond to each other, and the description of the corresponding configurations may be omitted here. In the differential amplifier 80, the transistor 811, the transistor 812, the output load circuit 860, the output load circuit 870, the resistor 821, and the resistor 823 are configured to have the same electrical characteristics, respectively.

[0094] In FIG. 7, the second replica circuit 203 includes a replica load circuit 270 modeled after the output load circuit 860 and a replica current source 276 modeled after the variable current source 866. The replica load circuit 270 is a parallel circuit of a replica transistor 271 modeled after the P-type transistor 861 and a replica transistor 272 modeled after the P-type transistor 862. The replica load circuit 270 is configured to have the same electrical characteristics as the output load circuit 860, that is, the replica transistor 271 has the same electrical characteristics as the transistor 861, and the replica transistor 272 has the same electrical characteristics as the transistor 862. The replica current source 276 is configured such that a current that is half of the current flowing through the variable current source 866 flows through it.

[0095] With such a configuration, similar to the foregoing embodiment, the output common voltage Vcm of the differential amplifier 80 is represented by the following equation (13). Also, the voltage headroom Vh of the differential amplifier 80 is represented by the foregoing equation (14).

[0096]

Number

[0097]

Number

[0098] As shown in the above formula (14), by using the common adjustment circuit 10 of this modification example, the voltage headroom Vh of the differential amplifier 80 does not depend on the power supply VDD, and depends only on the resistance ratio between the first resistor 121 and the fourth resistor 124, and the current ratio between the input current I1 and the output current I3. Thereby, the common adjustment circuit 10 acts so that the voltage headroom Vh of the differential amplifier 80 does not fluctuate even in the presence of process variations and power supply voltage fluctuations, and the problems of the prior art are solved. In addition, the voltage headroom Vh can be easily changed. The same applies to the differential amplifier 50.

[0099] Furthermore, in this modification example, the common adjustment circuit 10 that supplies the bias voltages Vpc and Vpc3 corresponding to the differential amplifiers 50 and 80, which are set to different output common voltages, respectively, can be realized while suppressing an increase in circuit scale.

[0100] <Second Embodiment> FIG. 8 is a circuit diagram showing a configuration example of a common adjustment circuit according to the second embodiment.

[0101] As shown in FIG. 8, the common adjustment circuit 10 includes a reference voltage generation circuit 11 for generating a reference voltage Vrf, a second comparator 19, and a replica circuit 20. In this embodiment, as an example of the differential amplifier, the differential amplifier 80 described in the above-mentioned "Modification Example 3 (FIG. 7) of the First Embodiment" is used. Therefore, the replica circuit 20 in FIG. 8 has the same configuration as the second replica circuit 203 in FIG. 7. In this embodiment, the differential amplifiers 50, 60, and 70 may be used, and in that case, the configuration of the replica circuit 20 is different.

[0102] -Reference Voltage Generation Circuit- The reference voltage generation circuit 11 includes a first comparator 152, a first transistor 118, a first resistor 128, and a second resistor 129.

[0103] A reference voltage Vid is applied to one input of the first comparator 152 via an input terminal 101, and the drain of the P-type first transistor 118 is connected to the other input via a first node 188. The first comparator 152 compares the reference voltage Vid with the drain voltage of the first transistor 118 and outputs the comparison result to the gate of the first transistor 118. As a result, the voltage of the first node 188 is adjusted to the reference voltage Vid. Similar to the first embodiment, the reference voltage Vid is supplied from a circuit (for example, a bandgap reference circuit) that reduces voltage fluctuations against variations in the manufacturing process and changes in the usage environment such as power supply voltage fluctuations and temperature fluctuations.

[0104] The first resistor 128 is provided between the first node 188 and the ground VSS (corresponding to the first power supply). As a result, a current I1 shown in the above formula (4) flows through the first transistor 118 . In formula (4), R1 is the resistance value of the first resistor 128. The source of the first transistor 118 is connected to the power supply VDD via the second resistor 129. For convenience of explanation, the node connecting the source of the first transistor 118 and the second resistor 129 is referred to as the "second node 189". The second node 189 is connected to one input of the second comparator 19. As a result, a reference voltage Vrf shown in the following formula (15) is applied to one input of the second comparator 19.

[0105]

Equation

[0106] Here, R2 is the resistance value of the second resistor 129.

[0107] -Second Comparator- The second comparator 19 has the reference voltage Vrf applied to one input as described above, and the output node 286 (corresponding to the replica output node) of the replica circuit 20 is connected to the other input. The second comparator 19 compares the reference voltage Vrf with the output of the replica circuit 20 and outputs the comparison result to node 285. The output terminal 108 and the gate of the replica transistor 271 of the replica circuit 20 are connected to node 285. As described above, the voltage of the output node 286 of the replica circuit 20 is adjusted to the reference voltage Vrf.

[0108] Therefore, the output common voltage Vcm of the differential amplifier 80 is represented by the following equation (16) from the above equation (15), and the voltage headroom Vh of the differential amplifier 80 is represented by the following equation (17) from equation (16) and equation (3).

[0109]

Equation

[0110]

Equation

[0111] As described above, according to this embodiment, similar to the first embodiment, the common adjustment circuit 10 that operates such that the voltage headroom Vh of the differential amplifier 80 does not depend on the power supply VDD and depends only on the resistance ratio between the first resistor 128 and the second resistor 129 is realized. Furthermore, the voltage headroom Vh can be set with fewer parameters than in the first embodiment.

[0112] <Application Example> FIG. 9 shows an example in which the differential amplifier connected with the common adjustment circuit according to the above embodiment is used in the continuous-time linear equalizer 94 of the analog front end (receiving circuit) of a high-speed interface device.

[0113] In FIG. 9, the data output from the transmission circuit 91 of the high-speed interface is input to the continuous-time linear equalizer 94 via the cable 92 and the termination circuit 93 of the receiving circuit.

[0114] The continuous-time linear equalizer 94 has a configuration in which, for example, the differential amplifier 60 shown in FIG. 5, the differential amplifier 80 shown in FIG. 8, and the differential amplifier shown in FIG. 2 50 are cascade-connected. In the differential amplifier 60, the attenuated gain is restored. In the differential amplifier 80, the amplitude of the gain-adjusted data is adjusted to the input range of the subsequent decision feedback equalizer 95. Then, the common adjustment circuit 10 described so far is connected to each of the differential amplifiers 60, 80, 50. Note that the applicable destinations of the differential amplifiers 50, 60, 70, 80 and the common adjustment circuit 10 are not limited to the high-speed interface. Also, as described in Modifications 1, 2, etc., the bias voltage Vpc may be supplied to a plurality of differential amplifiers 50, 60, 70, 80 by a common adjustment circuit 10 having a smaller number than the number of differential amplifiers.

Industrial Applicability

[0115] The common adjustment circuit of the present disclosure is extremely useful because it acts so that the voltage headroom of the differential amplifier does not vary even in the presence of process variations and power supply voltage fluctuations.

Explanation of Signs

[0116] 10 Common adjustment circuit 19 Second comparator 20 Replica circuit 50 Differential amplifier 60 Differential amplifier 70 Differential amplifier 80 Differential amplifier 111 First transistor 112 Second transistor 113 Third transistor 114 Fourth transistor 115 Fifth transistor 116 Sixth transistor 118 First Transistor 121 First Resistor 122 Second Resistor 123 Third Resistor 124 Third Resistor 128 First Resistor 129 Second Resistor 151 First Comparator 152 First Comparator 161 Current Mirror Circuit 181 First Node 182 Second Node 183 Third Node 185 Fifth Node 188 First Node 189 Second Node 193 Third Comparator 203 Second Replica Circuit 261 Replica Transistor 271 Replica Transistor 282 Output Node (Replica Output Node) 286 Output Node (Replica Output Node) 561,571 Output Load Transistor 641,651 Output Load Transistor 741,751 Output Load Transistor 861,871 Output Load Transistor VDD Power Supply (Second Power Supply) VSS Ground (First Power Supply)

Claims

1. A common adjustment circuit that outputs a first bias voltage for applying to the gate of the output load transistor of a differential amplifier, comprising: a first comparator having one input connected to a reference voltage and the other input connected to a first node, and comparing and outputting the two inputs; a first transistor having a gate connected to the output of the first comparator, a source connected to the first node, and a drain connected to a second node; a first resistor having one terminal connected to the first node and the other terminal connected to a first power supply; a current mirror circuit including a second transistor having a gate and a drain connected to the second node and flowing an input current, and a third transistor having a gate connected to the second node and flowing an output current; a second resistor having one terminal connected to the source of the third transistor via a third node; a second comparator having one input connected to the third node and the other input connected to a fourth node, and comparing the two inputs and outputting the first bias voltage; a replica circuit including a replica transistor corresponding to the output load transistor of the differential amplifier, the gate of the replica transistor being connected to the output of the second comparator, and a replica output node corresponding to the output node of the differential amplifier being connected to the fourth node. A common adjustment circuit characterized by the above.

2. In the common adjustment circuit according to Claim 1, further comprising a third resistor having one terminal connected to the source of the second transistor and the other terminal connected to a second power supply having a different potential from the first power supply, wherein the other terminal of the second resistor is connected to the second power supply. A common adjustment circuit characterized by the above.

3. In the common adjustment circuit according to Claim 2, the current mirror circuit is a cascode-type current mirror circuit in which a fourth transistor provided between the second transistor and the first transistor and a fifth transistor provided between the third transistor and the first power supply are cascode-connected.

4. In the common adjustment circuit according to Claim 1, the replica circuit has a plurality of first replica circuits each having the replica transistor and the replica output node and having different configurations from each other. The second comparator has a plurality of third comparators provided so as to correspond to each of the plurality of first replica circuits. Each of the third comparators has one input connected to the third node and the other input connected to the replica output node of the corresponding first replica circuit. A common adjustment circuit characterized by the above.

5. In the common adjustment circuit according to claim 1, The current mirror circuit includes a sixth transistor having a gate connected to the second node and through which an output current flows. A fourth resistor having one terminal connected to the source of the sixth transistor via a fifth node. A third comparator having one input connected to the fifth node, the other input connected to the sixth node, comparing the two inputs, and outputting a second bias voltage for applying to the gate of an output load transistor of a second differential amplifier different from the differential amplifier. A second replica circuit including a replica transistor corresponding to the output load transistor of the second differential amplifier, the gate of the replica transistor being connected to the output of the third comparator, and the replica output node corresponding to the output node of the second differential amplifier being connected to the sixth node. A common adjustment circuit characterized by the above.

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