Semiconductor device, power conversion device, and air conditioner

Abstract

Suppress ringing during switching while suppressing an increase in the size of the device. 【Solution means】The semiconductor device (50) includes semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f), a first conductor pattern (51) electrically connected to the first electrodes of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f), a second conductor pattern (52) disposed adjacent to the first conductor pattern (51) with a space therebetween, and a conductor (55) electrically connecting the second electrodes of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) and the second conductor pattern (52). The semiconductor device (50) has a resistor (59) having a relative permittivity lower than that of the sealing material (58) disposed between the first conductor pattern (51) and the second conductor pattern (52) or between the first conductor pattern (51) and the first conductor (55).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a power conversion device, and an air conditioner.

Background Art

[0002] Conventionally, a semiconductor device having a structure for suppressing ringing generated during switching has been known. The semiconductor device disclosed in Patent Document 1 suppresses ringing by using a snubber circuit.

[0003] In the semiconductor device disclosed in Patent Document 1, a snubber substrate including a snubber circuit is arranged so as to overlap at least one of a positive electrode conductor pattern on which a positive electrode side power semiconductor element is mounted, a negative electrode conductor pattern to which a negative electrode side electrode of a negative electrode side power semiconductor element is connected, and an alternating current electrode pattern on which a negative electrode side power semiconductor element is mounted and a negative electrode side electrode of a positive electrode side power semiconductor element is connected.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, a semiconductor device having a snubber circuit as in Patent Document 1 requires a space for arranging a resistor and a capacitor constituting the snubber circuit. In order to secure space, a semiconductor device having a snubber circuit inevitably increases in size in the planar direction or the direction perpendicular to the surface of the substrate.

[0006] An object of the present disclosure is to suppress ringing during switching while suppressing an increase in the size of the device.

Means for Solving the Problems

[0007] The first aspect is directed to a semiconductor device. A semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), a first conductor pattern (51, 251) electrically connected to a first electrode of the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), a second conductor pattern (52, 252) adjacently disposed at an interval from the first conductor pattern (51, 251), a conductor (55, 255) electrically connecting a second electrode of the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) and the second conductor pattern (52, 252) and facing the first conductor pattern (51, 251), and a sealing material (58) covering the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), the first conductor pattern (51, 251), the second conductor pattern (52, 252), and the conductor (55, 255). When the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a unipolar transistor, the first electrode is one of a drain electrode and a source electrode, the second electrode is the other of the drain electrode and the source electrode. When the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a bipolar transistor, the first electrode is one of a collector electrode and an emitter electrode, the second electrode is the other of the collector electrode and the emitter electrode. A resistor (59, 259) having a relative permittivity lower than that of the sealing material (58) is disposed between the first conductor pattern (51, 251) and the second conductor pattern (52, 252) or between the first conductor pattern (51, 251) and the conductor (55, 255).

[0008] In the first aspect, since the resistors (59, 259) are arranged in a free space such as when the first conductor patterns (51, 251) and the second conductor patterns (52, 252) face each other, no separate space is required for arranging the resistors (59, 259). Further, due to the resistance caused by the resistors (59, 259), the ringing energy is consumed as heat energy, so the ringing during switching is suppressed. Therefore, the semiconductor devices (50, 250) can suppress the ringing during switching while suppressing the increase in the size of the devices.

[0009] The second aspect is that, in the first aspect, the resistors (59, 259) are arranged in contact with the surface of the first conductor pattern (51, 251), the surface of the second conductor pattern (52, 252), or the surface of the conductor (55, 255).

[0010] In the second aspect, even if the distance between the first conductor pattern (51, 251) and the second conductor pattern (52, 252), or the distance between the first conductor pattern (51, 251) and the conductor (55, 255) is reduced, the resistors (59, 259) can be easily arranged. Since the semiconductor devices (50, 250) can arrange the first conductor pattern (51, 251), the second conductor pattern (52, 252), and the conductor (55, 255) compactly, they can suppress the ringing during switching while suppressing the increase in the size of the devices.

[0011] The third aspect is that, in the second aspect, the resistors (59, 259) are in a thin film shape.

[0012] In the third aspect, since the resistors are in a thin film shape, the peripheral structure of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is hardly enlarged. The semiconductor devices (50, 250) can suppress the increase in the size of the devices.

[0013] Aspect 4 is, in any one of Aspects 1 to 3, when the resistor (59, 259) is disposed between the first conductor pattern (51, 251) and the second conductor pattern (52, 252), the area of the portion of the first conductor pattern (51, 251) facing the resistor (59, 259) or the area of the portion of the second conductor pattern (52, 252) facing the resistor (59, 259) between the first conductor pattern (51, 251) and the second conductor pattern (52, 252), or when the resistor (59, 259) is disposed between the first conductor pattern (51, 251) and the conductor (55, 255), the area of the portion of the first conductor pattern (51, 251) facing the resistor (59, 259) or the area of the portion of the conductor (55, 255) facing the resistor (59, 259) between the first conductor pattern (51, 251) and the conductor (55, 255), being S [mm 2 , and when the resistivity of the resistor (59, 259) is ρ [Ω·m], ρ / S ≧ 0.01 satisfies the formula of.

[0014] In Aspect 4, even if the thickness of the resistor (59, 259) is made thin, an appropriate resistance value can be obtained. The semiconductor device (50, 250) can effectively suppress ringing while suppressing an increase in the size of the device.

[0015] Aspect 5 is, in any one of Aspects 1 to 4, the resistor (59, 259) is polysilicon.

[0016] In Aspect 5, the resistor (59, 259) can be easily configured. The semiconductor device (50, 250) can suppress ringing with a simple configuration.

[0017] Aspect 6 is, in Aspect 2, the thermal conductivity of the resistor (59, 259) is higher than the thermal conductivity of the encapsulant (58).

[0018] In the sixth aspect, the heat dissipation property from the portion where the resistors (59, 259) are disposed is improved in the semiconductor devices (50, 250).

[0019] The seventh aspect is a power conversion device (10) including any one of the semiconductor devices (50, 250) according to the first to sixth aspects.

[0020] The eighth aspect is an air conditioner (1) including the power conversion device (10) according to the seventh aspect.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the embodiments shown below, and various modifications are possible without departing from the technical idea of the present disclosure. Since each drawing is for conceptually explaining the present disclosure, dimensions, ratios, or numbers may be exaggerated or simplified as necessary for easy understanding.

[0023] (1) Configuration of the air conditioner FIG. 1 is a piping system diagram of an air conditioner (1) having a semiconductor device (50) according to the present embodiment. The air conditioner (1) is an air conditioner that performs cooling and heating indoors. As shown in FIG. 1, the air conditioner (1) includes a power conversion device (10), a control unit (40), and a refrigerant circuit (110). The semiconductor device (50) is applied to the power conversion device (10).

[0024] The refrigerant circuit (110) is a closed circuit filled with refrigerant. The refrigerant circuit (110) is provided with a compressor (120), a four-way switching valve (130), an outdoor heat exchanger (140), an expansion valve (150), and an indoor heat exchanger (160).

[0025] Various compressors can be adopted for the compressor (120). The compressor (120) is, for example, a scroll compressor or a rotary compressor. The compressor (120) includes a motor (30). The motor (30) is, for example, an IPM motor (Interior Permanent Magnet Motor). The motor (30) operates when three-phase AC power is supplied from the power conversion device (10).

[0026] The outdoor heat exchanger (140) is a heat exchanger that exchanges heat between outdoor air and refrigerant. The indoor heat exchanger (160) is a heat exchanger that exchanges heat between indoor air and refrigerant. The expansion valve (150) is an electronic expansion valve.

[0027] The four-way switching valve (130) is a valve having first to fourth ports. The four-way switching valve (130) can be switched between a first state (the state shown by the solid line in FIG. 1) and a second state (the state shown by the broken line in FIG. 1). In the first state, the four-way switching valve (130) communicates the first port and the third port and communicates the second port and the fourth port. In the second state, the four-way switching valve (130) communicates the first port and the fourth port and communicates the second port and the third port.

[0028] In the refrigerant circuit (110), the discharge port of the compressor (120) is connected to the first port of the four-way switching valve (130), and the suction port is connected to the second port of the four-way switching valve (130). In the refrigerant circuit (110), an outdoor heat exchanger (140), an expansion valve (150), and an indoor heat exchanger (160) are arranged in order from the third port to the fourth port of the four-way switching valve (130). When switching between the cooling operation and the heating operation, the air conditioner (1) switches the four-way switching valve (130).

[0029] The control unit (40) is electrically connected to the power conversion device (10). The control unit (40) outputs a control signal to the power conversion device (10) to control the power conversion device (10). The control unit (40) controls the motor (30) via the power conversion device (10).

[0030] Based on the control signal from the control unit (40), the power conversion device (10) adjusts the power supplied to the motor (30).

[0031] (2) Configuration of the power conversion device FIG. 2 schematically shows the configuration of the power conversion device (10). The power conversion device (10) has a resistor (59) and the like, which will be described later. However, in FIG. 2, for the sake of simplicity of the drawing, the resistor (59) and the like are omitted.

[0032] As shown in FIG. 2, the power conversion device (10) includes a converter circuit (11), a DC link section (12), and an inverter circuit (13). The power conversion device (10) converts the power supply voltage supplied from a single-phase AC power supply (20) into a predetermined AC voltage. The power conversion device (10) supplies the AC voltage obtained by the conversion to the motor (30). Note that the AC power supply (20) may be three-phase instead of single-phase.

[0033] The converter circuit (11) includes four diodes (D1, D2, D3, D4) connected in a bridge configuration. The converter circuit (11) is connected to an AC power supply (20) via a reactor (17). The converter circuit (11) full-wave rectifies the power supply voltage. Note that the reactor (17) may be provided in the DC link section (12) between the converter circuit (11) and the capacitor (18), rather than between the AC power supply (20) and the converter circuit (11).

[0034] The DC link section (12) includes a capacitor (18). The capacitor (18) is connected to the output node of the converter circuit (11).

[0035] The inverter circuit (13) has six semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) and six freewheeling diodes (15a, 15b, 15c, 15d, 15e, 15f). The semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) function as switching elements. Hereinafter, the six semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) may be referred to as the first semiconductor element (14a), the second semiconductor element (14b), the third semiconductor element (14c), the fourth semiconductor element (14d), the fifth semiconductor element (14e), and the sixth semiconductor element (14f), and the six freewheeling diodes (15a, 15b, 15c, 15d, 15e, 15f) may be referred to as the first freewheeling diode (15a), the second freewheeling diode (15b), the third freewheeling diode (15c), the fourth freewheeling diode (15d), the fifth freewheeling diode (15e), and the sixth freewheeling diode (15f). When there is no need to distinguish them, they may simply be referred to as semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) and freewheeling diodes (15a, 15b, 15c, 15d, 15e, 15f).

[0036] The semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) are bridge-connected to each other. As a result, the inverter circuit (13) includes three switching legs. Each switching leg is formed by connecting two semiconductor elements in series. Specifically, the first semiconductor element (14a) and the fourth semiconductor element (14d), the second semiconductor element (14b) and the fifth semiconductor element (14e), and the third semiconductor element (14c) and the sixth semiconductor element (14f) constitute each switching leg.

[0037] For each of the three switching legs, the midpoint between the upper-arm semiconductor elements (14a, 14b, 14c) and the lower-arm semiconductor elements (14d, 14e, 14f) is connected to the coil (not shown) of each phase (u-phase, v-phase, w-phase) of the motor (30). Specifically, the midpoint between the first semiconductor element (14a) and the fourth semiconductor element (14d) is connected to the u-phase, the midpoint between the second semiconductor element (14b) and the fifth semiconductor element (14e) is connected to the v-phase, and the midpoint between the third semiconductor element (14c) and the sixth semiconductor element (14f) is connected to the w-phase.

[0038] The freewheeling diodes (15a, 15b, 15c, 15d, 15e, 15f) are connected in anti-parallel to each of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f), one by one.

[0039] In this embodiment, the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) are composed of unipolar transistors. Specifically, the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) are MOSFETs. The freewheeling diodes (15a, 15b, 15c, 15d, 15e, 15f) are composed of parasitic diodes of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f).

[0040] The control unit (40) outputs a PWM signal as a control signal to cause the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) to perform a switching operation (on-off operation). The power conversion device (10) receives the PWM signal and supplies a voltage to the gate electrodes of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) at a set duty ratio to cause the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f) to perform a switching operation.

[0041] (3) Configuration of the semiconductor device The semiconductor device (50) according to this embodiment will be described in detail with reference to FIGS. 3 to 5. The semiconductor device (50) is configured for the semiconductor elements (14a, 14b, 14c) of the upper arm in each switching leg. Hereinafter, the semiconductor device (50) including the first semiconductor element (14a) will be described as an example. The semiconductor devices including the second semiconductor element (14b) and the semiconductor devices including the third semiconductor element (14c) have the same configuration.

[0042] The switching leg including the first semiconductor element (14a) includes, as the semiconductor device (50), the first semiconductor element (14a), the first conductor pattern (51), the second conductor pattern (52), the first conductor (55), the encapsulant (58), and the resistor (59). The switching leg also includes the fourth semiconductor element (14d), the third conductor pattern (53), the fourth conductor pattern (54), the second conductor (56), and the third conductor (57). The switching leg is mounted on the substrate (60). Hereinafter, the plane normal direction of the substrate (60) will be described as the vertical direction. This does not limit the direction in which the semiconductor device (50) is actually arranged.

[0043] As shown in FIG. 3, the first semiconductor element (14a) is a vertical MOSFET. The source electrode (14aS) of the first semiconductor element (14a) is formed on the upper surface of the chip, and the drain electrode (14aD) of the first semiconductor element (14a) is formed on the lower surface of the chip. As shown in FIG. 4, a gate electrode (14aG), which is a control electrode, is provided on the upper surface of the first semiconductor element (14a).

[0044] Although detailed illustration is omitted, the fourth semiconductor element (14d) is a vertical MOSFET similar to the first semiconductor element (14a). The source electrode (14dS) of the fourth semiconductor element (14d) is formed on the upper surface of the chip, and the drain electrode (14dD) of the fourth semiconductor element (14d) is formed on the lower surface of the chip. A gate electrode (14dG), which is a control electrode, is provided on the upper surface of the fourth semiconductor element (14d).

[0045] The first conductor pattern (51) is electrically connected to the drain electrode (14aD) of the first semiconductor element (14a). As shown in FIG. 3, the drain electrode (14aD) is mounted on the upper surface of the first conductor pattern (51) with solder or the like and is electrically connected to the first conductor pattern (51). The drain electrode (14aD) of the first semiconductor element (14a) is an example of the first electrode.

[0046] The second conductor pattern (52) is electrically connected to the source electrode (14aS) of the first semiconductor element (14a). The source electrode (14aS) is electrically connected to the second conductor pattern (52) via the first conductor (55). The second conductor pattern (52) corresponds to the midpoint between the first semiconductor element (14a) and the fourth semiconductor element (14d). The second conductor pattern (52) has a terminal (52a) for electrically connecting to the motor (30). The source electrode (14aS) of the first semiconductor element (14a) is an example of the second electrode.

[0047] The second conductor pattern (52) is adjacently arranged at a distance from the first conductor pattern (51). The side surface (51a) of the first conductor pattern (51) and the side surface (52b) of the second conductor pattern (52) face each other in the in-plane direction of the substrate (60). The distance between the side surface (51a) of the first conductor pattern (51) and the side surface (52b) of the second conductor pattern (52) is not particularly limited, but is, for example, 1 mm.

[0048] As shown in FIG. 4, the third conductor pattern (53) is electrically connected to the drain electrode (14dD) of the fourth semiconductor element (14d). The drain electrode (14dD) is mounted on the upper surface of the third conductor pattern (53) with solder or the like and is electrically connected to the third conductor pattern (53).

[0049] The fourth conductor pattern (54) is electrically connected to the source electrode (14dS) of the fourth semiconductor element (14d). The source electrode (14dS) is electrically connected to the fourth conductor pattern (54) via the second conductor (56).

[0050] The first conductor (55) extends across the gap between the first conductor pattern (51) and the second conductor pattern (52). The first conductor (55) faces the upper surface (51b) of the first conductor pattern (51) in a direction perpendicular to the surface of the substrate (60). The distance between the upper surface (51b) of the first conductor pattern (51) and the first conductor (55) is slightly larger than the thickness of the chip constituting the first semiconductor element (14a). The first conductor (55) is, for example, an aluminum wire.

[0051] The second conductor (56) extends across the gap between the third conductor pattern (53) and the fourth conductor pattern (54). The second conductor (56) is, for example, an aluminum wire.

[0052] The third conductor (57) electrically connects the second conductor pattern (52) and the third conductor pattern (53). The third conductor (57) electrically connects the source electrode (14aS) of the first semiconductor element (14a) and the drain electrode of the fourth semiconductor element (14d). The third conductor (57) is, for example, an aluminum wire.

[0053] The sealing material (58) covers and seals the first semiconductor element (14a), the fourth semiconductor element (14d), the first conductor pattern (51), the second conductor pattern (52), the third conductor pattern (53), the fourth conductor pattern (54), the first conductor (55), the second conductor (56), the third conductor (57), and the resistor (59). The sealing material (58) is, for example, an epoxy resin or a gel.

[0054] The resistor (59) is disposed between the first conductor pattern (51) and the second conductor pattern (52) facing each other and between the first conductor pattern (51) and the first conductor (55) facing each other. As shown in FIG. 3, the resistor (59) is disposed in contact with the surface of the first conductor pattern (51), the surface of the second conductor pattern (52), and the surface of the first conductor (55). The resistor (59) is a member separate from the sealing material (58).

[0055] The resistor (59) includes a first resistance portion (59a), a second resistance portion (59b), a third resistance portion (59c), and a fourth resistance portion (59d). The first resistance portion (59a) is located on the side surface (51a) of the first conductor pattern (51) on the side of the second conductor pattern (52) and is disposed over the entire side surface (51a). The second resistance portion (59b) is located on the side surface (52b) of the second conductor pattern (52) on the side of the first conductor pattern (51) and is disposed over the entire side surface (52b). The third resistance portion (59c) is located at a portion of the upper surface (51b) of the first conductor pattern (51) that is continuous with the side surface (51a) and extends along the side surface (51a). The fourth resistance portion (59d) is located on the lower surface of the first conductor (55) and extends along the first conductor (55). The corner between the side surface (51a) and the upper surface (51b) of the first conductor pattern (51) is covered by the first resistance portion (59a) and the third resistance portion (59c).

[0056] The resistor (59) is made of a material having a lower relative permittivity than the encapsulant (58) and a higher thermal conductivity than the encapsulant (58). The resistor (59) is, for example, polysilicon. The resistor (59) is in the form of a thin film. The thickness of each resistor portion (59a, 59b, 59c, 59d) of the resistor (59) is, for example, on the order of several tens of μm to several hundreds of μm.

[0057] The resistor (59) is formed after the first semiconductor element (14a) and the fourth semiconductor element (14d) are mounted and the first conductor (55), the second conductor (56), and the third conductor (57) are connected. The resistor (59) is formed by being applied with an applicator on the surface of the first conductor pattern (51), the surface of the second conductor pattern, and the surface of the first conductor (55).

[0058] In the present embodiment, the resistor (59) is not disposed on the third conductor pattern (53), the fourth conductor pattern (54), and the second conductor (56).

[0059] FIG. 5 is an equivalent circuit of the semiconductor device (50). Between the source of the first semiconductor element (14a) and the drain of the fourth semiconductor element (14d), a first parasitic inductance (L1) formed by the second conductor pattern (52) and a second parasitic inductance (L2) formed by the third conductor pattern (53) are connected in series. Between the drain and the source of the first semiconductor element (14a), a specific circuit (16) composed of a resistor and a capacitor is connected in parallel by the resistor (59). Two of the first specific circuit (16a) and the second specific circuit (16b) are formed in the specific circuit (16).

[0060] The first specific circuit (16a) is a circuit composed of a resistor (59) between a first conductor pattern (51) and a second conductor pattern (52). The first specific circuit (16a) has a first resistor (R1), a second resistor (R2), and a first capacitor (C1). The first capacitor (C1) corresponds to the parasitic capacitance formed between the first conductor pattern (51) and the second conductor pattern (52). That is, the first specific circuit (16a) is a circuit in which the first resistor (R1) and the second resistor (R2) are connected in series with respect to the parasitic capacitance formed between the first conductor pattern (51) and the second conductor pattern (52).

[0061] The value of the first resistor (R1) is determined by the resistivity ρ [Ω·m] of the resistor (59), the thickness d [mm] of the first resistor portion (59a), and the area S [mm 2 . Since a ringing suppression effect can be obtained if the resistance value is 10 Ω or more, the resistance value R satisfies R = ρ × (d × 10 -3 / S × 10 -6 ) ≥ 10 ··· (A) and the relational expression (A) holds.

[0062] The direction of the thickness of the first resistor portion (59a) is the direction in which the first conductor pattern (51) and the second conductor pattern (52) face each other.

[0063] The area of the first resistor portion (59a) corresponds to the area of the portion of the first conductor pattern (51) that faces the resistor (59) between the first conductor pattern (51) and the second conductor pattern (52) where the resistor (59) is disposed between the first conductor pattern (51) and the second conductor pattern (52) (hereinafter referred to as the first area). Specifically, the first area is the area of the portion of the first conductor pattern (51) that overlaps with the first resistor portion (59a) when looking at the first resistor portion (59a) from the second conductor pattern (52) side toward the first conductor pattern (51) side. In the present embodiment, the first area corresponds to the area of the side surface (51a) of the first conductor pattern (51).

[0064] When the resistor is arranged so as to fill the space where the first conductor pattern (51) and the second conductor pattern (52) face each other, the thickness d of the first resistor portion (59a) becomes maximum, and the resistivity for satisfying the relational expression becomes minimum. The thickness d in this case coincides with the distance between the first conductor pattern (51) and the second conductor pattern (52). This distance is at most about 1 mm from the viewpoint of miniaturization of the module. Substituting d = 1 mm, where d is the maximum condition, into the relational expression, ρ [Ω·m] / S [mm 2 ≧ 0.01 ···(B) the relational expression (B) holds. This relational expression (B) is an expression showing the lower limit of the resistivity for satisfying a resistance value of 10 Ω or more even when d is maximum. When d is not maximum, a resistivity equal to or higher than this lower limit is required.

[0065] The value of the second resistor (R2) is determined by the resistivity of the resistor (59), the thickness of the second resistor portion (59b), and the area of the second resistor portion (59b). The method of determining the value of the second resistor (R2) is the same as that of the first resistor (R1). The area of the second resistor portion (59b) corresponds to the area of the portion of the second conductor pattern (52) facing the first conductor pattern (51) (hereinafter referred to as the second area) between the first conductor pattern (51) and the second conductor pattern (52) where the resistor (59) is arranged. Specifically, the second area is the area of the portion of the second conductor pattern (52) overlapping the second resistor portion (59b) when the second resistor portion (59b) is viewed from the first conductor pattern (51) side toward the second conductor pattern (52) side. In the present embodiment, the second area corresponds to the area of the side surface (52b) of the second conductor pattern (52).

[0066] The resistor (59) is arranged so as to fill the space where the first conductor pattern (51) and the second conductor pattern (52) face each other. When the thickness d of the first resistor section (59a) is maximum, the resistance of the first specific circuit (16a) becomes one of the first resistor (R1) and the second resistor (R2). Similarly, even when the resistor (59) is not in contact with the first conductor pattern (51) and the second conductor pattern (52) and is between the first conductor pattern (51) and the second conductor pattern (52), the resistance of the first specific circuit (16a) becomes one of the first resistor (R1) and the second resistor (R2). In these cases, for only one of the resistors, the relational expression (B) may be considered.

[0067] The first capacitor (C1) is formed between the first conductor pattern (51) and the second conductor pattern (52) even when the resistor (59) is not arranged. The capacitance of the first capacitor (C1) changes when the resistor (59) is arranged. Since the relative permittivity of the resistor (59) is smaller than the relative permittivity of the encapsulant (58), the capacitance of the first capacitor (C1) is smaller when the resistor (59) is arranged than when the resistor (59) is not arranged. The capacitance of the first capacitor (C1) is determined by the relative permittivity of the resistor (59), the relative permittivity of the encapsulant (58), the distance between the side surface (51a) of the first conductor pattern (51) and the side surface (52b) of the second conductor pattern (52), the thickness of the first resistor section (59a), the thickness of the second resistor section (59b), and the first area or the second area.

[0068] The second specific circuit (16b) is a circuit constituted by the resistor (59) between the first conductor pattern (51) and the first conductor (55). The second specific circuit (16b) includes a third resistor (R3), a fourth resistor (R4), and a second capacitor (C2). The second capacitor (C2) corresponds to the stray capacitance formed between the first conductor pattern (51) and the first conductor (55). That is, the second specific circuit (16b) is a circuit in which the third resistor (R3) and the fourth resistor (R4) are connected in series with respect to the stray capacitance formed between the first conductor pattern (51) and the first conductor (55).

[0069] The value of the third resistor (R3) is determined by the resistivity of the resistor body (59), the thickness of the third resistor portion (59c), and the area of the third resistor (R3).

[0070] The direction of the thickness of the third resistor portion (59c) is the direction in which the first conductor pattern (51) and the first conductor (55) face each other.

[0071] The area of the third resistor portion (59c) corresponds to the area of the portion of the first conductor pattern (51) that faces the first conductor (55) between the first conductor pattern (51) and the first conductor (55) where the resistor body (59) is disposed (hereinafter referred to as the third area). Specifically, when the third resistor portion (59c) faces the first conductor (55), the third area is the area of the portion of the first conductor pattern (51) that overlaps the third resistor portion (59c) when viewed from the first conductor (55) side toward the first conductor pattern (51) side. In the present embodiment, the third area corresponds to the area of the portion of the upper surface (51b) of the first conductor pattern (51) that is in contact with the third resistor portion (59c).

[0072] The value of the fourth resistor (R4) is determined by the resistivity of the resistor body (59), the thickness of the fourth resistor portion (59d), and the area of the fourth resistor portion (59d).

[0073] The direction of the thickness of the fourth resistor portion (59d) is the direction in which the first conductor pattern (51) and the first conductor (55) face each other.

[0074] The area of the fourth resistance portion (59d) corresponds to the area of the portion of the first conductor (55) facing the first conductor pattern (51) between the first conductor pattern (51) and the first conductor (55) where the resistor (59) is disposed between the first conductor pattern (51) and the first conductor (55) (hereinafter referred to as the fourth area). Specifically, the fourth area is the area of the portion of the first conductor (55) overlapping the fourth resistance portion (59d) when viewing the fourth resistance portion (59d) from the first conductor pattern (51) side toward the first conductor (55) side in the plane direction of the first conductor pattern (51). When the first conductor (55) is a wire having a circular cross section, the fourth area is half of the total surface area of the portion of the first conductor (55) facing the fourth resistance portion (59d) on the first conductor pattern (51) side.

[0075] Similar to the first resistance (R1) and the second resistance (R2), the third resistance (R3) and the fourth resistance (R4) may satisfy the relational expression (B).

[0076] When the resistor (59) is disposed so as to fill the space where the first conductor pattern (51) and the first conductor (55) face each other, the resistance of the second specific circuit (16b) becomes one of the third resistance (R3) and the fourth resistance (R4). At this time, the relational expression (B) may be considered only for one of the resistances.

[0077] The second capacitor (C2) is formed between the first conductor pattern (51) and the first conductor (55) even when the resistor (59) is not disposed. The capacitance of the second capacitor (C2) changes when the resistor (59) is disposed. Specifically, the capacitance of the second capacitor (C2) is smaller when the resistor (59) is disposed than when the resistor (59) is not disposed. The capacitance of the second capacitor (C2) is determined by the relative permittivity of the resistor (59), the relative permittivity of the sealing material (58), the distance between the upper surface (51b) of the first conductor pattern (51) and the first conductor (55), the thickness of the third resistance portion (59c), the thickness of the fourth resistance portion (59d), and the third area or the fourth area.

[0078] (4) Switching voltage As shown in FIG. 5, when parasitic inductances (L1, L2) and floating capacitances (C1, C2) are formed, ringing due to LC resonance between the parasitic inductances (L1, L2) and the floating capacitances (C1, C2) is likely to occur when the first semiconductor element (14a) is switched. In particular, when the first semiconductor element (14a) is switched at high speed, the spike of the drain-source voltage of the first semiconductor element (14a) becomes high, so that ringing is likely to occur. If the noise level due to ringing during switching is large, it may adversely affect the operation of other devices.

[0079] The broken line in FIG. 6 is the result of calculating the voltage waveform of the first semiconductor element (14a) of the semiconductor device without the resistor (59) by simulation. Since the resistor (59) is not arranged, the first resistor (R1), the second resistor (R2), the third resistor (R3), and the fourth resistor (R4) in FIG. 5 do not exist. Also, the capacitance of the first capacitor (C1) and the capacitance of the second capacitor are larger than those in the case where the resistor (59) is provided.

[0080] As shown in FIG. 6, it can be seen that a semiconductor device without the resistor (59) generates ringing with a relatively large amplitude after switching.

[0081] The solid line in FIG. 6 is the result of calculating the voltage waveform of the first semiconductor element (14a) of the semiconductor device (50) provided with the resistor (59) as in this embodiment by simulation. It can be seen that the ringing of the semiconductor device (50) is suppressed.

[0082] In the semiconductor device (50), the energy of ringing is consumed as heat energy by the first resistor (R1), the second resistor (R2), the third resistor (R3), and the fourth resistor (R4). Also, since the relative dielectric constant of the resistor (59) is lower than that of the sealing material (58), the capacitance of the first capacitor (C1) and the capacitance of the second capacitor become smaller compared to the case where the resistor (59) is not arranged. As a result, the semiconductor device (50) can suppress ringing during switching.

[0083] (5) Effects of the Embodiment The semiconductor device (50) according to the present embodiment includes a first conductor pattern (51) electrically connected to the drain electrodes of the semiconductor elements (14a, 14b, 14c) of the upper arm, a second conductor pattern (52) adjacently arranged at an interval from the first conductor pattern (51), and a first conductor (55) that electrically connects the source electrode of the semiconductor elements (14a, 14b, 14c) and the second conductor pattern (52) and faces the first conductor pattern (51). While the first conductor pattern (51) and the second conductor pattern (52) face each other, and while the first conductor pattern (51) and the first conductor (55) face each other, a resistor (59) having a relative permittivity lower than that of the sealing material (58) is arranged. In the semiconductor device (50), since the resistor (59) is arranged in a free space such as when the first conductor pattern (51) and the second conductor pattern (52) face each other, no separate space is required for arranging the resistor (59). In the semiconductor device (50), due to the resistor (59), a resistor is connected in series to the parasitic capacitance between the first conductor pattern (51) and the second conductor pattern (52), and the parasitic capacitance between the first conductor pattern (51) and the conductor (55). The energy of ringing is consumed as heat energy due to the resistance caused by the resistor (59). Also, in the semiconductor device (50), due to the resistor (59), the parasitic capacitance between the first conductor pattern (51) and the second conductor pattern (52) and the parasitic capacitance between the first conductor pattern (51) and the first conductor (55) are reduced. Therefore, the semiconductor device (50) can suppress ringing during switching while suppressing an increase in the size of the device.

[0084] In this embodiment, the resistor (59) is disposed in contact with the surface of the first conductor pattern (51), the surface of the second conductor pattern (52), or the surface of the first conductor (55). In the semiconductor device (50), even if the distance between the first conductor pattern (51) and the second conductor pattern (52) and the distance between the first conductor pattern (51) and the conductor (55) are reduced, the resistor (59) can be easily disposed. Since the semiconductor device (50) can make the arrangements of the first conductor pattern (51), the second conductor pattern (52), and the conductor (55) compact, it is possible to suppress an increase in the size of the device while suppressing ringing during switching.

[0085] In this embodiment, the resistor (59) is in a thin film shape. In the semiconductor device (50), even if the resistor (59) is provided, the peripheral structure of the semiconductor elements (14a, 14b, 14c) is hardly enlarged. The semiconductor device (50) can suppress an increase in the size of the device.

[0086] In this embodiment, when any one of the first area, the second area, the third area, and the fourth area is S [mm 2 , and the resistivity of the resistor (59) is ρ [Ω·m], ρ / S ≧ 0.01 is satisfied. If the above formula is satisfied, even when the thickness of the resistor (59) is relatively thin, the resistance value of the resistor (59) becomes an appropriate size. Since the semiconductor device (50) can make the resistor (59) thin, it is possible to suppress an increase in the size of the device while effectively suppressing ringing.

[0087] In this embodiment, the resistor (59) is polysilicon. The resistor (59) can be easily configured. The semiconductor device (50) can suppress ringing with a simple configuration.

[0088] (6) Modification FIG. 7 and FIG. 8 show a modified example of the semiconductor device according to the present embodiment. FIGS. 7 and 8 show a semiconductor device (250) of a switching leg including a first semiconductor element (214a). The semiconductor device including the second semiconductor element and the semiconductor device including the third semiconductor element have the same configuration.

[0089] As shown in FIG. 7, the first semiconductor element (214a) is a lateral MOSFET. The drain electrode (214aD), source electrode (214aS), and gate electrode (214aG) of the first semiconductor element (214a) are all formed on the upper surface of the first semiconductor element (214a). The fourth semiconductor element (214d) is also a lateral MOSFET similar to the first semiconductor element (214a). The drain electrode (214dD), source electrode (214dS), and gate electrode (214dG) of the fourth semiconductor element (214d) are all formed on the upper surface of the fourth semiconductor element (214d).

[0090] The switching leg including the first semiconductor element (214a) includes, as a semiconductor device (250), the first semiconductor element (214a), a first conductor pattern (251), a second conductor pattern (252), a first conductor (255), a sealing material (58), and a resistor (259). The switching leg also includes a fourth semiconductor element (214d), a third conductor pattern (253), a second conductor (256), a third conductor (257), and a fourth conductor (258). The switching leg is mounted on a substrate (60).

[0091] The first conductor pattern (251) is the portion where the first semiconductor element (214a) is mounted. The first conductor pattern (251) is electrically connected to the source electrode (214aS) of the first semiconductor element (214a). The source electrode (214aS) is electrically connected to the first conductor pattern (251) via the second conductor (256). The first conductor pattern (251) is also electrically connected to the drain electrode (214dD) of the fourth semiconductor element (214d). The drain electrode (214dD) is electrically connected to the first conductor pattern (251) via the fourth conductor (258). The first conductor pattern (251) corresponds to the midpoint between the first semiconductor element (214a) and the fourth semiconductor element (214d). The source electrode (214aS) of the first semiconductor element (214a) is an example of the first electrode.

[0092] The second conductor pattern (252) is electrically connected to the drain electrode (214aD) of the first semiconductor element (214a). The drain electrode (214aD) is electrically connected to the second conductor pattern (252) via the first conductor (255). The drain electrode (214aD) of the first semiconductor element (214a) is an example of the second electrode.

[0093] The second conductor pattern (252) is arranged adjacent to the first conductor pattern (251) with a gap therebetween. The side surface (251a) of the first conductor pattern (251) and the side surface (252b) of the second conductor pattern (252) face each other in the in-plane direction of the substrate (60).

[0094] The third conductor pattern (253) is the portion where the fourth semiconductor element (214d) is mounted. The third conductor pattern (253) is electrically connected to the source electrode (214dS) of the fourth semiconductor element (214d). The source electrode (214dS) is electrically connected to the third conductor pattern (253) via the third conductor (257).

[0095] The first conductor (255) extends across the gap between the first conductor pattern (251) and the second conductor pattern (252). The first conductor (255) faces the upper surface (251b) of the first conductor pattern (251) in a direction perpendicular to the surface of the substrate (60). The first conductor (255) is, for example, an aluminum wire.

[0096] The second conductor (256) is disposed within the range of the first conductor pattern (251). The second conductor (256) is, for example, an aluminum wire.

[0097] The third conductor (257) is disposed within the range of the third conductor pattern (253). The third conductor (257) is, for example, an aluminum wire.

[0098] The fourth conductor (258) extends across the gap between the first conductor pattern (251) and the third conductor pattern (253). The fourth conductor (258) is, for example, an aluminum wire.

[0099] The encapsulant (58) covers and encapsulates the first semiconductor element (214a), the fourth semiconductor element (214d), the first conductor pattern (251), the second conductor pattern (252), the third conductor pattern (253), the first conductor (255), the second conductor (256), the third conductor (257), the fourth conductor (258), and the resistor (259). The encapsulant (58) is, for example, a resin.

[0100] The resistor (259) is disposed between the first conductor pattern (251) and the second conductor pattern (252) face each other and between the first conductor pattern (251) and the first conductor (255) face each other. As shown in FIG. 7, the resistor (259) is disposed in contact with the surface of the first conductor pattern (251), the surface of the second conductor pattern (252), and the surface of the first conductor (255). Since the material and shape of the resistor (259) are the same as those in the foregoing embodiment, a detailed description thereof is omitted.

[0101] Even in the configuration of the modified example, a specific circuit composed of a resistor and a capacitor is formed between the drain and the source of the first semiconductor element (214a) by a resistor (259). Thereby, even in the semiconductor device (250) of the modified example, ringing during switching can be suppressed while suppressing an increase in the size of the device.

[0102] (7) Other Embodiments The semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) may be composed of unipolar transistors other than MOSFETs such as JFETs, HFETs, and HEMTs. In this case, the first electrode electrically connected to the first conductor pattern (51, 251) is one of the drain electrode and the source electrode, and the second electrode electrically connected to the second conductor pattern (52, 252) is the other of the drain electrode and the source electrode. When the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a unipolar transistor, the control electrode is the gate electrode. Also, the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) may be composed of bipolar transistors such as IGBTs and HBTs. In this case, the first electrode electrically connected to the first conductor pattern (51, 251) is one of the collector electrode and the emitter electrode, and the second electrode electrically connected to the second conductor pattern (52, 252) is the other of the collector electrode and the emitter electrode. When the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a bipolar transistor, the control electrode is the gate electrode or the base electrode.

[0103] The resistor (59, 259) may be provided only in either one of the period when the first conductor pattern (51, 251) and the second conductor pattern (52, 252) face each other and the period when the first conductor pattern (51, 251) and the first conductor (55, 255) face each other. For example, the arrangement of the resistor (59, 259) may be selected from the following patterns. · It is arranged only on the surface of the first conductor patterns (51, 251) and not on the surfaces of the second conductor patterns (52, 252) and the first conductor (55, 255). · It is arranged only on the surface of the second conductor patterns (52, 252) and not on the surfaces of the first conductor patterns (51, 251) and the first conductor (55, 255). · It is arranged only on the surface of the first conductor (55, 255) and not on the surfaces of the first conductor patterns (51, 251) and the second conductor patterns (52, 252). · It is arranged on the surfaces of the first conductor patterns (51, 251) and the second conductor patterns (52, 252) and not on the surface of the first conductor (55, 255). · It is arranged on the surfaces of the second conductor patterns (52, 252) and the first conductor (55, 255) and not on the surface of the first conductor pattern (51, 251). · It is arranged on the surfaces of the first conductor patterns (51, 251) and the first conductor (55, 255) and not on the surface of the second conductor pattern (52, 252).

[0104] The ringing during switching is caused by LC resonance due to parasitic inductance and stray capacitance. If a resistance caused by the resistors (59, 259) is inserted at any one location in the path of the LC resonance, an effect of suppressing the ringing can be obtained. When the resistor (59, 259) is provided only on the second conductor pattern (52, 252), the area S in the relational expression (B) is the second area. When the resistor (59, 259) is provided only on the first conductor (55, 255), the area S in the relational expression (B) is the fourth area.

[0105] The resistor (59, 259) does not necessarily face the entire side surface (51a, 251a) of the first conductor pattern (51, 251), the entire side surface (52b, 252b) of the second conductor pattern (52, 252), and the entire first conductor (55, 255). For example, the resistor (59, 259) may be provided so as to face only half of the side surface (51a, 251a) of the first conductor pattern (51, 251). In this case, the first area becomes half of the area of the side surface (51a, 251a) of the first conductor pattern (51, 251).

[0106] The resistor (59, 259) may be separated from the surface of the first conductor pattern (51, 251), the surface of the second conductor pattern (52, 252), and the surface of the first conductor (55, 255). Also, the resistor (59, 259) may be in a configuration where it contacts the surface of the first conductor (55, 255) while being separated from the surfaces of the first conductor pattern (51, 251) and the second conductor pattern (52, 252).

[0107] The resistor (59, 259) does not necessarily have a thin film shape. For example, a configuration may be adopted in which the entire space between the first conductor pattern (51, 251) and the second conductor pattern (52, 252) and the entire space between the first conductor pattern (51, 251) and the first conductor (55, 255) as shown in FIGS. 4 and 7 are filled with the resistor (59, 259).

[0108] The material of the resistor (59, 259) does not necessarily have a higher thermal conductivity than the encapsulant (58) as long as its relative dielectric constant is lower than that of the encapsulant (58). When the resistors (59, 259) are arranged at a plurality of locations, some of the resistors (59, 259) may be made of a material having a higher thermal conductivity than the encapsulant (58), and the other resistors (59, 259) may be made of a material having the same or lower thermal conductivity as the encapsulant (58).

[0109] The resistor (59, 259) does not have to be polysilicon. When arranging a plurality of resistors (59, 259) at multiple locations, some of the resistors (59, 259) may be made of polysilicon and the other resistors (59, 259) may be made of another material.

[0110] The semiconductor device (50, 250) may be configured for the semiconductor elements (14d, 14e, 14f, 214d) that constitute the lower arm. For example, a resistor may be arranged while the third conductor pattern (53) and the fourth conductor pattern (54) face each other, or while the third conductor pattern (53) and the second conductor (56) face each other. Further, the semiconductor device (50, 250) may be configured for all of the semiconductor elements (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d).

[0111] Although the embodiments and modifications have been described above, it will be understood that various changes in form and details can be made without departing from the spirit and scope of the claims. Also, the above embodiments, modifications, and other embodiments may be combined or substituted as appropriate as long as the functions of the subject of the present disclosure are not impaired.

[0112] The descriptions such as "first", "second", "third",... described above are used to distinguish the phrases to which these descriptions are given, and do not limit even the number and order of those phrases.

Industrial Applicability

[0113] As described above, the present disclosure is useful for semiconductor devices.

Description of Reference Numerals

[0114] 1 Air conditioner 10 Power conversion device 14a First semiconductor element (semiconductor element) 14aD Drain electrode (first electrode) 14aS Source electrode (second electrode) 14b Second semiconductor element (semiconductor element) 14c Third semiconductor element (semiconductor element) 50 Semiconductor device 51 First conductor pattern 52 Second conductor pattern 55 First conductor 58 Encapsulant 59 Resistor 214a First semiconductor element (semiconductor element) 214aD Drain electrode (second electrode) 214aS Source electrode (first electrode) 214b Second semiconductor element (semiconductor element) 214c Third semiconductor element (semiconductor element) 250 Semiconductor device 251 First conductor pattern 252 Second conductor pattern 255 First conductor 259 Resistor

Claims

1. A semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), a first conductor pattern (51, 251) electrically connected to a first electrode of the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), a second conductor pattern (52, 252) disposed adjacent to and spaced apart from the first conductor pattern (51, 251), a conductor (55, 255) that electrically connects a second electrode of the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) to the second conductor pattern (52, 252) and faces the first conductor pattern (51, 251), a sealing material (58) covering the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d), the first conductor pattern (51, 251), the second conductor pattern (52, 252), and the conductor (55, 255), when the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a unipolar transistor, the first electrode is one of a drain electrode and a source electrode, the second electrode is the other of the drain electrode and the source electrode, and when the semiconductor element (14a, 14b, 14c, 14d, 14e, 14f, 214a, 214d) is a bipolar transistor, the first electrode is one of a collector electrode and an emitter electrode, and the second electrode is the other of the collector electrode and the emitter electrode, A semiconductor device in which a resistor (59, 259) having a relative dielectric constant lower than that of the sealing material (58) is disposed between the first conductor pattern (51, 251) and the second conductor pattern (52, 252) or between the first conductor pattern (51, 251) and the conductor (55, 255).

2. The semiconductor device according to claim 1, wherein the resistor (59, 259) is disposed in contact with the surface of the first conductor pattern (51, 251), the surface of the second conductor pattern (52, 252), or the surface of the conductor (55, 255).

3. The semiconductor device according to claim 2, wherein the resistor (59, 259) is in a thin film shape.

4. The semiconductor device according to claim 1, When the resistor (59, 259) is disposed between the first conductor pattern (51, 251) and the second conductor pattern (52, 252), the area of the portion of the first conductor pattern (51, 251) facing the resistor (59, 259) or the area of the portion of the second conductor pattern (52, 252) facing the resistor (59, 259) between the first conductor pattern (51, 251) and the second conductor pattern (52, 252), or when the resistor (59, 259) is disposed between the first conductor pattern (51, 251) and the conductor (55, 255), the area of the portion of the first conductor pattern (51, 251) facing the resistor (59, 259) or the area of the portion of the conductor (55, 255) facing the resistor (59, 259) between the first conductor pattern (51, 251) and the conductor (55, 255), be S [mm ２ , and when the resistivity of the resistor (59, 259) is ρ [Ω·m], satisfying the formula ρ / S ≧ 0.01 of the semiconductor device.

5. In the semiconductor device according to claim 1, The semiconductor device in which the resistor (59, 259) is polysilicon.

6. In the semiconductor device according to claim 2, The semiconductor device in which the thermal conductivity of the resistor (59, 259) is higher than the thermal conductivity of the encapsulant (58).

7. A power conversion device including the semiconductor device (50, 250) according to any one of claims 1 to 6.

8. An air conditioner including the power conversion device (10) according to claim 7.

Images