Technique for rapidly correcting waveforms after calibration of a quantum system

Abstract

A technique for facilitating rapid waveform modification after calibration of a quantum system. In one example, a system may include a processor executing computer-executable components stored in a memory. The computer-executable components include a calibration component and a playback component. The calibration component may identify parameters of the directed graph that are changed by calibration of the quantum system that occurs after generation of the directed graph. The playback component may modify the directed graph based on the identified parameters to generate an updated directed graph.

Description

Technical Field

[0001] The present disclosure relates to quantum computing, and more particularly, to techniques for facilitating rapid waveform correction after calibration of a quantum system.

Background Art

[0002] Some quantum computers receive quantum circuits or programs in a specialized language of waves and pulses. Considerable extraction has been achieved so that such quantum circuits can be submitted to computing services by an entity as a higher-level language rather than as a specialized language of waves and pulses received by some quantum computers. The computing service can convert the higher-level language quantum circuit or program submitted by the entity into a schedule of waveforms and pulses that can be interpreted by the quantum computer via waveform generation. In some respects, the waveform generation process can be interpreted as similar to the process implemented by an assembler to assemble instructions for implementation by a classical computer. The waveform generation process is generally performed based on calibration data from the most recent calibration of the quantum system that is to execute a given quantum circuit. Generally, a non-negligible amount of time and computational resources are required to perform such a waveform generation process before the quantum circuit can be executed or operate by the quantum system.

[0003] The control parameters of a quantum system deviate over time from a calibrated state, which introduces noise and other error sources into the results obtained from the execution of a quantum circuit on the quantum system. For example, a quantum circuit may include one or more gates. Through calibration, the definitions of these gates can be commanded as prescribed pulses. During the waveform generation process, these prescribed pulses can be converted into a directed graph of pulses. The head of the directed graph of pulses can be the end of the sequence of prescribed pulses, and each edge is directed in the direction of the previous pulse. Those pulses can then be scheduled to receive an exact timetable of when the pulses can be issued to the quantum system and when the issuance of the pulses is stopped. Any deviation from the calibrated state can affect that exact timetable, which in turn introduces further noise and other error sources.

[0004] Reducing such noise and other error sources generally involves calibrating the quantum system to return the control parameters to the calibrated state. When calibration occurs, any waveforms previously generated based on previous calibration data become invalid or obsolete. Rebuilding or reproducing the invalidated waveforms entirely and executing them on the recalibrated quantum system generally involves re-executing each step of the waveform generation process using new configuration data to generate updated waveforms. Modifying the invalidated waveforms without repeating each step of the waveform generation process, which generally requires a non-negligible amount of time and computational resources to execute, can achieve both error reduction and improved computational efficiency. SUMMARY OF THE INVENTION

[0005] The following presents an overview in order to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or critical elements nor to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, device, computer-implemented method, and / or computer program product that facilitate rapid waveform modification after calibration of a quantum system are described.

[0006] According to one embodiment, the system may comprise a processor that executes computer-executable components stored in a memory. The computer-executable components may include a calibration component and a playback component. The calibration component may identify parameters of a directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. The playback component may modify the directed graph based on the identified parameters to generate an updated directed graph.

[0007] According to another embodiment, a computer-implemented method may comprise the system identifying parameters of the directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. The computer-implemented method may further comprise the system modifying the directed graph based on the identified parameters to generate an updated directed graph.

[0008] According to another embodiment, a computer program product may include a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by a processor to cause the processor to perform operations. The operations may include procedures for identifying parameters of the directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. The operations may further include procedures for modifying the directed graph based on the identified parameters to generate an updated directed graph.

[0009] According to another embodiment, the computer-implemented method may comprise the step of identifying, by a system, a plurality of parameters of the directed graph that are changed by calibration of a quantum system occurring after generation of the directed graph. The computer-implemented method may further comprise the step of generating, by the system, an updated directed graph by modifying the directed graph in one pass based on the identified plurality of parameters.

[0010] According to another embodiment, the computer-implemented method may comprise the step of detecting, by a system, calibration of a quantum system that invalidates the directed graph after generation of the directed graph. The computer-implemented method may further comprise the step of identifying, by the system, parameters of the directed graph that are changed by the calibration of the quantum system. The computer-implemented method may further comprise the step of generating, by the system, an updated directed graph by modifying the directed graph based on the identified parameters. BRIEF DESCRIPTION OF THE DRAWINGS

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BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description is merely exemplary in nature and is not intended to limit embodiments, and / or the application or uses of embodiments. Further, there is no intention to be bound by any expressed or implied information presented in the foregoing background or summary sections, or in the detailed description section.

[0024] Here, one or more embodiments will be described with reference to the drawings. Throughout, like reference numerals are used to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, in various instances, it will be apparent that one or more embodiments may be practiced without these specific details.

[0025] Classical computers operate on binary numbers (or bits) that store or represent information as binary states for performing computing and information - processing functions. In contrast, quantum computing devices operate on qubits (or quantum bits) that store or represent information as both binary states and superpositions of binary states. In that regard, quantum computing devices utilize quantum - mechanical phenomena such as entanglement and interference.

[0026] Quantum computing uses qubits as its fundamental unit instead of classical computing bits. A qubit (e.g., a quantum binary number) is the quantum - mechanical analogue of a classical bit. While a classical bit can utilize only one of two basis states (e.g., 0 or 1), a qubit can be a superposition of those basis states (e.g., α|0⟩+β|1⟩), where α and β are such that |α| 2 +|β| 2It is possible to utilize a complex scalar (where = 1), whereby a certain number of qubits can, in theory, hold exponentially more information than the same number of classical bits. Therefore, a quantum computer (for example, a computer that uses qubits instead of only classical bits) can, in theory, quickly solve problems that can be extremely difficult for classical computers. The bits of a classical computer are simple binary numbers, with a value of either 0 or 1. Almost any device in two different states can function to represent a classical bit: switches, valves, magnets, coins, etc. Qubits are imbued with quantum mystery and can occupy a superposition of the 0 and 1 states. A qubit cannot have an intermediate value such as 0.63, and when the state of a qubit is measured, the result is either 0 or 1. However, during the progression of an operation, a qubit can act as if it were, for example, a mixture of 63 percent of the 0 state and 37 percent of the 1 state. A general quantum program requires the coordination of the quantum and classical parts of the operation. One way to think about a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, converting the algorithm into an executable form, performing an experiment or simulation, and analyzing the results. The concept that pervades these processes is the use of an intermediate representation. The intermediate representation (IR) of an operation is something in between its source language description or its target machine instructions. A compiler can use several IRs during the process of transforming and optimizing a program. The input is source code that describes the quantum algorithm and compile-time parameters. The output is a combination of a quantum / classical program represented using a high-level IR. The difference between a quantum computer and a classical computer is that a quantum computer is probabilistic, and therefore, the measurement of the algorithm output provides an appropriate solution within the confidence interval specific to the algorithm. The operation is then repeated until a solution with a satisfactory probability is achieved.

[0027] By processing information using the laws of quantum mechanics, quantum computers propose a new means for performing computational tasks such as molecular calculations, financial risk calculations, optimization, and more.

[0028] As described above, the control parameters of a quantum system deviate over time from a calibrated state, which introduces noise and other sources of error into the results obtained from the execution of quantum circuits on the quantum system. Reducing such noise and other sources of error generally involves calibrating the quantum system to return the control parameters to the calibrated state. When calibration occurs, any waveforms previously generated based on previous calibration data become invalid or outdated. Completely rebuilding or regenerating an invalidated waveform for execution on a recalibrated quantum system generally involves re-executing each step of the waveform generation process using new configuration data to generate an updated waveform.

[0029] Embodiments of the present disclosure describe techniques for modifying a waveform (or compiled quantum program) based on new configuration data without repeating each step of the waveform generation process to generate an updated waveform. According to one or more embodiments described herein, an existing waveform can be modified based on new configuration data using fewer computational resources than would be involved in repeating each step of the waveform generation process to generate an updated waveform. For example, calibration of a quantum system can increase or decrease the time for emitting a wave for implementing a particular gate on the quantum system. As described in more detail below, instead of repeating each step of the waveform generation process, the schedule of an existing waveform or pulse can be modified by editing the pulse duration to generate an updated waveform using embodiments of the present disclosure. Thus, embodiments of the present disclosure provide computationally efficient techniques that facilitate rapid waveform modification after calibration of a quantum system.

[0030] FIG. 1 shows a block diagram of an example of a non-limiting system 100 that can facilitate rapid waveform correction after calibration of a quantum system according to one or more embodiments described herein. System 100 includes a memory 110 for storing computer-executable components, and one or more processors 120 operatively coupled to the memory 110 via one or more communication buses 130 for executing the computer-executable components stored in the memory 110. As shown in FIG. 1, the computer-executable components include a calibration component 140 and a playback component 150.

[0031] The calibration component 140 can identify parameters of a directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. In one embodiment, the parameters include pulse phase, pulse duration, pulse frequency, pulse amplitude, gate definition, or combinations thereof. In one embodiment, the calibration component can identify the parameters using metadata associated with a plurality of specified pulses including the directed graph. In one embodiment, the calibration component can interrupt a job queue of a quantum system that includes the directed graph.

[0032] The playback component 150 may modify the directed graph based on the identified parameters to generate an updated directed graph. In one embodiment, the playback component 150 may modify the directed graph by modifying the pulses and the respective pulse frequencies of the associated pulses. In one embodiment, the playback component 150 may modify the respective pulse frequencies using a list traversal of the pulses and the associated pulses or respective hash tables. In one embodiment, the playback component 150 may modify the directed graph by inserting or removing placeholder pulses to maintain synchronization within the updated directed graph. In one embodiment, the playback component 150 may modify the directed graph by modifying the respective pulse amplitudes of the pulses and the associated pulses. In one embodiment, a subset of the directed graph may remain unchanged in the updated directed graph.

[0033] In one embodiment, the system 100 may evaluate, using a model, the computational cost associated with modifying the directed graph based on the identified parameters before the playback component 150 modifies the directed graph. In one embodiment, the model may be implemented using one or more machine-learned models trained to determine the computational cost associated with rebuilding and / or modifying the directed graph. Any artificial intelligence, machine learning, knowledge-based, or rule-based mechanism may be used to train one or more machine-learned models using training data. Examples of such mechanisms include support vector machines, neural networks, expert systems, Bayesian belief networks, fuzzy theory, data fusion engines, classifiers, and the like. The training data may be obtained from a data set including historical calibration data, historical computational cost data, or a combination thereof. In one embodiment, the system 100 may respond to an evaluation indicating that the computational cost associated with modifying the directed graph exceeds the computational cost associated with rebuilding the directed graph by rebuilding the directed graph to generate a new directed graph.

[0034] In one embodiment, the computer-executable components stored in the memory 110 may further include a tracking component 160. The tracking component 160 may monitor calibration data and detect changes that invalidate the directed graph. The functionality of the computer-executable components utilized by the embodiments is encompassed in more detail below.

[0035] FIG. 2 shows an example of a non-limiting quantum circuit 200 suitable for implementing aspects of one or more embodiments described herein. As shown by FIG. 2, the quantum circuit 200 includes a U1 gate 230 applied to a first qubit 210 and a U3 gate 240 applied to a second qubit 220. In one embodiment, the U1 gate 230 may implement a single-qubit rotation about the Z-axis of rotation, and the U3 gate 240 may implement a single-qubit rotation about three axes of rotation (e.g., the X-axis of rotation, the Y-axis of rotation, and the Z-axis of rotation). The quantum circuit 200 further includes a barrier operation 250 applied to the first qubit 210 and the second qubit 220 after the application of the U1 gate 230 and the U3 gate 240 to the first qubit 210 and the second qubit 220, respectively. In one embodiment, the barrier operation 250 facilitates maintaining separation between different gates or operations of the quantum circuit 200.

[0036] After the application of the barrier operation 250, the quantum circuit 220 includes a U1 gate 235 applied to the second qubit 220. FIG. 2 further shows that the quantum circuit 200 includes a controlled-X gate 260 applied to the first qubit 210 and the second qubit 220 after the application of the barrier operation 250, and U1 gates 235 for the first qubit 210 and the second qubit 220, respectively. In one embodiment, the controlled-X gate 260 can flip the state of the target qubit (e.g., the second qubit 220) when the control qubit (e.g., the first qubit 210) is in the |1〉 state. The quantum circuit 200 further includes a U3 gate 245 applied to the first qubit 210 after the application of the controlled-X gate 260. In the quantum circuit 200, a measurement operation 270 is applied to the first qubit 210 after the application of the U3 gate 245, and a measurement operation 275 is applied to the second qubit 220 after the application of the controlled-X gate 260.

[0037] In some embodiments, a quantum circuit (e.g., the quantum circuit 200 of FIG. 2) can be converted into a waveform for input to a quantum system that physically implements or executes the quantum circuit via waveform generation. The waveform can be a directed graph of specified pulses (or pulse trains) that includes associated metadata and a mapping of the specified pulses to the signals that a drive source applies to the quantum system to execute the quantum circuit. Waveform generation can include three steps. One of those steps can include converting high-level information that defines the quantum circuit into a directed graph of specified pulses having directed edges towards future pulses. The directed graph generated by such a conversion can be referred to as a circuit graph, which is described in more detail below with respect to FIG. 3.

[0038] Another step in waveform generation may include adding timing information to the circuit graph based on calibration data from the most recent calibration performed on the quantum system. By adding such timing information, the alignment (or matching) of the specified pulses of the circuit graph with the time slots of the signals applied by the drive source to the quantum system to execute the quantum circuit can be facilitated. In one embodiment, each time slot defines an equal time interval. When such timing information is added, the circuit graph is transformed into a graph that may be referred to as a pulse-in-time graph, which is described in more detail below with respect to FIG. 4. Generally, a pulse-in-time graph can be a directed graph having vertices that include metadata. Examples of such metadata include start time st, end time et, parent gate pg, specified pulse p, data p' of the associated pulse, and combinations thereof. In one embodiment, the quantum system can include a plurality of qubits that process the pulse-in-time graph in parallel to execute the quantum circuit.

[0039] Another step in waveform generation may include adding frequency information, information, and / or shape information to the pulse-in-time graph to facilitate the generation of the waveform. In one embodiment, the waveform can be implemented as a set of two elements {P, T}, where P is the pulse-in-time graph and T is a look-up table from the specified pulse p to the actual wave. The look-up table T can include the frequency f, amplitude a, and / or the shape of each actual wave. In one embodiment, the look-up table T can be a mapping of the specified pulse, including the associated pulse-in-time graph P, to the signal applied by the drive source to the quantum system to execute the quantum circuit. In one embodiment, the set of two elements {P, T} including the waveform can facilitate the implementation of the quantum circuit by an instruction sequence for the control electronics that drive the hardware of the quantum system.

[0040] Figure 3 shows an example of a non - limiting circuit graph 300 according to one or more embodiments described herein. In one embodiment, the circuit graph 300 may be generated by transforming the high - level information that defines the quantum circuit 200 of FIG. 2. As shown in FIG. 3, the circuit graph 300 includes a plurality of pulses each corresponding to one or more specified pulses for implementing a particular gate or operation of the quantum circuit 200. In the circuit graph 300, pulses 302 and 304 respectively correspond to C0 and C2 pulses that can be applied to the first qubit 210 to implement the U1 gate 230 of the quantum circuit 200. Pulses 316 and 318 respectively correspond to C1 and C0 pulses that can be applied to the second qubit 220 to implement the U3 gate 240 of the quantum circuit 200. Pulses 306 and 320 can be respectively applied to the first qubit 210 and the second qubit 220 to implement the barrier operation 250 of the quantum circuit 200.

[0041] In the circuit graph 300, pulses 322 and 324 of the circuit graph 300 respectively correspond to C0 and C2 pulses that can be applied to the second qubit 220 to implement the U1 gate 235 of the quantum circuit 200. Pulses 308 and 310 correspond to two C1 pulses that can be applied to the first qubit 210 to implement the controlled - X gate 260 with respect to the first qubit 210. Pulses 326, 328, and 330 respectively correspond to C1, C3, and C0 pulses that can be applied to the second qubit 220 to implement the controlled - X gate 260 with respect to the second qubit 220. Pulses 312 and 314 correspond to C1 and C0 pulses that can be applied to the first qubit 210 to implement the U3 gate 245 of the quantum circuit 200.

[0042] FIG. 4 shows an example of a non-limiting pulse time series graph 400 according to one or more embodiments described herein. In one embodiment, the pulse time series graph 400 can be generated by adding timing information to the circuit graph 300 of FIG. 3 based on calibration data from the most recent calibration performed on the quantum system to implement or execute the quantum circuit 200. Adding timing information to the circuit graph 300 can involve allocating or scheduling time slots to the pulses of the circuit graph 300 using the pulse durations of the corresponding designated pulses determined or set based on the calibration data. As an example, based on calibration data from the most recent calibration, the C0, C1, and C3 pulses can each be determined to have a pulse duration in units of one hour, and the C2 pulse can be determined to have a pulse duration in units of two hours. The time slots can be allocated to the pulses of the circuit graph 300 using those pulse durations to generate the pulse time series graph 400.

[0043] As illustrated in FIG. 4 and represented by the double arrow → with the indicator p', some of the pulses of the pulse time series graph 400 have associated pulses. In the allocation or scheduling of time slots, a pulse having an associated pulse can be allocated such that the associated pulse is scheduled to input to the quantum system simultaneously (or substantially simultaneously). For example, FIG. 4 illustrates pulses 306 and 320 as having associated pulses. Accordingly, both pulses 306 and 320 can be allocated to a time slot defined by the start time st of t3 and the end time et of t4. As another example, FIG. 4 also illustrates pulses 308 and 326 as having associated pulses. Both pulses 308 and 326, which are associated pulses, can be allocated to a time slot defined by the start time st of t7 and the end time et of t8.

[0044] Identity (or placeholder) pulses may be added or inserted into the pulse time series graph 400 to account for any gaps in time resulting from the assignment of associated pulses. For example, an identity pulse 460 may be added to the pulse time series graph 400 to account for the gap in time between pulse 318 and pulse 320 resulting from the assignment of associated pulses 306 and 320. As shown by FIG. 4, the pulse time series graph 400 further includes identity pulses 440, 450, and 470 added to account for similar gaps in time.

[0045] In one embodiment, adding or inserting an identity pulse may involve qubit q i encountering a pulse p having an associated pulse p' on another qubit q j . In response, a start time of t i may be proposed to schedule pulse p for qubit qi. When qubit q j encounters the associated pulse p', a start time of t j may be proposed to schedule the associated pulse p'. Pulses p and the associated pulse p' may be scheduled in the pulse time series graph at a proposed start time that occurs at a later time (e.g., t i or t j ). An identity pulse having a pulse duration of |t i - t j | may be inserted in the pulse time series graph before the pulse (e.g., pulse p or the associated pulse p') corresponding to the proposed start time that occurs at an earlier time.

[0046] For example, the first qubit 210 may encounter a pulse 308 having an associated pulse (i.e., pulse 326) on the second qubit 220. In response thereto, a start time of t4 may be proposed to schedule the pulse 308 on the first qubit 210. When the second qubit 220 encounters the pulse 326, a start time of t7 may be proposed to schedule the pulse 326 to facilitate the scheduling of pulses 322 and 324. Pulses 308 and 326 may be scheduled to a proposed start time (i.e., t7) that occurs at a later time in the pulse time series graph 400. An identity pulse 440 having a pulse duration of three time units (i.e., |t4 - t7|) may be inserted before the pulse 308 in the pulse time series graph 400.

[0047] When generating the pulse time series graph 400 by adding timing information to the circuit graph 300 of FIG. 3, the pulse time series graph 400 may be added to the job queue of the quantum system that stores the existing directed graph. After the generation of the pulse time series graph 400, existing waveforms or directed graphs, such as the directed graph stored in the job queue, may become invalid due to the calibration of the quantum system. One or more parameters of the pulse time series graph 400 may be changed by that calibration of the quantum system.

[0048] For example, the calibration of a quantum system may change the pulse frequencies associated with the C1 and C2 pulses of the pulse time series graph 400. Based on the calibration data available when the pulse time series graph 400 was generated, the pulse frequencies associated with the C1 and C2 pulses were each set to 2 Hertz (Hz). However, based on new configuration data from a calibration that invalidated the pulse time series graph 400, the pulse frequencies associated with the C1 and C2 pulses should each be set to 3 Hz. Instead of repeating each step of the waveform generation process above, the pulse time series graph 400 may be modified based on the new configuration data to generate an updated pulse time series graph 500 of FIG. 5. In one embodiment, the pulses associated with the parameters (e.g., pulse frequency) of the invalidated pulse time series graph that are changed by the calibration of the quantum system occurring after the generation of the directed graph may be identified for modification using a traversal of a list of those pulses (e.g., using lookup table T) or a hash table.

[0049] A comparison of FIGS. 4 and 5 shows that each pulse of the pulse time series graph 400 corresponding to the C1 or C2 pulse has been modified to include a pulse frequency of 3 Hz. For example, the pulse time series graph 400 includes pulses 308, 310, 312, 316, and 326 each corresponding to a C1 pulse including a pulse frequency of 2 Hz; and pulses 304 and 324 each corresponding to a C2 pulse including a pulse frequency of 2 Hz. The pulse frequency of each of those pulses of the pulse time series graph 400 corresponding to the C1 or C2 pulse is modified from 2 Hz to 3 Hz to generate an updated pulse time series graph 500. As shown in FIG. 5, a subset of the pulse time series graph 400 (e.g., pulses 302, 314, 320, and 328) remains unchanged in the updated pulse time series graph 500. Only the pulses corresponding to the C1 pulse (e.g., pulses 508, 510, 512, 516, and 526) or the pulses corresponding to the C2 pulse (e.g., pulses 504 and 524) are changed in the updated pulse time series graph 500.

[0050] As another example, the calibration of the quantum system may change the pulse amplitudes associated with the C0 and identity (or placeholder) pulses of the pulse time series graph 400. Based on the calibration data available when the pulse time series graph 400 was generated, the pulse amplitudes associated with the C0 and identity pulses were each set to 0.1 volts (V). However, based on the new configuration data from the calibration that invalidated the pulse time series graph 400, the pulse amplitudes associated with the C0 and identity pulses should each be set to 0.2 V. Instead of repeating each step of the waveform generation process above, the pulse time series graph 400 may be modified based on the new configuration data to generate the updated pulse time series graph 600 of FIG. 6.

[0051] A comparison of FIGS. 4 and 6 shows that each pulse of the pulse time series graph 400 corresponding to the C0 or identity pulse has been modified to include a pulse amplitude of 0.2 V. For example, the pulse time series graph 400 includes pulses 302, 314, 318, 322, and 330 each corresponding to a C0 pulse with a pulse amplitude of 0.1 V; and pulses 440, 450, 460, and 470 each corresponding to an identity pulse with a pulse amplitude of 0.1 V. The pulse amplitude of each of those pulses of the pulse time series graph 400 corresponding to the C0 or identity pulse is modified from 0.1 V to 0.2 V to generate the updated pulse time series graph 600. As shown in FIG. 6, a subset of the pulse time series graph 400 (e.g., pulses 304, 310, 320, and 326) remains unchanged in the updated pulse time series graph 600. Only the pulses corresponding to the C0 pulse (e.g., pulses 602, 614, 618, 622, and 630) or the pulses corresponding to the identity pulse (e.g., pulses 640, 650, 660, and 670) are changed in the updated pulse time series graph 600.

[0052] As another example, the calibration of the quantum system may change the pulse duration associated with the C2 pulse of the pulse time series graph 400. Based on the calibration data available when the pulse time series graph 400 was generated, the pulse duration associated with the C2 pulse was set in 2-hour units. However, based on the new configuration data from the calibration that invalidated the pulse time series graph 400, the pulse duration associated with the C2 pulse should be set in 1-hour units. Instead of repeating each step of the waveform generation process described above, the pulse time series graph 400 may be modified based on the new configuration data to generate the updated pulse time series graph 700 of FIG. 7.

[0053] To generate the updated pulse time series graph 700, each identity pulse inserted into the pulse time series graph 400 may be removed. Accordingly, the identity pulses 440, 450, 460, and 470 may each be removed from the pulse time series graph 400 to generate the updated pulse time series graph 700. When removing the inserted identity pulses, when the C2 pulse is encountered for the first time on a particular qubit (e.g., at t i ), the end time of the C2 pulse (e.g., t i+1 ) is set 1 hour after the corresponding start time. For example, pulse 304 is the first time the C2 pulse is encountered on the first qubit 210, which is at t1. The end time of pulse 304 in the pulse time series graph 400 is set to t3. In the updated pulse time series graph 700, the start time of pulse 704 corresponding to that C2 pulse remains t1. However, the end time of pulse 704 has been corrected from t3 to t2 to reflect the updated 1-hour pulse duration for the C2 pulse. Similarly, pulse 324 in the pulse time series graph 400 is the first time the C2 pulse is encountered on the second qubit 220. In the updated pulse time series graph 700, the end time of pulse 724 has been similarly corrected to reflect the updated 1-hour pulse duration for the C2 pulse.

[0054] The downstream portion of the pulse time series graph 400, including each future gate or operation scheduled after the C2 pulse for the first qubit 210 (e.g., pulses 308, 310, 312, and 314) or the second qubit 220 (e.g., pulses 326, 328, and 330), is rescheduled according to the respective end times of pulses 704 and 724. Those future gates or operations can be rescheduled, while ensuring that the associated pulses remain scheduled to enter the quantum system simultaneously (or substantially simultaneously), as shown in FIG. 7. After rescheduling those future gates or operations, identity (or placeholder) pulses can be added or inserted into the updated pulse time series graph 700 to account for any gaps in time resulting from the assignment of the associated pulses, as described above with respect to FIG. 4. In FIG. 7, such identity pulses inserted into the updated pulse time series graph 700 include pulses 740, 750, and 770. The foregoing disclosure regarding changes in pulse duration resulting from calibration of the quantum system has been described in terms of a reduction in pulse duration. However, one of ordinary skill in the art will recognize that the disclosed techniques can be applied equally to an increase in pulse duration resulting from calibration of the quantum system.

[0055] As another example, the calibration of the quantum system may change the gate definition of each U1 gate (e.g., UI gates 230 and 235 of FIG. 2) implemented by the pulses of the pulse time series graph 400. Based on the calibration data available when the pulse time series graph 400 was generated, the gate definition for implementing the U1 gate involved applying a pulse sequence including a C0 pulse followed by a C2 pulse to the qubit to implement the U1 gate. However, based on the new configuration data from the calibration that invalidated the pulse time series graph 400, the gate definition for implementing the U1 gate involves applying a C0 pulse to the qubit to implement the U1 gate. Instead of repeating each step of the waveform generation process described above, the pulse time series graph 400 may be modified based on the new configuration data to generate the updated pulse time series graph 800 of FIG. 8.

[0056] To generate the updated pulse time series graph 800, each identity pulse inserted into the pulse time series graph 400 may be removed. Accordingly, identity pulses 440, 450, 460, and 470 may each be removed from the pulse time series graph 400 to generate the updated pulse time series graph 800. When removing the inserted identity pulses, each pulse of the pulse time series graph 400 implementing the U1 gate is identified. In one embodiment, each pulse of the invalidated pulse time series graph implementing the gate associated with the changed gate definition may be identified for modification using a traversal of a list of those pulses (e.g., using lookup table T) or a hash table. Each pulse of the pulse time series graph 400 implementing the U1 gate (e.g., pulses 302 and 304 for implementing U1 gate 230; and pulses 322 and 324 for implementing U1 gate 235) may be removed and replaced with pulses that conform to the new gate definition (e.g., pulse 802 for implementing U1 gate 230 and pulse 822 for implementing U1 gate 235).

[0057] For each future gate or operation scheduled after the U1 gate for the first qubit 210 (e.g., pulses 306, 308, 310, 312, and 314) or the second qubit 220 (e.g., pulses 326, 328, and 330), the downstream portion of the pulse time series graph 400 is rescheduled according to the respective end times of pulses 802 and 822. Those future gates or operations may be rescheduled, while ensuring that the associated pulses remain scheduled to input to the quantum system simultaneously (or substantially simultaneously), as shown in FIG. 8. After rescheduling those future gates or operations, identity (or placeholder) pulses may be added or inserted into the updated pulse time series graph 800 to account for any gaps in time resulting from the assignment of the associated pulses, as described above with respect to FIG. 4. In FIG. 8, such identity pulses inserted into the updated pulse time series graph 800 include pulses 840, 850, 870, and 880.

[0058] FIG. 9 shows a flowchart of an example of a non-limiting computer-implemented method 900 for facilitating waveform correction after calibration of a quantum system, according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity.

[0059] At 910, the computer-implemented method 900 may include identifying, by a system (e.g., the calibration component 140 of FIG. 1), parameters of a directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. In one embodiment, the parameters include pulse phase, pulse duration, pulse frequency, pulse amplitude, gate definition, or combinations thereof. In one embodiment, the system may identify the parameters using metadata associated with a plurality of specified pulses that include the directed graph.

[0060] At 920, computer-implemented method 900 may include a step of modifying a directed graph based on identified parameters by a system (e.g., playback component 150 of FIG. 1) to generate an updated directed graph. In one embodiment, the system may modify the directed graph by modifying the pulse frequency of a pulse. In one embodiment, the system may modify the pulse frequency using a pulse list traversal or a hash table. In one embodiment, the system may modify the directed graph by inserting or removing placeholder pulses to maintain synchronization within the updated directed graph. In one embodiment, the system may modify the directed graph by modifying the pulse amplitude of a pulse.

[0061] In one embodiment, computer-implemented method 900 may further include a step of monitoring calibration data by a system (e.g., tracking component 160 of FIG. 1) to detect changes that invalidate the directed graph. In one embodiment, computer-implemented method 900 may further include a step of interrupting a job queue of a quantum system including the directed graph by a system (e.g., calibration component 140).

[0062] FIG. 10 shows a flowchart of another example of a non - limiting computer - implemented method 1000 for facilitating waveform correction after calibration of a quantum system, according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. At 1010, the computer - implemented method 1000 may include identifying, by a system (e.g., the calibration component 140 of FIG. 1), a plurality of parameters of a directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. For example, the system may identify a pulse phase and a pulse duration associated with the directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. As another example, the system may identify a pulse amplitude and a pulse frequency associated with the directed graph that are changed by calibration of a quantum system that occurs after generation of the directed graph. At 1020, the computer - implemented method 1000 may include generating, by a system (e.g., the playback component 150 of FIG. 1), an updated directed graph by modifying the directed graph in one pass based on the identified plurality of parameters. In one embodiment, a subset of the directed graph remains unchanged in the updated directed graph.

[0063] FIG. 11 shows a flowchart of another example of a non - limiting computer - implemented method 1100 for facilitating waveform correction after calibration of a quantum system, according to one or more embodiments described herein. Repeated descriptions of similar elements utilized in other embodiments described herein are omitted for brevity. At 1110, the computer - implemented method 1100 may include detecting, by a system (e.g., the tracking component 160 of FIG. 1), a calibration of a quantum system that invalidates a directed graph after generation of the directed graph.

[0064] At 1120, the computer-implemented method 1100 may include a step of identifying, by a system (e.g., the calibration component 140 of FIG. 1), parameters of a directed graph that are changed by calibration of a quantum system occurring after generation of the directed graph. In one embodiment, the system may identify the parameters using metadata associated with a plurality of specified pulses including the directed graph. At 1130, the computer-implemented method 1100 may further include a step of modifying, by a system (e.g., the playback component 150 of FIG. 1), the directed graph based on the identified parameters to generate an updated directed graph. In one embodiment, a subset of the directed graph remains unchanged in the updated directed graph.

[0065] In one embodiment, the computer-implemented method 1100 may further include a step of evaluating, by the system, using a model, a computational cost associated with modifying the directed graph based on the identified parameters before modifying the directed graph. In one embodiment, the computer-implemented method 1100 may further include a step of rebuilding the directed graph to generate a new directed graph in response to an evaluation indicating that the computational cost associated with modifying the directed graph exceeds the computational cost associated with rebuilding.

[0066] To provide context for the various aspects of the disclosed subject matter, FIGS. 12 and the following description are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter may be implemented. Referring to FIG. 12, a suitable operating environment 1200 for implementing the various aspects of the present disclosure may also include a computer 1212. The computer 1212 may also include a processing unit 1214, a system memory 1216, and a system bus 1218. The system bus 1218 couples system components including, but not limited to, the system memory 1216 to the processing unit 1214. The processing unit 1214 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be utilized as the processing unit 1214. The system bus 1218 may use any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Cardbus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (R) (IEEE1094), Small Computer System Interface (SCSI), a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus, in any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus. The system memory 1216 may also include volatile memory 1220 and nonvolatile memory 1222. A basic input / output system (BIOS) containing basic routines for transferring information between elements within the computer 1212 during startup, such as, is stored in the nonvolatile memory 1222. By way of example and not limitation, the nonvolatile memory 1222 may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)).Volatile memory 1220 may also include a random access memory (RAM) that operates as an external cache memory. By way of example and not limitation, the RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0067] Computer 1212 may also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 12 shows, for example, disk storage 1224. Disk storage 1224 may also include devices such as, but not limited to, magnetic disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 1224 may also include storage media separately or in combination with other storage media, and the other storage media may include, but are not limited to, optical disk drives such as compact disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital versatile disc ROM drives (DVD-ROM). To facilitate connection of disk storage 1224 to system bus 1218, a removable or non-removable interface such as interface 1226 is typically used. FIG. 12 also illustrates software that operates as an intermediary between a user and the basic computer resources described in a suitable operating environment 1200. Such software may also include, for example, operating system 1228. Operating system 1228 stored on disk storage 1224 operates to control and allocate resources of computer 1212. System applications 1230 utilize the resource management by operating system 1228 through program modules 1232 and program data 1234 stored in either system memory 1216 or disk storage 1224, for example. It should be recognized that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user inputs commands or information into computer 1212 through input device 1236.The input device 1236 includes pointing devices such as, but not limited to, a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, television tuner card, digital camera, digital video camera, web camera, etc. These and other input devices are connected to the processing unit 1214 through the system bus 1218 via the interface port 1238. The interface port 1238 includes, for example, a serial port, parallel port, game port, Universal Serial Bus (USB). The output device 1240 uses some of the same type of ports as the input device 1236. Thus, for example, a USB port can be used to provide input to the computer 1212 and to output information from the computer 1212 to the output device 1240. An output adapter 1242 is provided to indicate that among several other output devices 1240 that require a special adapter, there are some output devices 1240 such as a monitor, speaker, and printer. The output adapter 1242 includes, by way of example and not limitation, video and sound cards that provide connection means between the output device 1240 and the system bus 1218. It may be noted that other devices and / or systems of devices provide both input and output capabilities, such as the remote computer 1244.

[0068] Computer 1212 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1244. Remote computer 1244 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device, or other common network node, etc., and can typically include many or all of the elements described with respect to computer 1212. For the sake of brevity, only memory storage device 1246 is shown with remote computer 1244. Remote computer 1244 is logically connected to computer 1212 through network interface 1248 and then physically connected via communication connection 1250. Network interface 1248 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet (registered trademark), token ring, etc. WAN technologies include, but are not limited to, circuit switched networks such as point-to-point links, integrated services digital network (ISDN (registered trademark)) and its variations, packet switching networks, and digital subscriber line (DSL). Communication connection 1250 refers to the hardware / software used to connect network interface 1248 to system bus 1218. For purposes of illustration, communication connection 1250 is shown inside computer 1212, but it can also be outside computer 1212. The hardware / software for connecting to network interface 1248 can also include internal and external technologies such as, for purposes of illustration only, normal telephone grade modems, cable modems, modems including DSL modems, ISDN adapters, Ethernet cards, etc.

[0069] The present invention can be a system, method, apparatus, and / or computer program product at any possible technical detail level of integration. The computer program product can include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to execute aspects of the present invention. The computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium can be, but is not limited to, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium can also include a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. The computer-readable storage medium should not be construed to be a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire, as used herein.

[0070] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing devices, or may be downloaded from an external computer or an external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out operations of the present invention may be source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk (registered trademark), C++, or the like, and conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet service provider).In some embodiments, to carry out aspects of the present invention, an electronic circuit, for example, including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by personalizing the electronic circuit using state information of the computer-readable program instructions.

[0071] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions / acts specified in the block or blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium containing the instructions comprises an article of manufacture including instructions which implement the function / act specified in the block or blocks of the flowchart and / or block diagram. The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the block or blocks of the flowchart and / or block diagram.

[0072] Flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions described in the blocks may occur in a different order than shown in the figures. For example, in fact, two blocks shown consecutively may be executed substantially simultaneously, depending on the functionality involved, or the blocks may, in some cases, be executed in the reverse order. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks of the block diagrams and / or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or a combination of dedicated hardware and computer instructions.

[0073] The subject matter has been described above in the general context of computer-executable instructions of a computer and / or a computer program product that runs on a computer or computers, but one of ordinary skill in the art will recognize that the present disclosure may also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Further, one of ordinary skill in the art will recognize that the computer-implemented methods of the present invention may be implemented in other computer system configurations including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs (registered trademark), telephones), microprocessor-based or programmable consumer or industrial electronic devices, and the like. The illustrated aspects may also be implemented in a distributed computing environment where tasks are performed by remote processing devices connected via a communications network. However, although not all, some aspects of the present disclosure may be implemented on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from memory that may include, or be constituted of, one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Further, one or more embodiments described herein may execute the code of computer-executable components in a distributed fashion (e.g., a plurality of processors that cooperate to combine or operate to execute code from one or more distributed memory units). As used herein, the term "memory" may include single memory or memory unit at one location, or multiple memories or memory units at one or more locations.

[0074] As used herein, terms such as "component", "system", "platform", "interface" may refer to and / or include a computer-related entity, or an entity related to an operating machine having one or more specific functionalities. The entities disclosed herein may be any of hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. By way of example, both an application running on a server and the server may be components. One or more components may be present within a process and / or thread of execution, and a component may be localized on one computer and / or distributed between two or more computers. In another example, each component may execute from various computer-readable media storing various data structures. A component may communicate through local and / or remote processes according to, for example, one or more data packets (e.g., data from one component interacting with another component in a network such as a local system, a distributed system, and / or the Internet via signals). As another example, a component may be a device having specific functionality provided by mechanical parts operating by an electrical or electronic circuit that operates by software or a firmware application executed by a processor. In such a case, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component can be a device that provides unique functionality through electronic components without using mechanical parts, and the electronic components can include a processor or other means for executing software or firmware that at least partially provides the functionality of the electronic components. In some aspects, a component can emulate the electronic components, for example, via a virtual machine within a cloud computing system.

[0075] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, "X uses A or B" is satisfied under any of the foregoing examples when X uses A, X uses B, or X uses both A and B. Further, the articles "a" and "an" as used in this specification and the appended drawings are generally to be construed to mean "one or more" unless otherwise specified or clear from the context that they are intended to refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean an example, instance, or serves as an illustration. To avoid doubt, the subject matter disclosed herein is not limited to such examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as more preferred or advantageous than other aspects or designs, nor is there any intention to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0076] As used herein, the term "processor" may refer to substantially any computing processing unit or device, including but not limited to a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, the processor may utilize nanoscale architectures such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates to optimize space utilization or enhance the performance of the user equipment. The processor may also be implemented as a combination of computing processing units. In the present disclosure, terms such as "store", "storage", "data store", "data storage", "database" and substantially any other information storage component related to the operation and functionality of the components are used to refer to a "memory component" entity embodied in a "memory" or a component including a memory. It should be recognized that the memory and / or memory component described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that may operate as an external cache memory. By way of example and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of the systems or computer-implemented methods herein are intended to include these and any other suitable types of memory, but are not limited thereto.

[0077] The foregoing are merely examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for the purposes of explaining the present disclosure, but one of ordinary skill in the art will recognize that many additional combinations and permutations of the present disclosure are possible. Further, as used in the detailed description, claims, the accompanying drawings, and the like, terms such as "including," "having," "comprising," and the like are intended to be inclusive in a manner similar to the way the term "comprising" is construed when utilized as a transitional phrase in a claim.

[0078] The descriptions of the various embodiments are presented for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, the practical application of technology found in the marketplace, or the technical improvement thereof, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A processor that executes the following computer-executable components stored in a memory: A calibration component that identifies parameters of the directed graph that are changed by calibration of the quantum system occurring after generation of the directed graph, including mapping of pulses corresponding to signals applied to the quantum system; and A playback component that modifies the directed graph based on the identified parameters to generate an updated directed graph A system comprising.

2. The system according to claim 1, wherein the parameters include: pulse phase of the pulse; pulse duration of the pulse; pulse frequency of the pulse; pulse amplitude of the pulse; gate definition; or a combination thereof.

3. The system according to claim 1 or 2, wherein the calibration component identifies the parameters using metadata associated with a plurality of specified pulses including the directed graph.

4. The system according to any one of claims 1 to 3, wherein the playback component modifies the directed graph by modifying the pulse frequency of the pulse.

5. The system according to claim 4, wherein the playback component modifies the pulse frequency using a pulse list traversal or hash table of the pulse.

6. The system according to any one of claims 1 to 5, wherein the playback component modifies the directed graph by inserting or removing placeholder pulses that occupy any gaps in time caused by the assignment of the pulses, to maintain synchronization within the updated directed graph.

7. The system according to any one of claims 1 to 6, wherein the playback component modifies the directed graph by modifying the pulse amplitude of the pulse.

8. A tracking component that monitors calibration data to detect changes that invalidate the directed graph The system according to any one of claims 1 to 7, further comprising.

9. The system according to any one of claims 1 to 8, wherein the calibration component interrupts a job queue of the quantum system including the directed graph.

10. identifying, by the system, parameters of the directed graph that are changed by calibration of the quantum system occurring after generation of the directed graph, including mapping of pulses corresponding to signals applied to the quantum system; and modifying, by the system, the directed graph based on the identified parameters to generate an updated directed graph A computer-implemented method comprising:

11. The computer-implemented method according to claim 10, wherein the parameters include: pulse phase of the pulse; pulse duration of the pulse; pulse frequency of the pulse; pulse amplitude of the pulse; gate definition; or a combination thereof.

12. The computer-implemented method according to any one of claims 10 to 11, wherein the system identifies the parameters using metadata associated with a plurality of specified pulses including the directed graph.

13. The computer-implemented method according to any one of claims 10 to 12, wherein the system modifies the directed graph by modifying the pulse frequency of the pulse.

14. The computer-implemented method according to claim 13, wherein the system modifies the pulse frequency using a pulse list traversal or a hash table of the pulses.

15. The computer-implemented method according to any one of claims 10 to 14, wherein the system modifies the directed graph by inserting or removing placeholder pulses that occupy any gaps in time caused by the assignment of the pulses to maintain synchronization within the updated directed graph.

16. The computer-implemented method according to any one of claims 10 to 15, wherein the system modifies the directed graph by modifying the pulse amplitude of the pulse.

17. further comprising, by the system, monitoring calibration data to detect changes that invalidate the directed graph The computer-implemented method according to any one of claims 10 to 16.

18. further comprising, by the system, interrupting a job queue of the quantum system including the directed graph The computer-implemented method according to any one of claims 10 to 17.

19. To a processor: A procedure for identifying parameters of the directed graph that are changed by calibration of the quantum system occurring after generation of the directed graph, including mapping of pulses corresponding to signals applied to the quantum system; and A procedure for modifying the directed graph based on the identified parameters to generate an updated directed graph A computer program for causing execution.

20. The computer program according to claim 19, wherein the parameters include: the pulse phase of the pulse; the pulse duration of the pulse; the pulse frequency of the pulse; the pulse amplitude of the pulse; a gate definition; or a combination thereof.

21. A stage in which a system identifies a plurality of parameters of the directed graph that are changed by calibration of the quantum system occurring after generation of the directed graph, including mapping of pulses corresponding to signals applied to the quantum system; and A stage in which the system modifies the directed graph in one pass based on the identified plurality of parameters to generate an updated directed graph A computer-implemented method comprising.

22. The computer-implemented method according to claim 21, wherein a subset of the directed graph remains unchanged in the updated directed graph.

23. A stage in which a system detects calibration of the quantum system that invalidates the directed graph after generation of the directed graph, including mapping of pulses corresponding to signals applied to the quantum system; A stage in which the system identifies parameters of the directed graph that are changed by the calibration of the quantum system; and A stage in which the system modifies the directed graph based on the identified parameters to generate an updated directed graph A computer-implemented method comprising.

24. The computer-implemented method according to claim 23, wherein the system identifies the parameters using metadata associated with a plurality of specified pulses including the directed graph.

25. A stage in which the system uses a model to evaluate the computational cost associated with modification of the directed graph based on the identified parameters before modifying the directed graph; and In response to an evaluation indicating that the computational cost associated with the modification of the directed graph exceeds the computational cost associated with a rebuild, the system performs the rebuild of the directed graph to generate a new directed graph The computer-implemented method according to any one of claims 23 to 24, further comprising

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