Transferable pillar structure for a fan-out package or an interconnect bridge

Abstract

A pillar structure is provided that includes a plurality of pillars, each of which has a capping material layer formed in a pit etched in a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attachment material layer formed on the base layer, the pillars being coupled to each other in a vertical direction to form the pillar structure.

Description

Technical Field

[0001] The present invention relates to the fields of electrical, electronic, and semiconductor devices. More particularly, the present invention relates to a transferable pillar structure for fan-out packages or interconnect bridges for articles such as semiconductor integrated circuit (IC) chips, and a method of forming the pillar structure.

[0002] A typical semiconductor integrated circuit (IC) chip has layers in which layer features are stacked on top of each other to form individual devices and stacked to connect the devices to each other. ICs are mass-produced by forming an array of chips on a thin semiconductor wafer. Each array position is known as a die, and each die can accommodate a multilayer structure such as an IC chip or a structure for testing or alignment.

[0003] As transistor technology has evolved, chip features and devices have become increasingly smaller, generally having minimum dimensions well below 1 micrometer (1 μm) or 1 micron. The smaller the chip features and devices, the more functionality IC manufacturers can integrate within the same physical chip footprint. A typical IC can include billions of transistors wired together to provide chip functionality. Further, the IC circuit can include micromachine structures such as microsensors or other microelectromechanical systems (MEMS) structures. Typical MEMS structures such as the formation of cantilevers and membranes have been formed by stacking multiple interlayer via layers under a surface wiring structure and undercutting the surface wiring without damaging surrounding features.

[0004] Generally, probe-style off-chip pads for connecting chip power and input / output (I / O) signals are implemented on the surface layer of each completed chip or die. Increasing the function of packing each die generally means increasing the I / O signals provided to each die on one side (top) or to the three-dimensional (3D) chip structure on both sides (top and bottom). Each die has at least one surface pad for each I / O signal and several power (supply and ground) connection pads. As the size of the die is reduced, these I / O signals and supplies are provided, leading to more stringent off-chip I / O connection requirements, that is, an even more densely packed I / O pad array. On a typical state-of-the-art IC wafer, for example, thousands of connection pads may be densely packed on the surface layer of each die. To achieve this, ultra-fine pitch pads with a very dense pitch of less than 50 microns (<50μm) are required.

[0005] For the heterogeneous integration of multiple chips within a package, it is often desirable to incorporate a silicon bridge structure above the laminate to provide fine pitch wiring for connecting two or more active dies. This structure may require multiple electrical interconnects of two different heights and, in some cases, different lateral sizes. Some interconnects may require a high aspect ratio structure (i.e., a large height-to-pitch ratio). Additionally, face-to-face interconnects may be required between two different pitches. SUMMARY OF THE INVENTION

[0006] Embodiments of the present invention relate to a pillar structure. The pillar structure includes a plurality of pillars. Each of the plurality of pillars has a capping material layer formed in a pit etched in a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and a mounting material layer formed on the base layer. These pillars are coupled to each other in the vertical direction to form a pillar structure.

[0007] Other embodiments of the present invention relate to a method of forming a pillar structure. The method includes forming a plurality of pillars, each pillar being formed by forming a capping material layer in a pit etched in a template wafer, forming a conductive plug on the capping material layer, forming a base layer on the conductive plug, and forming a mounting material layer on the base layer; and coupling the plurality of pillars vertically to each other to form a pillar structure.

[0008] Other embodiments relate to a bridge structure. The bridge structure includes a substrate; a bridge formed on the substrate; a plurality of pillar stacks formed on the substrate, each pillar stack having a plurality of pillars formed overlapping each other, each pillar including a capping material layer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and a mounting material layer formed on the base layer; and a plurality of chips formed on top of the pillar stacks.

[0009] The above summary is not intended to describe every illustrated embodiment or every implementation of the present invention.

Brief Description of the Drawings

[0010] The drawings included in this application are incorporated herein and form a part hereof. They illustrate embodiments of the present invention and, together with the description, explain the principles of the present invention. The drawings are only examples of specific embodiments and do not limit the present invention.

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[0044] It should be understood that the elements in the drawings are shown for simplicity and clarity. For simplicity, and to aid in the understanding of the illustrated embodiments, well-understood elements that may be useful or necessary in commercially realizable embodiments may not be shown.

DETAILED DESCRIPTION OF THE INVENTION

[0045] The present disclosure describes a pillar structure that can be used in conjunction with a fan-out structure or an interconnect bridge. Specifically, the present disclosure describes a pillar structure that includes a plurality of pillars. Each of the pillars includes a capping material layer formed in a pit etched in a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attachment material layer formed on the base layer. These pillars are joined together in the longitudinal direction to form a pillar structure. The pillars can be stacked on top of each other to form a pillar structure of a desired total height, and the pillar structure can be used within a fan-out structure or an interconnect bridge.

[0046] Various embodiments of the present invention are described herein with reference to the accompanying drawings. It is also possible to devise alternative embodiments without departing from the scope of the present invention. Note that in the following description and in the drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described. These connections and / or positional relationships may be direct or indirect, unless otherwise specified, and the present disclosure is not intended to be limited in this regard. Thus, the coupling between entities can refer to a direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, when it is said in this description that layer "A" is formed on layer "B", one or more intermediate layers (e.g., layer "C") are present between layer "A" and layer "B", provided that the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by that intermediate layer.

[0047] The following definitions and abbreviations are used in the interpretation of the claims and the specification. As used herein, the words "comprises", "comprising", "includes", "including", "has", "having", "contains" or "containing", or any other variant thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not explicitly listed, or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0048] For the purposes of the following description, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the orientation within the drawing and to the structures and methods being described. Phrases such as "overlaying", "on top of", "at the top of", "positioned on", or "positioned on top of" shall mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements, such as an interface structure, may be present between the first and second elements. Phrases such as "in direct contact" shall mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intervening conductive, insulating, or semiconductor layer at the interface of the two elements. For example, it should be noted that phrases such as "is selective with respect to" mean that the first element is etchable and the second element is capable of acting as an etch stop.

[0049] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Further, the various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. Specifically, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, many conventional steps are only briefly described herein or are omitted entirely without providing well-known process details for the sake of brevity.

[0050] Generally, the various processes used to form microchips that are packaged into ICs are included in four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0051] Deposition is any process of growing, coating, or transferring material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Another deposition technique is plasma enhanced chemical vapor deposition (PECVD), which is a process that uses the energy within a plasma to induce reactions on the wafer surface that would normally require higher temperatures associated with conventional CVD. It is also possible to improve the electrical and mechanical properties of the film through energetic ion bombardment during PECVD deposition.

[0052] Removal / etching is any process of removing material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by means of physical inert gas and / or chemical reactive gas. Like other plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a highly chemically reactive plasma to remove material deposited on a wafer. With RIE, a plasma is generated by an electromagnetic field under low pressure (vacuum). High energy ions from the RIE plasma collide with and react with the wafer surface to remove the material.

[0053] Semiconductor doping, for example, involves changing the electrical properties of the source and drain of a transistor, generally by doping through diffusion and / or ion implantation. Following these doping steps, furnace annealing or rapid thermal annealing ("RTA") is performed. Annealing serves to activate the implanted dopants. To connect and isolate transistors and their components, films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon oxide, silicon nitride, etc.) are used. Selective doping of various regions of the semiconductor substrate enables changing the conductivity of the substrate by applying a voltage. By creating the structures of these various components, millions of transistors can be built and interconnected to form the complex circuits of modern microelectronic devices.

[0054] Semiconductor lithography involves forming a three-dimensional relief image or pattern on a semiconductor substrate, which is then performed to transfer the pattern to the substrate. In semiconductor lithography, a pattern is formed by a photosensitive polymer called a photoresist. To build the complex structures for making transistors and the many wires connecting the millions of transistors in a circuit, the steps of lithography and etching pattern transfer are repeated multiple times. Each pattern during printing onto the wafer is aligned with the patterns formed before it, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0055] Referring now to an overview of the technology specifically related by aspects of the present invention, there are two methods for creating tall (i.e., high aspect ratio) interconnects, each of which has certain drawbacks. One of these methods uses Cu balls, which are dropped, sieved, and soldered at a height-to-width ratio of 1 to form spheres. The other of these methods uses plated Cu pillars, which are generally plated on the die. In this second method, the aspect ratio of the height to width of the pillars is at most 2:1 to 3:1. In this second method, there is a basic limitation of plating through a patterned wet film mask or dry film mask.

[0056] This embodiment uses a release process to transfer a plated pillar structure from another substrate to the die. By transferring the selected area, the pillars are placed only in the required areas. Further, in certain embodiments, the required area for selective transfer is the area including the capture pads. In other words, the pillars are transferred only when there are corresponding capture pads. Also, by using a flip chip bonding process, multiple transfers can be performed to create a high aspect ratio structure with an accurate height by lithography control. This height can be controlled using a flip chip bonder in position mode. Further, this height can be controlled by making multiple tips act as "stops" with solder layers placed here and there.

[0057] For the heterogeneous integration of multiple chips within a package, it is often desirable to incorporate a silicon bridge structure above the laminate to provide fine pitch wiring for connecting two or more active dies. This structure may require multiple electrical interconnects of two different heights and, in some cases, different lateral sizes. Some interconnects may require a high aspect ratio structure, i.e., a large height-to-pitch ratio. It may also be necessary to have face-to-face interconnects between two different pitches. Considering these challenges in constructing a package having an interconnect bridge that may need to account for different pitches and heights for each chip, embodiments of the present invention use a transferable pillar structure to accurately adjust the size of the pillar features to create an offset for the bridge structure.

[0058] This embodiment utilizes a transferable pillar method of creating a pillar structure on an independent substrate and selectively transferring the structure to a desired package to form an offset for the chips within the fan-out package or bridge structure. This process can be repeated to further increase the overall height of the pillar structure without being limited by the aspect ratio.

[0059] Referring now to the drawings, and initially to FIG. 1A, this figure is a cross-sectional view of an example of a template wafer having pits provided at the protrusion positions in an intermediate stage of a manufacturing process according to an embodiment. Certain steps of the following steps include an electrochemical plating process step within the manufacturing process. As shown in FIG. 1A, the template wafer 100 has pits 105 provided at at least one protrusion position 103 (see also FIG. 1B), and is covered with a low-adhesion surface layer or seed layer 102 that covers each pit 105. Although a single pit 105 is shown in FIG. 1A, it should be understood that the template wafer 100 may include multiple pits 105. The covered pits 105 provide a non-planar surface that causes local current concentration within each pit 105 to assist in nucleation within the pits 105 without adversely affecting current stability, because this enables continuous power supply due to the anchor effect. Further, the cavity of the pit 105 provides a fluid boundary layer, which causes mass transfer by diffusion rather than overall flow, and prevents the nucleation site from being unintentionally removed by tank agitation. Further, when electroplating a continuous film on the template wafer 100, the seed layer 102 cooperates with the underlying structure (pit 105) to supply a stable and uniform current for continuous deposition while fixing the film and preventing delamination. The nucleation site adheres to the seed layer 102, and since the seed layer 102 adheres to the pits 105 and the horizontal plane between them, the electroplating solution remains relatively free of particle contamination. The pits 105 enable the expansion of the horizontally deposited film to be plated next, and the stress is released. Finally, the stressed material forming the template wafer 100 facilitates thicker and damage-free plating, thereby releasing both the stress in the metal plating the cavity and the stress due to film delamination in the flat portion between adjacent pits 105. Further, the template wafer 100 can be regenerated and reused to create protrusions and attach them to additional articles.

[0060] In certain embodiments, the template wafer 100 is a silicon wafer having prismatic, conical, cylindrical, or pyramid-shaped pits 105. In this example, the pits 105 have an inverted pyramid shape with a square bottom surface and sides 101 of an equilateral triangular shape. To bump an IC chip using an array of micropillars, or a micro C4 ball grid array (BGA) of 50 micrometers or microns (50 μm) and below, or to form test probes for such wafers, the pits 105 are from 1 to 25 μm in depth, preferably 8 μm in depth, and the diagonal / diameter of the surface is from 1 to 50 μm, for example, 14 μm. The pits 105 can be formed using any well-known semiconductor patterning and etching processes, such as those used in deep or shallow trench isolation (STI) trench formation. Any suitable wet or dry etching can be used. For example, anisotropic wet etching using tetramethylammonium hydroxide (TMAH or TMAOH) etches pyramid-shaped pits 105 into the surface of the template wafer 100. In other examples, KOH can be used for wet etching. Further, since the pits 105 can be formed using well-known patterning and etching, they can be scaled to any size and any pitch depending on the particular technical features selected.

[0061] The seed layer 102 covers each pit 105. In certain embodiments, the seed layer 102 has a plurality of sub-layers (not shown in FIG. 1A) that are metal layers. In one example, the seed layer 102 includes, as a first sub-layer, a base layer, such as titanium, that is formed directly on the silicon template wafer 100 (e.g., a silicon substrate) to ensure good adhesion to the template wafer 100. In this example, the seed layer 102 includes, as a second sub-layer, a highly conductive layer (not shown), such as copper (Cu), silver (Ag), or gold (Au), that is formed on the base layer to ensure a uniform current distribution and maintain current stability during electroplating. In this example, the seed layer 102 includes, as a third sub-layer, a surface layer (not shown) of a seed material, such as Ti, that is formed on the highly conductive layer. A native oxide (not shown) formed on the Ti surface layer ensures that the adhesion to the Ti surface layer is low enough so that later, the electroplated material can be separated with a relatively low force.

[0062] Due to surface non-linearity or other surface roughness, in this example due to the pits, it is facilitated to plate the nucleation sites, and then the adhesion of the metal to be plated to the template wafer during plating is maintained, and since the adhesion is low enough, the plating is released with a relatively low force. Other suitable seed materials can include, for example, stainless steel and chromium (Cr). Also, the seed layer 102 can be a single metal layer (e.g., as shown in FIG. 1A) if the layer adheres well to the template wafer 100 and provides a sufficiently uniform current distribution.

[0063] Referring now to FIG. 1B, this figure is a cross-sectional view of an example of the formation of transferable pillars on the template wafer 100 of FIG. 1A in the next stage of the manufacturing process according to an embodiment. In a particular embodiment, as shown in FIG. 1B, each transferable pillar includes a capping material layer (or hard cap layer 106) that forms a hard tip cap, and this layer is electroplated onto the seed layer 102 after the sacrificial layer 104 is formed and patterned on the template wafer 100. The patterned sacrificial layer 104 defines a protrusion position 103 above each pit 105 covered by the seed layer 102. Alternatively, in embodiments with a plurality of pointed tips, each transferable pillar is formed over a plurality of pits 105, and the surface between the pits 105 is not blocked midway by the patterned sacrificial layer 104, and the subsequent plating process is performed uniformly at and between the pits 105. In this example of a single pointed tip, the hard cap layer 106 covers the seed layer 102 only at the protrusion position 103 and completely lines the pits 105. In a particular embodiment, the capping material of the hard cap layer 106 is nickel (Ni), cobalt (Co), iron (Fe), gold (Au), or a suitable refractory metal, or an alloy thereof, and is electroplated to a thickness of, for example, 1 to 30 μm, preferably 5 μm.

[0064] Referring now to FIG. 1C, this figure is a cross-sectional view of an example of the formation of the transferable pillars 150 on the template wafer 100 of FIG. 1B in the next stage of the manufacturing process according to an embodiment. As shown in FIG. 1C, a conductive plug 108, for example made of copper, is plated onto the hard cap layer 106 such that the plated copper conductive plug 108 has a minimum thickness of, for example, from 1 to 100 μm, preferably 10 μm. Next, a base layer 110, preferably made of nickel, is electroplated onto the conductive plug 108. Next, an intermediate layer 112, for example made of gold, is applied onto the base layer 110. In certain embodiments, the intermediate layer 112 may be omitted. Then, a mounting material 114, preferably a lead-free solder such as a tin / silver (Sn / Ag) solder, is electroplated onto the intermediate layer 112. In this example, the thickness of the base layer 110 is from 0.5 to 3 μm, preferably 2 μm, and the thickness of the mounting material 114 is from 1 to 100 μm, preferably 10 μm. Also, in this example, an inverted metal protrusion, or transferable pillar 150 (i.e., the cap layer 106, conductive plug 108, base layer 110, intermediate layer 112, and mounting material 114) completely fills each pit 105 (see FIG. 1B). In the example shown in FIG. 1B, the conductive plug 108 is shown to only partially fill (or planarize) the pit 105 (i.e., there is a small portion at the top of the conductive plug 108 that still has the shape of the pit 105). However, it should be understood that in other examples, a conductive plug 108 of sufficient material is used such that the pit 105 is completely filled.

[0065] Referring now to FIG. 1D, this figure is a cross-sectional view of an example of the formation of the transferable pillars 150 on the template wafer 100 in the next stage of the manufacturing process according to an embodiment. As shown in FIG. 1D, the patterned sacrificial layer 104 is removed in any typical wet strip, rinse, and dry process. This removal step exposes the upside-down transferable pillars 150 of FIG. 1D. Although the adhesiveness is relatively low, there is still sufficient adhesiveness to hold the features (i.e., the upside-down transferable pillars 150) in place when the resist material of the patterned sacrificial layer 104 is peeled off.

[0066] Referring now to FIG. 1E, this figure is a cross-sectional view of an example of the formation of the transferable pillars 150 on the template wafer 100 in the next stage of the manufacturing process according to an embodiment. As shown in FIG. 1E, the transferable pillars 150 are turned upside down relative to the view shown in FIG. 1D and moved to the position where they are to be attached to the article 116. In certain embodiments, the article 116 (or transfer substrate) can be a ceramic, silicon, or organic substrate, as shown in FIG. 1E. In other embodiments, if the article 116 is a temporary fixture, it may be glass. In this example, the pad 151 is a layered pad that includes a base layer 118 formed on the article 116, preferably copper, an interface layer 120 formed on the base layer 118, preferably nickel, and an oxidation-resistant layer 122 formed on the interface layer 120, preferably gold. Although described with reference to soldering, any suitable attachment method such as adhesion can be used to attach the transferable pillars 150 to the pad 151.

[0067] Referring now to FIG. 1F, this figure is a cross-sectional view of an example of a transferable pillar 150 according to an embodiment, after the transferable pillar has been attached to the article 116 and after the transferable pillar 150 has been removed from the template wafer 100. As shown in FIG. 1F, the exposed metal protrusion (i.e., the transferable pillar 150) is attached to the article 116. For example, it is soldered to the pad 151 on the article 116 by reflowing the solder-based attachment material 114. Once the transferable pillar 150 is attached to the pad 151, the template wafer 100 is separated from the completed transferred pillar 152 (i.e., the transferable pillar 150 and the pad 151) (which can also be referred to as the transferred pillar) using a very small force to twist or pull it off. Further, since the transferred pillar 152 can be defined by lithography, a plurality of transferred pillars 152 can be made with a very fine pitch and can be formed to a very uniform height.

[0068] Referring now to FIG. 1G, this figure is a cross-sectional view of an example of a transferred pillar 152 according to an embodiment, after the transferable pillar has been removed from the template wafer 100 and after the tip of the transferred pillar 152 has pierced the solder ball 126. It should be understood that in some of the embodiments described herein, the tip of the transferred pillar 152 is pointed or sharp. However, in other embodiments, the tip of the transferred pillar 152 does not necessarily have a sharp and pointed profile. Further, the tip of the transferred pillar 152 in the exemplary embodiments of FIGS. 1A to 1G has a truncated shape, but other suitable shapes (e.g., conical or flat shapes) can also be utilized. As shown in FIG. 1G, solder balls 126 are formed on the solder substrate 124. As the article 116 is moved closer to the solder substrate 124, the tip of the transferred pillar 152 is partially (or completely) embedded in the solder ball. In certain embodiments, the solder ball 126 can be heated to soften the ball (i.e., not completely melt or reflow the solder), which can thereby increase the amount by which the tip of the transferred pillar 152 penetrates into the solder ball 126. In certain embodiments, after insertion of the tip of the transferred pillar 152, there is a mechanical engagement between the solder ball 126 and the transferred pillar 152, which can help withstand the separation of the transferred pillar 152 from the solder ball 126 next time. In certain embodiments, after the tip of the transferred pillar 152 has been inserted into the solder ball 126, the article 116 (i.e., the upper substrate in FIG. 1G) is removed, leaving behind a completed structure 153 (i.e., the transferred pillar 152 and the solder ball 126) on the solder substrate 124. As further described below, a plurality of such completed structures 153 can be stacked on top of each other to form a pillar of a desired total height. Further, a plurality of different pillars can be formed using stacks of different numbers of completed structures 153, resulting in pillars of various total heights. Thus, by making the pillars of various heights, electrical interconnections of two or more different heights can be enabled.As described above, it is often desirable to incorporate a silicon bridge structure above a laminate to provide fine pitch wiring that connects two or more active dies, and this structure may require electrical interconnects of various heights. The pillars that make up one or more of the completed structures 153 of this embodiment can accommodate these various heights.

[0069] Referring now to FIG. 1H, this figure is a cross-sectional view of an example of the transferred pillar 152 of FIG. 1F according to an embodiment, after the transferable pillar has been removed from the template wafer 100 and after the tip of the transferred pillar 152 has been coined (or deformed) to form a hook shape. As shown in FIG. 1H, the transferred pillar 152 is pressed against the deformed substrate 180 until the tip of the transferred pillar 152 is deformed (i.e., the coining operation) or flattened to some extent. In a particular example, as a result of this coining process, the shape of the top of the transferred pillar 152 becomes somewhat hook-shaped, which aids in the mechanical engagement between the solder ball 126 and the transferred pillar 152.

[0070] In various embodiments described herein, the completed transferred pillar 152 is used in many different stacking configurations (i.e., a plurality of completed structures 153 including the transferred pillar 152 and solder balls 126 stacked on top of each other), enabling many different fan-out capabilities and configurations. That is, the completed structure of the transferred pillar 152 (or stack of multiple completed structures 153) can function as a spacer that enables these different fan-out configurations. In other words, the completed structures 153 can be built to various heights to accommodate various fan-outs. The examples in FIGS. 1A through 1H show a single tip on the transferred pillar 152, but it should be understood that the transferred pillar 152 may include a plurality of different tips (e.g., two tips as shown in FIG. 2A) to prevent or minimize the tilt of the pillar. In other words, a transferred pillar 152 having two or more tips has multiple contact points with which the tips contact some surface, and these multiple tips provide a certain degree of vertical stability to the high aspect ratio pillar. Although a single transferred pillar 152 itself may have the ability to function as a probe, in this embodiment, it should be understood that the completed structure 153 functions as a spacer (or interconnect pillar) or conductive structure similar to a lithographically formed pin grid array with an extremely fine pitch.

[0071] Referring now to FIGS. 2A through 2G, beginning with FIG. 2A, this drawing is a cross-sectional view of an example of the first completed structure 153-1 (i.e., the transferred pillar 152 and solder ball 126) of FIG. 1G after the tip of the transferred pillar 152 has been inserted into the solder ball 126 and before the article 116 has been removed, according to an embodiment. For ease of illustration, the transferred pillar 152 is not shown with all of the component layers previously described for FIGS. 1A through 1G. As shown in FIG. 2B, the article 116 is removed, leaving the first completed structure 153-1 on the solder substrate 124.

[0072] Referring now to FIG. 2C, this figure is a cross-sectional view of an example of the first completed structure 153-1 shown in FIG. 2B before being transferred to a transfer substrate 200 (e.g., the substrate of an element die) according to an embodiment. As shown in FIG. 2C, the transfer substrate 200 is provided with, for example, a copper layer 202 and a solder layer 204. The solder substrate 124 is positioned such that the first completed structure 153-1 formed thereon is close to the solder layer 204 of the transfer substrate 200.

[0073] As shown in FIG. 2D, the solder substrate 124 is moved so as to approach the transfer substrate 200, whereby the transfer pillar 152 comes into contact with the solder layer 204. Then, the solder layer 204 is reflowed to connect the transfer pillar 152 to the copper layer 202 of the transfer substrate 200.

[0074] In certain embodiments, as an alternative to the process of transferring the transferable pillar 150 from the template wafer 100 to the article 116 as shown in FIG. 1F (e.g., here the article can be a ceramic, silicon, or organic substrate), then from the article 116 to the solder substrate 124 as shown in FIG. 2B, and then from the solder substrate 124 to the transfer substrate 200 shown in FIG. 2C, the transferable pillar 150 may be directly bonded to the transfer substrate 200. That is, in certain embodiments, the transferable pillar 150 can be transferred without using a solder substrate. In other words, there can be any suitable number of different types of methods for transferring the transferable pillar 150 to the final destination substrate. Also, in other embodiments, it should be understood that the pointed tips of the transferable pillars 150 can reach their final destination substrates with those tips oriented either upward or downward. That is, the tips can be oriented upward or downward.

[0075] Referring now to FIG. 2E, this figure is a cross-sectional view of an example of a second completed structure 153-2 prior to being transferred to the transfer substrate 200 shown in FIG. 2D according to an embodiment. It should be understood that the second completed structure 153-2 can be formed in exactly the same way (or a different way) as the first completed structure 153-1 and can have exactly the same structure (or a different structure). For example, after the transferred pillars 152 shown in FIG. 1F are removed from the template wafer 100 (e.g., for the first completed structure 153-1), the template wafer 100 can be reused in the same way as discussed above for FIGS. 1A to 1F to form the transferred pillars 152 of the second completed structure 153-2. As shown in FIG. 2E, the transferred pillars 152 of the second completed structure 153-2 are brought close to the solder balls 126 of the first completed structure 153-1 that was transferred previously.

[0076] As shown in FIG. 2F, after the transferred pillars 152 of the second completed structure 153-2 contact the solder balls 126 of the first completed structure 153-1, the solder balls 126 of the first completed structure 153-1 are reflowed to connect the transferred pillars 152 of the second completed structure 153-2 to the transferred pillars 152 of the first completed structure 153-1. In certain embodiments, the tip portions (i.e., the apexes of the pyramidal-shaped tip portions) of the transferred pillars 152 of the first completed structure 153-1 are buried sufficiently deeply in the solder balls of the first completed structure 153-1 such that they contact the transferred pillars 152 of the second completed structure 153-2. In other words, the post-reflow height H of the solder balls 126 of the first completed structure 153-1 is the same as the height of the conical tip portions of the transferred pillars 152 of the first completed structure 153-1. Thus, it is possible to achieve an overall pillar structure of appropriately controlled height when the tip portions are brought into contact. However, it should be understood that even if the tip portions are not brought into contact, the height can be controlled by a flip-chip bonder as is known to those skilled in the art.

[0077] Referring now to FIG. 2G, this figure is a cross-sectional view of an example of the transferred pillars of a third completed structure 153-3 after being transferred to the transferred substrate 200 shown in FIG. 2D according to an embodiment. It should be understood that the second completed structure 153-3 can be formed in exactly the same way (or a different way) as the first completed structure 153-1 and the second completed structure 153-2, and can have exactly the same structure (or a different structure) as them. The third completed structure 153-3 shown in FIG. 2G is shown without solder balls 126, but it should be understood that in other examples, this structure may have solder balls. Thus, as shown in FIG. 2G, a very tall (i.e., high aspect ratio) pillar structure 250 is formed by a combination of three independent completed structures. It should be understood that this process of combining the completed structures can be repeated any suitable number of times to obtain a pillar structure 250 of the desired height for a particular application. After each individual pillar transfer (i.e., which may require a solder hierarchical structure such as different solder compositions for each successive pillar transfer level), or after the entire plurality of pillar structures are formed, a solder reflow operation can also be performed. This combined reflow operation can be performed on a temporary carrier substrate or on the final destination substrate.

[0078] Also, in certain embodiments, the transferable pillars 150 can be formed as previously described, where the transferable pillars 150 are transferred to a temporary carrier, then stacked on the temporary carrier, then transferred from the temporary carrier to the device wafer, and then the solder is reflowed.

[0079] Referring now to FIG. 3, this figure is a cross-sectional view of an example of a pillar structure 250 attached to different substrate layer configurations according to an embodiment. As shown in FIG. 3, the pillar structure 250 is attached to the substrate 200 to be transferred through different copper layer and solder layer configurations. In contrast to the embodiment shown in FIG. 2C where a single copper layer 202 and a single solder layer 204 are provided for each of the pillar structures 250, in this embodiment shown in FIG. 3, a plurality of copper layers 300 and solder layers 302 are provided for each of the pillar structures. In other respects, the pillar structure 250 has the same configuration as that previously described with respect to FIG. 2G.

[0080] In certain embodiments, the stack of pillars (i.e., the pillar structure 250) may already be attached to a laminate substrate (e.g., the laminate substrate 600 shown in FIG. 6A), and then the substrate 200 to be transferred may be bonded thereto. In this way, the combination of the substrate 200 to be transferred and the pillar structure 250 will necessarily involve a laminate.

[0081] Referring now to FIG. 4A, this figure is a cross-sectional view of an example of a pillar structure 450 having a thick terminal solder layer 400 before solder reflow according to an embodiment.

[0082] Referring now to FIG. 4B, this figure is a cross-sectional view of an example of the pillar structure 450 of FIG. 4A having a thick terminal solder layer 400 after solder reflow according to an embodiment.

[0083] Referring now to FIGS. 5A through 5C, first referring to FIG. 5A, an example of a premolded pillar chip 506 including a plurality of different pillar structures 550 according to an embodiment is shown. As shown in FIG. 5A, a plurality of pillar structures 550 (e.g., the pillar structure 250 shown in FIG. 2G or FIG. 3, or the pillar structure 450 shown in FIG. 4B) are provided on a template wafer 100 and will be transferred to a temporary processing substrate 500. A release layer 502 can be formed on the temporary processing substrate 500 to enable release of the pillar structure 550 from the temporary processing substrate 500 next.

[0084] Referring now to FIG. 5B, there is shown an example of a premolded pillar chip 506 as shown in FIG. 5A after a pillar structure 550 has been transferred to a temporary processing substrate 500 according to an embodiment. As shown in FIG. 5B, the template wafer 100 has been removed and a mold compound layer 552 is formed around the pillar structure 550.

[0085] Referring now to FIG. 5C, there is shown an example of a premolded chip 506 as shown in FIG. 5B after the pillar structure 550 has been transferred to a temporary processing substrate 500 and after the release layer 502 and the temporary processing substrate 500 have been removed. In certain embodiments, during transfer to the laminate substrate, the temporary processing substrate 500 can be left attached to enable a transfer process at the wafer level of the premolded pillars (e.g., laminate substrate 600 shown in FIG. 6A). As shown in FIG. 5C, the release layer 502 and the temporary processing substrate 500 have been removed, leaving a premolded chip 506 that includes a plurality of pillar structures 550. In certain embodiments, the tip of the uppermost transferred pillar 152 can be removed by a planarization process (e.g., CMP) such that the upper surface of the premolded pillar chip 506 is planar (not shown in FIG. 5C). That is, the sharp pyramidal tip of the transferred pillar 152 is useful for transferring and stacking a plurality of different transferred pillars 152, but is not useful for the uppermost transferred pillar 152.

[0086] Here, referring to FIGS. 6A to 6E, first referring to FIG. 6A, an example of a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure including the premolded pillar chip shown in FIG. 5C according to an embodiment is shown. As shown in FIG. 6A, a laminate substrate 600 is provided. A bridge 602 is attached to the laminate substrate 600 using a die attach film (DAF) 604. As shown in FIG. 6A, the bridge 602 may be attached using the laminate substrate 600 (or bridge processing substrate) attached to the top surface of the bridge 602, and then this laminate substrate is removed after the attachment of the bridge 602. Thus, by moving the bridge 602 in the direction of the arrow shown in FIG. 6A, the bridge 602 is attached to the top side of the laminate substrate 600. A laminate copper layer 606 and laminate solder bumps 608 are formed in various portions of the laminate substrate 600. The positions of these laminate copper layers 606 and laminate solder bumps 608 correspond to the positions of the pillar structure 550 in the premolded pillar chip 506 to be attached hereinafter, as will be discussed in more detail below.

[0087] Now referring to FIG. 6B, a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure including the premolded pillar chip 506 of FIG. 6A after the bridge 602 is attached to the laminate substrate 600 according to an embodiment is shown. As shown in FIG. 6B, after the bridge 602 is attached to the laminate substrate 600 by the DAF 604, the laminate substrate 600 (or bridge processing substrate) is removed from the top surface of the bridge 602.

[0088] Referring now to FIG. 6C, a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure, including the premolded pillar chip 506 of FIG. 6B, according to an embodiment, is shown, where the premolded pillar chip 506 is positioned proximate to the surface of the laminate substrate 600. As shown in FIG. 6C, the premolded pillar chip 506 is positioned proximate to the laminate substrate 600. As discussed above, the premolded pillar chip 506 can be designed such that the positions of the individual pillar structures 550 correspond to the positions of the laminate copper layer 606 and the laminate solder bumps 608.

[0089] Referring now to FIG. 6D, there is shown a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure including the premolded pillar chip 506 of FIG. 6C after the premolded pillar chip 506 according to an embodiment is attached to the laminate substrate 600. As shown in FIG. 6D, the premolded pillar chip 506 is brought into contact with the laminate solder bumps 608 such that the position of the pillar structure 550 is the same as the position of the laminate solder bumps 608. In certain embodiments, the laminate solder bumps 608 can be heated or reflowed to fix the premolded pillar chip 506 to the laminate substrate 600. As discussed previously, the premolded pillar chip 506 includes one or several completed structures 153 (see FIG. 2G) stacked on top of each other, so that the overall height of the pillar structure 550 generally corresponds to the upper surface of the bridge 602. It should be understood that as long as there are multiple bridges 602 having different heights, it is possible to design different premolded pillar chips 506 to have an appropriate number of completed structures 153, so that the height of each pillar structure 550 corresponds to the various heights of the bridges 602. Then, if there are gaps between adjacent laminate solder bumps 608 and between the bridge 602 and the premolded pillar chip 506, an underfill layer 610 (or mold compound) is added to fill the gaps. As shown in FIG. 6D, in certain embodiments, a specific amount of the underfill layer 610 can also be added to the tops of the premolded pillar chip 506 and the bridge 602.

[0090] Referring now to FIG. 6E, there is shown a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure, after the planarization process and after the chip has been added, including the premolded pillar chip 506 of FIG. 6D. As shown in FIG. 6E, the pointed surface at the tip of the pillar structure 550 is planarized using a CMP process (or other suitable material removal process). Thus, after the planarization process, the top surface of the entire premolded pillar chip 506 is at the same height as the top surface of the bridge 602. In certain embodiments, the bridge structure may require some type of protective film to stop the planarization, which in turn can be etched away later, etc. In these embodiments, the use of such a protective film may depend on whether a redistribution layer (RDL) or pads are to be formed, etc. In certain embodiments, an optional redistribution layer (RDL), pads, or a bump fabrication process may be performed after the planarization of the structure. In the example shown in FIG. 6E, bumps 612 are formed. The positions of the bumps 612 may correspond to specific electrical contact points on the pillar structure 550 and on the bridge 602. The first chip 616 and the second chip 618 can be attached to the overall structure in any suitable manner. In a specific example, an underfill layer 614 may be added to fill the gap space around the bumps 612. In a specific example, a mold layer 620 may be added at a position between the chips 616, 618. In certain embodiments, multiple underfills can be used, such that different underfills may exist inside and outside the bridge region due to differences in bump pitch, etc.

[0091] Referring now to FIGS. 7A - 7D, and first to FIG. 7A, an example of a transfer pillar structure for a fan - out package - on - package (PoP) structure or a bridge structure including a pillar structure 550 (e.g., the pillar structure 250 shown in FIG. 2G) molded after insertion according to an embodiment is shown. As shown in FIG. 7A, the exposed tip of the pillar structure 550 (e.g., a pyramidal - shaped tip) is brought into contact with the laminate solder bump 608 until the pillar structure pierces the solder bump 608 as described above. In contrast to the embodiments described above with respect to FIGS. 6A - 6E, the pillar structure 550 of this embodiment is not embedded (or pre - formed therein) in the molded chip structure. Thus, at this stage, after the solder bump 608 is reflowed, the high - aspect - ratio pillar structure 550 becomes a self - standing structure after the removal of the transfer substrate (not shown in FIG. 7A). Note that, in contrast to the embodiments described with respect to FIGS. 6A - 6E where the tip of the pillar structure 550 is oriented towards the top side of the pillar structure (i.e., away from the underlying substrate), in FIG. 7C, the tip of the pillar structure 550 is oriented towards the bottom side of the pillar structure 550. In this regard, it should be understood that depending on the nature of the transfer or formation process of the pillar structure, which side the tip of the pillar structure is formed on is not of critical importance for the operation of the device.

[0092] Referring now to FIG. 7B, this figure shows a mold layer 706 formed in the intervening space between the vertical pillar structures 550.

[0093] As shown in FIG. 7C, the pillar structure 550 is planarized using a CMP process (or other suitable material removal process). Thus, after the planarization step, the top surface of the entire pillar structure 550 is at the same height as the top surface of the bridge 602. In certain embodiments, after planarization of the structure, an optional redistribution layer (RDL), pad, or bump fabrication process may be performed. In the example shown in FIG. 7C, bumps 612 are formed. The positions of the bumps 612 may correspond to specific electrical contact points on the pillar structure 550 and on the bridge 602. The first chip 616 and the second chip 618 can be attached to the overall structure in any suitable manner. In a specific example, an underfill layer 614 may be added to fill the gap space around the bumps 612. In a specific example, a mold layer 620 may be added at a position between the chips 616, 618.

[0094] Referring now to FIG. 7D, an example of the transferred pillar structure of FIG. 7C after removal of the laminate substrate 600 according to an embodiment is shown. As shown in FIG. 7D, the laminate substrate 600 (or a fixture or a temporary substrate) has been removed and various interconnect bumps 750 have been added. It should be understood that any suitable number or various interconnect features can be added to electrically connect the interconnect bumps 750 to the bridge 602 and the various pillar structures 550 (not shown in FIG. 7D).

[0095] Referring now to FIGS. 8A through 8C, and initially to FIG. 8A, an example of a transfer pillar structure for a fan-out package on package (PoP) structure or a bridge structure is shown that includes a pillar structure 550 (e.g., the pillar structure 250 shown in FIG. 2G) inserted into a pre-formed b-stage underfill / thermoplastic mold compound according to an embodiment. As shown in FIG. 8A, a mold compound layer 806 (or b-stage underfill) is formed over a laminate substrate 600, above and around a laminate copper layer 606, laminate solder bumps 608, DAF 604, and a bridge 602. In a particular example, the mold compound layer 806 is formed to a height above the top surface of the bridge 602.

[0096] Referring now to FIG. 8B, this figure shows a pillar structure 550 (attached to a temporary transfer substrate 808) being inserted into the mold compound layer 806 in the direction of the arrow. Similar to other embodiments described previously, tall pillars can be formed using single or multiple stacked transfer pillars and inserted into this b-stage underfill (or mold compound layer 806) with a high filler content.

[0097] As shown in FIG. 8C, the pillar structure 550 is planarized using a CMP process (or other suitable material removal process). Thus, after the planarization step, the top surface of the entire pillar structure 550 is at the same height as the top surface of the bridge 602. In a particular embodiment, an optional redistribution layer (RDL), pads, or bump fabrication process can be performed after the planarization of the structure. In the example shown in FIG. 7C, bumps 612 are formed. The location of the bumps 612 can correspond to specific electrical contact points on the pillar structure 550 and on the bridge 602. The first chip 616 and the second chip 618 can be attached to the overall structure in any suitable manner. In a particular example, an underfill layer 614 can be added to fill the gap space around the bumps 612. In a particular example, a mold layer 620 can be added at a location between the chips 616, 618.

[0098] In certain embodiments, an electrical inspection can be performed on the transferable pillar stack to ensure that the solder reflow operation was successful and that the pillar structure is conductive. Depending on how the pillar structure is fabricated, the electrical inspection can be performed one or more times, and this inspection can be performed before or after the solder reflow.

[0099] Thus, this embodiment utilizes a transferable pillar method for creating a pillar structure on an independent substrate and selectively transferring the structure to a desired package to form an offset for a chip within a fan-out package or a bridge structure. This process can be repeated to further increase the overall height of the pillar structure without being limited by the aspect ratio.

[0100] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application of technologies found in the marketplace, or improvements thereto, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

[0101] In one embodiment of the present invention, a bridge structure is provided that includes a substrate; a bridge formed on the substrate; at least one pillar, each pillar having a capping material layer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and a mounting material layer formed on the base layer; and at least one chip formed on top of the at least one pillar. The pillar can have a pointed tip.

Claims

1. A method of forming a pillar structure, comprising: forming a plurality of pillars, each pillar comprising: forming a capping material layer within a pit etched in a template wafer; forming a conductive plug on the capping material layer; forming a base layer on the conductive plug; forming an attachment material layer on the base layer; thereby formed; and coupling the plurality of pillars to each other in a vertical direction so as to form the pillar structure. A method comprising the steps of.

2. The method according to claim 1, wherein the attachment material layer is a solder material.

3. The step of coupling the plurality of pillars to each other in a vertical direction comprises: providing a transfer substrate; attaching a first pillar of the plurality of pillars to the transfer substrate; removing a first template wafer from the first pillar of the plurality of pillars; attaching a second pillar of the plurality of pillars to the first pillar of the plurality of pillars; and removing a second template wafer from the second pillar of the plurality of pillars. The method according to claim 1 or 2, comprising the steps of.

4. The method according to claim 3, further comprising the step of reflowing the attachment material for each of the plurality of pillars.

5. The method according to any one of claims 1 to 4, further comprising the step of embedding the pillar structure in a premolded chip.

6. The method according to any one of claims 1 to 5, wherein each of the plurality of pillars includes a tip corresponding to the shape of the pit formed in the template wafer.

7. The method according to claim 6, wherein the tip has a conical shape or a pyramid shape.

8. attaching a plurality of the pillar structures to a fan-out PoP structure or a bridge structure; and providing a filling layer to fill a space between the pillar structures. The method according to any one of claims 1 to 5, further comprising the steps of.

9. The method according to claim 8, wherein a first pillar structure of the pillar structures includes a first number of pillars, and a second pillar structure of the pillar structures includes a second number of pillars different from the first number of pillars.

10. The method according to any one of claims 1 to 5, wherein each of the plurality of pillars has a pointed tip corresponding to the shape of the pit, and the method further comprises the step of deforming the pointed tip.

11. A pillar structure comprising a plurality of pillars, each pillar having a capping material layer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and a mounting material layer formed on the base layer and having, the plurality of pillars are joined to each other in the longitudinal direction to form the pillar structure, the capping material layer of one of the pillars joined to each other in the longitudinal direction and the other pillar are joined by a solder layer Pillar structure.

12. The pillar structure according to claim 11, wherein the mounting material layer is a solder material.

13. The pillar structure according to claim 11, wherein the tip of each of the plurality of pillars has a conical shape or a pyramid shape.

14. A plurality of the pillar structures are attached to a fan-out PoP structure or a bridge structure, and a mold layer is formed to fill the space between the pillar structures, according to claim 11 or 12. Pillar structure.

15. The pillar structure according to claim 14, wherein the first pillar structure among the pillar structures includes a first number of pillars, and the second pillar structure among the pillar structures includes a second number of pillars different from the first number of pillars.

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