Upward state dual memory cell

Abstract

The circuit includes a memory cell. The memory cell has a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element is connected to a bit line. The second memory element is connected to a select line. The first transistor is connected to a first word line. The second transistor is connected to a second word line. The first memory element is programmed by applying a first write voltage to the bit line, a second write voltage to the second word line, a first intermediate voltage to the select line, and a second intermediate voltage to the first word line. The select line is connected to a high impedance. The first write voltage may be a positive supply voltage and the second write voltage may be a negative supply voltage.

Description

Background Art

[0001] The present invention generally relates to a memory array structure and a method of programming the same. More specifically, the present invention relates to a memory array structure including improved state dual memory cells.

[0002] Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. Deep learning can be used in a wide range of applications including image processing, machine translation, speech recognition, and many others. In each of these areas, deep neural networks achieve better accuracy through the use of very large and deep models. These deep models may include methods with reduced accuracy for data representation and computation.

Summary of the Invention

[0003] According to one aspect of the present invention, a circuit including a memory array is provided. The memory array has a plurality of bit lines, a plurality of word lines, and a plurality of select lines. The plurality of bit lines and the plurality of select lines intersect the plurality of word lines. The memory array further has a plurality of memory cells, each including a first transistor, a second transistor, a first memory element, and a second memory element. The first memory element and the second memory element are connected to the plurality of word lines using the first transistor and the second transistor. The first memory element and the second memory element are connected to the plurality of bit lines and the plurality of select lines. The first transistor and the second transistor may be a complementary pair of bipolar junction pass transistors. The complementary pair of bipolar junction pass transistors may include an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor. The first transistor and the second transistor may be a complementary pair of junction field effect transistors. The complementary pair of junction field effect transistors may include an n-channel junction field effect transistor and a p-channel junction field effect transistor. The first memory element may be connected between one of the plurality of bit lines and the first shared collector-emitter or source-drain terminal of the complementary pair. The second memory element may be connected between one of the plurality of select lines and the second shared collector-emitter or source-drain terminal of the complementary pair. The second transistor in one of the plurality of memory cells and the transistor of the opposite channel type in a memory cell adjacent to one of the plurality of memory cells may have a base or gate terminal connected to the same one of the plurality of word lines. The first memory element and the second memory element may be a phase change memory, a resistive random access memory, or a magnetic random access memory. The first memory element and the second memory element may have the same characteristics, the first memory element and the second memory element may be programmable to N states, and the memory cell is

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[0004] According to another aspect of the present invention, a circuit including a memory cell is provided. The memory cell has a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element is connected to a bit line. The second memory element is connected to a selection line. The first transistor is connected to a first word line, and the second transistor is connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the selection line, and applying a second intermediate voltage to the first word line. The selection line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage, and the first intermediate voltage and the second intermediate voltage may be a ground voltage. The first write voltage may be greater than the first intermediate voltage, the first intermediate voltage may be greater than or equal to the second intermediate voltage, and the second intermediate voltage may be greater than the second write voltage. The first memory element may be erased by applying a first erase voltage to the first word line, applying a second erase voltage to the bit line, applying a first intermediate voltage to the selection line, and applying a second intermediate voltage to the second word line. The first erase voltage may be a positive supply voltage, the second erase voltage may be a negative supply voltage, and the first intermediate voltage and the second intermediate voltage may be a ground voltage. The first erase voltage may be greater than the first intermediate voltage, the first intermediate voltage may be greater than or equal to the second intermediate voltage, and the second intermediate voltage may be greater than the second erase voltage. The first transistor and the second transistor may be a complementary pair of bipolar junction pass transistors. The complementary pair of bipolar junction pass transistors may include an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor.The first transistor and the second transistor may be a complementary pair of junction field effect transistors. The complementary pair of junction field effect transistors may include an n-type junction field effect transistor and a p-type junction field effect transistor. The first memory element and the second memory element may be a phase change memory, a resistive random access memory, or a magnetic random access memory.

[0005] According to another aspect of the present invention, a method of reading memory cells in a memory array comprises: applying a first read voltage of a first pair of read voltages to a bit line; applying a second read voltage of the first pair of read voltages to a select line connected to a second memory element; applying a first read voltage of a second pair of read voltages to a first word line; applying a second read voltage of the second pair of read voltages to a second word line; and applying an intermediate voltage to the remaining ones of the bit line, word line, and select line in the memory array. The bit line is connected to a first memory element. The first word line is connected to a first transistor. The second word line is connected to a second transistor. The first transistor and the second transistor may be a complementary pair of bipolar junction pass transistors. The first transistor may be an NPN bipolar junction pass transistor, and the second transistor may be a PNP bipolar junction pass transistor. The first word line may be connected to the base of the NPN bipolar junction pass transistor, and the second word line may be connected to the base of the PNP bipolar junction pass transistor. The first transistor and the second transistor may be a complementary pair of junction field effect transistors. The first transistor may be an n-channel junction field effect transistor, and the second transistor may be a p-channel junction field effect transistor. The first word line may be connected to the gate of the n-channel junction field effect transistor, and the second word line may be connected to the gate of the p-channel junction field effect transistor.The first read voltage of the first pair of read voltages may be greater than the first read voltage of the second pair of read voltages, the first read voltage of the second pair of read voltages may be greater than the intermediate voltage, the intermediate voltage may be greater than the second read voltage of the second pair of read voltages, and the second read voltage of the second pair of read voltages may be greater than the second read voltage of the first pair of read voltages. The first read voltages of the first and second pairs of read voltages may be positive voltages, the second read voltages of the first and second pairs of read voltages may be negative voltages, the second read voltage may have the same amplitude as the first read voltage, and the intermediate voltage may be a ground voltage.

Brief Description of the Drawings

[0006] The following detailed description is given by way of example and is not intended to limit the invention thereto, and will be best understood when read in conjunction with the accompanying drawings.

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[0013] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to represent specific parameters of the present invention. The drawings are intended to show merely typical embodiments of the present invention. In the drawings, like reference numerals represent like elements.

DETAILED DESCRIPTION OF THE INVENTION

[0014] Detailed embodiments of the claimed structures and methods are disclosed herein, however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Details of well-known features and techniques may be omitted herein to avoid obscuring the presented embodiments needlessly.

[0015] For the purposes hereinafter of this specification, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "upper part", "lower part", and derivatives thereof, shall relate to the disclosed structures and methods as oriented in the images of the drawings. The terms "overlap", "at the top of", "on", "positioned on" or "positioned at the top of" shall mean that a first element such as a first structure etc. is present on a second element such as a second structure etc., and intervening elements such as interface structures etc. may be present between the first element and the second element. The term "direct connection" shall mean that a first element such as a first structure etc. and a second element such as a second structure etc. are connected without any intervening conductive, insulating or semiconductor layers at the interface of these two elements.

[0016] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined both for the purpose of presentation and for illustrative purposes, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is rather focused on the discriminative features or elements of the various embodiments of the present invention.

[0017] Deep learning is a machine learning method based on artificial neural networks. Deep learning can be used in a wide range of applications including image processing, machine translation, speech recognition, and many others. In each of these areas, deep neural networks achieve better accuracy through the use of very large-scale and deep models. These deep models may include methods that reduce the accuracy for data representation and calculation. The calculations for deep neural networks may include both training and forward inference.

[0018] Multiplication operations (including convolution and matrix multiplication) are one of the most area- and power-consuming components in the hardware implementation of deep neural networks. Recent advances in reduced-precision optimization suggest that at least some of the multiplication operations can be performed at a lower precision. This means that the multiplication operations can be performed using fewer bits without compromising end-to-end accuracy. This provides an opportunity for power and / or area savings by leveraging analog devices such as resistive random access memory (RRAM™) for weight storage. Further, it is desirable to utilize analog devices (i.e., memory elements) having multiple (more than two) states to increase the memory density for a given memory cell or a given memory design.

[0019] Conventional memory elements are dual-state in that, in practical use, they have either state 0 or state 1. These conventional memory elements cannot have more than two states due to reliability issues. As a result, conventional memory elements can be limited by a practical number of states (typically two).

[0020] In theory, increasing the number of memory elements per cell can increase the number of effective states per cell. For example, having two memory elements in each memory cell can increase the number of states from two to four, assuming each memory element has two states. The two memory elements can be combined to obtain four states by using the mathematical permutation of their two states. For example, if the first memory element has state 0 and the second memory element has state 0, the combination of the two memory element states can provide memory cell state 1. If the first memory element has state 0 and the second memory element has state 1, the combination of the two memory element states can provide memory cell state 2. If the first memory element has state 1 and the second memory element has state 0, the combination of the two memory element states can provide memory cell state 3. If the first memory element has state 1 and the second memory element has state 1, the combination of the two memory element states can provide memory cell state 4.

[0021] However, in practice, additional circuitry and processors, such as transistors, are required to combine the states of two or more memory elements in a usable way, which can then be expanded. Having additional transistors and corresponding wires can increase the footprint of the circuit, and thus reduce the memory density. The result can be a single memory cell that contains more than two states but has a larger footprint than two memory cells, each having two states. Therefore, there is a need for memory cells that contain more than two states and have a smaller footprint than the combined footprint of two memory cells.

[0022] Embodiments of the present invention provide a new circuit structure. This new circuit structure is a cross-point memory array comprising a plurality of improved state dual memory cells. Each of the dual memory cells has two transistors and two memory elements. Thus, the memory cell may also be referred to as a 2T2R cell. A cross-point memory array having a plurality of 2T2R cells can increase the number of valid states per cell as compared to conventional memory arrays. In one embodiment, the transistors within the memory cell are configured as complementary pass gates (transmission gates). In one embodiment, the memory cell is configured as an RRAM / pass gate / RRAM vertical stack structure, and thus, self-footprint is minimized and high density of bits per area is achieved.

[0023] Figures 1-6 show an exemplary circuit structure comprising a plurality of memory cells. Each memory cell has two transistors integrated with two memory elements.

[0024] Referring now to FIG. 1, a memory array 100 according to one embodiment is shown. Memory array 100 includes two rows and four columns, although it should be understood that embodiments of the present invention may include memory arrays 100 having any number of rows and columns. Memory array 100 includes a plurality of bit lines 102, a plurality of word lines 104, and a plurality of select lines 106. Bit lines 102 and select lines 106 extend in parallel with each other and are perpendicular to word lines 104. The plurality of word lines 104 intersect the plurality of bit lines 102 and the plurality of select lines 106. Memory array 100 also includes a plurality of memory cells 200. Each memory cell 200 has a complementary pair of transistors 108a, 108b, a first memory element 110a, and a second memory element 110b. Although eight memory cells 200 are shown, it should be understood that embodiments of the present invention may include any number of memory cells 200.

[0025] As described above, each memory cell 200 has a complementary pair of transistors 108a, 108b. The transistors 108a, 108b may be bipolar junction transistors (BJTs) or junction field effect transistors (JFETs). In a preferred embodiment, the transistors 108a, 108b are a complementary pair of BJTs such that transistor 108a is of NPN type and transistor 108b is of PNP type. In an alternative embodiment, the transistors 108a, 108b are a complementary pair of JFETs such that transistor 108a is an n-channel JFET (nJFET) and transistor 108b is a p-channel JFET (pJFET). In one embodiment, the transistors 108a, 108b are configured as complementary transmission gates. In one embodiment, transistor 108b in memory cell 200 and transistor 108a in a memory cell adjacent to memory cell 200 have base or gate terminals connected to the same respective word line 104b. Transistor 108a is of a channel type opposite to that of transistor 108b.

[0026] The first and second memory elements 110a, 110b may be any type of memory element such as, for example, RRAM, phase change memory, magnetic random access memory, etc. The first memory element 110a is connected between bit line 102a and the first shared collector-emitter terminal (in the BJT embodiment) or source-drain terminal (in the JFET embodiment) of the complementary pair of transistors 108a, 108b. The second memory element 110b is connected between select line 106a and the second shared collector-emitter or source-drain terminal of the complementary pair of transistors 108a, 108b.

[0027] Referring now to FIG. 2, an example of a programming or writing operation of a first memory element 110a within a memory array 100 according to one embodiment is shown. Embodiments of the present invention provide a method of programming a first memory element 110a without substantially disturbing a second memory element 110b within a memory cell 200. During the programming operation, the resistance of the first memory element 110a is reduced to create a programmed state of the memory element (e.g., which may be referred to as 1).

[0028] To program the first memory element 110a, a first write voltage is applied to a bit line 102b connected to the first memory element 110a. In one embodiment, a word line 104c is connected to the base of a PNP transistor 108b. In an alternative embodiment, the word line 104c is connected to the gate of a pJFET transistor 108b. The first write voltage is a positive supply voltage V + . A second write voltage is applied to the word line 104c. The second write voltage is a negative supply voltage V - . The first write voltage is sufficiently greater than the second write voltage to forward bias the base or gate junction of the transistor 108b, enabling the first memory element 110a to be selected for programming. For example, if the voltage drop across the forward-biased junction (typically for a silicon p-n junction) is approximately 0.7 volts, the program voltage selectively applied across the first memory element 110a is approximately V + - V ― - 0.7 volts.

[0029] During the programming of the first memory element 110a as described above, a first intermediate voltage and a second intermediate voltage may be applied to a specific portion of the memory array 100 to minimize interfering with the second memory element 110b and all other memory elements in the rest of the memory cells. In one embodiment, the first intermediate voltage is applied to the select line 106b connected to the second memory element 110b. In an alternative embodiment, the select line 106b is connected to high impedance. The second intermediate voltage is applied to the remaining bit lines 102, word lines 104, and select lines 106. For example, as shown in FIG. 2, the select line 106b may be connected to either a first intermediate voltage V m or float, which may refer to high impedance. The second intermediate voltage V0 is applied to the bit line 102a, select line 106a, and word lines 104a, 104b, 104d, and 104e. As described above, the first write voltage V + is applied to the bit line 102b, and the second write voltage V - is applied to the word line 104c. In this example, the voltages are selected as follows:

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[0030] As described above, during the programming operation of the first memory element 110a, current flows through the emitter-base or source-gate junctions of the first memory element 110a and the transistor 108b. The transistor 108b functions as a two-terminal device during this operation. By selecting the different write and intermediate voltages described above, the first memory element 110a may be programmed to a desired value without disturbing the second memory element 110b in the memory cell 200 or any other memory element in other memory cells within the memory array 100. As a result, the first memory element 110a is independently programmable.

[0031] Referring now to FIG. 3, an example of an erase operation of the first memory element 110a within the memory array 100 according to one embodiment is shown. The erase operation is similar to the write operation with an opposite voltage polarity applied across the first memory element 110a. The write operation of the first memory element 110a shown in FIG. 2 may be performed via the PNP BJT transistor 108b, while the erase operation of the first memory element 110a shown in FIG. 3 may be performed via the NPN BJT transistor 108a.

[0032] The erasure operation independently erases the state of only the first memory element 110a. All other memory elements including the second memory element 110b within the memory cell 200 are not substantially affected by this operation. To erase the state of the first memory element 110a, its resistance increases. This is achieved by applying a first erasure voltage to the word line 104b. The word line 104b is connected to the transistor 108a. In one embodiment, when the transistor 108a is an NPN BJT transistor, the word line 104b is connected to the base of the NPN BJT transistor. In an alternative embodiment, when the transistor 108b is an nJFET transistor, the word line 104b is connected to the gate of the nJFET transistor. The transistor 108a is connected to the first memory element 110a. The first erasure voltage is the positive supply voltage V + In addition to the first erasure voltage, a second erasure voltage is applied to the bit line 102b. The bit line 102b is connected to the upper terminal of the first memory element 110a. The second erasure voltage is the negative supply voltage V - The first erasure voltage is large enough compared to the second erasure voltage to forward bias the base or gate junction of the transistor 108b, enabling it to be selected for erasing the first memory element 110a. For example, if the voltage drop across the forward-biased junction (typically for a silicon p-n junction) is approximately 0.7 volts, the erasure voltage selectively applied across the first memory element 110a is approximately V + - V ― - 0.7 volts.

[0033] During the erasure of the first memory element 110a as described above, a first intermediate voltage and a second intermediate voltage may be applied to a particular portion of the memory array 100 to minimize interfering with the second memory element 110b and all other memory elements in the rest of the memory cells. In one embodiment, the first intermediate voltage is applied to the select line 106b connected to the second memory element 110b. In an alternative embodiment, the select line 106b is connected to high impedance. The second intermediate voltage is applied to the remaining bit lines 102, word lines 104, and select lines 106. For example, as shown in FIG. 3, the select line 106b may be connected to either the first intermediate voltage

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[0034] Referring now to FIG. 4, an example of the write operation of a second memory element 110b within memory array 100, according to one embodiment, is shown. The write or programming of the second memory element 110b is similar to the write operation of the first memory element 110a described herein with reference to FIG. 2. In the example shown in FIG. 2, the first memory element 110a is written via transistor 108b, while in the example shown in FIG. 4, the second memory element 110b is written via transistor 108a.

[0035] In one embodiment, to write or program the second memory element 110b without substantially disturbing the first memory element 110a within memory cell 200, or any other memory element within memory array 100, a first write voltage and a second write voltage are applied to word line 104b and select line 106b, respectively. As described herein with respect to FIG. 2, word line 104b may be connected to either the gate of nJFET transistor 108a, or the base of NPN BJT transistor 108a. Transistor 108a is connected to the second memory element 110b. Select line 106b is connected to the bottom terminal of the second memory element 110b.

[0036] During programming of the second memory element 110b, the first intermediate voltage and the second intermediate voltage may be applied to a particular bit line 102, word line 104, and select line 106. In one embodiment, the first intermediate voltage is applied to a bit line 102b connected to the upper terminal of the first memory element 110a. In an alternative embodiment, the bit line 102b is connected to a high impedance. The second intermediate voltage is applied to the remaining ones of the bit line 102, word line 104, and select line 106. For example, as shown in FIG. 4, the bit line 102b may be connected to either a float that may refer to the first intermediate voltage

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[0037] By having a first write voltage greater than the second write voltage, it becomes possible to select the second memory element 110b for the write operation. The first write voltage is sufficiently greater than the second write voltage to forward bias the base or gate junction of the transistor 108a. For example, the write voltage selectively applied across the second memory element 110b is approximately V + - V ―It may be -0.7 volts. Thus, current flows through the base-emitter or gate-source junction of transistor 108a to the second memory element 110b. Transistor 108a functions as a two-terminal device during this operation. When current flows through the second memory element 110b, the second memory element 110b may be programmed to a desired state without substantially interfering with any other memory element in the memory array 100 or the first memory element 110a in the memory cell 200. Thus, the second memory element 110b may be independently programmed.

[0038] Referring now to FIG. 5, an example of an erase operation of the second memory element 110b within the memory array 100 according to one embodiment is shown. The erase of the second memory element 110b is similar to the erase operation of the first memory element 110a described herein with reference to FIG. 3. In the example shown in FIG. 3, the first memory element 110a is erased via transistor 108a, while in the example shown in FIG. 5, the second memory element 110b is erased via transistor 108b. As described above with respect to FIG. 3, embodiments of the present invention provide a method for independently erasing the state of one memory element within the memory array 100.

[0039] Continuing to refer to FIG. 5, to erase the state of the second memory element 110b, a first erase voltage V + is applied to the select line 106b connected to the bottom terminal of the second memory element 110b, and a second erase voltage V -is applied to word line 104c. In one embodiment, word line 104c is connected to the base of PNP BJT transistor 108b. In an alternative embodiment, word line 104c is connected to the gate of pJFET transistor 108b. In both embodiments, transistor 108b is connected to a second memory element 110b. The first erase voltage is sufficiently greater than the second erase voltage to forward bias the base or gate junction of transistor 108b. For example, the erase voltage selectively applied across the second memory element 110b may be approximately V + - V ― - 0.7 volts. Accordingly, current flows from the second memory element 110b through the emitter - base or source - gate junction of transistor 108b. Transistor 108b functions as a two - terminal device during this operation. When current flows through the second memory element 110b, the second memory element 110b may be erased to a desired state without substantially disturbing any other memory element within memory array 100 or the first memory element 110a within memory cell 200. Accordingly, the second memory element 110b may be erased independently.

[0040] In addition to the first erase voltage and the second erase voltage, a first intermediate voltage and a second intermediate voltage may also be applied to specific bit lines 102, word lines 104, and select lines 106. In one embodiment, the first intermediate voltage is applied to bit line 102b that is connected to the upper terminal of the first memory element 110a. In an alternative embodiment, bit line 102b is connected to a high impedance. The second intermediate voltage is applied to bit line 102a, word lines 104a, 104b, 104d, 104e, and select line 106a.

[0041] In the example shown in FIG. 5, the voltages are selected as follows:

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[0042] Referring now to FIG. 6, an example of a read operation of a memory cell 200 within a memory array 100 according to one embodiment is shown. To read the memory cell 200, two pairs of read voltages having correct values related to each other are applied to the memory array 100. The first pair of voltages includes a first read voltage

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[0043] In the example shown in FIG. 6, the read voltages are selected as follows:

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[0044] In one embodiment, the first read voltages of the first and second pairs of voltages are a positive voltage V + and the second read voltages of the first and second pairs of voltages are a negative voltage V having the same amplitude as the first read voltage - . In another embodiment, the voltages are as follows:

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[0045] It should be understood that the read voltages are typically smaller than the write and erase voltages as known from memory element operation.

[0046] As described above, during the read of memory cell 200, the read voltage is applied with the use of an external circuit such that current flows through both the first memory element 110a and the second memory element 110b, and the read current sensed by the read circuit is a measure of the combined state of the first and second memory elements 110a, 110b. As a result, memory cell 200 can have more states compared to a single memory element 110, as further explained below.

[0047] In addition, as described above, during the readout of the memory cell 200, both transistors 108a and 108b are switched on so as to form a complementary pass transistor pair also known as a transmission gate. As is known, this is advantageous because the transmission gate has a lower voltage drop and a higher dynamic range than a single pass transistor. Thus, the read current measured by an external circuit is substantially proportional to R1 + R2, which is the sum of the resistance values of the memory elements 110a and 110b, and this can be interpreted as the state of the memory cell. In one embodiment, the first and second memory elements 110a, 110b and the transistors 108a, 108b may be configured as a vertical stacked structure. For example, the memory element 110a may be stacked on top of the transistors 108a and 108b, which in turn are stacked on top of the memory element 110b. In addition, the transistors 108a and 108b may be vertical transistors having a stacked transistor region. These stacked structures minimize the footprint of the memory cell 200 and achieve a high density of memory states per unit area.

[0048] Embodiments of the present invention provide a memory array 110 comprising a plurality of memory cells 200. Each of the memory cells 200 has two memory elements and two transistors. Each of the memory cells 200 may be programmed to a number of states greater than the number of each of the memory elements. In some embodiments, if the first and second memory elements 110a, 110b within the memory cell 200 have different characteristics, a greater number of memory cell states may be possible. For example, if the first and second memory elements 110a, 110b are identical and have a first state R H (indicating high resistance) and a second state R L (indicating low resistance), the memory cell 200 may have three states 2R H , 2R L , and R H +R L . Similarly, if the first memory element 110a and the second memory element 110b have three states R H , R L , and R MWhen having (showing medium resistance), there are six possible states: 2R H , 2R L , 2R M , R H +R L , R H +R M and R L +R M exist. More generally, when two memory elements in the memory cell 200 are identical and the first memory element 110a and the second memory element 110b have N states, the memory cell 200 is programmable to

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[0049] The memory cell 200 may have a maximum of N states for N bits when the first memory element 110a is different from the second memory element 110b. For example, by using different material compositions, thicknesses, and / or structures, the first memory element 110a may be different from the second memory element 110b. For example, when the first memory element 110a has two states: R 2 and R H1 and the second memory element 110b has two states: R L1 and R H2 and R L2 , the memory cell 200 has four possible states: R H1 +R H2 , R H1 +R L2 , R L1 +R H2 and R L1 +R L2may have. Similarly, when the memory elements 110a and 110b are identical but are biased with asymmetric and opposite voltage polarities with respect to each other (for example, when the bottom terminal of the memory element 110a is connected to BL102b and its upper terminal is connected to the transistors 108a and 108b), the first memory element 110a has two states R H1 and R L1 may have, and the second memory element 110b has two states R H2 and R L2 may have, and the memory cell 200 has four possible states: R H1 +R H2 、R H1 +R L2 、R L1 +R H2 and R L1 +R L2 may have. More generally, using N states instead of 2, the memory cell 200 may have up to N 2 states in this way.

[0050] The embodiments of the present invention described herein with reference to FIGS. 1-6 provide a new circuit structure. This new circuit structure is a cross-point memory array 100 comprising a plurality of memory cells 200. The memory cell 200 may also be referred to as an improved state dual memory cell. The memory cell 200 is a 2T2R memory cell. As described above herein, each of the memory cells 200 has two transistors 108a, 108b and two memory elements 110a, 110b. The combination of transistors and memory elements increases the effective number of states per cell compared to conventional memory arrays.

[0051] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

Claims

1. A memory array comprising, wherein the memory array: A plurality of bit lines; A plurality of word lines; A plurality of select lines, the plurality of bit lines and the plurality of select lines intersect the plurality of word lines; and A plurality of memory cells having, each memory cell: A first transistor, A second transistor, A first memory element, and A second memory element, the first memory element and the second memory element are connected to the plurality of word lines using the first transistor and the second transistor, and the first memory element and the second memory element are connected to the plurality of bit lines and the plurality of select lines including, a circuit.

2. The first transistor and the second transistor are a complementary pair of bipolar junction pass transistors, the complementary pair of bipolar junction pass transistors includes an NPN bipolar junction pass transistor and a PNP bipolar junction pass transistor, the circuit according to claim 1.

3. The first transistor and the second transistor are a complementary pair of junction field effect transistors, the complementary pair of junction field effect transistors includes an n-channel junction field effect transistor and a p-channel junction field effect transistor, the circuit according to claim 1.

4. The first memory element is connected between one of the plurality of bit lines and the first shared collector-emitter or source-drain terminal of the complementary pair, and the second memory element is connected between one of the plurality of select lines and the second shared collector-emitter or source-drain terminal of the complementary pair, the circuit according to claim 2.

5. The second transistor in one of the plurality of memory cells and the transistor of the opposite channel type in the memory cell adjacent to the one of the plurality of memory cells have a base or gate terminal connected to the same one of the plurality of word lines, the circuit according to claim 1.

6. The first memory element and the second memory element are a phase change memory, a resistive random access memory, or a magnetic random access memory, the circuit according to any one of claims 1 to 5.

7. The first memory element and the second memory element have the same characteristics, the first memory element and the second memory element are programmable into N states, and the memory cell is 【Number 1】 programmable into a state, the circuit according to any one of the preceding claims 1 to 6.

8. The first memory element and the second memory element have different characteristics, the first memory element and the second memory element are programmable to N states, and the memory cell is N ２ programmable to states, the circuit according to any one of claims 1 to 6.

9. Memory cell comprising, the memory cell having a first memory element, a second memory element, a first transistor, and a second transistor, the first memory element being connected to a bit line, the second memory element being connected to a selection line, the first transistor being connected to a first word line, and the second transistor being connected to a second word line.

10. The first memory element is programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the selection line, and applying a second intermediate voltage to the first word line, the circuit according to claim 9.

11. The selection line is connected to a high impedance, the circuit according to claim 10.

12. The first write voltage is a positive supply voltage, the second write voltage is a negative supply voltage, and the first intermediate voltage and the second intermediate voltage are ground voltages, the circuit according to claim 10.

13. The first write voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second write voltage, the circuit according to claim 10.

14. The first memory element is erased by applying a first erase voltage to the first word line, applying a second erase voltage to the bit line, applying a first intermediate voltage to the selection line, and applying a second intermediate voltage to the second word line, the circuit according to claim 9.

15. The first erasure voltage is a positive supply voltage, the second erasure voltage is a negative supply voltage, the first intermediate voltage and the second intermediate voltage are ground voltages, the first erasure voltage is greater than the first intermediate voltage, the first intermediate voltage is greater than or equal to the second intermediate voltage, and the second intermediate voltage is greater than the second erasure voltage. The circuit according to claim 14.

16. The first transistor and the second transistor are a complementary pair of bipolar junction transistors, and the complementary pair of bipolar junction transistors includes an NPN bipolar junction transistor and a PNP bipolar junction transistor. The circuit according to claim 9.

17. The first transistor and the second transistor are a complementary pair of junction field effect transistors, and the complementary pair of junction field effect transistors includes an n-type junction field effect transistor and a p-type junction field effect transistor. The circuit according to claim 9.

18. The first memory element and the second memory element are a phase change memory, a resistive random access memory, or a magnetic random access memory. The circuit according to claim 9.

19. A method of reading a memory cell in a memory array, comprising: applying a first read voltage of a first pair of read voltages to a bit line, the bit line being connected to a first memory element; applying a second read voltage of the first pair of read voltages to a select line connected to a second memory element; applying a first read voltage of a second pair of read voltages to a first word line, the first word line being connected to a first transistor; applying a second read voltage of the second pair of read voltages to a second word line, the second word line being connected to a second transistor; and applying an intermediate voltage to the remaining ones of the bit line, word line, and select line in the memory array. A method comprising the steps of

20. The first transistor and the second transistor are a complementary pair of bipolar junction pass transistors, the first transistor is an NPN bipolar junction pass transistor, and the second transistor includes a PNP bipolar junction pass transistor, the method according to claim 19.

21. The first word line is connected to the base of the NPN bipolar junction pass transistor, and the second word line is connected to the base of the PNP bipolar junction pass transistor, the method according to claim 20.

22. The first transistor and the second transistor are a complementary pair of junction field effect transistors, the first transistor is an n-channel junction field effect transistor, and the second transistor is a p-channel junction field effect transistor, the method according to claim 19.

23. The first word line is connected to the gate of the n-channel junction field effect transistor, and the second word line is connected to the gate of the p-channel junction field effect transistor, the method according to claim 22.

24. The first read voltage of the first pair of read voltages is greater than the first read voltage of the second pair of read voltages, the first read voltage of the second pair of read voltages is greater than the intermediate voltage, the intermediate voltage is greater than the second read voltage of the second pair of read voltages, and the second read voltage of the second pair of read voltages is greater than the second read voltage of the first pair of read voltages, the method according to claim 19.

25. The first read voltages of the first pair and the second pair of read voltages are positive voltages, the second read voltages of the first pair and the second pair of read voltages are negative voltages, the second read voltage has the same amplitude as the first read voltage, and the intermediate voltage is a ground voltage, the method according to claim 19.

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