System and method for manufacturing a superconducting integrated circuit

Abstract

A system and method for mitigating magnetic flux trapping in a superconducting integrated circuit includes forming a first metal layer having a first critical temperature and a first device, and forming a magnetic flux steering layer having a second critical temperature. The magnetic flux steering layer is positioned in communication with an opening location, and the opening location is spaced from the first device to isolate the first device from magnetic flux trapped at the opening. The superconducting integrated circuit is cooled by a cryocooler from a first temperature above both the first and second critical temperatures to a second temperature below both the first and second critical temperatures. The relative temperature difference between the first and second critical temperatures causes the magnetic flux steering layer to direct magnetic flux away from the first device and trap magnetic flux at the opening location.

Description

Technical Field

[0001] Field The present disclosure generally relates to systems and methods for manufacturing superconducting integrated circuits, and more particularly to the manufacture of superconducting integrated circuits including flux traps by design.

Background Art

[0002] Background Superconducting Processor A quantum processor can take the form of a superconducting processor. A superconducting processor can include processors not targeted for quantum computing. For example, some implementations of superconducting processors can operate by emphasizing different principles (such as the principles that control the operation of classical computer processors) rather than focusing on quantum effects (such as quantum tunneling, superposition, and entanglement). Certain advantages may still exist for such implementations of superconducting "classical" processors. Due to natural physical characteristics, superconducting classical processors can enable faster switching speeds and shorter computation times than non-superconducting processors, and thus it is more practical to solve certain problems with superconducting classical processors. The present system and method are particularly well-suited for use in manufacturing both superconducting quantum processors and superconducting classical processors.

[0003] Superconducting Quantum Bit Superconducting qubits are a type of superconducting quantum device that can be included in a superconducting integrated circuit. Depending on the physical properties used to encode information, superconducting qubits can be classified into several categories. For example, superconducting qubits can be classified into charge, flux, and phase devices. Charge devices store and manipulate information in the charge state of the device. Flux devices store and manipulate information in variables related to the magnetic flux passing through a part of the device. Phase devices store and manipulate information in variables related to the difference in superconducting phase between two sites of the device. Recently, hybrid devices using two or more of the degrees of freedom of charge, flux, and phase have been developed. Superconducting qubits typically include at least one Josephson junction. A Josephson junction is a small obstacle in another continuous superconducting current path, typically realized by a thin insulating barrier sandwiched between two superconducting electrodes. Thus, a Josephson junction is usually formed as a three-layer or "triple-layer" structure. Further, superconducting qubits are described, for example, in U.S. Patent No. 7,876,248, U.S. Patent No. 8,035,540, and U.S. Patent No. 8,098,179.

[0004] Integrated circuit manufacturing An integrated circuit is also referred to as a chip in this application, and a superconducting integrated circuit is also referred to as a superconducting chip in this application.

[0005] Conventionally, superconducting integrated circuits have not been manufactured in state-of-the-art semiconductor fabrication facilities. This is because some of the materials used in superconducting integrated circuits may contaminate semiconductor factories. For example, gold can be used as a resistor in superconducting circuits, but gold may contaminate the manufacturing tools used to fabricate complementary metal-oxide-semiconductor (CMOS) wafers in semiconductor factories.

[0006] Superconductor manufacturing is typically carried out in a research environment that can optimize standard industrial techniques for superconducting circuit manufacturing. Superconducting integrated circuits are often manufactured using tools conventionally used for manufacturing semiconductor chips or integrated circuits. Due to issues specific to superconducting circuits, not all semiconductor processes and techniques can necessarily be transferred to superconducting chip manufacturing. Converting semiconductor processes and techniques for use in superconducting chips and circuits often requires changes and fine-tuning. Such changes and adjustments are typically not obvious and may require many experiments. The semiconductor industry faces problems and issues that are not necessarily related to the superconducting industry. Similarly, problems and issues related to the superconducting industry are often of little or no concern in standard semiconductor manufacturing.

[0007] Any impurities within a superconducting chip can become noise that can impair or reduce the functionality of individual devices (e.g., superconducting qubits) and the superconducting chip as a whole. Since noise is a significant concern for the operation of a quantum computer, measures should be taken to reduce noise as much as possible.

[0008] Hamiltonian Description of a Quantum Processor According to some implementations of the present system and device, a quantum processor can be designed to perform adiabatic quantum computing and / or quantum annealing. A general problem Hamiltonian includes a first component proportional to diagonal single-qubit terms and a second component proportional to diagonal multi-qubit terms. The form of the problem Hamiltonian can be, for example, in the following form.

Number

Number

[0009] Noise in Quantum Processors Low noise is a desirable characteristic of quantum devices. Noise can impair or degrade the functionality of individual devices (e.g., superconducting qubits) and superconducting processors as a whole. Noise can have an adverse effect on qubit coherence and reduce the effectiveness of qubit tunneling phenomena. Since noise is a significant concern for the operation of quantum processors, measures should be taken to reduce noise as much as possible so that the environment does not cause a transition from coherent quantum tunneling phenomena to incoherent quantum tunneling phenomena.

[0010] Impurities can be deposited on the metal surface and / or can arise from the chemical properties of the etch / photoresist and the interaction with the metal. Noise can be caused by impurities on the upper surface of the quantum processor. In some cases, superconducting devices that are susceptible to the effects of noise are fabricated in the upper wiring layer of the superconducting integrated circuit and are thus sensitive to post - manufacturing processes. There is a risk of incorporating impurities that cause noise during post - manufacturing processes. One way to reduce noise is to use a barrier passivation layer, such as an insulating layer, to overlap on the top wiring layer. Using a barrier passivation layer to minimize noise from impurities on the upper surface of the quantum processor is described in U.S. Patent Application Publication No. 2018 / 02219150A1.

[0011] Furthermore, noise can result from the external environment or the surrounding circuitry in a superconducting processor. In a quantum processor, flux noise on a qubit can prevent the quantum processor from being properly annealed due to the abrupt transitions between qubit states when sweeping the magnetic flux bias. Flux noise can be the result of currents passing through the wiring of other devices included in the superconducting processor and can particularly adversely affect the qubit at each degeneracy point. For example, flux noise can cause errors in the calculations performed by the superconducting processor due to errors in setting the magnetic flux bias and coupling strength values. Such values are important for using integrated circuits as part of a quantum processor. By adding circuitry (e.g., an on-chip shield) to compensate for any non-ideal flux qubit behavior, a processor with a careful layout and a high-precision flux source can be designed to remove most of the static control errors. However, often the limitations of integrated circuit manufacturing capabilities can make it difficult to address noise by changing the processor layout and adding circuitry. Thus, there is a general need for systems and methods for manufacturing integrated circuits with reduced flux noise.

[0012] shielding Magnetic fields generated externally can cause unwanted interactions with devices in an integrated circuit. Thus, a superconducting shield may be required in proximity to the device on which the integrated circuit is mounted to reduce the intensity of interference such as magnetic and electric fields. This example is described in International Publication No. WO 96 / 09654.

[0013] Superconducting shields incorporated into integrated circuits are used to protect superconducting quantum interference device (SQUID) packages from DC and AC noise such as magnetic and electric fields that could otherwise interfere with the operation of the integrated circuit. Parts of the integrated circuit may not be shielded to allow for the transfer of magnetic and electric fields external to the SQUID package. An example of this approach is described in U.S. Patent No. 5,173,660.

[0014] To isolate a device from a DC power line that could otherwise apply an undesirable bias to the device, a superconducting shielding layer can be used in single flux quantum (SFQ) or rapid single flux quantum (RSFQ) technology. The device mounts an integrated circuit and is isolated from the DC power line by placing a ground plane between the device and the DC power line. Examples of this type of approach are described, for example, in Nagasawa et al., “Development of advanced Nb process for SFQ circuits” Physica C 412 - 414 (2004) 1429 - 1436 (referred to herein as Nagasawa) and Satoh et al., “Fabrication Process of Planarized Multi - Layer Nb Integrated Circuits” IEEE Transactions on Applied Superconductivity, Vol. 15, No.2, (June 2005).

[0015] In an SFQ circuit, the ground plane and the shielding layer are terms used interchangeably. The ground plane in an SFQ integrated circuit is a metal layer that appears as the ground potential for most signals in the circuit, like an infinite ground potential. The ground plane helps reduce noise within the integrated circuit and can be used to ensure that all components within the SFQ integrated circuit have a common potential for comparing voltage signals. Nagasawa shows the use of contacts between the wiring layer and the ground plane throughout the SFQ circuit.

[0016] The superconducting current flowing in a superconducting wire has an associated magnetic field in the same way as the electrons flowing in a normal - conducting metal wire. The magnetic field can inductively couple to the superconducting wire and induce a current to flow. Quantum information processing using superconducting integrated circuits necessarily involves superconducting currents moving in the wires and thus the associated magnetic fields. The quantum properties of quantum devices are very sensitive to noise, and stray magnetic fields in superconducting quantum devices can adversely affect the quantum information processing properties of such circuits.

[0017] The above examples of related technical fields and limitations related thereto are illustrative and are not intended to be exclusive. Other limitations of the related technical fields will be apparent to those skilled in the art upon reading this specification and examining the drawings. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0018] BRIEF SUMMARY According to an aspect, a method for reducing magnetic flux trapping in a superconducting integrated circuit includes forming a first device, the first device including at least a portion of a first metal layer within the superconducting integrated circuit, the first metal layer including a first superconducting material having a first critical temperature, and forming a magnetic flux directing layer including a second superconducting material having a second critical temperature, wherein the first superconducting material and the second superconducting material are selected such that when the superconducting integrated circuit is cooled from a first temperature above both the first critical temperature and the second critical temperature to a second temperature below both the first critical temperature and the second critical temperature, a relative temperature difference between the first critical temperature and the second critical temperature causes magnetic flux to be directed away from the first device and toward a magnetic flux trapping position spaced apart from the first device in the magnetic flux directing layer, and as the superconducting integrated circuit is cooled, the magnetic flux is trapped at the magnetic flux trapping position and separated from the first device.

[0019] According to another aspect, forming the flux guiding layer may include forming a flux guiding layer positioned in flux transfer communication with the flux trap position, and directing flux away from the first device and towards the flux trap position in the flux guiding layer may include directing flux to the flux trap position in the flux guiding layer. The method may further include forming a flux trap opening at the flux trap position. Forming a flux trap opening at the flux trap position may include forming one of a parallel tube opening and a groove in a superconducting integrated circuit at the flux trap position. The method may further include forming a shield for sealing the flux trap position. Forming a shield for sealing the flux trap position may include forming a plurality of superconducting stud vias in the superconducting integrated circuit. Forming the flux guiding layer may include depositing a superconducting metal layer including an opening aligned with the flux trap opening. Forming the first device may include forming the first device as one of a qubit and a coupler. Forming the first device may include forming a first metal layer so as to overlap at least a portion of the flux guiding layer. Forming the flux guiding layer may include selecting a second critical temperature to be below a first critical temperature. The method may further include forming a second metal layer adjacent to the first metal layer. The second metal layer may include a shielding structure for shielding the first device. The second metal layer may include a superconducting material having a third critical temperature. Forming a flux guiding layer including the second superconducting material may include providing a relative temperature difference between the second critical temperature and the third critical temperature to direct flux away from the first device and trap flux at the flux trap position. Forming the first device may include forming a first metal layer so as to overlap at least a portion of the flux guiding layer. Forming the flux guiding layer may include selecting a second critical temperature to be below a third critical temperature. The method may further include forming one or more additional superconducting metal layers so as to overlap at least a portion of the flux guiding layer. The critical temperature of each of the one or more additional superconducting metal layers may be able to exceed the second critical temperature. Forming the first metal layer,Forming one or more additional superconducting metal layers and forming a flux guiding layer may include selecting the respective critical temperature of each layer to gradually increase layer by layer from the flux guiding layer to the topmost layer of the first metal layer and the one or more additional superconducting metal layers. Forming a flux guiding layer including a second superconducting material may include forming a flux guiding layer overlapping at least a portion of the first metal layer. The method may further include forming a second metal layer. The first metal layer may overlap at least a portion of the second metal layer. The second metal layer may include a shielding structure that shields the first device. The second metal layer may include a superconducting material having a third critical temperature. The method may further include forming a base metal layer. The second metal layer may overlap the base metal layer. The third critical temperature may be higher than the critical temperature of the base metal layer, and the critical temperature of the base metal layer may be higher than the second critical temperature. Forming a flux guiding layer using a second superconducting material may include selecting the second critical temperature to be higher than a first critical temperature. Forming a flux guiding layer may include forming a flux trapping structure overlapping at least a portion of a flux trap position. Forming a flux trapping structure may include forming at least one port. The method may further include forming a second device within the flux trap position. Forming a second device within the flux trap position may include forming a digital-to-analog converter. Forming a flux guiding layer including a second superconducting material may include forming a flux guiding layer including a high kinetic inductance material. Forming a flux guiding layer including a high kinetic inductance material may further include forming at least one port in the flux guiding layer.,

[0020] According to an aspect, a superconducting integrated circuit includes a first device including at least a part of a first metal layer within the superconducting integrated circuit, the first metal layer including a first superconducting material having a first critical temperature, a first device; a flux trap position spaced apart from the first device and positioned such that the flux trapped within the flux trap position is separated from the first device; and a flux guiding layer including a superconducting material having a second critical temperature and positioned in communication with the flux trap position, wherein the first critical temperature and the second critical temperature have a relative temperature difference such that when the superconducting integrated circuit is cooled to a temperature below both the first critical temperature and the second critical temperature, the flux leaves the first device, is guided to the flux guiding layer, and the flux guiding layer guides and traps the flux within the flux trap position, a superconducting integrated circuit is provided.

[0021] According to another aspect, the superconducting integrated circuit may further include a flux trap opening at the flux trap position, the flux trap opening may include one of a parallel tube opening and a groove positioned within the superconducting integrated circuit, the superconducting integrated circuit may further include a shield that seals the flux trap position, the shield may include a plurality of superconducting stud vias, the flux directing layer may include an opening aligned with the flux trap opening, the first device may include one of a qubit and a coupler, the first metal layer may overlap at least a portion of the flux directing layer, the first critical temperature may be able to exceed the second critical temperature, the superconducting integrated circuit may further include a second metal layer positioned adjacent to the first metal layer, the second metal layer may include a shielding structure that shields the first device, the second metal layer may include a superconducting material having a third critical temperature, the relative temperature difference between the second critical temperature and the third critical temperature may be selected to be away from the first device and to direct the magnetic flux to the flux trap position, the first metal layer may overlap at least a portion of the flux directing layer, the second critical temperature may be able to be lower than the third critical temperature, the superconducting integrated circuit may further include one or more additional metal layers that overlap at least a portion of the flux directing layer, the critical temperature of each additional metal layer may be able to exceed the second critical temperature, the critical temperatures of the first metal layer, the one or more additional metal layers, and the flux directing layer may gradually increase layer by layer from the flux directing layer to the topmost layer of the first metal layer and the one or more additional metal layers, the flux directing layer may overlap at least a portion of the first metal layer, the superconducting integrated circuit may further include a second metal layer, the first metal layer may overlap at least a portion of the second metal layer, the second metal layer may include a shielding structure that shields the first device, the second metal layer may include a superconducting material having a third critical temperature, and may further include forming a base metal layer, the second metal layer may overlap on the base metal layer, the third critical temperature may be able to exceed the critical temperature of the base metal layer, and the critical temperature of the base metal layer may be able to exceed the second critical temperature, the first critical temperature may be able to be lower than the second critical temperature, the flux directing layer may include a flux trap structure that overlaps at least a portion of the flux trap position, and the flux trap structure may include at least one port.The magnetic flux trap position may include a second device, which may be a digital-to-analog converter. The magnetic flux directing layer may include a high kinetic inductance material, and the magnetic flux directing layer may further include at least one port. At least 10% of the energy stored in the high kinetic inductance material may be stored as kinetic inductance, and the kinetic inductance ratio of the high kinetic inductance material may be 0.1 < α ≦ 1.

[0022] In other aspects, as will be recognized by those skilled in the art, the above features may be combined in any reasonable combination.

[0023] Brief Description of Some of the Drawings In the drawings, the same reference numerals identify similar elements or operations. The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the visibility of the drawings. Further, a particular shape of an element as illustrated is not necessarily intended to convey any information regarding the actual shape of the particular element, but is merely selected to simplify recognition in the drawings.

Brief Description of the Drawings

[0024]

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Best Mode for Carrying Out the Invention

[0025] Detailed Description In the following description, specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one of ordinary skill in the art will recognize that the implementations may be practiced without one or more of these specific details or using other methods, components, materials, and the like. In other instances, well-known structures related to computer systems, server computers, and / or communication networks are not shown or described in detail to avoid unnecessarily obscuring the description of the implementations.

[0026] Unless the context dictates otherwise, throughout the following specification and claims, the term "comprising" is synonymous with "including" and is inclusive or non-limiting (i.e., does not exclude additional, non-enumerated elements or method acts).

[0027] References to "one implementation" or "an implementation" throughout this specification mean that at least one implementation includes the particular features, structures, or characteristics described in connection with that implementation. Thus, appearances of the phrases "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0028] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally used in its inclusive sense (i.e., "and / or") unless the context clearly dictates otherwise.

[0029] The headings and abstracts of the disclosure provided in this specification are for convenience only and do not interpret the scope or meaning of the implementations.

[0030] A superconducting material undergoes a transition to superconducting behavior at a critical temperature T C . When T is higher than T C , the material is in a non-superconducting state, while when T is lower than T C , the material behaves as a superconductor. The critical temperature is also referred to as the transition temperature in this application.

[0031] One of the characteristics of a superconductor is that the superconductor expels an internal magnetic field. When there is an external magnetic field present when cooling a superconducting integrated circuit through the critical temperature of the constituent superconducting material, the magnetic flux can become trapped within the superconducting integrated circuit because the magnetic flux can no longer pass through the superconducting material and reach other locations.

[0032] A magnetic flux trap can occur, for example, at the location of defects or impurities in the superconducting materials that make up a superconducting integrated circuit and at various structural features of the superconducting integrated circuit or the component devices that make up the superconducting integrated circuit. For example, in a superconducting circuit having both superconducting and non-superconducting regions, the non-superconducting regions can be preferred locations where magnetic flux is trapped. A magnetic flux trap can result from the cooling power of a particular structure or implementation form of a superconducting integrated circuit or a component device of a superconducting integrated circuit.

[0033] T C If it is lower than, the magnetic flux can no longer move out of or through the superconductor, and as such, it remains trapped within the superconducting integrated circuit, which can result in the generation of a magnetic flux trap. The trapped magnetic flux can contribute to noise within the superconducting integrated circuit. Further, the trapped magnetic flux can shift the operating points of superconducting quantum interference devices and other on-chip devices. It may be desirable to reduce the trapped magnetic flux within the superconducting integrated circuit and / or direct the magnetic flux to a safe pinning site.

[0034] To form a quantum computer having a sufficient number of operating components to solve complex problems, it is necessary to use a combination of multiple superconducting components. When implementing a group of nominally identical devices at different locations within a superconducting integrated circuit, it is necessary to implement an on-chip control architecture to adjust the individual components. For example, a magnetic digital-to-analog converter can be used to compensate for individual variations in the operating point. However, the trapped magnetic flux can cause a magnetic flux offset that exceeds what the digital-to-analog converter can compensate for, thereby rendering the device non-functional within the circuit.

[0035] External and / or on-chip magnetic shields can be used to reduce the background magnetic field during the cooling of a superconducting integrated circuit (see, e.g., U.S. Patent No. 8,441,330). As a result, the amount of available magnetic flux trapped within the superconducting integrated circuit is reduced. However, some background magnetic field typically remains (the remaining background magnetic field is also referred to herein as the residual magnetic field), and elements on the superconducting integrated circuit can generate magnetic flux, so external and / or on-chip magnetic shields cannot fully prevent magnetic flux from being trapped within the integrated circuit. Thus, the resulting trapped magnetic flux can be a source of noise within the superconducting integrated circuit. Further, the trapped magnetic flux can shift the operating points of some superconducting devices and can become a problematic magnetic flux offset. As used herein, a "magnetic flux sensitive component" means both a component that is affected by noise within the superconducting integrated circuit generated by trapped magnetic flux and a component that is affected by trapped magnetic flux that shifts the operating point of these components.

[0036] Accordingly, it is beneficial to design a superconducting integrated circuit that includes elements for reducing and / or preventing the effects of magnetic flux trapping on magnetic flux sensitive components of the superconducting integrated circuit. Guard ground vias and moats (elongated holes or recesses) can be used in the design of a superconducting integrated circuit to function as a secure pinning site for trapped magnetic flux. See, e.g., Robertazzi et al. FLUX TRAPPING EXPERIMENTS IN SINGLE FLUX QUANTUM SHIFT REGISTERS, IEEE Trans. On Appl. Supercond., Vol. 7, pp. 3164-3167, June 1997.

[0037] As described above, when cooling the superconducting material in one or more constituent devices, wires, or other components of a superconducting integrated circuit through the critical temperature of the superconducting material, magnetic flux can become trapped within the superconducting integrated circuit. Magnetic flux trapped within a superconducting integrated circuit can be a source of noise that causes errors, for example, in the calculation results from quantum annealing. Further, magnetic flux trapped within a superconducting integrated circuit can move the operating point of a device beyond the compensation limits of a control device and render the device inoperable.

[0038] Magnetic flux trapping can be limited by shielding the superconducting integrated circuit from an external magnetic field. However, a residual external magnetic field and an induced magnetic field from the components of the superconducting integrated circuit can still generate magnetic flux. Magnetic flux can cause noise, errors, and inoperable components, and in particular, should become trapped near a magnetic flux sensitive superconducting device or cause the operating point of these devices to move.

[0039] Throughout this specification, the term "magnetic flux sensitive superconducting device" is used to describe a superconducting device that is susceptible to the effects of noise and for which an operating environment free of noise is highly desirable for the performance of a superconducting integrated circuit (e.g., a quantum processor). Further, "magnetic flux sensitive superconducting device" is used to describe a superconducting device (e.g., a qubit) that is susceptible to having its operating point moved by trapped magnetic flux. It is understood that the same device can be susceptible to both the effects of noise and the movement of the operating point of the device. Due to the poor performance of magnetic flux sensitive devices, a quantum processor can produce inaccurate or sub-optimal solutions to problems, e.g., inaccurate or sub-optimal results from quantum annealing.

[0040] In some implementations, the superconducting integrated circuit includes a quantum processor, and the quantum processor includes superconducting qubits. A qubit is an example of a superconducting device that can be considered a flux-sensing device. Flux noise and flux traps in the vicinity of a superconducting flux qubit can, for example, produce inaccurate or suboptimal results and / or results that are solutions to problems different from those programmed, thereby degrading the performance of the quantum processor.

[0041] In some implementations, the superconducting integrated circuit includes a magnetometer. A magnetometer is a device used to measure magnetic flux. The magnetometer in the quantum processor can be used to measure residual magnetic flux from an external magnetic field and induced magnetic flux from components of the quantum processor. The flux noise in the magnetometer may cause little or no degradation in the performance of the quantum processor. Thus, as used herein, a magnetometer is an example of a device that is described as being little or not affected by noise or magnetic flux. Another example of a device that is described as being little or not affected by noise may be a digital-to-analog converter (DAC). It should be noted that the terms “noise-sensitive” and “susceptible to noise” do not necessarily imply that the device itself is physically more or less susceptible to the effects of noise compared to other devices that are not described as noise-sensitive. Instead, “noise-sensitive” is used to mean the sensitivity of processor performance to flux noise within a given device. The sensitivity of processor performance to flux noise is higher in noise-sensitive devices than in devices described as being little affected by noise. Further, devices that are little affected by noise are also little affected by the movement of the operating point of the device due to trapped magnetic flux.

[0042] One way to reduce the effect of trapped magnetic flux on the operation of the superconducting integrated circuit is to configure the circuit to provide locations where magnetic flux can be trapped away from the flux-sensitive superconducting devices. These locations are also referred to herein as safe (or safer) pinning sites for trapped magnetic flux.

[0043] During cooling, a superconducting integrated circuit that draws magnetic flux away from a flux-sensitive superconducting device and incorporates a movement path for the magnetic flux to a secure pinning site for trapping the magnetic flux can be provided. Since the movement path of the magnetic flux through the superconducting integrated circuit during cooling depends on the critical temperature of each superconducting layer, a superconducting material that provides a favorable progression of the critical temperature when cooling the superconducting integrated circuit can be selected.

[0044] An electric current flowing through a metallic material stores energy in both the magnetic field of the metal and the kinetic energy of the charge carriers (e.g., electrons or Cooper pairs). In a non-superconducting metal, the charge carriers collide frequently with the lattice and lose the kinetic energy of the charge carriers as Joule heating. This is also called scattering and releases energy rapidly. In a superconducting material, since the charge carriers are Cooper pairs that are protected against dissipation by scattering, the scattering is significantly reduced. As a result, the superconducting material can store energy in the form of kinetic inductance. Due to this phenomenon, the kinetic inductance can efficiently store energy within the superconducting material. The kinetic inductance is at least partially determined by the inertial mass of the charge carriers of a given material and increases as the carrier density decreases. As the carrier density decreases, fewer carriers need to have a proportionally faster velocity to generate the same current. A material having a high kinetic inductance for a given region (described later) is called a "kinetic inductance material" or a "high kinetic inductance material".

[0045] A kinetic inductance material is a material having a high base state resistance and / or a small superconducting energy gap and has a higher kinetic inductance per unit area. Generally, the total inductance L of a superconducting material is given by L = L K + L G (where L G is the geometric inductance and L K is the kinetic inductance). The kinetic inductance of a superconducting film at approximately zero temperature is the effective penetration depth λ effis proportional. In particular, for a film having a given thickness t, the kinetic inductance of the film is proportional to the ratio of the width W of the film to the length L of the film (where the length is the direction of the current and the width is orthogonal to the length (note that both the width and the length are orthogonal to the dimension in which the thickness is measured)). That is, for a superconducting film having a given thickness, [Number] is. The kinetic inductance ratio of the material is [Number] characterized as. Materials that are considered to have a high kinetic inductance typically have an α in the range of 0.1 < α ≦ 1. Materials having less than 10% of the energy stored as kinetic inductance are considered to be conventional magnetic memory inductors with small corrections.

[0046] The superconducting integrated circuit can be cooled by a cryogenic refrigerator. The cryogenic refrigerator can be, for example, a dilution refrigerator and / or a cryocooler (e.g., a pulse tube cryocooler, also referred to as a pulse tube refrigerator in this application). The superconducting integrated circuit can be cooled to a temperature below 1 K. In some implementations, the superconducting integrated circuit is cooled to below 20 mK. In some implementations, the superconducting integrated circuit and the cryogenic refrigerator are elements of a superconducting computer. In some implementations, the superconducting computer is a superconducting quantum computer.

[0047] FIG. 1 shows a partial cross-sectional view of an example implementation of a superconducting integrated circuit 100 manufactured by the method 500 of FIG. 5. For an explanation of the method 500 of FIG. 5, see below.

[0048] The superconducting integrated circuit 100 includes a first metal layer 102 having a first device 104, and the first metal layer 102 has a first critical temperature T C1It is formed from a superconducting material having []. The first device 104 can be a flux-sensitive superconducting device as described above. For example, the first device 104 can be a qubit or a coupler formed as part of the superconducting integrated circuit 100. As shown in FIG. 1, a part of the wiring shown as the first device 104 forms only a part of the first device 104, has other components in other parts of the superconducting integrated circuit 100, and can also extend to other layers of the superconducting integrated circuit 100. It is understood that the term "device" is used throughout this specification in this way, and only a part of the device can be shown in the drawings. In the specific implementation shown in FIG. 1, the device 104 can be a part of the body of a qubit or a coupler.

[0049] The flux trap position (e.g., the opening 106 in the example of the implementation of FIG. 1) is selected at a position within the superconducting integrated circuit 100 that is a preferred or "safe" position for trapping magnetic flux. In a preferred implementation, the flux trap position in the form of the opening 106 is a series of continuous openings intentionally fabricated through the superconducting material such that openings are provided in each superconducting layer and the openings are aligned or connected throughout the entire superconducting integrated circuit. The opening 106 is disposed away from the first device 104. When cooling the superconducting integrated circuit 100, the opening 106 is positioned so as to preferentially trap magnetic flux within the opening 106 and separate the magnetic flux trapped within the opening 106 from the first device 104.

[0050] As used herein, the term "separation" is used to mean an interval or configuration such that the magnetic flux trapped within the opening does not have a sufficient impact on the flux-sensitive device to cause an error. It is understood that the tolerance for errors depends on the sensitivity of the flux-sensitive device and the configuration of the superconducting integrated circuit. As such, "separation" means an interval or configuration that is small enough such that the coupling between the trapped magnetic flux and the flux-sensitive device does not affect the operation of the circuit element.

[0051] In some embodiments, the aperture 106 can be a box-shaped opening or recess formed in the superconducting integrated circuit 100 or a groove positioned through a portion of the superconducting integrated circuit 100. In some embodiments, it can be beneficial to provide the aperture 106 in the form of a spiral opening or recess to give the aperture 106 a large surface area.

[0052] The example of the embodiment of FIG. 1 shows an aperture 106 formed in the superconducting integrated circuit 100 that functions as a magnetic flux trap position, but it is understood that the magnetic flux trap position can also be a component or region of the superconducting integrated circuit 100 that is not flux sensitive. For example, the magnetic flux trap position can be a junction or seam within the superconducting integrated circuit 100 positioned away from the flux sensitive device, or it can be an empty region of the superconducting integrated circuit 100 positioned away from the flux sensitive device. The magnetic flux trap position in the form of the aperture 106 is preferably a series of aligned apertures in each superconducting layer that penetrates the entire superconducting integrated circuit.

[0053] Optionally, a shield can be provided to seal the magnetic flux trap position. As shown in FIG. 1, a shield 108 can be provided to seal the aperture 106. Advantageously, the shield 108 can be formed from a layer of superconducting material of sufficient thickness that does not penetrate the shield 108 such that the magnetic flux trapped in the aperture 106 reaches the first device 104. In some embodiments, the shield 108 can be formed from a plurality of superconducting stud vias formed through the layers of the integrated circuit 100 to provide a barrier around the aperture 106.

[0054] The superconducting integrated circuit 100 has a second critical temperature T C2It includes a flux-aligning layer 110 formed from a superconducting material having []. In some implementations, the flux-aligning layer 110 is positioned in magnetic flux transfer communication with the opening 106. As used herein, it is understood that the flux-aligning layer and the flux trap position may not be in contact and may not be directly adjacent, but magnetic flux transfer communication means sufficient physical proximity and arrangement to transfer magnetic flux from the flux-aligning layer to the flux trap position. In the example of the implementation of FIG. 1, the flux-aligning layer 110 is the base layer of the superconducting integrated circuit 100. In some implementations, the opening 106 may be formed through a portion of the flux-aligning layer 110.

[0055] In some implementations, the first critical temperature T C1 and the second critical temperature T C2 The materials of the first metal layer 102 and the flux-aligning layer 110 are selected such that they have a relative temperature difference. In these implementations, the first metal layer 102 and the flux-aligning layer 110 reach the critical temperatures of these layers at different stages during the cooling process (also referred to as cooling in this application).

[0056] When the superconducting integrated circuit 100 is cooled to a temperature below both the first critical temperature T C1 and the second critical temperature T C2 As will be described further below, the magnetic flux leaves the first device 104 and is directed to the flux-aligning layer 110, which directs and traps the magnetic flux within the opening 106.

[0057] In the implementation shown in FIG. 1, the first metal layer 102 overlaps at least a portion of the flux-aligning layer 110. In one implementation, the first critical temperature T C2 above the second critical temperature T C1 Can be used to select the relative critical temperature.

[0058] In some implementations, the superconducting integrated circuit 100 includes a second metal layer 112 positioned adjacent to the first metal layer 104. In some implementations, the second metal layer 112 provides an on-chip shielding structure to shield the first device 104 from a magnetic field. In some implementations, the on-chip shielding structure can control the magnetic flux behavior of the device shielded by the on-chip shielding structure. That is, the on-chip shield can direct magnetic flux away from the first device 104 when the first device 104 passes through the critical temperature of the first device, and the critical temperature of the first device becomes less related to magnetic flux trapping. Further, although an on-chip shield is provided in the example of the implementation of FIG. 1, it is understood that it is not necessary to provide an on-chip shield as shown. The first wiring layer 102 may include a magnetic flux directing structure, or the nature of the first device 104 may be such that the first device 104 can direct magnetic flux such that it is controlled by the magnetic flux directing layer 110 without the assistance of the second metal layer 112.

[0059] On-chip shielding, such as by a layer of superconducting metal close to a flux-sensitive superconducting device, is further described in U.S. Patent No. 7,687,938 and U.S. Patent No. 8,247,799.

[0060] A third critical temperature T C3 The second metal layer 112 can be formed from a superconducting material having. Direct the magnetic flux away from the first device 104 and direct it to the magnetic flux directing layer 110, the second critical temperature T C2 And the third critical temperature T C3 The relative temperature difference between and can be selected.

[0061] One or more additional metal layers (e.g., metal layers 114, 116, and 118) can be included in the superconducting integrated circuit 100, each additional metal layer overlapping at least a portion of the magnetic flux directing layer 110, and the critical temperature of each additional metal layer (e.g., each of the metal layers 114, 116, 118) is the second critical temperature T C2exceeds. Further, the additional metal layers 114, 116, and 118 may include flux-sensitive superconducting devices.

[0062] In some implementations, the critical temperature may be selected to gradually increase layer by layer from the lower layer to the upper layer (i.e., from the base layer, also referred to as the flux orientation layer 110 in this application, to the topmost metal layer 114) in the superconducting integrated circuit 100.

[0063] In the implementation shown in FIG. 1, the cooling process may first start with the additional metal layer 114 having the highest critical temperature and first transitioning to superconductivity, and each critical temperature may be selected to push the magnetic flux into the aperture 106 and the lower metal layer (e.g., the first metal layer 102). The next layer to transition is the first metal layer 102, followed by the shielding layer 112, the additional layers 116 and 118, and finally the base layer 110 that also functions as the flux orientation layer 110.

[0064] The flux orientation layer 110 directs the remaining magnetic flux that is continuously pushed downward into the flux orientation layer 110 towards the aperture 106 that separates the magnetic flux from the first device 104. As described above, the aperture 106 may be located in the flux orientation layer 110 that can also have a shield 108 and separates the magnetic flux from the first device 104.

[0065] In some implementations, the superconducting integrated circuit 100 is formed from a single superconducting material (which may be, for example, niobium or aluminum in some implementations). Different layers of the single superconducting material may have different critical temperatures as a result of processing during the formation of the superconducting integrated circuit 100, for example, during multiple deposition steps when forming the superconducting integrated circuit 100. One cause of this change in the critical temperature may be, for example, oxidation during processing that may have the effect of lowering the critical temperature of niobium.

[0066] FIG. 1 shows a superconducting integrated circuit 100 formed on a substrate layer 120. It is understood that the superconducting integrated circuit 100 may also be placed on other structures (e.g., other wiring layers and / or dielectric layers). In some implementations, the substrate 120 may be formed of silicon or sapphire.

[0067] Furthermore, FIG. 1 shows components of a superconducting integrated circuit 100 surrounded by a dielectric material 122. The dielectric material can be, for example, SiO2, SiN, or any other suitable dielectric material known in the art.

[0068] In a superconducting integrated circuit, the order in which different wiring layers pass through their respective critical temperatures when cooling can affect the position of trapped magnetic flux. In some implementations, advantageously, the preferred arrangement of the wiring layer critical temperatures within the superconducting integrated circuit will result in less magnetic flux being trapped near the flux-sensitive superconducting devices.

[0069] In the example implementation shown in FIG. 1, a general pattern of flux movement is driven by layers 114, 112, and 110. In the first stage of cooling, layer 114 (which has the highest critical temperature of the layers shown in FIG. 1) is the first layer to expel magnetic flux. In the second stage of cooling, the shielding layer 112 is the next layer to expel magnetic flux. The shielding layer 112 moves magnetic flux away from the first device 104 and passes the magnetic flux through a wall (e.g., wall 108) between the superconducting integrated circuit, such as between layer 114 and layer 112. In the final stage of cooling, the flux-aligning layer 110 pushes magnetic flux into the flux trap positions in the superconducting integrated circuit 100 that trap magnetic flux away from the first device 104 and other flux-sensitive superconducting devices. These positions can be near other devices that are not flux-sensitive (e.g., a digital-to-analog converter (DAC) and / or a magnetometer). These positions can preferably be the openings 106.

[0070] In an alternative implementation of the design shown in FIG. 1, T C2 is another critical temperature recognized for the superconducting integrated circuit 100, particularly T C1The critical temperature of the layer can be arranged to exceed this. In this implementation, the flux orienting layer 110 transitions to the superconducting state before the first metal layer 102. The flux orienting layer orients the magnetic flux towards the opening 106 and moves the magnetic flux away from the flux sensing device 104. When the remaining layers transition to the superconducting state, the magnetic flux is oriented towards the opening 106. In this implementation, if the layers that do not include the flux sensing device 104 can first become superconducting, the flux orienting layer can control the flux trapping behavior and move the magnetic flux away from these sensing devices before the layers including the sensing devices become superconducting. Generally, any layer including the flux sensing device has a T that is lower than the critical temperature of the provided flux orienting layer C If it has, a similar circuit can be designed. Thereby, the layer including the flux sensing device can pass through the critical temperature of the layer in an environment where there is no magnetic flux due to the direction of the magnetic flux by the flux orienting layer.

[0071] FIG. 2A shows a cross-sectional view of a part of the superconducting integrated circuit 100 of FIG. 1 manufactured by an alternative implementation of the method 500 of FIG. 5.

[0072] The superconducting integrated circuit 200 includes a first metal layer 202 having a first device 204, and the first metal layer 202 is made of a superconducting material having a first critical temperature T C1 formed therefrom. The first device 204 can be a flux-sensitive superconducting device as described above. For example, the first device 204 can be a qubit or a coupler formed as part of the superconducting integrated circuit 200.

[0073] A flux orienting layer 210 formed of a superconducting material having a second critical temperature T C2 is provided in the integrated circuit 200. In the implementation of FIG. 2A, the flux orienting layer 210 is an upper layer of the superconducting integrated circuit 200. A flux trapping structure 224 overlapping at least a part of the opening 206 is provided in the flux orienting layer 210.

[0074] In the example of the implementation form of FIG. 2, the magnetic flux trap structure 224 is a series of ports provided in the magnetic flux directing layer 210. Preferably, the ports are formed as a single twist or turn (e.g., meander) port formed in the magnetic flux directing layer 210. The ports can be provided in the superconducting metal layer by small gaps or cuts and can be used to trap magnetic flux.

[0075] Select the opening 206 as a location within the integrated circuit 200 that is disposed away from the first device 204 so as to separate the magnetic flux trapped within the opening 206 from the first device 204. When cooling the superconducting integrated circuit 200, dispose the magnetic flux trap structure 224 so as to overlap the opening 206 and direct magnetic flux to the opening 206. In some implementation forms, the opening 206 can be in the form of a box, parallel tube, groove, or spiral formed in the superconducting integrated circuit 200.

[0076] The magnetic flux directing layer 210 overlaps at least a portion of the first metal layer 202 and provides the superconducting integrated circuit 200 with a second metal layer 212 positioned adjacent to the first metal layer 202. The second metal layer 212 functions as an on-chip shield that shields the first device 204. The shielding layer 212 can at least partially control the magnetic flux behavior that affects the first device 204. The critical temperature T of the magnetic flux directing layer 210 C3 The second metal layer 212 can be formed from a superconducting material having. During cooling of the superconducting integrated circuit 200, the second metal layer 212 directs magnetic flux away from the first device 204 and directs magnetic flux to the magnetic flux directing layer 210. When cooling the magnetic flux directing layer through the critical temperature T of the magnetic flux directing layer C2 210, the magnetic flux trap structure 224 can serve to trap magnetic flux within the opening 206.

[0077] The superconducting integrated circuit 200 can include a base metal layer 214. The base metal layer 214 has a critical temperature T that is higher than the critical temperature T of the magnetic flux directing layer C2 and lower than the critical temperature T of the second metal layer 212 C3 of the critical temperature T C4It may have. In this implementation, when cooling the superconducting integrated circuit 200, the magnetic flux can first be pushed out from the second metal layer 212. Then, the magnetic flux can be pushed into the base metal layer 214 and finally into the magnetic flux orientation layer 210. In this implementation, the relationship of the critical temperatures is T C3 >T C4 >T C2 is.

[0078] The superconducting material of the superconducting integrated circuit 200 can be selected to generate the desired relationship between the critical temperatures (for example, the relationship described above). Different materials can be used to form the superconducting portions of the superconducting integrated circuit 200. For example, a hybrid stack technique such as that described in U.S. Provisional Patent Application No. 62 / 760,253 can be used.

[0079] In one implementation, the lower layers 214, 216, and 218 of the superconducting integrated circuit 200 can be formed from niobium having a critical temperature of about 9.3K. The upper layers 210 and 202 can be formed from aluminum having a critical temperature of about 1.2K.

[0080] To ensure that layer 212 becomes superconducting before the base layer 214, the base layer 214 can be formed from niobium with a lower critical temperature. This can be achieved, for example, by the intentional oxidation of niobium during the formation of the superconducting integrated circuit 200.

[0081] It is understood that the example of the implementation shown in FIG. 2A can be modified to include many different materials on different layers. In one implementation, three different materials can be used to form the superconducting integrated circuit 200. In another implementation, one or more layers of the superconducting integrated circuit 200 can be selected to have a motional inductance that allows control of the position where magnetic flux is easily trapped and / or can reduce the coupling to the surrounding structure. In some implementations, one or more layers can be a high motional inductance material, as will be described in more detail later.

[0082] A shield 208 may be provided to separate the flux trap position (e.g., aperture 206) from the first device 204. Advantageously, the shield 208 may be formed from a layer of superconducting material having a sufficient thickness such that the magnetic flux trapped in the aperture 206 does not penetrate the shield 208 and reach the first device 204. In some implementations, the shield 208 may be formed from a plurality of superconducting stud vias formed through various layers of the integrated circuit 200 to provide a barrier around the aperture 206.

[0083] Referring to FIG. 2A, in some implementations, the aperture 206 may include a second device 226 that is not a flux-sensitive superconducting device. This is beneficial for increasing the circuit density of the superconducting integrated circuit 100. The second device 226 may be, for example, a digital-to-analog converter (DAC) spiral or a magnetometer.

[0084] FIG. 2A shows a superconducting integrated circuit 200 formed on a substrate layer 220. It is understood that the superconducting integrated circuit 200 may also be placed on other structures (e.g., other wiring layers and / or dielectric layers). In some implementations, the substrate 220 may be formed of silicon or sapphire.

[0085] Further, FIG. 2A shows components of the superconducting integrated circuit 200 surrounded by a dielectric material 222. The dielectric material may be, for example, SiO2 or any other suitable dielectric material known in the art.

[0086] In some implementations (e.g., the implementation shown in FIG. 2A), the flux trap may be controlled by design. In particular, the flux trap mechanism may depend on the order of reducing the critical temperature during cooling, such that the shielding layer 212 becomes superconducting first, the base layer 214 becomes superconducting second, and the upper layer 210 becomes superconducting third (T C3 >T C4 >T C2 ).

[0087] In some implementations, it may be beneficial to form the shielding layer 212 as a continuous layer to form a ground plane under any flux-sensitive superconducting device (e.g., a qubit or a coupler). Next, the shielding layer 212 passes through the critical temperature T C3 and enters the superconducting state, expelling magnetic flux from the holes (e.g., opening 206) in the shielding layer 212 of the superconducting integrated circuit 200. Next, the base layer 214 undergoes a transition through the critical temperature of the base layer, trapping magnetic flux within the holes in the shielding layer 212.

[0088] Next, the upper layer 210, which functions as the flux-directing layer 210, undergoes a transition through the critical temperature T C2 of the upper layer, and the magnetic flux trapped within the opening 206 becomes confined within the magnetic flux trap structure 224. In some implementations, the magnetic flux trap structure 224 includes at least one port. As shown in FIG. 2A, an optional non-flux-sensitive device 226 can be present within the opening 206. In the implementation shown in FIG. 2A, the hierarchy of critical temperatures has the critical temperature of the shielding layer 212 above the critical temperature of the base layer 214 and the critical temperature of the base layer 214 above the critical temperature of the flux-directing layer 210 (T C3 >T C4 >T C2 ).

[0089] In some implementations (e.g., the implementation shown in FIG. 2B), the introduction of a second material (e.g., aluminum) into the fabrication of the superconducting integrated circuit 100 of FIG. 1 can provide a more favorable magnetic flux trapping mechanism regardless of the presence or absence of the magnetic flux trap structure 224 present in the flux-directing layer 210.

[0090] During the cooling of the superconducting integrated circuit 200 from T1 to T2, the shielding layer 212 passes through the critical temperature T C3After passing through, it first enters the superconducting state and expels magnetic flux from the shield under the first device 204 and any other potentially present flux-sensitive superconducting devices. As a result, the magnetic flux can be expelled into a region (the DAC plate or other flux trap locations designed in the superconducting integrated circuit 200). By providing the opening 206, the magnetic flux is preferentially expelled into the opening 206 and trapped within the opening 206.

[0091] After cooling these layers, the low critical temperature material (e.g., the aluminum layer) can pass through the critical temperature of the layer and enter a state where magnetic flux is trapped in the gap of the wall between the shielding layer 212 and the flux trap layer 210. This can provide a trapped magnetic flux configuration similar to the configuration described for the implementation form in FIG. 1, which moves the magnetic flux away from the flux-sensitive superconducting devices in the superconducting integrated circuit 200. In the case of a similar hybrid material circuit, it may be sufficient to ensure that the shielding layer 212 has a critical temperature higher than the critical temperature of the lower layer 214. Advantageously, when expelling the magnetic flux from these layers, an opening 206 is provided at the position for accommodating the magnetic flux.

[0092] In some implementation forms, an individual superconducting layer having a rather high critical temperature (referred to as a sky shield in this application) can be introduced into the superconducting integrated circuit as a magnetic flux orientation layer. FIGS. 3A and 3B show partial cross-sectional views of superconducting integrated circuits 300a and 300b manufactured by an alternative implementation form of the method 500 in FIG. 5.

[0093] Referring to FIG. 3A, the superconducting integrated circuit 300a includes a first metal layer 302 having a first device 304, and the first metal layer 302 is formed from a superconducting material having a first critical temperature. The first device 304 can be a flux-sensitive superconducting device as described above. For example, the first device 304 can be a qubit or a coupler formed as part of the superconducting integrated circuit 300a.

[0094] The second critical temperature T C2An integrated circuit 300a is provided with a flux-directing layer 310 formed from a superconducting material having. The flux-directing layer 310 is an upper layer of superconducting integrated circuits 300a and 300b. Advantageously, the flux-directing layer 310 can be placed overlapping on at least a first metal layer 302 and other layers including a flux-sensitive superconducting device. A flux trap structure 324 (e.g., a moat as described above) overlapping on at least a part of the opening 306 is provided in the flux-directing layer 310. When cooling the superconducting integrated circuit 300a, the flux trap structure 324 can be positioned to overlap on the opening 306 and direct flux into the opening 306. The flux trapped in the opening 306 is separated from the first device 304.

[0095] In some implementations, the opening 306 can be in the form of a box, parallel tubes, grooves, or spirals formed in the superconducting integrated circuit 300a. The flux-directing layer 310 overlaps on at least a part of the first metal layer 302. The superconducting integrated circuit 300 includes a second metal layer 312 positioned adjacent to the first metal layer 302, and the second metal layer 312 functions as an on-chip shield that shields the first device 304 and controls the flux behavior that can affect the first device 304.

[0096] In some implementations, the flux-directing layer 310 is a sky shield formed from a material having a critical temperature much higher than other superconducting materials forming the superconducting integrated circuit 300a and placed across the entire superconducting integrated circuit 300a. For example, the flux-directing layer 310 can be formed from Nb3Sn having a critical temperature of about 15K. In other implementations, as will be described in more detail later, the flux-directing layer 310 can be formed from a high kinetic inductance material having a higher critical temperature. In this case, the flux trap structure 324 (e.g., which can be a moat) is patterned in the flux-directing layer 310 to surround the flux seen in the superconducting integrated circuit 300a into the opening 306. The lower layer of the superconducting integrated circuit 300a has a critical temperature (T C1 、T C3Before passing through ([0]]) and being cooled and becoming superconducting, the magnetic flux can be enclosed in the opening 306. As a result, the remaining layers can pass through the critical temperature of the layers in an environment without magnetic flux.

[0097] When the magnetic flux directing layer 310 passes through the critical temperature of the magnetic flux directing layer and expels the magnetic flux to the magnetic flux trapping structure 324, regardless of the critical temperature order of the remaining layers of the superconducting integrated circuit 300a, any magnetic flux remaining in the upper wiring layer 326 is likely to be guided to the port 328 also formed in the upper wiring layer 326. Using an individual magnetic flux directing layer having a significantly higher critical temperature than other wiring layers of the superconducting integrated circuit 300a can play a role in preventing magnetic flux trapping during cooling of the lower layers of the superconducting integrated circuit 300a.

[0098] In some implementations, the critical temperatures of the various layers of the superconducting integrated circuit 300a may not significantly affect the pattern of magnetic flux trapping, but the manufacturing of the superconducting integrated circuit 300a includes a hybrid stack approach as described above. As described above, a second metal layer 312 for directing magnetic flux away from the first device 304 may be provided in the superconducting integrated circuit 300a. The base metal layer 314 may be formed from the same material as the second metal layer 312 or may be manufactured to have a lower critical temperature.

[0099] A shield 308 may be provided to seal the area below the magnetic flux trapping structure 324. The shield 308 may be arranged so that the magnetic flux trapped in the opening 306 does not penetrate the shield 308 and reach the first device 304. In some implementations, the shield 308 may be formed from a plurality of superconducting stud vias formed through the layers of the integrated circuit 300 to provide a barrier around the opening 306. In some implementations, it is beneficial to form the shield 308 as a plurality of superconducting stud vias that are at least three times thicker than the London penetration depth of the superconducting material selected to form the stud vias.

[0100] The aperture 306 may include a second device 330 that is not a flux-sensitive superconducting device. In some implementations, it may be beneficial to leave the aperture 306 empty, which is beneficial for increasing the circuit density of the superconducting integrated circuit 300a. The second device 330 can be, for example, a digital-to-analog converter (DAC) spiral or a magnetometer.

[0101] FIG. 3A shows a superconducting integrated circuit 300a formed on a substrate layer 320. It is understood that the superconducting integrated circuit 300a can also be placed on other structures (e.g., other wiring layers and / or dielectric layers). In some implementations, the substrate 320 can be formed of silicon or sapphire. Further, FIG. 3A shows the components of the superconducting integrated circuit 300a surrounded by a dielectric material 322. The dielectric material can be, for example, SiO2 or any other suitable dielectric material known in the art.

[0102] In the implementation shown in FIG. 3B, the superconducting integrated circuit 300b has the same structure as the superconducting integrated circuit 300a of FIG. 3A, except for the spacing between the flux biasing layer 310 and the upper wiring layer 326 (T C2 >T C3 , T C1 ). When the flux biasing layer 310 and the upper wiring layer 326 are spaced apart from each other, a layer of dielectric material 322 can be provided therebetween. In some implementations, separating the flux biasing layer 310 from other elements of the superconducting integrated circuit 300b by providing a layer of dielectric having a thickness sufficient to minimize or at least reduce the amount by which the capacitance of the qubits and couplers can be increased is beneficial. In some implementations, the thickness of the interlayer dielectric between the individual flux biasing layer 310 and the topmost metal layer of the remainder of the superconducting integrated circuit 300b can be proportional to the width of the flux trap structure 324. In implementations where the flux trap structure 324 takes the form of a moat, the dielectric thickness can be proportional to 1 / w 3 (where w is the width of the moat in the flux biasing layer). It is understood that the required thickness can also depend on the materials used to form the circuit, the type of devices formed in the layers, and the amount of flux in the circuit.

[0103] In the various implementations described above, by a method of manufacturing a superconducting integrated circuit so as to include a flux trap position, the flux trap is minimized or at least reduced and controlled. A superconducting integrated circuit is manufactured using a material having a hierarchy of transition temperatures, and the flux in the superconducting integrated circuit can be minimized or at least reduced by directing the flux to a region of the superconducting integrated circuit that is less affected by the trapped flux.

[0104] The critical temperature of each layer in the superconducting integrated circuit can be controlled by material selection or a process applied to the material. The process applied to the material can include a process resulting from post-processing of the superconducting integrated circuit during manufacturing.

[0105] One example of a process known to affect the critical temperature of a niobium layer is oxidation that can be performed during the manufacture of a superconducting integrated circuit. Oxidation can be used to affect the critical temperature of a metal layer in the superconducting integrated circuit and thereby the pattern of flux trapping. Specific structures (e.g., one or more ports) can be provided, for example, by a single-twist port structure or by narrowing the gap between strips of superconductor or narrowing a notch formed in the superconductor. Ports can be used to trap flux at a location in the superconducting integrated circuit that does not cause or causes few errors in the flux-sensitive superconducting device.

[0106] One example of material selection includes the selection of a high kinetic inductance superconducting material. A superconducting material having a high kinetic inductance can have a high critical temperature (T C c). A high kinetic inductance material can be defined as a material that stores at least 10% of the energy stored in the high kinetic inductance material as kinetic inductance or a material having a kinetic inductance ratio of 0.1 < α ≦ 1 for the high kinetic inductance material. In some implementations, the high kinetic inductance material can be one of WSi, MoN, NbN, NbTiN, TiN, and granular aluminum.

[0107] FIG. 4 illustrates a computing system 400 that includes a digital computer 402. Examples of digital computers 402 include one or more digital processors 406 that can be used to perform classical digital processing tasks. The digital computer 402 may further include at least one system bus 420 that couples at least one system memory 422 and various system components including the system memory 422 to the digital processor 406. The system memory 422 may store a set of modules 424.

[0108] The digital processor 406 can be any logical processing unit or circuit (e.g., an integrated circuit), such as one or more central processing units (“CPUs”), graphics processing units (“GPUs”), digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”), field programmable gate arrays (“FPGAs”), programmable logic controllers (“PLCs”), etc., and / or combinations thereof.

[0109] In some implementations, the computing system 400 includes an analog computer 404 that can include one or more quantum processors 426. The quantum processor 426 can include flux-sensitive superconducting devices and can be at least one superconducting integrated circuit manufactured using the systems and methods described in this application that advantageously trap flux during cooling. The quantum processor 426 can include at least one integrated circuit manufactured using methods as described in more detail herein. The digital computer 402 can communicate with the analog computer 404, for example, via a controller 418. As described in more detail herein, certain computations can be performed by the analog computer 404 under the instructions of the digital computer 402.

[0110] The digital computer 402 may include a user input / output subsystem 408. In some implementations, the user input / output subsystem includes one or more user input / output components (e.g., display 410, mouse 412, and / or keyboard 414).

[0111] The system bus 420 may use any known bus structure or architecture including a memory bus having a memory controller, a peripheral bus, and a local bus. The system memory 422 may include non-volatile memory (e.g., read-only memory (“ROM”), static random access memory (“SRAM”), flash NAND) and volatile memory (e.g., random access memory (“RAM”)) (not shown).

[0112] Furthermore, the digital computer 402 may include other persistent computers or processor-readable storage media or non-volatile memory 416. The non-volatile memory 416 may take various forms including a hard disk drive that reads and writes to a hard disk (e.g., magnetic disk), an optical disk drive that reads and writes to a removable optical disk, and / or a solid state drive (SSD) that reads and writes to solid state media (e.g., NAND-based flash memory). The non-volatile memory 416 may communicate with the digital processor via the system bus 420 and may include a suitable interface or controller 418 coupled to the system bus 420. The non-volatile memory 416 may function as a long-term storage device for processor or computer-readable instructions, data structures, or other data (which may also be referred to as program modules) for the digital computer 402.

[0113] Although digital computer 402 is described as using a hard disk, optical disk, and / or solid state storage media, one of ordinary skill in the art will appreciate that other types of persistent and nonvolatile computer-readable media may be used. One of ordinary skill in the art will appreciate that some computer architectures use persistent volatile memory and persistent nonvolatile memory. For example, data in volatile memory may be cached in nonvolatile memory. Or, a solid state disk provides nonvolatile memory using integrated circuits.

[0114] A variety of processors or computer-readable instructions, data structures, or other data may be stored in system memory 422. For example, system memory 422 may store instructions that communicate with remote clients and schedule the use of resources including resources on digital computer 402 and analog computer 404. Further, for example, system memory 422 may store at least one of processor-executable instructions or data that cause at least one processor to execute various algorithms that execute instructions when executed by at least one processor. In some implementations, system memory 422 may store processor or computer-readable computational instructions and / or data that perform preprocessing, co-processing, and postprocessing on analog computer 404. System memory 422 may store a set of analog computer interface instructions that interact with analog computer 404.

[0115] Analog computer 404 may include at least one analog processor (e.g., quantum processor 426). Analog computer 404 may be provided in an isolated environment (e.g., an isolated environment that shields the internal components of the quantum computer from heat, magnetic fields, and other external noise). The isolated environment may include a refrigerator (e.g., a dilution refrigerator) operable to cryogenically cool the analog processor to a temperature of, for example, less than about 1K.

[0116] The analog computer 404 may include programmable elements (e.g., qubits, couplers, and other devices). Qubits can be read out via a readout system 428. The readout results can be sent to other computers or processor-readable instructions of the digital computer 402. Qubits can be controlled via a qubit control system 430. The qubit control system 430 may include an on-chip DAC and analog lines operable to bias the target device. A coupler that couples qubits can be controlled via a coupler control system 432. The coupler control system 432 may include tuning elements (e.g., on-chip DAC and analog lines). The qubit control system 430 and the coupler control system 432 can be used to implement a quantum annealing schedule as described herein on the analog computer 404. The programmable elements can be included in a quantum processor 426 in the form of an integrated circuit. Qubits and couplers can be positioned in a layer of the integrated circuit that includes a first material. Other devices (e.g., a readout control system 432) can be positioned in another layer of the integrated circuit that includes a second material.

[0117] FIG. 5 is a flowchart illustrating a method 500 of manufacturing a portion of a superconducting integrated circuit that includes reducing magnetic flux traps according to the present system and method. In other implementations, certain operations may be omitted, additional operations may be added, and / or operations may be performed in a different order, but method 500 includes operations 502-506. Method 500 may be performed, for example, by an integrated circuit manufacturing apparatus in response to the start of a manufacturing process.

[0118] In operation 502, a first metal layer is formed within the superconducting integrated circuit using a first superconducting material having a first critical temperature T C1 A first device is formed within the first metal layer. The first device can be a flux-sensitive superconducting device (e.g., a qubit or a coupler).

[0119] The second metal layer may be formed adjacent to the first metal layer, and the second metal layer has a shielding structure that shields the first device in the first metal layer and at least partially controls the flux trapping behavior of the first metal layer. The second metal layer can be formed from the same material as the first metal layer or a different material having a third critical temperature T C3 and.

[0120] In operation 504, the flux directing layer is formed using a superconducting material having a second critical temperature T C2 and. The material of the flux directing layer can be selected to provide a preferred flux trapping behavior during cooling.

[0121] In operation 506, a flux trap opening can be formed at the flux trap position. In some implementations, the flux trap opening can be a parallel tube opening or a groove having a shielding wall. The flux directing layer is positioned in flux transfer communication with the opening position, and the opening position is located away from the first device at a position where the trapped flux can be separated from the first device. As used herein, it is understood that the flux directing layer and the flux trap position may not be in contact and may not be directly adjacent to each other, but flux transfer communication means sufficient physical proximity and arrangement to transfer flux from the flux directing layer to the flux trap position. The opening position can be formed inside a part of the flux directing layer or in an individual component of the superconducting integrated circuit. A flux trap structure (e.g., one or more ports) that overlaps at least a part of the opening position can be formed in the flux directing layer.

[0122] When performing 502 and 504 described above, from a first temperature (T1>T C1 , T C2 ) that exceeds both the first critical temperature and the second critical temperature, to a second temperature (T2<T C1 , T C2) When cooling a superconducting integrated circuit (e.g., by a cryogenic refrigerator), the relative temperature difference between the first critical temperature and the second critical temperature is such that when the flux directing layer directs the flux away from the first device and cools the superconducting integrated circuit, the first superconducting material and the second superconducting material are selected to trap the flux at the flux trap position.

[0123] When providing a shielding layer, a relative temperature difference between the second critical temperature and the third critical temperature is given to the second superconducting material to direct the flux away from the first device, and thus the flux directing layer can direct the flux to the flux trap position.

[0124] As described above, depending on the structure of the superconducting integrated circuit, it may be beneficial for the first metal layer to cool first through the critical temperature of the first metal layer, or for the flux directing layer to cool first through the critical temperature of the flux directing layer.

[0125] When the flux directing layer is part of the integrated circuit structure, it may be beneficial for the flux directing layer to have the lowest critical temperature within the superconducting integrated circuit so that it is the last to transition during cooling. The first metal layer may overlap on part of the flux directing layer, or the flux directing layer may overlap on the first metal layer.

[0126] When the flux directing layer is provided as an individual shielding structure on the first metal layer, it may be beneficial for the flux directing layer to have the highest critical temperature within the superconducting integrated circuit so that it is the first to transition during cooling.

[0127] In some implementations, it may be beneficial to have a layer that does not include a flux-sensitive device transition first, serve as the flux directing layer, and direct the flux to a safety aperture that includes the flux. Thereby, the layer that includes the flux-sensitive device can transition in an environment without flux.

[0128] Forming a superconducting integrated circuit may further include providing one or more additional superconducting metal layers that overlap on or under the flux biasing layer. In some implementations, the superconducting metal layers may have a critical temperature value that decreases from the upper layer to the lower layer, and the flux biasing layer may be the lower layer and may be adjacent to the substrate.

[0129] A shield may be formed to seal the flux trap location, and the shield may be formed by a plurality of superconducting stud vias deposited within the superconducting integrated circuit. The flux trap location may be an aperture that can be generated by forming a box-shaped or parallel tubular cavity or groove within the superconducting integrated circuit at the aperture location. The aperture location may be selected to be a location that includes a second device (e.g., a DAC, a magnetometer) or other device that is less flux sensitive.

[0130] In the example of the implementation of FIG. 6, the superconducting integrated circuit 600 has one or more flux-sensitive superconducting devices 602 and a flux biasing layer 604. As described above, a non-superconducting site 606 (referred to herein as a port) that functions as a preferred location for trapping flux may be provided in the superconducting integrated circuit, particularly in the flux biasing layer 604. As described above, the port may be placed near a device that is not flux sensitive (e.g., a digital-to-analog converter (DAC) and / or a magnetometer), or at a site (e.g., site 608 in FIG. 6) that is sufficiently far from any flux-sensitive element such that any coupling to the flux trapped in the port 606 does not affect the operation of the flux-sensitive device 602. It is understood that any number of ports 606 may be included in the circuit to ensure sufficient flux away from the flux-sensitive device 602.

[0131] In some embodiments, in order to prevent the operation of the flux-sensitive device from being adversely affected by coupling to trapped flux, the port needs to be placed sufficiently far from the flux-sensitive device, so the addition of ports in the superconducting material can reduce the circuit density of the components. The flux trapped in the high kinetic inductance material can have a smaller coupling to the surrounding structure and thus can be placed closer to the flux-sensitive device without adversely affecting the flux-sensitive device. As described above, a high kinetic inductance material can be defined as a material that stores at least 10% of the energy as kinetic inductance or a material with a kinetic inductance ratio of 0.1 < α ≤ 1. The fluxoid quantization condition is given by the following equation. (L k +L g )I s -Φ a =nΦ0

[0132] Here, L k is the kinetic inductance of the port material, L g is the geometric inductance of the port material, I s is the screening current, Φ a is the external magnetic flux (which may be applied to the flux-sensitive device), n is an integer, and Φ0 is the magnetic flux quantum. For the same values of n, Φ a and L g , a port formed of a higher kinetic inductance material has a smaller screening current. This smaller screening current can result in a smaller magnetic flux coupling to the surrounding structure.

[0133] A high kinetic inductance material as described above can have a critical temperature higher than that of the superconducting material (e.g., Nb or Al) used for superconducting devices in the superconducting integrated circuit 600. In some embodiments, the flux-orienting layer 604 is formed of a high kinetic inductance material, and the T of the flux-orienting layer is before all of the other layers of the superconducting integrated circuit 600. CAfter passing through, direct the magnetic flux to the port (or ports) 606 to trap the ambient magnetic flux at a site 608 that is sufficiently far from the flux-sensitive device 602 so as not to affect the operation of the flux-sensitive device 602.

[0134] FIGS. 7A, 7B, and 7C are partial cross-sectional views of superconducting integrated circuits 700a, 700b, 700c, respectively, where like numbers indicate like components. The superconducting integrated circuits 700a, 700b, and 700c have first and second flux-sensitive devices 702 positioned in different layers. As shown, the flux-sensitive device 702 is a three-layer Josephson junction that can form part of the wiring for qubits or couplers. It is understood that any flux-sensitive device may be included. Superconducting integrated circuit 700a has a flux-directing layer 704 in the form of a ground plane, while circuit 700b has a flux-directing layer 704 in the form of a shielding layer within the stack, and circuit 700c has a flux-directing layer 704 in the form of a sky shield. In any case, the flux-directing layer 704 has ports 706 at flux trap locations 708. It is understood that more than one port 706 can be provided and the ports can be placed at various locations within the superconducting integrated circuit to control the flux trap throughout the circuit. The preferred movement of the magnetic flux through the circuit during cooling of superconducting integrated circuit 700a is T C Select the material of the flux-directing layer 704 such that the flux-directing layer 704 has it. In some implementations, select the flux-directing layer 704 to be a material having a low T C so that the flux-directing layer 704 transitions last during cooling and thereby controls the movement of the magnetic flux expelled from the other layers. In other implementations, select the flux-directing layer 704 to have an intermediate T CThe magnetic flux biasing layer 704 can be selected to be a material having []. In other implementations, the magnetic flux biasing layer 704 transfers before any other layer of the circuit and moves the magnetic flux away from the magnetic flux sensitive device 702 to the magnetic flux trapping location 708 before the magnetic flux sensitive device 702 goes into the superconducting state, so that a high T C The magnetic flux biasing layer 704 can be selected to be a material having [].

[0135] The T of the magnetic flux biasing layer 704 can be selected through material selection or the processing applied to the material. C In some implementations, the material can be selected based on the material motion inductance. Often, materials having a higher T C also have a higher motion inductance. Materials with a higher motion inductance can have a smaller magnetic flux coupling to the surrounding structure of any magnetic flux contained in the mote in the higher motion inductance material. Thereby, the circuit density can be increased and there is no need to place the mote away from the magnetic flux sensitive device.

[0136] FIG. 8 is a top view of a typical superconducting circuit 800 having one or more flux-sensitive superconducting devices 802a, 802b (collectively 802) and a flux-directing layer 804. As shown, the flux-sensitive superconducting devices 802 include qubits 802a and couplers 802b. These flux-sensitive superconducting devices are merely typical structures, and it is understood that the structure of the flux-sensitive superconducting devices 802 can vary. The superconducting circuit 800 has a port 806 disposed away from the flux-sensitive superconducting device 802 in the form of an elongated groove. As described above, the port can take other forms (e.g., a spiral that increases the surface area). An opening 808 is shown in dashed lines for clarity. The flux-directing layer 804 can have an opening that houses the flux-sensitive device 802, but it is understood that the flux-directing layer 804 can be continuous above or below the flux-sensitive device 802. Most of the superconducting material can improve the control of the flux trap and help ensure that the flux is directed to the port 806, so it is beneficial to have a flux-directing layer 804 that is continuous or substantially continuous across the superconducting circuit 800 except at the location of the port 806.

[0137] The methods, processes, or techniques described above can be implemented by a series of processor-readable instructions stored on one or more persistent processor-readable media. Some examples of the methods of the methods, processes, or techniques described above are implemented in part by a dedicated device (e.g., an adiabatic quantum computer or a quantum annealing device (e.g., a computer including at least one digital processor) that programs or otherwise controls the operation of an adiabatic quantum computer or a quantum annealing device or system). Those skilled in the art will appreciate that in alternative embodiments, certain operations can be omitted and / or additional operations can be added, but the methods, processes, or techniques described above can include various operations. Those skilled in the art will appreciate that the order of the example operations is shown for illustrative purposes only and can vary in alternative embodiments. Some of the illustrative actions or operations of the methods, processes, or techniques described above are repeatedly executed. Some of the operations of the methods, processes, or techniques described above can be executed during each iteration, after multiple iterations, or at the end of all iterations.

[0138] The foregoing description of illustrative implementations, including the content set forth in the abstract, is not intended to be exhaustive or to limit the implementations to the exact form disclosed. Specific implementations and examples are described herein for illustrative purposes, but as will be apparent to one of ordinary skill in the art, various equivalent modifications may be made without departing from the spirit and scope of the present disclosure. The teachings provided herein for the various implementations may be applied to other methods of quantum computing (not necessarily limited to the exemplary methods for quantum computing generally described above).

[0139] Combinations of the various implementations described above may provide further implementations. All U.S. Patent Application Publications, U.S. Patent Applications, foreign patents, and foreign patent applications by the same applicant as referenced herein and / or listed on the application data sheet, including but not limited to U.S. Patent No. 8,441,330, U.S. Patent No. 8,247,799, U.S. Patent No. 7,687,938, U.S. Provisional Patent Application No. 62 / 760,253, U.S. Provisional Patent Application No. 62 / 944,143, and U.S. Non-Provisional Patent Application No. 16 / 481,788, are hereby incorporated by reference in their entirety.

[0140] Based on the foregoing description, these and other modifications to the implementations may be made. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific implementations disclosed herein, but rather the claims should be construed to include all possible implementations together with the full scope of equivalents given in such claims. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A superconducting integrated circuit, comprising: A first device including at least a part of a first metal layer within the superconducting integrated circuit, wherein the first metal layer includes a first superconducting material having a first critical temperature; A flux trap position spaced apart from the first device, the flux trap position being one or more flux trap openings having one opening or a series of aligned and continuous openings that open into and extend through each superconducting layer of the superconducting integrated circuit, the flux trap position being positioned such that the flux trapped within the flux trap position is separated from the first device; A flux directing layer including a superconducting material having a second critical temperature, the flux directing layer being positioned in communication with the flux trap position such that the flux directing layer includes an opening aligned with the one or more flux trap openings; Comprising; The first critical temperature and the second critical temperature have a relative temperature difference such that when the superconducting integrated circuit is cooled to a temperature below both the first critical temperature and the second critical temperature, flux leaves the first device, is directed to the flux directing layer, and the flux directing layer directs and traps the flux within the flux trap position. Superconducting integrated circuit.

2. The superconducting integrated circuit according to claim 1, wherein the flux trap opening includes one of a parallel tube opening and a groove positioned within the superconducting integrated circuit.

3. Further comprising a shield including a superconducting material, the shield sealing the flux trap position to separate the flux trap position from the first device such that the flux trapped within the flux trap position is separated from the first device. Superconducting integrated circuit according to claim 1.

4. The superconducting integrated circuit according to claim 1, wherein the first device includes one of a qubit and a coupler.

5. Further comprising a second metal layer positioned adjacent to the first metal layer, the second metal layer including a shielding structure for shielding the first device, the second metal layer including a superconducting material having a third critical temperature. Superconducting integrated circuit according to claim 1.

6. The first metal layer overlaps at least a part of the magnetic flux directing layer and further includes a second metal layer positioned adjacent to the first metal layer, the second metal layer including a shielding structure for shielding the first device, the second metal layer including a superconducting material having a third critical temperature, the superconducting integrated circuit according to claim 1.

7. The first critical temperature is higher than the second critical temperature, the second critical temperature is lower than the third critical temperature, and the relative temperature difference between the second critical temperature and the third critical temperature is selected to be away from the first device and to direct magnetic flux to the magnetic flux trapping position, the superconducting integrated circuit according to claim 6.

8. Further including one or more additional metal layers overlapping at least a part of the magnetic flux directing layer, the critical temperature of each additional metal layer being higher than the second critical temperature, the superconducting integrated circuit according to claim 6 or 7.

9. The magnetic flux directing layer overlaps at least a part of the first metal layer, and the first critical temperature is lower than the second critical temperature, the superconducting integrated circuit according to claim 1.

10. A second metal layer, wherein the first metal layer overlaps at least a part of the second metal layer, the second metal layer including a shielding structure for shielding the first device, the second metal layer including a superconducting material having a third critical temperature, further including forming a second metal layer, and forming a base metal layer, the second metal layer overlapping on the base metal layer, the third critical temperature being higher than the critical temperature of the base metal layer, and the critical temperature of the base metal layer being higher than the second critical temperature, the superconducting integrated circuit according to claim 9.

11. The magnetic flux directing layer includes a magnetic flux trapping structure overlapping at least a part of the magnetic flux trapping position, the superconducting integrated circuit according to claim 9 or 10.

12. The magnetic flux trapping position includes a second device, the superconducting integrated circuit according to claim 1.

13. The magnetic flux directing layer includes a high kinetic inductance material and at least one moat, the superconducting integrated circuit according to claim 1.

14. A method for reducing magnetic flux trapping in a superconducting integrated circuit, forming a first device, the first device including at least a portion of a first metal layer within the superconducting integrated circuit, the first metal layer including a first superconducting material having a first critical temperature; forming a magnetic flux directing layer including a second superconducting material having a second critical temperature; forming a magnetic flux trap position spaced apart from the first device, the magnetic flux trap position being one or more magnetic flux trap openings having one opening or a series of aligned and continuous openings that open into and extend through each superconducting layer of the superconducting integrated circuit; comprising; forming the magnetic flux directing layer includes forming an opening aligned with the one or more magnetic flux trap openings; the first superconducting material and the second superconducting material are selected such that when the superconducting integrated circuit is cooled from a first temperature above both the first critical temperature and the second critical temperature to a second temperature below both the first critical temperature and the second critical temperature, a relative temperature difference between the first critical temperature and the second critical temperature causes magnetic flux to be directed away from the first device and towards the magnetic flux trap position spaced apart from the first device in the magnetic flux directing layer, and as the superconducting integrated circuit is cooled, the magnetic flux is trapped at the magnetic flux trap position and separated from the first device;

15. forming the magnetic flux directing layer includes forming the magnetic flux directing layer to be positioned in magnetic flux transfer communication with the magnetic flux trap position, and causing magnetic flux to be directed away from the first device and towards the magnetic flux trap position in the magnetic flux directing layer includes causing magnetic flux to be directed towards the magnetic flux trap position in the magnetic flux directing layer, the method according to claim 14.

16. further comprising forming a second metal layer adjacent to the first metal layer, the second metal layer including a shielding structure that shields the first device, the second metal layer including a superconducting material having a third critical temperature, the method according to claim 14.

17. Forming the first device includes forming the first metal layer to overlap at least a portion of the magnetic flux directing layer. Forming a flux guiding layer that includes a second superconducting material includes selecting the second critical temperature to be below the first critical temperature, selecting the second critical temperature to be below the third critical temperature, providing a relative temperature difference between the second critical temperature and the third critical temperature to direct flux away from the first device, and trapping flux at the flux trap location, the method of claim 16.

18. Further comprising forming one or more additional superconducting metal layers overlapping at least a portion of the flux guiding layer, wherein the critical temperature of each of the one or more additional superconducting metal layers exceeds the second critical temperature, and selecting the respective critical temperature of each layer such that the critical temperature increases gradually layer by layer from the flux guiding layer to the topmost layer of the first metal layer and the one or more additional superconducting metal layers, the method of claim 17.

19. Forming the flux guiding layer that includes a second superconducting material includes forming a flux guiding layer overlapping at least a portion of the first metal layer, and selecting the second critical temperature to exceed the first critical temperature, the method of claim 14 or 15.

20. Forming a second metal layer, wherein the first metal layer overlaps at least a portion of the second metal layer, the second metal layer includes a shielding structure that shields the first device, the second metal layer further includes a superconducting material having a third critical temperature, and forming a base metal layer, wherein the second metal layer overlaps the base metal layer, the third critical temperature exceeds the critical temperature of the base metal layer, and the critical temperature of the base metal layer exceeds the second critical temperature, the method of claim 19.

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