Semiconductor device

Abstract

To provide a semiconductor device with excellent reliability.SOLUTION: A semiconductor device includes a transistor including, first to fifth insulators, first to third oxides, first to third conductors. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. There are cases where display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. can be said to have semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0004] As a semiconductor thin film applicable to a transistor, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials. As oxide semiconductors, for example, not only oxides of single-element metals such as indium oxide and zinc oxide, but also oxides of multi-element metals are known. Among the oxides of multi-element metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

[0005] Research on IGZO has found a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure in oxide semiconductors that are neither single crystals nor amorphous (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 also disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

[0006] Furthermore, a transistor using IGZO as an active layer has an extremely low off-current (see Non-Patent Document 6), and LSIs and displays utilizing such characteristics have been reported (see Non-Patent Documents 7 and 8).

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

[0008] One aspect of the present invention is to provide a semiconductor device with a large on-current as one of the problems. Another aspect of the present invention is to provide a semiconductor device having high frequency characteristics as one of the problems. Another aspect of the present invention is to provide a semiconductor device with good reliability as one of the problems. Another aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. Another aspect of the present invention is to provide a semiconductor device having good electrical characteristics as one of the problems. Another aspect of the present invention is to provide a highly productive semiconductor device as one of the problems.

[0009] One aspect of the present invention aims to provide a semiconductor device capable of retaining data for a long period. One aspect of the present invention aims to provide a semiconductor device with a high writing speed of information. One aspect of the present invention aims to provide a semiconductor device with a high degree of design freedom. One aspect of the present invention aims to provide a semiconductor device capable of suppressing power consumption. One aspect of the present invention aims to provide a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device having a transistor. The transistor includes a first insulator, a second insulator on the first insulator, a first oxide on the second insulator, a second oxide on the first oxide, a third oxide on the second oxide, a first conductor and a second conductor on the second oxide, a third insulator on the third oxide, a third conductor on the third insulator, a fourth insulator on the first conductor and the second conductor, and a fifth insulator on the fourth insulator. The fourth insulator and the fifth insulator are provided with an opening reaching the second oxide. The third oxide is disposed so as to cover the inner wall of the opening. The third insulator is disposed so as to cover the inner wall of the opening via the third oxide. The third conductor is disposed so as to fill the opening via the third oxide and the third insulator. In the channel length direction of the transistor, at least a part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap is in contact with the first insulator. In the channel width direction of the transistor, with reference to the height of the bottom surface of the first insulator, the height of the bottom surface of the third conductor in a region where the third conductor and the second oxide do not overlap is lower than the height of the bottom surface of the second oxide. In the channel width direction of the transistor, at least a part of the third oxide in a region where the third oxide and the second oxide do not overlap is in contact with the first insulator.

[0012] In the above semiconductor device, it is preferable that the third oxide has a stacked structure including a first layer and a second layer. The first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator. Further, it is preferable that the second layer has higher crystallinity than the first layer. Alternatively, both the first layer and the second layer have In, an element M (M is Al, Ga, Y, or Sn), and Zn, and in the second layer, the atomic ratio of In in the constituent elements is smaller than the atomic ratio of In in the constituent elements in the first layer, which is preferable.

[0013] Another aspect of the present invention is a semiconductor device having a transistor. The transistor includes a first insulator, a second insulator on the first insulator, a first oxide on the second insulator, a second oxide on the first oxide, a third oxide on the second oxide, a third insulator on the third oxide, a conductor on the third insulator, a fourth insulator in contact with at least a part of the third oxide, at least a part of the upper surface of the second oxide, at least a part of the side surface of the second oxide, at least a part of the side surface of the first oxide, at least a part of the side surface of the second insulator, and at least a part of the first insulator, a fifth insulator on the fourth insulator, a sixth insulator in contact with at least a part of the upper surface of the third oxide, at least a part of the upper surface of the third insulator, at least a part of the upper surface of the conductor, and at least a part of the upper surface of the fifth insulator. The second oxide has a first region, a second region, and a third region located between the first region and the second region. The resistance of the first region and the second region is lower than that of the third region. The conductor is provided above the third region so as to overlap with the third region. A part of the third oxide and a part of the third insulator are provided between the side surface of the conductor and the side surface of the fifth insulator. The fourth insulator has a region in contact with the first region and the second region. In the channel width direction of the transistor, with reference to the height of the bottom surface of the first insulator, the height of the bottom surface of the conductor in the region where the conductor and the second oxide do not overlap is lower than the height of the bottom surface of the second oxide. In the channel width direction of the transistor, at least a part of the third oxide in the region where the third oxide and the second oxide do not overlap is in contact with the first insulator.

[0014] In the semiconductor device, it is preferable that the first region and the second region contain one of phosphorus and boron.

[0015] Also, in the semiconductor device, it is preferable that the first region and the second region have more oxygen vacancies than the third region.

[0016] In the semiconductor device, it is preferable that the fourth insulator has a stacked structure including a third layer and a fourth layer, the third layer is in contact with the first insulator, and the fourth layer is in contact with the fifth insulator. Further, it is preferable that the third layer contains silicon oxide and the fourth layer contains aluminum oxide.

[0017] In the semiconductor device, it is preferable that the third oxide has a stacked structure including a first layer and a second layer, the first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator. Further, it is preferable that both the first layer and the second layer contain In, an element M (M is Al, Ga, Y, or Sn), and Zn, and in the second layer, the atomic ratio of In to the element M is smaller than the atomic ratio of In to the element M in the first layer.

Advantages of the Invention

[0018] According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Further, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Further, according to one aspect of the present invention, a highly productive semiconductor device can be provided.

[0019] Further, a semiconductor device capable of retaining data for a long period can be provided. Further, a semiconductor device with a high information writing speed can be provided. Further, a semiconductor device with a high degree of design freedom can be provided. Further, a semiconductor device capable of suppressing power consumption can be provided. Further, a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Thus, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally decrease in thickness due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same part or parts having similar functions among different drawings, and repeated descriptions thereof may be omitted. Also, when referring to similar functions, the hatching patterns may be the same and may not be particularly labeled.

[0024] Also, especially in top views (also referred to as "plan views") and perspective views, etc., for ease of understanding the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0025] Also, in this specification, etc., ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third", etc. for explanation. Also, the ordinal numbers described in this specification, etc. may not match the ordinal numbers used to specify an aspect of the present invention.

[0026] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components may change as appropriate according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification, and can be appropriately rephrased according to the situation.

[0027] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is assumed that the cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also assumed to be disclosed in the figure or the text.

[0028] Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0029] In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0030] Also, the functions of the source and the drain may be interchanged when transistors of different polarities are adopted or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms source and drain may be used interchangeably in some cases.

[0031] Note that the channel length refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0032] Note that the channel width refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the channel formation region in the vertical direction with respect to the channel length direction in the channel formation region. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0033] Note that in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may be different from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0035] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0036] Note that the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water may also function as an impurity. Also, in the case of an oxide semiconductor, for example, oxygen deficiency may be formed due to the incorporation of impurities. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen.

[0037] Note that in this specification and the like, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition. Also, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0038] In addition, in this specification and the like, the term "insulator" can be rephrased as an insulating film or an insulating layer. Also, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be rephrased as a semiconductor film or a semiconductor layer.

[0039] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, cases of -5 degrees or more and 5 degrees or less are also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases of 85 degrees or more and 95 degrees or less are also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] Note that in this specification, a barrier film is a film having a function of suppressing the permeation of impurities such as water, hydrogen, and oxygen, and when the barrier film has conductivity, it may be called a conductive barrier film.

[0041] In this specification and the like, metal oxide means an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be paraphrased as a transistor having an oxide or an oxide semiconductor.

[0042] In addition, in this specification and the like, normally-off means that when no potential is applied to the gate or when the gate is given a ground potential, the current per 1 μm of channel width flowing through the transistor is 1×10 -20 A or less at room temperature, 1×10 -18 A or less at 85 °C, or 1×10 at 125 °C-16 It means being less than A.

[0043] (Embodiment 1) Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

[0044] <Configuration Example 1 of Semiconductor Device> FIGS. 1(A) to 1(C) are top views and cross-sectional views of a transistor 200 according to one aspect of the present invention and the periphery of the transistor 200.

[0045] FIG. 1(A) is a top view of a semiconductor device having a transistor 200. FIGS. 1(B) and 1(C) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1(A), and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 1(A), some elements are omitted for clarity of the figure.

[0046] Also, FIG. 2 is a perspective view of a transistor 200 according to one aspect of the present invention. In the perspective view of FIG. 2, some elements are omitted for clarity of the figure.

[0047] A semiconductor device according to one aspect of the present invention includes a transistor 200, insulators 214, 280, 274, and 281 that function as interlayer films, and conductors 240 (conductor 240a and conductor 240b) that are electrically connected to the transistor 200 and function as plugs. Note that insulators 241 (insulator 241a and insulator 241b) are provided in contact with the side surfaces of the conductors 240 that function as plugs.

[0048] Further, an insulator 241 is provided in contact with the side walls of the openings of the insulator 254, insulator 280, insulator 274, and insulator 281. A first conductor of the conductor 240 is provided in contact with the side surface thereof, and a second conductor of the conductor 240 is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. In the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned in the order of formation for distinction.

[0049] [Transistor 200] As shown in FIG. 1, the transistor 200 includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, conductors 242a and 242b in contact with a part of the upper surface of the oxide 230b, and an insulator 254 disposed in contact with a part of the upper surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, the upper surface of the conductor 242a, the side surface of the conductor 242b, and the upper surface of the conductor 242b.

[0050] The conductor 260 functions as the gate electrode of the transistor 200, and the conductors 242a and 242b function as a source electrode or a drain electrode, respectively. In the transistor 200, the conductor 260 functioning as the gate electrode is self-alignedly formed so as to fill an opening formed in an insulator 280 or the like. By forming the conductor 260 in this manner, it is possible to surely arrange the conductor 260 in the region between the conductors 242a and 242b without alignment.

[0051] Note that the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. Further, as shown in FIG. 1(B), the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Note that, in the transistor 200, the conductor 260 is shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0052] The insulators 222, 254, and 274 preferably have a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule) and a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule). For example, it is preferable that the insulators 222, 254, and 274 each have lower permeability of one or both of hydrogen and oxygen than the insulator 224. It is preferable that the insulators 222, 254, and 274 each have lower permeability of one or both of hydrogen and oxygen than the insulator 250. It is preferable that the insulators 222, 254, and 274 each have lower permeability of one or both of hydrogen and oxygen than the insulator 280.

[0053] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least partially in contact with the upper surface of the oxide 230b.

[0054] Note that in the transistor 200, the structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided.

[0055] Further, in the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0056] The transistor 200 using an oxide semiconductor in the channel formation region has an extremely small leakage current (off-current) in the non-conducting state, so that a low-power semiconductor device can be provided. In addition, since the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device.

[0057] For example, as the oxide 230, a metal oxide such as an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Further, an In-Ga oxide, an In-Zn oxide, or a Ga-Zn oxide may be used as the oxide 230.

[0058] In addition, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may deteriorate. Further, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the insulator 250 or the like to compensate for the oxygen deficiencies. Thereby, fluctuations in electrical characteristics can be suppressed, a transistor having stable electrical characteristics and improved reliability can be provided.

[0059] Further, when an element contained in the conductor 242 (conductor 242a and conductor 242b) provided so as to be in contact with the oxide 230 and functioning as a source electrode or a drain electrode has a function of absorbing oxygen of the oxide 230, a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, in the low-resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen deficiencies may function as donors, and the carrier density may increase. In the following, hydrogen that has entered the oxygen deficiencies may be referred to as VH. o H.

[0060] In addition, an enlarged view of a partial region of the transistor 200 shown in FIG. 1(B) is shown in FIG. 3(A). As shown in FIG. 3(A), a conductor 242 is provided so as to be in contact with the oxide 230, and regions 243 (region 243a and region 243b) may be formed as low-resistance regions at the interface between the oxide 230 and the conductor 242 and in the vicinity thereof. The oxide 230 includes at least a part of a region 234 that functions as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) that functions as a source region or a drain region. In the following drawings, even when the region 243 is not shown in an enlarged view or the like, a similar region 243 may be formed.

[0061] Note that, although regions 243a and 243b are shown as being provided so as to diffuse in the depth direction in the vicinity of the conductor 242 of the oxide 230b, the present invention is not limited to this. Regions 243a and 243b may be formed as appropriate according to the required electrical characteristics of the transistor. Also, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentration of the element detected within each region is not limited to a stepwise change for each region, and may also change continuously (also referred to as gradation) within each region.

[0062] Also, as shown in FIG. 1(B), the insulator 254 preferably contacts the upper surfaces of the conductors 242a and 242b, the side surfaces of the conductors 242a and 242b other than the side surfaces facing each other, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and a part of the upper surface of the insulator 222. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, it is possible to suppress impurities such as hydrogen contained in the insulator 280 and the like from being mixed into the insulator 224, the oxide 230a, and the oxide 230b.

[0063] The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 3(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact. By adopting such a structure, it is possible to suppress impurities such as hydrogen contained in the insulator 281 and the like from being mixed into the insulator 250. Therefore, it is possible to suppress an adverse effect on the electrical characteristics of the transistor and the reliability of the transistor.

[0064] Also, as shown in FIG. 3(A), with respect to the bottom surface of the insulator 224, the height of the bottom surface of the conductor 260 in the region overlapping the region 234 may be lower than the heights of the upper surfaces of the conductors 242a and 242b, respectively. For example, the difference between the height of the bottom surface of the conductor 260 in the region overlapping the region 234 and the heights of the upper surfaces of the conductors 242a and 242b, respectively, is set to be 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0065] Also, an enlarged view of a partial region of the transistor 200 shown in FIG. 1(C) is shown in FIG. 3(B). As shown in FIGS. 1(C) and 3(B), in the channel width direction of the transistor 200, with respect to the bottom surface of the insulator 222, it is preferable that the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the bottom surface of the oxide 230b. By adopting a configuration in which the conductor 260 functioning as a gate electrode covers the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, it becomes easier for the electric field of the conductor 260 to act on the entire region 234 of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. If the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxides 230a and 230b and the conductor 260 do not overlap is defined as T2, then T2 is set to be 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0066] Also, as shown in FIG. 3(B), in the channel width direction of the transistor 200, at least a part of the oxide 230c in the region that does not overlap with the oxide 230b, the oxide 230a, and the insulator 224 preferably contacts the insulator 222. With this configuration, it is possible to prevent oxygen contained in the oxide 230c from diffusing outside the transistor 200 via the insulator 224. Or, it is possible to prevent oxygen contained in the oxide 230b and the oxide 230a from diffusing outside the transistor 200 via the insulator 224. Or, by reducing the area of the insulator 224, the amount of oxygen taken into the insulator 224 can be reduced, and a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b and the oxide 230a, and a decrease in the low resistance of the oxide 230 in the region 234 can be suppressed. Accordingly, fluctuations in the electrical characteristics of the transistor can be suppressed, stable electrical characteristics can be realized, and reliability can be improved.

[0067] Or, with the above configuration, it is possible to suppress impurities such as hydrogen contained in the insulator 224 and the like from mixing into the oxide 230. That is, a decrease in the low resistance of the oxide 230 can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, stable electrical characteristics can be realized, and reliability can be improved. Note that the configuration can be formed by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a.

[0068] Also, by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a, as shown in FIG. 1(C), in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the bottom surface height of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is likely to be lower than the bottom surface height of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0069] As described above, it is possible to provide a semiconductor device having a transistor with a large on-current. Further, it is possible to provide a semiconductor device having a transistor with high frequency characteristics. Further, it is possible to provide a semiconductor device in which fluctuations in electrical characteristics are suppressed, which has stable electrical characteristics and improved reliability. Further, it is possible to provide a semiconductor device having a transistor with a small off-current.

[0070] Hereinafter, a detailed configuration of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

[0071] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided by being embedded in the insulators 214 and 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Thereby, the flatness of the insulator 224 formed on the conductor 205 can be improved, and the crystallinity of the oxides 230a, 230b, and 230c can be improved.

[0072] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate electrode. In that case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when no potential is applied.

[0073] Note that, as shown in Fig. 1(A), the conductor 205 may be provided to be larger than the channel formation region in the oxide 230. In particular, as shown in Fig. 1(C), it is preferable that the conductor 205 extends also in a region outside the end portion intersecting the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator outside the side surface in the channel width direction of the oxide 230.

[0074] By having the above configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0075] Also, as shown in Fig. 1(C), the conductor 205 is extended to function also as a wiring. However, it is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 205. Also, it is not always necessary to provide one conductor 205 for each transistor. For example, a configuration may be adopted in which the conductor 205 is shared by a plurality of transistors.

[0076] Also, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205. Although the conductor 205 is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium, titanium nitride, and the above conductive material.

[0077] Further, a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (it is difficult for the above impurities to permeate) may be used under the conductor 205. Alternatively, it is preferable to use a conductor having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is difficult for the above oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0078] By using a conductor having a function of suppressing the diffusion of oxygen under the conductor 205, it is possible to suppress the oxidation of the conductor 205 and the decrease in conductivity. As the conductor having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, as the conductor used under the conductor 205, the above conductive material may be a single layer or a laminate.

[0079] The insulator 214 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, it is preferable to use an insulating material for the insulator 214 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (it is difficult for the above impurities to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is difficult for the above oxygen to permeate).

[0080] For example, it is preferable to use aluminum oxide, silicon nitride, etc. as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side rather than the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc. to the substrate side rather than the insulator 214.

[0081] Also, the insulators 216, 280, and 281 that function as interlayer films preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 280, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having pores, etc. may be appropriately used.

[0082] Also, the insulator 216 may have a laminated structure. For example, in the insulator 216, a structure may be adopted in which an insulator similar to the insulator 214 is provided at least in a portion in contact with the side surface of the conductor 205. By adopting such a structure, oxidation of the conductor 205 by the oxygen contained in the insulator 216 can be suppressed. Or, absorption of the oxygen contained in the insulator 216 by the conductor 205 can be suppressed.

[0083] The insulators 222 and 224 have a function as a gate insulator.

[0084] Here, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. In this specification, oxygen desorbed by heating may be referred to as excess oxygen. For example, as the insulator 224, silicon oxide, silicon oxynitride, etc. may be appropriately used. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0085] Specifically, as the insulator 224, it is preferable to use an oxide material in which a part of the oxygen desorbs by heating. An oxide film that desorbs oxygen by heating means that, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19atoms / cm 3 Above, more preferably 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 It is an oxide film that is above. In addition, as the surface temperature of the film during the above TDS analysis, a range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower is preferable.

[0086] The insulator 222 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, etc. with the insulator 222 and the insulator 254, the diffusion of impurities such as water and hydrogen from the outside to the insulator 224 and the oxide 230 can be suppressed.

[0087] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, the oxygen possessed by the oxide 230 can be reduced from diffusing to the substrate side, which is preferable. Also, the conductor 205 can be suppressed from reacting with the oxygen possessed by the insulator 224 and the oxide 230.

[0088] The insulator 222 may preferably be made of an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials. As the insulator containing one or both of oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Among the above-mentioned materials, it is particularly preferable to use hafnium oxide as the insulator 222. For example, when the insulator 222 is used as a gate insulating film, using hafnium oxide for the insulator 222 may reduce the interface state density compared to aluminum oxide.

[0089] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulator and used.

[0090] In addition, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0091] Also, as shown in FIG. 1(C), in the insulator 222, the film thickness of the region that does not overlap with the oxide 230b may be thinner than the film thickness of other regions. In the insulator 222, the film thickness of the region that does not overlap with the oxide 230b is preferably a film thickness that can function as an etching stopper film when forming an opening provided in the insulator 280 or the like, or a film thickness sufficient to prevent the surface of the insulator 216 or the conductor 205 from being exposed.

[0092] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. For example, a structure may be adopted in which an insulator similar to the insulator 224 is provided under the insulator 222.

[0093] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed. Also, by having the oxide 230c on the oxide 230b, diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0094] Note that the oxide 230 preferably has a laminated structure of oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. Additionally, the oxide 230c can use a metal oxide that can be used for the oxide 230a or the oxide 230b.

[0095] Also, the oxides 230b and 230c preferably have crystallinity. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later. Oxides with crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen deficiencies) and high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0096] Further, it is preferable that the lower end of the conduction band of the oxide 230a and the oxide 230c is closer to the vacuum level than the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. In this case, it is preferable that the metal oxide used for the oxide 230c can be used for the oxide 230a. Specifically, in the metal oxide used for the oxide 230c, it is preferable that the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230c, it is preferable that the atomic ratio of the element M to In is larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, it is preferable that the atomic ratio of In to the element M is larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.

[0097] Further, when the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, it is preferable that the lower end of the conduction band of the oxide 230a and the oxide 230c2 is closer to the vacuum level than the lower end of the conduction band of the oxide 230b and the oxide 230c1. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c2 is smaller than the electron affinity of the oxide 230b and the oxide 230c1. In this case, it is preferable that the metal oxide that can be used for the oxide 230a is used for the oxide 230c2, and the metal oxide that can be used for the oxide 230b is used for the oxide 230c1.

[0098] Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the lower end of the conduction band changes gently. In other words, it can also be said that the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c changes continuously or is continuously joined. To achieve this, it is advisable to lower the density of defect levels in the mixed layer formed at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c.

[0099] Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element other than oxygen (as a main component), so that a mixed layer with a low defect level density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide. When the oxide 230c is made to have a stacked structure of the oxide 230c1 and the oxide 230c2, for example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 230c.

[0100] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or an atomic ratio of In:Ga:Zn=1:1:0.5. The oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or an atomic ratio of In:Ga:Zn=3:1:2. The oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0101] At this time, the main path of the carrier becomes the oxide 230b. Alternatively, when the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, not only the oxide 230b but also the oxide 230c1 may become the main path of the carrier. By configuring the oxide 230a and the oxide 230c as described above, the density of defect levels at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a high on-current and high frequency characteristics. When the oxide 230c has a stacked structure, in addition to the effect of reducing the density of defect levels at the interface between the oxide 230b and the oxide 230c described above, it is expected to suppress the diffusion of the constituent elements of the oxide 230c to the insulator 250 side. More specifically, since the oxide 230c has a stacked structure and an oxide not containing In is positioned above the stacked structure, the diffusion of In to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250 or the like, the characteristics of the transistor deteriorate. Therefore, by configuring the oxide 230c as a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0102] As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. For example, as the metal oxide that becomes the region 234, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a large band gap in this way, the off-current of the transistor can be reduced. By using such a transistor, a low-power consumption semiconductor device can be provided.

[0103] On the oxide 230b, conductors 242 (conductor 242a and conductor 242b) that function as a source electrode and a drain electrode are provided. The film thickness of the conductor 242 may be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0104] As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0105] Similar to the insulator 214, etc., the insulator 254 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side to the transistor 200. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Further, as shown in FIGS. 1(B) and 1(C), the insulator 254 preferably contacts the upper surface and side surface of the conductor 242a, the upper surface and side surface of the conductor 242b, the side surfaces of the oxides 230a and 230b, and the side surface of the insulator 224. With such a configuration, the insulator 280 is separated from the insulator 224 and the oxides 230 by the insulator 254. Thereby, it is possible to suppress the diffusion of hydrogen contained in the insulator 280 from the upper surface or side surface of the conductor 242a, the conductor 242b, the oxides 230a, the oxides 230b, and the insulator 224 to the oxide 230, so that good electrical characteristics and reliability can be imparted to the transistor 200.

[0106] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). For example, the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224.

[0107] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added in the vicinity of the region where the insulator 254 is in contact with the insulator 224. Thereby, oxygen can be supplied from the said area | region into the oxide 230 through the insulator 224. Here, since the insulator 254 has a function of suppressing the upward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the oxide 230 to the insulator 280. Further, since the insulator 222 has a function of suppressing the downward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the oxide 230. Thereby, the oxygen deficiency of the oxide 230 can be reduced, and the normal ionization of the transistor can be suppressed.

[0108] As the insulator 254, for example, an insulator containing one or both oxides of aluminum and hafnium may be formed. In addition, as the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. In this case, the insulator 254 is preferably formed by an atomic layer deposition (ALD) method. Since the ALD method is a film formation method with good coverage, it is possible to prevent steps and the like from being formed due to the unevenness of the insulator 254.

[0109] In this way, by covering the insulator 224 and the oxide 230 with the insulator 254 having a barrier property against hydrogen, the insulator 280 is separated from the insulator 224 and the oxide 230. As a result, impurities such as hydrogen can be prevented from entering from the outside of the transistor 200, so that good electrical characteristics and reliability can be imparted to the transistor 200.

[0110] Further, as the insulator 254, for example, an insulator containing aluminum nitride may be used. As the insulator 254, it is preferable to use a nitride insulator satisfying the compositional formula AlNx (x is a real number greater than 0 and less than or equal to 2, preferably x is a real number greater than 0.5 and less than or equal to 1.5). Thereby, a film excellent in insulation property and heat conductivity can be obtained, so that the heat dissipation property of the heat generated when the transistor 200 is driven can be enhanced. Also, as the insulator 254, aluminum titanium nitride, titanium nitride, etc. can also be used. In this case, by forming a film using a sputtering method, a film can be formed without using a strongly oxidizing gas such as oxygen or ozone in the film-forming gas, which is preferable. Also, silicon nitride or silicon oxynitride, etc. can also be used.

[0111] Further, the insulator 254 can have a multilayer structure of two or more layers. For example, as the insulator 254, the first layer may be formed using a sputtering method in an oxygen-containing atmosphere, and then the second layer may be formed using an ALD method to form a two-layer structure. Since the ALD method is a film-forming method with good coverage, it is possible to prevent steps or the like from being formed due to the unevenness of the first layer. When the insulator 254 has a multilayer structure of two or more layers, it may have a multilayer structure made of different materials. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. Also, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or both of oxides of aluminum and hafnium can be used.

[0112] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with at least a part of the oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0113] Similar to the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing, as the insulator 250, an insulator that releases oxygen upon heating in contact with at least a part of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0114] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Also, oxidation of the conductor 260 by the oxygen in the insulator 250 can be suppressed.

[0115] Note that the above metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide, silicon oxynitride, etc. for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the above metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the above metal oxide, a laminated structure which is stable against heat and has a high relative permittivity can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator.

[0116] Further, the above metal oxide may function as part of the first gate. For example, an oxide semiconductor which can be used as the oxide 230 can be used as the above metal oxide. In that case, by forming the conductor 260 by sputtering, the electric resistance value of the above metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0117] By having the above metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by maintaining the distance between the conductor 260 and the oxide 230 by the physical thickness of the insulator 250 and the above metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Further, by providing a laminated structure of the insulator 250 and the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted as appropriate.

[0118] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, such as aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). Further, by reducing the resistance of the oxide semiconductor that can be used for the oxide 230, it can be used as the above metal oxide.

[0119] Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may be a single-layer structure or a laminated structure of three or more layers.

[0120] For the conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0121] Further, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0122] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, for the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

[0123] The insulator 280 is provided on the insulator 222, the insulator 224, the oxide 230, and the conductor 242 via the insulator 254. For example, as the insulator 280, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs upon heating.

[0124] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Also, the upper surface of the insulator 280 may be planarized.

[0125] The insulator 274 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 280, similar to the insulator 214 and the like. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0126] Also, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281 preferably has a reduced concentration of impurities such as water and hydrogen in the film, similar to the insulator 224 and the like.

[0127] Also, the conductor 240a and the conductor 240b are disposed in the openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the upper surfaces of the conductor 240a and the conductor 240b may be on the same plane as the upper surface of the insulator 281.

[0128] In addition, an insulator 241a is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of a conductor 240a is formed in contact with its side surface. A conductor 242a is located at least in part at the bottom of the opening, and the conductor 240a is in contact with the conductor 242a. Similarly, an insulator 241b is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of a conductor 240b is formed in contact with its side surface. A conductor 242b is located at least in part at the bottom of the opening, and the conductor 240b is in contact with the conductor 242b.

[0129] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 240a and the conductor 240b. Also, the conductor 240a and the conductor 240b may have a laminated structure.

[0130] When the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b. Also, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the upper layer than the insulator 281 through the conductor 240a and the conductor 240b to the oxide 230.

[0131] As the insulators 241a and 241b, for example, insulators that can be used for the insulator 254 or the like may be used. Since the insulators 241a and 241b are provided in contact with the insulator 254, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 from diffusing into the oxide 230 through the conductors 240a and 240b. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b. Note that, for the formation of the insulators 241a and 241b, an ALD method or a chemical vapor deposition (CVD) method can be used.

[0132] Also, although not shown, conductors that function as wiring may be arranged in contact with the upper surfaces of the conductor 240a and the conductor 240b. As the conductor that functions as wiring, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. Further, the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0133] Also, although not shown, an insulator having a resistivity of 1.0×10 13 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more and 5.0×10 14 Ωcm or less is preferably provided so as to cover the above conductor. By providing an insulator having the above resistivity on the above conductor, the insulator can disperse charges accumulated in the transistor 200, wiring (for example, the above conductor), etc., while maintaining insulation, and can suppress characteristic deterioration and electrostatic breakdown of the transistor due to the charges and the electronic device having the transistor, which is preferable.

[0134] <Constituent Materials of Semiconductor Device> Hereinafter, constituent materials that can be used for a semiconductor device will be described.

[0135] <<Substrate>> As the substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those in which elements are provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0136] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc. having insulating properties.

[0137] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low relative permittivity for the insulator functioning as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0138] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0139] In addition, examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0140] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator (such as insulator 214, insulator 222, insulator 254, and insulator 274) having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0141] In addition, the insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0142] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0143] In addition, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen may be used. Further, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0144] In the case of using an oxide in the channel formation region of a transistor, it is preferable to use a stacked structure in which a conductor functioning as a gate electrode combines a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more likely to be supplied to the channel formation region.

[0145] In particular, as the conductor functioning as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which a channel is formed. Or it may be possible to capture hydrogen mixed from an external insulator or the like.

[0146] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide that functions as a semiconductor. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0147] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, it may contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like.

[0148] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Elements applicable to other element Ms include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. However, in some cases, a plurality of the aforementioned elements may be combined as element M.

[0149] In this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0150] [Structure of Metal Oxide] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0151] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. Note that the strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

[0152] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, it is difficult to confirm a clear grain boundary (also called a grain boundary) even in the vicinity of the strain. That is, it can be seen that the formation of the grain boundary is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0153] Also, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0154] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to the grain boundary is unlikely to occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS is free of impurities and defects (oxygen vacancies (V O: Also referred to as oxygen vacancy. It can be said to be a metal oxide with few (such as...) Therefore, the metal oxide having CAAC-OS has stable physical properties. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0155] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0156] Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may take a stable structure by using the above-mentioned nanocrystals. In particular, since IGZO tends to be difficult to grow crystals in the air, a crystal smaller than a large crystal (here, a crystal of several mm or a crystal of several cm), for example, the above-mentioned nanocrystal, may be structurally more stable.

[0157] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0158] The oxide semiconductor (metal oxide) has various structures and each has different characteristics. The oxide semiconductor according to one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0159] [Impurities] Here, the influence of each impurity in the metal oxide will be described.

[0160] When a metal oxide contains an alkali metal or an alkaline earth metal, it may form defect levels and generate carriers. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by secondary ion mass spectrometry (SIMS) (the concentration obtained by SIMS) is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0161] In addition, hydrogen contained in the metal oxide may react with oxygen bonded to metal atoms to form water, thereby forming oxygen deficiencies. When hydrogen enters the oxygen deficiencies, electrons as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics.

[0162] For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, still more preferably 1×10 18 atoms / cm 3 less than. By using a metal oxide with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0163] As the metal oxide used for the semiconductor of the transistor, it is preferable to use a highly crystalline thin film. By using such a thin film, the stability or reliability of the transistor can be improved. Examples of such a thin film include a single-crystalline metal oxide thin film or a polycrystalline metal oxide thin film. However, to form a single-crystalline metal oxide thin film or a polycrystalline metal oxide thin film on a substrate, a high-temperature or laser heating process is required. Therefore, the cost of the manufacturing process increases, and furthermore, the throughput also decreases.

[0164] In 2009, it was reported in Non-Patent Document 1 and Non-Patent Document 2 that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered. Here, it was reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at a low temperature. Furthermore, it was reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

[0165] Also, in 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it was reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is seen in the crystal orientation between different such regions.

[0166] In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation for each of the above-mentioned CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO thin films is shown. In the low-crystallinity IGZO thin film, crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it has been reported here that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, compared with the low-crystallinity IGZO thin film, the CAAC-IGZO thin film and the nc-IGZO thin film have been shown to be highly stable against electron beam irradiation. Therefore, it is preferable to use the CAAC-IGZO thin film or the nc-IGZO thin film as the semiconductor of the transistor.

[0167] Transistors using metal oxides have extremely low leakage current in the non-conducting state. Specifically, it is shown in Non-Patent Document 6 that the off-current per 1 μm channel width of the transistor is on the order of yA / μm (10 -24 A / μm). For example, a low-power consumption CPU etc. that applies the characteristic of low leakage current of a transistor using a metal oxide is disclosed (see Non-Patent Document 7).

[0168] In addition, an application of the transistor using a metal oxide to a display device by utilizing the characteristic of low leakage current has been reported (see Non-Patent Document 8). In a display device, the displayed image is switched several tens of times per second. The number of times the image is switched per second is called the refresh rate. Also, the refresh rate may be called the driving frequency. Such a high-speed screen switching that is difficult for the human eye to perceive is considered to be a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device and reduce the number of times the image is rewritten. Also, by driving with a reduced refresh rate, it is possible to reduce the power consumption of the display device. Such a driving method is called idling stop (IDS) driving.

[0169] The discovery of the CAAC structure and the nc structure has contributed to the improvement of the electrical characteristics and reliability of transistors using metal oxides having the CAAC structure or the nc structure, as well as the reduction of the cost of the manufacturing process and the improvement of throughput. In addition, application research of the transistor to display devices and LSIs has been advanced by utilizing the characteristic that the leakage current of the transistor is low.

[0170] <Method for manufacturing a semiconductor device> Next, a manufacturing method of a semiconductor device having a transistor 200 according to an aspect of the present invention shown in FIG. 1 will be described with reference to FIGS. 4 to 11. In FIGS. 4 to 11, (A) of each figure shows a top view. Further, (B) of each figure is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) of each figure is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of (A) of each figure, some elements are omitted for clarity of the figure.

[0171] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed by using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0172] Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Further, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on the raw material gas used.

[0173] The plasma CVD method can obtain high-quality films at relatively low temperatures. Also, the thermal CVD method does not use plasma, so it is a film-forming method that can reduce plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in semiconductor devices may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of semiconductor devices can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0174] Also, the ALD method utilizes the self-limiting property of atoms and can deposit atoms one by one, so it enables extremely thin film formation, film formation on structures with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, and other effects. Also, the ALD method includes the PEALD (Plasma Enhanced ALD) method that uses plasma. Utilizing plasma may make it possible to form films at lower temperatures in some cases. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, the films formed by the ALD method may contain more impurities such as carbon compared to the films formed by other film-forming methods. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0175] Unlike film deposition methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film deposition methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and is a film deposition method having good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film deposition rate, it may be preferably used in combination with other film deposition methods such as the CVD method having a high film deposition rate.

[0176] The composition of the obtained film can be controlled by the flow rate ratio of the source gases in the CVD method and the ALD method. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film having a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened because it does not require the time required for transfer or pressure adjustment as compared with the case of forming a film using a plurality of film formation chambers. Therefore, the productivity of the semiconductor device may be improved.

[0177] In the present embodiment, aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multilayer structure. For example, it may be structured such that aluminum oxide is formed by a sputtering method and aluminum oxide is formed on the aluminum oxide by an ALD method. Alternatively, it may be structured such that aluminum oxide is formed by an ALD method and aluminum oxide is formed on the aluminum oxide by a sputtering method.

[0178] Next, a conductive film that becomes the conductor 205 is formed on the insulator 214. The formation of the conductive film that becomes the conductor 205 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Also, the conductive film that becomes the conductor 205 can be a multilayer film. In the present embodiment, tungsten is formed as the conductive film that becomes the conductor 205.

[0179] Next, the conductive film that becomes the conductor 205 is processed using a lithography method to form the conductor 205.

[0180] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed may be used. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0181] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material. The etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the etching of the conductive film that will become the conductor 205. On the other hand, when the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0182] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency power sources to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources having the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources having different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0183] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the upper surface and the side surface of the conductor 205. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed by CVD as the insulating film that will become the insulator 216.

[0184] Here, the film thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the film thickness of the conductor 205. For example, if the film thickness of the conductor 205 is set to 1, the film thickness of the insulating film that becomes the insulator 216 is set to be 1 or more and 3 or less. In the present embodiment, the film thickness of the conductor 205 is 150 nm, and the film thickness of the insulating film that becomes the insulator 216 is 350 nm.

[0185] Next, by performing CMP (Chemical Mechanical Polishing) treatment on the insulating film that becomes the insulator 216, a part of the insulating film that becomes the insulator 216 is removed, and the surface of the conductor 205 is exposed. As a result, it is possible to form the conductor 205 with a flat upper surface and the insulator 216 in contact with the side surface of the conductor 205 (see FIG. 4). By improving the flatness of the upper surfaces of the insulator 216 and the conductor 205, the crystallinity of the CAAC-OS in which the oxides 230b and 230c are formed can be improved.

[0186] From here, a method for forming the conductor 205 different from the above will be described below.

[0187] An insulator 216 is formed on the insulator 214. The formation of the insulator 216 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0188] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, grooves and slits. In some cases, the region where the opening is formed may be referred to as an opening portion. The opening may be formed using wet etching, but dry etching is more preferable for microfabrication. In addition, it is preferable to select the insulator 214 as an insulating film that functions as an etching stopper film when forming a groove by etching the insulator 216. For example, when a silicon oxide film is used for the insulator 216 for forming the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0189] After the formation of the opening, a conductive film that will become the conductor 205 is formed. It is desirable that the conductive film contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc. The formation of the conductive film that will become the conductor 205 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc.

[0190] In this embodiment, the conductive film that will become the conductor 205 has a multilayer structure. First, tantalum nitride is formed by a sputtering method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride for the lower layer of the conductive film that will become the conductor 205, even if a metal such as copper that is easy to diffuse is used as the conductive film for the upper layer of the conductive film that will become the conductor 205 described later, it is possible to prevent the metal from diffusing out of the conductor 205.

[0191] Next, a conductive film for the upper layer of the conductive film that will become the conductor 205 is formed. The formation of the conductive film can be performed using a plating method, sputtering method, CVD method, MBE method, PLD method, ALD method, etc. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film for the upper layer of the conductive film that will become the conductor 205.

[0192] Next, by performing CMP processing, a part of the upper layer of the conductive film that will become the conductor 205 and a part of the lower layer of the conductive film that will become the conductor 205 are removed, and the insulator 216 is exposed. As a result, the conductive film that will become the conductor 205 remains only in the opening. Thereby, the conductor 205 with a flat upper surface can be formed. Note that a part of the insulator 216 may be removed by the CMP processing. The above are different formation methods of the conductor 205.

[0193] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, it is preferable to form an insulator containing one or both of oxides of aluminum and hafnium. Note that, as the insulator containing one or both of oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. The insulator containing one or both of oxides of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing inside the transistor 200 through the insulator 222, and generation of oxygen vacancies in the oxide 230 can be suppressed.

[0194] The formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0195] Next, an insulating film 224A which becomes the insulator 224 is formed on the insulator 222. The formation of the insulating film 224A can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0196] Subsequently, it is preferable to perform a heat treatment. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Also, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen.

[0197] In this embodiment, as the heat treatment, after the formation of the insulating film 224A, a treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By this heat treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. Further, the heat treatment can also be performed at a timing such as after the formation of the insulator 222.

[0198] Here, in order to form an excess oxygen region in the insulating film 224A, a plasma treatment containing oxygen may be performed in a reduced pressure state. For the plasma treatment containing oxygen, it is preferable to use, for example, a device having a power source for generating high-density plasma using microwaves. Alternatively, it may have a power source for applying RF (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulating film 224A. Alternatively, after performing a plasma treatment containing an inert gas using this device, a plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed.

[0199] Here, on the insulating film 224A, for example, after forming aluminum oxide by sputtering, CMP treatment may be performed until reaching the insulating film 224A. By performing the CMP treatment, planarization and smoothing of the surface of the insulating film 224A can be performed. By disposing the aluminum oxide on the insulating film 224A and performing the CMP treatment, it becomes easy to detect the end point of the CMP treatment. Also, although a part of the insulating film 224A may be polished by the CMP treatment and the film thickness of the insulating film 224A may become thinner, the film thickness may be adjusted at the time of forming the insulating film 224A. By performing planarization and smoothing of the surface of the insulating film 224A, it may be possible to prevent deterioration of the coverage rate of the oxide to be formed later and prevent a decrease in the yield of the semiconductor device. Further, it is preferable to form aluminum oxide by sputtering on the insulating film 224A because oxygen can be added to the insulating film 224A.

[0200] Next, an oxide film 230A that becomes the oxide 230a and an oxide film 230B that becomes the oxide 230b are sequentially formed on the insulating film 224A (see FIG. 4). Note that it is preferable to form these oxide films continuously without exposing them to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and it is possible to keep the vicinity of the interface between the oxide film 230A and the oxide film 230B clean.

[0201] The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0202] For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. When the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used. In addition, a DC power source or an AC power source such as an RF power source is connected to the target, and necessary power can be applied according to the electrical conductivity of the target.

[0203] In particular, when forming the oxide film 230A, a part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

[0204] Also, when forming the oxide film 230B by sputtering, if the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor is formed. A transistor using an oxygen-deficient type oxide semiconductor in the channel formation region can obtain a relatively high field-effect mobility. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved. However, one aspect of the present invention is not limited to this. When forming the oxide film that becomes the oxide 230b by sputtering, if the proportion of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excessive type oxide semiconductor is formed. A transistor using an oxygen-excessive type oxide semiconductor in the channel formation region can obtain relatively high reliability.

[0205] In this embodiment, the oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target with In:Ga:Zn = 1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or In:Ga:Zn = 1:3:4 [atomic ratio]. Further, the oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target with In:Ga:Zn = 4:2:4.1 [atomic ratio]. Note that each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio.

[0206] Here, it is preferable to form the insulator 222, the insulating film 224A, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere. For example, a multi-chamber type film forming apparatus may be used.

[0207] Next, heat treatment may be performed. The heat treatment conditions described above can be used. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour in an oxygen atmosphere is continuously performed.

[0208] Next, a conductive film 242A is formed on the oxide film 230B. The formation of the conductive film 242A can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see Fig. 4).

[0209] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into an island shape to form the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see Fig. 5).

[0210] Here, the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are formed so that at least a part thereof overlaps with the conductor 205. Also, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are preferably substantially perpendicular to the upper surface of the insulator 222. When a plurality of transistors 200 are provided, miniaturization and high density are possible because the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B are substantially perpendicular to the upper surface of the insulator 222. Alternatively, the configuration may be such that the angle formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B and the upper surface of the insulator 222 is a low angle. In that case, the angle formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the covering property of the insulator 254 and the like is improved in the subsequent process, and defects such as looseness can be reduced.

[0211] Also, a curved surface is provided between the side surface of the conductive layer 242B and the upper surface of the conductive layer 242B. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter, also referred to as a round shape). The curved surface has, for example, a curvature radius of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductive layer 242B. By having no corner at the end, the covering property of the film in the subsequent film formation process is improved.

[0212] Note that the processing of the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A may be performed using a lithography method. Further, dry etching or wet etching may be used for the processing. Processing by the dry etching method is suitable for microfabrication. Also, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A may be processed under different conditions respectively.

[0213] Next, an insulating film 254A is formed on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIG. 6).

[0214] It is preferable to use an insulating film having a function of suppressing oxygen permeation for the insulating film 254A. For example, it is preferable to form an aluminum oxide film by a sputtering method. By forming an aluminum oxide film using a gas containing oxygen by a sputtering method, oxygen can be injected into the insulator 224. That is, the insulator 224 can have excess oxygen.

[0215] Next, an insulating film that becomes the insulator 280 is formed on the insulating film 254A. The insulating film that becomes the insulator 280 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, CMP processing is performed on the insulating film that becomes the insulator 280 to form the insulator 280 having a flat upper surface (see FIG. 6).

[0216] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are processed to form an opening reaching the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By the opening, the conductor 242a, the conductor 242b, and the insulator 254 are formed (see FIG. 7).

[0217] Also, the processing of a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B may be processed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulating film 254A may be processed by a wet etching method, and a part of the conductive layer 242B may be processed by a dry etching method.

[0218] By performing processes such as dry etching up to now, impurities caused by etching gas or the like may adhere to or diffuse into the surface or inside of the oxide 230a, the oxide 230b, or the like. Examples of the impurities include fluorine, chlorine, and the like.

[0219] In order to remove the above impurities and the like, cleaning is performed. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

[0220] As the wet cleaning, a cleaning process may be performed using an aqueous solution in which oxalic acid, phosphoric acid, hydrofluoric acid, or the like is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

[0221] Next, heat treatment may be performed. The heat treatment is performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere. By performing such a process, moisture and hydrogen adsorbed on the surface of the oxide 230b or the like can be removed, and furthermore, the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is set to 200°C (see FIG. 8).

[0222] The formation of the oxide film 230C can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. According to the characteristics required for the oxide film 230C, an oxide film that becomes the oxide film 230C may be formed using the same film formation method as the oxide film 230A or the oxide film 230B. In the present embodiment, the oxide film 230C is formed by a sputtering method using an In-Ga-Zn oxide target with In:Ga:Zn = 1:3:4 [atomic ratio] or In:Ga:Zn = 4:2:4.1 [atomic ratio].

[0223] In particular, when forming the oxide film 230C, a part of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

[0224] Next, heat treatment may be performed. The heat treatment is carried out under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C, etc. can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or more and 400°C or less (see Fig. 9).

[0225] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. As the insulating film 250A, it is preferable to form silicon oxynitride by a CVD method. Note that the film formation temperature when forming the insulating film 250A is preferably 350°C or more and less than 450°C, particularly around 400°C. By forming the insulating film 250A at 400°C, an insulating film with few impurities can be formed.

[0226] Next, the conductive film 260A and the conductive film 260B are formed. The formation of the conductive film 260A and the conductive film 260B can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In the present embodiment, the conductive film 260A is formed using the ALD method, and the conductive film 260B is formed using the CVD method (see FIG. 10).

[0227] Next, by performing CMP processing, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 11). As a result, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the opening reaching the oxide 230b. Further, the insulator 250 is disposed so as to cover the inner wall of the opening via the oxide 230c. Further, the conductor 260 is disposed so as to fill the opening via the oxide 230c and the insulator 250.

[0228] Next, a heat treatment may be performed. In the present embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.

[0229] Next, an insulator 274 may be formed on the oxide 230c, insulator 250, conductor 260, and insulator 280. The film formation of the insulator 274 can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. As the insulator 274, for example, it is preferable to form an aluminum oxide film by a sputtering method. By forming an aluminum oxide film by a sputtering method, it may be possible to suppress the diffusion of hydrogen contained in the insulator 281 into the oxide 230. Also, by forming the insulator 274 so as to be in contact with the conductor 260, oxidation of the conductor 260 can be suppressed, which is preferable. Further, by forming the insulator 274, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 may be supplied to the region 234 of the oxide 230b via the oxide 230c. Also, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 274 may be supplied to the region 234 of the oxide 230b via the oxide 230c.

[0230] Next, a heat treatment may be performed. The heat treatment conditions described above can be used. By this heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced. Also, oxygen contained in the insulator 274 can be injected into the insulator 280.

[0231] Note that, as a method of forming the insulator 274 on the insulator 280, first, an insulating film made of the same material as the insulator 274 is formed by the same film formation method as the insulator 274, then a heat treatment is performed using the heat treatment conditions described above, then the insulating film is removed by a CMP process, then the insulator 274 is formed, and then a heat treatment is performed using the heat conditions described above. By this method, more excessive oxygen regions can be formed in the insulator 280. Note that, in the step of removing the insulating film, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.

[0232] Also, an insulator may be provided between the insulator 280 and the insulator 274. As the insulator, for example, silicon oxide formed by a sputtering method may be used. By providing the insulator, an excess oxygen region can be formed in the insulator 280.

[0233] Next, an insulating film to be the insulator 281 may be formed on the insulator 274. The formation of the insulating film to be the insulator 281 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see FIG. 11).

[0234] Next, openings reaching the conductor 242a and the conductor 242b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281. The formation of the openings may be performed using a lithography method.

[0235] Next, an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, it is preferable to use an insulating film having a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by the ALD method. Further, a silicon nitride film may be formed using the ALD method or the CVD method. When forming a silicon nitride film using the ALD method, a precursor containing silicon and a halogen or a precursor of aminosilanes can be used. As the precursor containing silicon and a halogen, SiCl4, SiH2Cl2, Si2Cl6, Si3Cl8, etc. can be used. Further, as the precursor of aminosilanes, monovalent, divalent, or trivalent aminosilanes can be used. Further, ammonia or hydrazine can be used as the nitriding gas. Further, for the anisotropic etching, for example, a dry etching method or the like may be performed. By configuring the side wall portion of the opening in this way, oxygen permeation from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. Further, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0236] Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive film preferably has a laminated structure including a conductor having a function of suppressing diffusion of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0237] Next, by performing CMP processing, a part of the conductive film is removed to expose the insulator 281. As a result, the conductive film remains only in the above opening, and conductors 240a and 240b having a flat upper surface can be formed (see FIG. 1). Note that a part of the insulator 281 may be removed by the CMP processing.

[0238] As described above, a semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 4 to 11, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device according to the present embodiment.

[0239] According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Also, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Also, according to one aspect of the present invention, a highly productive semiconductor device can be provided.

[0240] <Configuration Example 2 of Semiconductor Device> FIG. 12 is a top view and a cross-sectional view of the transistor 200A according to one aspect of the present invention and the periphery of the transistor 200A. The transistor 200A is a modified example of the transistor 200.

[0241] FIG. 12(A) is a top view of a semiconductor device having the transistor 200A. FIGS. 12(B) and 12(C) are cross-sectional views of the semiconductor device. Here, FIG. 12(B) is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 12(A), and is also a cross-sectional view in the channel length direction of the transistor 200A. FIG. 12(C) is a cross-sectional view of the portion indicated by the one-dot chain line A3 - A4 in FIG. 12(A), and is also a cross-sectional view in the channel width direction of the transistor 200A. In the top view of FIG. 12(A), some elements are omitted for clarity of the drawing.

[0242] In the semiconductor device shown in FIG. 12, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device>.

[0243] Hereinafter, the configuration of the semiconductor device will be described with reference to FIG. 12. In this section, as the constituent materials of the semiconductor device, the materials described in detail in <Configuration Example 1 of Semiconductor Device> can be used.

[0244] [Transistor 200A] As shown in FIG. 12, the transistor 200A includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, conductors 260 (conductor 260a and conductor 260b) disposed on the insulator 250, conductors 242a and 242b in contact with a part of the upper surface of the oxide 230b, a barrier film 244a disposed on the conductor 242a, a barrier film 244b disposed on the conductor 242b, and insulators 254 (insulator 254a and insulator 254b) disposed in contact with a part of the upper surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 242a, the upper surface of the barrier film 244a, the side surface of the conductor 242b, and the upper surface of the barrier film 244b.

[0245] The insulator 254 is configured by laminating two layers of the insulator 254a and the insulator 254b, the oxide 230c is configured by laminating two layers of the oxide 230c1 and the oxide 230c2, and the fact that it has the barrier film 244a and the barrier film 244b is different from the aforementioned transistor 200. Hereinafter, the differences from the transistor 200 will be described.

[0246] As shown in FIG. 12, the insulator 254 includes an insulator 254a and an insulator 254b disposed on the insulator 254a. For example, the insulator 254a preferably functions as a barrier film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side into the transistor 200A. Also, for example, the insulator 254b preferably suppresses the diffusion of oxygen in the oxide 230 to the insulator 280 side. By adopting such a configuration in which two layers are laminated, it is possible to prevent hydrogen from being mixed into the channel formation region of the oxide 230. Furthermore, it is possible to prevent the release of oxygen from the channel formation region of the oxide 230. Specifically, silicon nitride formed by a sputtering method may be used as the insulator 254a, and aluminum oxide formed by an ALD method may be used as the insulator 254b.

[0247] Also, for example, as the insulator 254a, an insulating material having an excess oxygen region or an insulating material in which an excess oxygen region is likely to be formed may be used, and as the insulator 254b, an insulating material in which an excess oxygen region is likely to be formed in the film to be formed may be preferably used. Specifically, silicon oxide formed by a sputtering method may be used as the insulator 254a, and aluminum oxide formed by a sputtering method may be used as the insulator 254b. By adopting such a configuration in which two layers are laminated, the excess oxygen possessed by the insulator 254a can be efficiently supplied to the oxide 230.

[0248] In addition, when the insulator 254a has excess oxygen, it is preferable that a barrier film 244a is provided in contact with the upper surface of the conductor 242a and a barrier film 244b is provided in contact with the upper surface of the conductor 242b. The barrier film 244a and the barrier film 244b have a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Thereby, it is possible to prevent the excess oxygen in the oxide 230c and the insulator 250 from diffusing into the conductor 242a and the conductor 242b. That is, it is possible to prevent the surrounding excess oxygen from being used for the oxidation of the conductor 242a and the conductor 242b. Furthermore, it is possible to prevent the increase in the electrical resistance values of the conductor 242a and the conductor 242b due to the oxidation of the conductor 242a and the conductor 242b. The measurement of the electrical resistance value of the conductor can be performed using a two-terminal method or the like.

[0249] As the barrier film 244a and the barrier film 244b, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. may be used.

[0250] Also, a conductive material through which impurities hardly permeate may be used as the barrier film 244a and the barrier film 244b. When a conductive material is used for the barrier film 244a and the barrier film 244b, it is preferable to use a conductive material from which oxygen is hardly released or absorbed. Note that a configuration in which the barrier film 244a and the barrier film 244b are not provided may also be adopted.

[0251] Note that the insulator 254 is not limited to a configuration in which the insulator 254a and the insulator 254b are laminated, and it may be a single layer, or may be a configuration in which three layers of the insulator 254a, the insulator 254b, and the insulator 254c are laminated. When adopting a configuration of laminating three layers, for example, as the insulator 254a, an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen may be used, as the insulator 254b, an insulating material having an excess oxygen region may be used, and as the insulator 254c, an insulating material having a function of suppressing the diffusion of oxygen may be used. By adopting such a configuration of laminating three layers, it is possible to suppress the excess oxygen possessed by the insulator 254b from diffusing to the outside of the insulator 254a and the insulator 254c. Therefore, the excess oxygen possessed by the insulator 254b can be efficiently supplied to the oxide 230.

[0252] Note that when the insulator 254 is configured to be laminated in two or more layers, the combination and lamination order of the insulating materials used for the insulator 254 may be appropriately designed according to the required transistor characteristics.

[0253] Also, as shown in FIG. 12, the oxide 230c has an oxide 230c1 and an oxide 230c2 disposed on the oxide 230c1. The oxide 230c1 preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably contains all of the metal elements. Thereby, the density of defect energy levels at the interface between the oxide 230b and the oxide 230c1 can be lowered. Further, the oxide 230c2 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c1. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, it is possible to suppress the oxygen contained in the insulator 280 from diffusing into the insulator 250. Therefore, the oxygen is more likely to be supplied to the oxide 230 through the oxide 230c1.

[0254] Also, the oxide 230c1 and the oxide 230c2 preferably have crystallinity, and more preferably, the oxide 230c2 has higher crystallinity than the oxide 230c1. In particular, it is preferable to use CAAC-OS as the oxide 230c1 and the oxide 230c2, and it is preferable that the c-axis of the crystal possessed by the oxide 230c1 and the oxide 230c2 faces a direction substantially perpendicular to the formed surface or the upper surface of the oxide 230c1 and the oxide 230c2. CAAC-OS has the property of making it difficult to move oxygen in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, the oxygen possessed by the oxide 230c1 can be suppressed from diffusing into the insulator 250, and the oxygen can be efficiently supplied to the oxide 230.

[0255] Specifically, as the oxide 230c1, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] may be used, and as the oxide 230c2, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] may be used. In the metal oxide used for the oxide 230c2, by making the atomic ratio of In in the constituent elements smaller than the atomic ratio of In in the constituent elements of the metal oxide used for the oxide 230c1, it is possible to suppress the diffusion of In to the insulator 250 side. Since the insulator 250 functions as a gate insulator, when In is mixed into the insulator 250 or the like, the characteristics of the transistor deteriorate. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device.

[0256] Also, the insulator 280 may be configured to have a two-layer stacked structure. As shown in FIG. 12, when the insulator 280 has the insulator 280a and the insulator 280b disposed on the insulator 280a, the insulator 280a preferably has an excess oxygen region. Since the physical distance from the insulator 280a to the channel formation region of the oxide 230 is shorter than that of the insulator 280b, the oxygen contained in the insulator 280 can be efficiently supplied to the channel formation region of the oxide 230.

[0257] Specifically, as the insulator 280a, silicon oxide formed by a sputtering method may be used, and as the insulator 280b, silicon oxynitride formed by a CVD method may be used. The film thickness of the insulator 280a is preferably 30 nm or more and 100 nm or less, and more preferably 40 nm or more and 80 nm or less. Note that in the transistor 200A, a configuration in which the insulator 280 is laminated is shown, but the present invention is not limited to this. For example, the insulator 280 may be provided as a single layer or a laminated structure of three or more layers.

[0258] Also, as shown in FIG. 12, a configuration may be adopted in which an insulator 282 is provided between the insulator 274 and the insulator 281. As the insulator 282, an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen is preferably used. For example, it is preferable to form silicon nitride, aluminum oxide, or the like by a sputtering method or an ALD method. By providing the insulator 282, it is possible to suppress diffusion of oxygen in the insulator 280, the insulator 250, etc. to the insulator 281 side.

[0259] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0260] (Embodiment 2) Hereinafter, an example of a semiconductor device having a transistor 200B according to one aspect of the present invention will be described.

[0261] <Configuration Example 3 of Semiconductor Device> FIGS. 13(A) to 13(D) are top views and cross-sectional views of a transistor 200B according to one aspect of the present invention and the periphery of the transistor 200B. The transistor 200B is a modified example of the transistor 200.

[0262] In the semiconductor device shown in this embodiment, structures having the same functions as the structures constituting the semiconductor device shown in the previous embodiment are marked with the same reference numerals. Further, regarding the details of the configuration, materials, etc. of the semiconductor device shown in this embodiment, which are common to those of the semiconductor device shown in the previous embodiment, and the details of the structures, materials, etc. marked with the same reference numerals, the description of the previous embodiment can be referred to.

[0263] FIG. 13(A) is a top view of a semiconductor device having a transistor 200B. FIGS. 13(B) to 13(D) are cross-sectional views of the semiconductor device. Here, FIG. 13(B) is a cross-sectional view of the portion indicated by the dashed-dotted line A1 - A2 in FIG. 13(A), and is also a cross-sectional view in the channel length direction of the transistor 200B. FIG. 13(C) is a cross-sectional view of the portion indicated by the dashed-dotted line A3 - A4 in FIG. 13(A), and is also a cross-sectional view in the channel width direction of the transistor 200B. FIG. 13(D) is a cross-sectional view of the portion indicated by the dashed-dotted line A5 - A6 in FIG. 13(A), and is also a cross-sectional view in the vicinity of the region 243b that functions as a low-resistance region of the transistor 200B. Note that in the top view of FIG. 13(A), some elements are omitted for clarity of the drawing.

[0264] A semiconductor device according to an aspect of the present invention includes a transistor 200B, and insulators 214, 280, 274, and 281 that function as interlayer films. Further, it has conductors 240 (conductor 240a and conductor 240b) that are electrically connected to the transistor 200B and function as plugs. Insulators 241 (insulator 241a and insulator 241b) are provided in contact with the side surfaces of the conductors 240 that function as plugs.

[0265] Also, an insulator 241 is provided in contact with the side walls of the openings of the insulator 254 (insulator 254a and insulator 254b), insulator 280, insulator 274, and insulator 281. A first conductor of the conductor 240 is provided in contact with the side surface thereof, and a second conductor of the conductor 240 is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. Note that in the transistor 200B, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the formation order for distinction.

[0266] [Transistor 200B] As shown in FIG. 13, the transistor 200B includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, and an insulator 254 (insulator 254a and insulator 254b) disposed in contact with a part of the upper surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the upper surface of the oxide 230b.

[0267] Note that hereinafter, the oxide 230c1 and the oxide 230c2 may be collectively referred to as the oxide 230c.

[0268] As shown in FIG. 13, regions 243a and 243b are formed on the upper surface of the oxide 230b so as to be separated from each other. The insulator 280 is provided with an opening formed so as to overlap with a region between the regions 243a and 243b.

[0269] The conductor 260 functions as a gate electrode of the transistor, and the regions 243a and 243b function as a source region or a drain region, respectively. In the transistor 200B, the conductor 260 is self-alignedly formed so as to be embedded in an opening formed in the insulator 280 and the insulator 254, and in a region sandwiched between the regions 243a and 243b. By forming the conductor 260 in this manner, it is possible to surely arrange the conductor 260 between the region 243a and the region 243b without alignment. Therefore, the occupied area of the transistor 200B can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0270] Note that the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. Further, as shown in FIG. 13(B), the upper surface of the conductor 260 preferably substantially coincides with the upper surfaces of the insulator 250, the oxide 230c, and the insulator 280.

[0271] The oxide 230 preferably has an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c1 disposed on the oxide 230b and at least partially in contact with the upper surface of the oxide 230b, and an oxide 230c2 disposed on the oxide 230c1.

[0272] Note that, in the transistor 200B, a structure in which four layers of the oxide 230a, the oxide 230b, the oxide 230c1, and the oxide 230c2 are stacked in the channel formation region and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c1, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c2, or a stacked structure of five or more layers may be provided. Further, each of the oxide 230a and the oxide 230b may have a stacked structure of two or more layers. Further, the oxide 230c may have a single-layer structure or a stacked structure of three or more layers.

[0273] Further, for example, when the oxide 230c has a stacked structure composed of the oxide 230c1 and the oxide 230c2 on the oxide 230c1, it is preferable that the oxide 230c1 has the same composition as the oxide 230b and the oxide 230c2 has the same composition as the oxide 230a.

[0274] Further, in the transistor 200B, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c1, and the oxide 230c2) including the channel formation region.

[0275] In the transistor 200B using an oxide semiconductor in the channel formation region, since the leakage current (off-current) is extremely small in the non-conducting state, a semiconductor device with low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film using a sputtering method or the like, it can be used for the transistor 200B that constitutes a highly integrated semiconductor device.

[0276] For example, as the oxide 230, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. In particular, as element M, aluminum, gallium, yttrium, or tin may be used. Also, as the oxide 230, indium oxide, zinc oxide, In-Ga oxide, In-Zn oxide, Ga-Zn oxide, or gallium oxide may be used.

[0277] Here, when an element that forms an oxygen deficiency or an element that binds to the oxygen deficiency is added to the oxide 230, the carrier density may increase and the resistance may decrease. Representative examples of such elements include boron and phosphorus. In addition to boron and phosphorus, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. can also be used. Representative examples of noble gases include helium, neon, argon, krypton, xenon, etc. Also, the oxide 230 may be added with any one or more metal elements selected from metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum. Among the above, the elements to be added are preferably boron and phosphorus. For the addition of boron and phosphorus, the equipment of the manufacturing line of amorphous silicon or low-temperature polysilicon can be used, so that capital investment can be suppressed. The concentration of the above elements may be measured using SIMS or the like.

[0278] Further, an enlarged view of a partial region of the transistor 200B shown in FIG. 13(B) is shown in FIG. 14(A). Region 243 is a region formed by adding the above elements to the oxide 230. As shown in FIGS. 13(B) and 14(A), regions 243a and 243b are formed to face each other with the conductor 260 interposed therebetween, and it is preferable that their upper surfaces are in contact with the insulator 254. In a top view, the side surfaces of regions 243a and 243b on the side of the conductor 260 preferably coincide with the side surfaces of the conductor 260, or a part of regions 243a and 243b preferably overlaps with the conductor 260. Here, the concentration of the above elements in region 243 is preferably equal to or higher than the concentration of the above elements in the portion of the oxide 230 where region 243 is not formed. Also, the amount of oxygen deficiency contained in region 243 is preferably equal to or higher than the amount of oxygen deficiency in the portion of the oxide 230 where region 243 is not formed. Thereby, region 243 has a higher carrier density and a lower resistance compared to the portion of the oxide 230 where region 243 is not formed.

[0279] In the oxide 230, the region overlapping with the conductor 260 is defined as region 234, the region overlapping with the insulator 254 is defined as region 231 (regions 231a and 231b), and the region between region 234 and region 231 is defined as region 232 (regions 232a and 232b). As shown in FIG. 14(A), region 234 is located between regions 231a and 231b, region 232a is located between region 231a and region 234, and region 232b is located between region 231b and region 234. Here, region 231 is a region with a higher carrier density and lower resistance compared to region 234. Also, region 232 is a region with a higher carrier density and lower resistance compared to region 234, and a region with a lower carrier density and higher resistance compared to region 231. Alternatively, region 232 may have a carrier density equivalent to that of region 231 and an equivalent resistance. Therefore, region 234 functions as a channel formation region of the transistor 200B, region 231 functions as a source region or a drain region, and region 232 functions as a junction region.

[0280] By adopting such a configuration, it is possible to prevent the formation of an offset region between the channel formation region of the oxide 230 and the source region or the drain region, and suppress the effective channel length from becoming larger than the width of the conductor 260. As a result, the on-current of the transistor 200B can be increased, the S value (also referred to as Subthreshold Swing, SS) can be improved, and the frequency characteristics can be enhanced.

[0281] By forming the region 231 that functions as the source region or the drain region in the oxide 230, it is possible to connect the conductor 240 that functions as a plug to the region 231 without providing source and drain electrodes formed of metal. If source and drain electrodes formed of metal are provided in contact with the oxide 230, when a high-temperature heat treatment is performed in the manufacturing process or a subsequent process of the transistor 200B, the source and drain electrodes formed of metal may be oxidized, and the on-current, S value, and frequency characteristics of the transistor 200B may deteriorate. However, in the semiconductor device shown in this embodiment, it is not necessary to provide source and drain electrodes formed of metal. Therefore, even when a high-temperature heat treatment is performed in the manufacturing process or a subsequent process of the transistor 200B, a semiconductor device with good on-current, S value, and frequency characteristics can be provided. For example, in the semiconductor device shown in this embodiment, after manufacturing the transistor 200B, a process involving a high temperature of about 750°C or higher and 800°C or lower can be performed.

[0282] Also, as described above, by adding an element that forms an oxygen deficiency to the region 243 and performing a heat treatment, the hydrogen contained in the region 234 that functions as the channel formation region may be captured by the oxygen deficiency contained in the region 243. Thereby, stable electrical characteristics can be imparted to the transistor 200B, and the reliability can be improved.

[0283] Note that in FIG. 14(A), although the region 243 is formed near the interface between the oxide 230b and the insulator 254 in the film thickness direction of the oxide 230b, it is not limited thereto. For example, the region 243 may have a thickness approximately the same as the film thickness of the oxide 230b, or may be formed in the oxide 230a as well. Further, in FIG. 14(A), although the region 243 is formed only in the region 231, it is not limited thereto. For example, it may be formed in the region 231 and the region 232, or may be formed in the region 231 and a part of the region 232, or may be formed in the region 231, the region 232, and a part of the region 234.

[0284] In addition, in the oxide 230, it may be difficult to clearly detect the boundary of each region. The concentration of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected in each region is not limited to a stepwise change for each region, and may continuously change (also referred to as gradation) within each region. That is, the concentration of metal elements, as well as impurity elements such as hydrogen and nitrogen, may decrease in a region closer to the channel formation region.

[0285] Further, as shown in FIG. 13(B), it is preferable that the insulator 254 is disposed between the insulator 224, the oxide 230a, and the oxide 230b, and the insulator 280. Here, the insulator 254 preferably contacts the upper surface and the side surface of the region 243a, the upper surface and the side surface of the region 243b, the side surfaces of the oxide 230a and the oxide 230b, the side surface of the insulator 224, and the upper surface of the insulator 222. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, it is possible to suppress impurities such as hydrogen contained in the insulator 280, the insulator 281, etc. from mixing into the insulator 224, the oxide 230a, and the oxide 230b.

[0286] Further, the insulator 254 may have a laminated structure including an insulator 254a and an insulator 254b. At this time, the insulator 254a is preferably provided so as to be in contact with the upper surface and the side surface of the region 243a, the upper surface and the side surface of the region 243b, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and the upper surface of the insulator 222. Further, the insulator 254b is preferably provided on the insulator 254a so as to be in contact with the insulator 280. When the insulator 254 has the laminated structure as described above, one of the insulator 254a and the insulator 254b may have a function of suppressing the diffusion of hydrogen, and the other may have a function of suppressing the diffusion of oxygen.

[0287] Further, the insulator 254a may have a function of supplying oxygen to the insulator 224, the oxide 230a, and the oxide 230b.

[0288] The insulator 274 is in contact with the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280, respectively. Further, as shown in FIG. 14(A), in the transistor 200B which is one aspect of the present invention, the insulator 274 and the insulator 250 are in contact with each other. By adopting such a structure, it is possible to suppress impurities such as hydrogen contained in the insulator 281 and the like from being mixed into the insulator 250. Therefore, it is possible to suppress adverse effects on the electrical characteristics of the transistor and the reliability of the transistor.

[0289] Also, an enlarged view of a partial region of the transistor 200B shown in FIG. 13(C) is shown in FIG. 14(B). As shown in FIGS. 13(C) and 14(B), in the channel width direction of the transistor 200B, with respect to the bottom surface of the insulator 222, it is preferable that the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, it becomes easier for the electric field of the conductor 260 to act on the entire region 234 of the oxide 230b. Therefore, the on-current of the transistor 200B can be increased and the frequency characteristics can be improved. If the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is T2, then T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0290] Also, as shown in FIG. 14(B), in the channel width direction of the transistor 200B, at least a part of the oxide 230c in the region that does not overlap with the oxide 230b, the oxide 230a, and the insulator 224 preferably contacts the insulator 222. By adopting such a configuration, it is possible to prevent oxygen contained in the oxide 230c from diffusing to the outside of the transistor 200B via the insulator 224. Alternatively, it is possible to prevent oxygen contained in the oxide 230b and the oxide 230a from diffusing to the outside of the transistor 200B via the insulator 224. Alternatively, by reducing the area of the insulator 224, the amount of oxygen taken into the insulator 224 can be reduced, and a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b and the oxide 230a, and a decrease in the low resistance of the oxide 230 in the region 234 can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, stable electrical characteristics can be realized, and reliability can be improved.

[0291] Alternatively, by adopting the above configuration, it is possible to suppress impurities such as hydrogen contained in the insulator 224 from mixing into the oxide 230. That is, it is possible to suppress the reduction in the resistance of the oxide 230. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, stable electrical characteristics can be realized, and reliability can be improved. The said structure can be formed by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a.

[0292] Also, as shown in FIG. 14(B), it is preferable to remove the insulator 224 in the region that does not overlap with the oxide 230b and form it in an island shape similar to the oxide 230a and the oxide 230b. By adopting such a configuration, in the channel width direction of the transistor 200B, with the bottom surface of the insulator 222 as a reference, the height of the bottom surface of the conductor 260 in the region where the oxide 230a, the oxide 230b, and the conductor 260 do not overlap is more likely to be lower than the height of the bottom surface of the oxide 230b. Therefore, the on-current of the transistor 200B can be increased and the frequency characteristics can be improved.

[0293] From the above, it is possible to provide a semiconductor device having a transistor with a large on-current. It is also possible to provide a semiconductor device having a transistor with high frequency characteristics. It is also possible to provide a semiconductor device in which fluctuations in electrical characteristics are suppressed, having stable electrical characteristics and improved reliability. It is also possible to provide a semiconductor device having a transistor with a small off-current.

[0294] Hereinafter, the detailed configuration of the semiconductor device having the transistor 200B according to one aspect of the present invention will be described. Regarding the details of the configuration, materials, etc. of the semiconductor device shown in this embodiment that are common to the configuration, materials, etc. of the semiconductor device shown in the previous embodiment, and the details of the structure, materials, etc. denoted by the same reference numerals, the description of the previous embodiment can be referred to.

[0295] Oxide 230b and oxide 230c preferably have crystallinity. For example, it is preferable to use CAAC-OS. Oxides with crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and have a highly crystalline and dense structure. By having such an oxide 230, transistor 200B becomes stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0296] As shown in FIGS. 13(B) and 13(C), insulator 254 preferably contacts a part of the side surface of oxide 230c, the upper surface and side surface of region 243a, the upper surface and side surface of region 243b, that is, a part of the upper surface and a part of the side surface of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the upper surface of insulator 222. With such a configuration, insulator 280 is separated from insulator 224 and oxide 230 by insulator 254. Thereby, hydrogen contained in insulator 280 can be suppressed from diffusing into oxide 230 from the upper surface or side surface of oxide 230a, oxide 230b, and insulator 224, so that good electrical characteristics and reliability can be imparted to transistor 200B.

[0297] Also, as will be described later, insulator 254 may have a function as a protective film when forming regions 243a and 243b. When ion implantation or ion doping is used to form regions 243a and 243b, providing insulator 254 as a protective film can prevent the surface of oxide 230 from being directly exposed to ions or plasma, and can suppress damage to oxide 230 during the formation of regions 243a and 243b, which is preferable. Here, the damage to oxide 230 refers to the formation of excessive oxygen deficiencies in oxide 230, or excessive reduction in the crystallinity of oxide 230. For example, as insulator 254, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores can be used.

[0298] In this embodiment, the insulator 254 has a laminated structure. When the insulator 254 has a laminated structure of an insulator 254a and an insulator 254b, for example, the insulator 254a may be formed by sputtering in an oxygen-containing atmosphere, and then the insulator 254b may be formed by ALD. Since the ALD method is a film-forming method with good coating properties, it is possible to prevent steps or the like from being formed due to the unevenness of the insulator 254a. Note that the insulator 254a and the insulator 254b may be made of the same material selected from the materials described above, or may be made of different materials. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. Further, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. Note that the insulator 254 is shown as a two-layer structure in FIG. 13, but may have a single-layer structure or a laminated structure of three or more layers.

[0299] The insulator 280 is provided on the insulator 222, the insulator 224, and the oxide 230 via the insulator 254.

[0300] An insulator 241a is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240a is formed in contact with the side surface thereof. A region 243a is located at at least a part of the bottom of the opening, and the conductor 240a is in contact with the region 243a. Similarly, an insulator 241b is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240b is formed in contact with the side surface thereof. A region 243b is located at at least a part of the bottom of the opening, and the conductor 240b is in contact with the region 243b.

[0301] When the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen in the conductor in contact with the oxide 230a, the oxide 230b, the insulator 254, the insulator 280, the insulator 274, and the insulator 281.

[0302] <Method of manufacturing a semiconductor device> Next, a method of manufacturing a semiconductor device having the transistor 200B according to an aspect of the present invention shown in FIG. 13 will be described with reference to FIGS. 15 to 22. In FIGS. 15 to 22, (A) in each figure shows a top view. Further, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line A1 - A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200B. Further, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line A3 - A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200B. Further, (D) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line A5 - A6 in (A), and is also a cross-sectional view in the vicinity of the region 243b of the transistor 200B. In the top view of (A) in each figure, some elements are omitted for clarity of the figure. Note that the description of the same portions as those in the first embodiment will be omitted.

[0303] First, a substrate (not shown) is prepared, an insulator 214 is formed on the substrate, a conductor 205 and an insulator 216 are formed on the insulator 214, an insulator 222 is formed on the conductor 205 and the insulator 216, an insulating film 224A is formed on the insulator 222, and an oxide film 230A and an oxide film 230B are sequentially formed on the insulating film 224A (see FIG. 15).

[0304] Note that in the method of manufacturing a semiconductor device having the transistor 200B, the steps until the oxide film 230B is formed are the same as those of the semiconductor device having the transistor 200 shown in the first embodiment, and thus the detailed description of the steps until the oxide film 230B is formed will be omitted.

[0305] Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are processed into an island shape to form the insulator 224, the oxide 230a, and the oxide 230b. Note that in this process, the film thickness of the region of the insulator 222 that does not overlap with the insulator 224 may become thin (see FIG. 16).

[0306] Here, the insulator 224, the oxide 230a, and the oxide 230b are formed so that at least a part thereof overlaps with the conductor 205. Further, the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are preferably substantially perpendicular to the upper surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when providing the plurality of transistors 200B, it is possible to reduce the area and increase the density. Alternatively, the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the upper surface of the insulator 222 may form a low angle. In that case, the angle formed by the side surfaces of the insulator 224, the oxide 230a, and the oxide 230b and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, in the subsequent process, the covering property of the insulator 254 and the like is improved, and defects such as looseness can be reduced.

[0307] Further, between the side surface of the oxide 230b and the upper surface of the oxide 230b, there is a curved surface. That is, the end of the side surface and the end of the upper surface are preferably curved (hereinafter also referred to as a round shape). The curved surface, for example, at the end of the oxide 230b, has a curvature radius of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less. By not having an angle at the end, the covering property of the film in the subsequent film forming process is improved.

[0308] Note that the processing of the insulating film 224A, the oxide film 230A, and the oxide film 230B may be performed using a lithography method. Further, for the processing, a dry etching method or a wet etching method can be used. The processing by the dry etching method is suitable for microfabrication. Further, the insulating film 224A, the oxide film 230A, and the oxide film 230B may be processed under different conditions respectively.

[0309] Also, by performing processes such as dry etching, impurities caused by etching gas or the like may adhere to or diffuse into the surface or inside of the oxide 230a, oxide 230b, etc. Examples of the impurities include fluorine, chlorine, and the like.

[0310] In order to remove the above-mentioned impurities and the like, cleaning is performed. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, cleaning by heat treatment, etc., and the above cleaning may be appropriately combined.

[0311] As the wet cleaning, a cleaning process may be performed using an aqueous solution in which oxalic acid, phosphoric acid, hydrofluoric acid, etc. are diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In the present embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

[0312] Subsequently, heat treatment may be performed. The conditions of the heat treatment can use the conditions of the aforementioned heat treatment. Alternatively, it is preferable to perform heat treatment before forming the insulating film 254A. The heat treatment may be performed at 100°C or higher and 400°C or lower, for example, at 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the insulating film 254A. Here, the film formation temperature is not limited to the substrate temperature during film formation, but includes the case of the set temperature of the film formation apparatus. For example, when the insulating film 254A is formed at 200°C, it is preferable that the heat treatment is 200°C. The heat treatment is preferably performed under reduced pressure, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting with a turbo molecular pump or the like. In the vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0313] Next, an insulating film 254A that becomes the insulator 254a is formed on the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 16). The insulating film 254A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen for the formation of the insulating film 254A. In the present embodiment, a silicon nitride film is formed by a sputtering method.

[0314] Next, an insulating film 254B that becomes the insulator 254b is formed on the insulating film 254A (see FIG. 16). The insulating film 254B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen for the formation of the insulating film 254B. For example, it is preferable to form an aluminum oxide film by a sputtering method. By forming an aluminum oxide film using a gas containing oxygen by a sputtering method, oxygen can be injected into the insulator 224. That is, the insulator 224 can have excess oxygen.

[0315] Also, as the insulating film 254B, aluminum oxide may be formed while heating the substrate at a high temperature. The substrate heating temperature during the formation of the insulating film 254B may be 200 ° C or higher, preferably 250 ° C or higher, more preferably 350 ° C or higher. In the present embodiment, aluminum oxide is formed by a sputtering method.

[0316] Next, a dummy gate film that becomes the dummy gate layer 262A is formed on the insulating film 254B. The dummy gate film is processed and used as a dummy gate. The dummy gate is a temporary gate electrode. That is, by processing the dummy gate film, a temporary gate electrode is formed, and in a later process, the dummy gate is removed and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that is easy to microfabricate and easy to remove for the dummy gate film.

[0317] The formation of the dummy gate film can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. For example, an insulator, a semiconductor, or a conductor can be used. Specifically, a silicon film such as polysilicon, microcrystalline silicon, or amorphous silicon, a metal film such as aluminum, titanium, or tungsten, etc. can be used. Alternatively, a film containing carbon, SOG (Spin On Glass), a resin film, etc. may be formed using a coating method. As the material of the resin film, for example, there are photoresist, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. By forming the SOG and the resin film by a coating method, the surface of the dummy gate film can be made flat. By making the surface of the dummy gate film flat in this way, microfabrication becomes easy, and furthermore, removal is also easy.

[0318] In addition, the dummy gate film can also be made into a multilayer film using different film types. For example, the dummy gate film can be made into a two-layer film structure in which a conductive film and a resin film are formed on the conductive film. By making the dummy gate film have such a structure, for example, in a subsequent CMP process, the conductive film may function as a stopper film for CMP processing. Or, it may be possible to detect the end point of CMP processing, and it may be possible to reduce processing variations.

[0319] Next, the dummy gate film is etched by a lithography method to form a dummy gate layer 262A (see FIG. 17). The dummy gate layer 262A is formed so that at least a part thereof overlaps the conductor 205 and the oxide 230.

[0320] Next, using the dummy gate layer 262A as a mask, a dopant 257 is added to the oxide 230b (see FIG. 17). As a result, regions 243a and 243b containing the dopant 257 are formed in regions of the oxide 230b that do not overlap with the dummy gate layer 262A. Note that FIG. 17 shows a state in which the dopant 257 is not added to the region overlapping with the dummy gate layer 262A of the oxide 230b. However, the present embodiment is not limited to this. For example, the dopant 257 may be diffused and added to a region overlapping with the dummy gate layer 262A (for example, region 232 shown in FIG. 14(A)). At this time, a part of regions 243a and 243b is also formed in the region overlapping with the dummy gate layer 262A. In this way, the distance between regions 243a and 243b, that is, the channel length can be controlled.

[0321] As a method for adding the dopant 257, an ion implantation method in which an ionized source gas is mass-separated and added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. When mass separation is performed, the ion species to be added and its concentration can be precisely controlled. On the other hand, when mass separation is not performed, ions with a high concentration can be added in a short time. Also, an ion doping method in which clusters of atoms or molecules are generated and ionized may be used. Note that the dopant may be rephrased as an ion, a donor, an acceptor, an impurity, an element, or the like.

[0322] As the dopant 257, elements that form the above-described oxygen deficiency or elements that bind to the oxygen deficiency may be used. Typical examples of such elements include boron or phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. may also be used. Representative examples of noble gases include helium, neon, argon, krypton, xenon, etc. Further, one or more metal elements selected from among metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum may be added. Among those described above, boron and phosphorus are preferable as the dopant 257. When boron or phosphorus is used as the dopant 257, since the apparatus of the production line of amorphous silicon or low-temperature polysilicon can be used, capital investment can be suppressed.

[0323] Further, in FIG. 17, the dopant 257 is added substantially perpendicular to the upper surface of the insulator 214, but the present invention is not limited to this, and the addition of the dopant 257 may be performed obliquely with respect to the upper surface of the insulator 214. By adding the dopant obliquely with respect to the upper surface of the insulator 214, the regions 243a and 243b can be easily formed in a part of the region overlapping with the dummy gate layer 262A.

[0324] Further, in the manufacturing method of the present embodiment, the dopant 257 is added to the oxide 230 through the insulating film 254A and the insulating film 254B. By adopting such a manufacturing method, the dopant 257 is also added to the insulating film 254A and the insulating film 254B. That is, both the oxide 230 and the insulating films 254A and 254B have elements contained in the dopant 257. Further, when the insulating films 254A and 254B have excess oxygen, the dopant 257 may be able to suppress the diffusion of excess oxygen to the outside.

[0325] As described above, by forming the region 243, the conductor 260 formed in a subsequent process can be self-alignedly disposed between the regions 243a and 243b.

[0326] Next, an insulating film 280A that becomes the insulator 280 is formed on the insulating film 254B and the dummy gate layer 262A (see FIG. 18). The insulating film 280A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0327] Next, a part of the insulating film 280A and the dummy gate layer 262A is removed until a part of the dummy gate layer 262A is exposed, thereby forming the insulator 280 and the dummy gate 262 (see FIG. 19). It is preferable to use a CMP process for forming the insulator 280 and the dummy gate 262.

[0328] Also, as described above, when the dummy gate layer 262A is, for example, a film having a two-layer structure in which a first layer and a second layer are formed on the first layer, in the CMP process, the first layer may function as a stopper film for the CMP process. Alternatively, it may be possible to detect the end point of the CMP process for the first layer, and in some cases, it may be possible to reduce the variation in the height of the dummy gate 262. As shown in FIG. 19(B), the upper surface of the dummy gate 262 and the upper surface of the insulator 280 substantially coincide.

[0329] Next, the dummy gate 262, and a part of the insulating film 254A and the insulating film 254B that overlap the dummy gate 262 are removed to form an opening 263 (see FIG. 20). The removal of the dummy gate 262, the insulating film 254A, and the insulating film 254B can be performed using wet etching, dry etching, ashing, or the like. Alternatively, the above processes may be appropriately combined in plural. For example, a wet etching process may be performed after an ashing process. By removing a part of the insulating film 254A and the insulating film 254B, insulators 254a and 254b are formed. By removing the dummy gate 262, the insulating film 254A, and the insulating film 254B, a part of the surface of the oxide 230b is exposed from the opening 263. At this time, a part of the surface of the region 243 may be exposed from the opening 263.

[0330] Next, it is preferable to perform a heat treatment before forming the oxide film 230C1. The heat treatment may be performed at 100°C or higher and 400°C or lower, for example, at 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the oxide film 230C1 or the oxide film 230C2. Here, the film formation temperature includes not only the substrate temperature during film formation but also the case of the set temperature of the film formation apparatus. For example, when forming the oxide film 230C1 or the oxide film 230C2 at 300°C, it is preferable that the heat treatment be 300°C. The heat treatment is preferably performed under reduced pressure. For example, it may be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuating with a turbo molecular pump or the like. In the vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0331] Next, the oxide film 230C1 and the oxide film 230C2 are sequentially formed so as to be embedded in the opening 263 (see FIG. 21). Further, after the heat treatment, it is preferable to continuously form the oxide film 230C1 and the oxide film 230C2 without exposing them to the atmosphere. For example, it is preferable to continuously perform the heat treatment and the film formation process in different chambers using a film formation apparatus of a multi-chamber method described later. By performing such a process, impurities such as moisture, hydrogen, and carbon adsorbed on the surface of the oxide 230a and the oxide 230b can be removed, and further, the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The impurities removed by the heat treatment include impurities having a bond between hydrogen and carbon, impurities having a bond between hydrogen and oxygen, and the like. Further, by continuously performing the heat treatment and the film formation without exposing them to the outside air, re-invasion of impurities such as hydrogen into the oxide 230 can be prevented.

[0332] The oxide film 230C1 and the oxide film 230C2 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C1 and the oxide film 230C2 may be formed by the same film formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C1 and the oxide film 230C2. The oxide film 230C1 and the oxide film 230C2 may be formed of In-Ga-Zn oxide or an oxide not containing In. The oxide not containing In may be formed of Ga-Zn oxide or gallium oxide. The oxide film 230C1 and the oxide film 230C2 may be formed of a laminated structure of In-Ga-Zn oxide and an oxide not containing In. The oxide film 230C1 and the oxide film 230C2 are formed by sputtering using an oxide target having an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:4.1, Ga:Zn=2:1, or Ga:Zn=2:5. In this embodiment, the oxide film 230C1 is formed by sputtering using an oxide target having an atomic ratio of In:Ga:Zn=4:2:4.1, and the oxide film 230C2 is formed by sputtering using an oxide target having an atomic ratio of In:Ga:Zn=1:3:4.

[0333] That is, the oxide film 230C1 may be formed using a target similar to that used to form the oxide film 230B, and the oxide film 230C2 may be formed using a target similar to that used to form the oxide film 230A.

[0334] The oxide film 230C1 and the oxide film 230C2 are preferably formed while heating the substrate. At this time, by setting the substrate temperature to 300° C. or higher, oxygen vacancies in the oxide 230a, the oxide 230b, the oxide film 230C1, and the oxide film 230C2 can be reduced. In addition, for example, the film may be formed at the same temperature as the film formation temperature of the insulating film 250A described later. In addition, by forming the film while heating the substrate in this way, the crystallinity of the oxide 230a, the oxide 230b, the oxide film 230C1, and the oxide film 230C2 can be improved.

[0335] In particular, when forming the oxide films 230C1 and 230C2, part of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide films 230C1 and 230C2 may be 70% or more, preferably 80% or more, and more preferably 100%. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0336] Next, it is preferable to perform a heat treatment before forming the insulating film 250A. The heat treatment may be performed at 100°C or higher and 400°C or lower, for example, at 200°C. Alternatively, it is preferably performed at the same temperature as the film formation temperature of the insulating film 250A. Here, the film formation temperature is not limited to the substrate temperature during film formation, but includes the case of the set temperature of the film formation apparatus. For example, when forming the insulating film 250A at 350°C, the heat treatment is preferably set at 350°C. The heat treatment is preferably performed under reduced pressure, and may be performed, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuating with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less.

[0337] Next, the insulating film 250A is formed (see FIG. 21). The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferable to form silicon oxide, hafnium oxide, or gallium oxide using the ALD method. For example, as the insulating film 250A, a laminated film of silicon oxide and gallium oxide on silicon oxide may be used. The film formation temperature when forming the insulating film 250A is preferably 300°C or higher and less than 450°C, preferably 350°C or higher and 400°C or lower. For example, by forming the insulating film 250A at 400°C, a film with few impurities and high density can be formed.

[0338] Note that oxygen can be introduced into the insulating film 250A by exciting oxygen with microwaves to generate a high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.

[0339] Also, heat treatment may be performed. The heat treatment conditions described above can be used. By this heat treatment, the moisture concentration and hydrogen concentration of the insulating film 250A can be reduced.

[0340] Next, the conductive film 260A and the conductive film 260B are formed. The formation of the conductive film 260A and the conductive film 260B can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In the present embodiment, the conductive film 260A is formed using the ALD method, and the conductive film 260B is formed using the CVD method (see FIG. 21).

[0341] Next, by CMP processing, the oxide film 230C1, the oxide film 230C2, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, thereby forming the oxide 230c (the oxide 230c1 and the oxide 230c2), the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 22). Thereby, the oxide 230c is disposed so as to cover the inner walls (side walls and bottom surface) of the opening reaching the oxide 230b. Further, the insulator 250 is disposed so as to cover the inner wall of the opening via the oxide 230c. Further, the conductor 260 is disposed so as to fill the opening via the oxide 230c and the insulator 250.

[0342] Next, heat treatment may be performed. The heat treatment may be carried out at a temperature of 100°C or higher and 400°C or lower, for example, at 200°C. Alternatively, it is preferably carried out at the same temperature as the film formation temperature of the insulator 274. Here, the film formation temperature is not limited to the substrate temperature during film formation, but includes the case of the set temperature of the film formation apparatus. For example, when the insulator 274 is formed at 250°C, the heat treatment is preferably set at 250°C. The heat treatment is preferably carried out under reduced pressure, for example, it may be carried out in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuating with a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less. By this heat treatment, the moisture concentration and hydrogen concentration in the insulator 280 can be reduced.

[0343] Next, an insulator 274 may be formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The film formation of the insulator 274 can be carried out using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 274, for example, it is preferable to form an aluminum oxide film by a sputtering method. By forming an aluminum oxide film by a sputtering method, it may be possible to suppress the diffusion of hydrogen contained in the insulator 281 to the oxide 230. Further, by forming the insulator 274 so as to be in contact with the conductor 260, oxidation of the conductor 260 can be suppressed, which is preferable. Further, by forming the insulator 274, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 may be supplied to the region 234 of the oxide 230b via the oxide 230c1. Further, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 274 may be supplied to the region 234 of the oxide 230b via the oxide 230c1.

[0344] Next, heat treatment may be performed. The heat treatment conditions described above can be used. By this heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced. In addition, oxygen contained in the insulator 274 can be implanted into the insulator 280.

[0345] Note that, as a method of forming the insulator 274 on the insulator 280, first, an insulating film made of the same material as the insulator 274 is formed by the same formation method as the insulator 274, next, heat treatment is performed using the heat treatment conditions described above, next, the insulating film is removed by CMP treatment, next, the insulator 274 is formed, and then, heat treatment may be performed using the heating conditions described above. By this method, more excessive oxygen regions can be formed in the insulator 280. Note that, in the step of removing the insulating film, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.

[0346] In addition, an insulator may be provided between the insulator 280 and the insulator 274. As the insulator, for example, silicon oxide formed by a sputtering method may be used. By providing the insulator, an excessive oxygen region can be formed in the insulator 280.

[0347] Next, an insulating film to be the insulator 281 may be formed on the insulator 274. The insulating film to be the insulator 281 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 22).

[0348] Next, openings reaching the regions 243a and 243b are formed in the insulator 254, the insulator 280, the insulator 274, and the insulator 281. The openings may be formed using a lithography method.

[0349] Note that, in the semiconductor device having the transistor 200B, the steps after forming the above openings are the same as those of the semiconductor device having the transistor 200 shown in the first embodiment, and thus a detailed description of the steps after forming the above openings is omitted.

[0350] According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Also, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Also, according to one aspect of the present invention, a highly productive semiconductor device can be provided.

[0351] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0352] (Embodiment 3) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 23 to 26.

[0353] [Storage device 1] An example of a semiconductor device (storage device) using a transistor which is one aspect of the present invention is shown in FIG. 23. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor 200 described in the previous embodiment can be used.

[0354] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-current of the transistor 200 is small, by using this in a memory device, it is possible to hold the stored content for a long time. That is, since it does not require a refresh operation or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

[0355] In the semiconductor device shown in FIG. 23, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor element 100. In the following, the node at which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitor element 100 are connected may be referred to as the node FG.

[0356] The semiconductor device shown in FIG. 23 has the property that the potential of the gate (node FG) of the transistor 300 can be held by the switching of the transistor 200, so that information can be written, held, and read out.

[0357] Further, the memory device shown in FIG. 23 can be configured as a memory cell array by arranging it in a matrix.

[0358] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 may be either p-channel type or n-channel type.

[0359] Here, in the transistor 300 shown in FIG. 23, the semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Note that the conductor 316 may use a material for adjusting the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN-type transistor. Note that an insulator that functions as a mask for forming the convex portion may be in contact with the upper portion of the convex portion. Also, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0360] Note that the transistor 300 shown in FIG. 23 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0361] <Capacitor element 100> The capacitor element 100 is provided above the transistor 200. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.

[0362] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300.

[0363] In FIG. 23, the conductor 112 and the conductor 110 are shown as single-layer structures, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, a conductor having barrier properties, and a conductor having high adhesiveness to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0364] Further, the insulator 130 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and may be provided in a laminated or single-layer form.

[0365] For example, it is preferable to use a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high permittivity (high-k) material for the insulator 130. With this configuration, the capacitor element 100 can secure a sufficient capacitance by having a high permittivity (high-k) insulator, and can improve the dielectric strength by having an insulator having a high dielectric strength, thereby suppressing the electrostatic breakdown of the capacitor element 100.

[0366] Note that examples of the insulator of the high permittivity (high-k) material (material having a high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, and a nitride having silicon and hafnium.

[0367] On the other hand, examples of the material having a high dielectric strength (material having a low relative permittivity) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resin.

[0368] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the respective structures. Also, a plurality of wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral when a plurality of structures are grouped together. Also, in this specification etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0369] For example, on the substrate 311, as an interlayer film, insulators 320, 322, 324, and 326 are sequentially stacked and provided. Note that the insulator 315 and the conductor 316 are provided so as to be embedded in the insulator 320. Also, in the insulators 320, 322, 324, and 326, a capacitor element 100 or conductors 328 and 330 electrically connected to the transistor 200 are embedded. Note that the conductors 328 and 330 function as plugs or wiring.

[0370] Also, the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0371] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 23, insulators 350, 352, and 354 are sequentially stacked and provided. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0372] On the insulator 354 and the conductor 356, the insulators 210, 212, 214, and 216 are sequentially stacked and provided. Further, in the insulators 210, 212, 214, and 216, conductors such as the conductor 218 and the conductor (conductor 205) constituting the transistor 200 are embedded. Note that the conductor 218 has a function as a plug or wiring that is electrically connected to the capacitor element 100 or the transistor 300. Furthermore, an insulator 150 is provided on the conductor 120 and the insulator 130.

[0373] Examples of insulators that can be used as interlayer dielectrics include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

[0374] For example, by using a material with a low relative permittivity for the insulator that functions as an interlayer dielectric, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0375] For example, it is preferable that the insulators 212, 352, 354, etc. have an insulator with a low relative permittivity. For example, the insulator preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, resin, and the like. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added or silicon oxide with pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

[0376] Also, one or both of the insulator 130 and the insulator 150 provided on the conductor 112 or the conductor 120 are made of an insulator having a resistivity of 1.0×10 12 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13 Ωcm or less. By making one or both of the insulator 130 and the insulator 150 an insulator having the above resistivity, the insulator can disperse the charges accumulated between the wirings such as the transistor 200, the transistor 300, the capacitor element 100, the conductor 112, and the conductor 120 while maintaining insulation, and can suppress the characteristic deterioration and electrostatic breakdown of the transistor and the memory device having the transistor caused by the charges, which is preferable. As such an insulator, silicon nitride or silicon oxynitride can be used.

[0377] Also, as the insulator having the above resistivity, the insulator 140 may be provided under the conductor 112. In this case, the insulator 140 is formed on the insulator 281, openings are formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 254, etc., and the insulator 241 may be formed in the openings, or the conductor 240 electrically connected to the transistor 200, the conductor 218, etc. may be formed. The insulator 140 can use the same material as the insulator 130 or the insulator 150.

[0378] Also, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, the insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0379] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used.

[0380] As a conductor that can be used for wiring and plugs, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0381] For example, as the conductor 328, conductor 330, conductor 356, conductor 218, conductor 110, conductor 112, conductor 120, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, a metal oxide material formed of the above materials can be used in a single layer or in a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Or, it is preferably formed of a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0382] <<Wiring or plug of the layer provided with the oxide semiconductor>> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In this case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and a conductor provided on the insulator having the excess oxygen region.

[0383] For example, in FIG. 23, an insulator 241 may be provided between the insulators 280 and 281 and the conductor 240. By the insulator 241 existing between the insulators 280 and 281 and the conductor 240, absorption of oxygen contained in the insulators 280 and 281 by the conductor 240, that is, oxidation of the conductor 240 can be suppressed.

[0384] That is, by providing the insulator 241, absorption of excess oxygen included in the insulator 280 by the conductor 240 can be suppressed. Further, by having the insulator 241, diffusion of hydrogen, which is an impurity, into the transistor 200 through the conductor 240 can be suppressed.

[0385] As the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon oxynitride, and silicon nitride can also be used.

[0386] The above is the description of the configuration example. By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. In addition, a transistor having an oxide semiconductor with a large on-current can be provided. In addition, a transistor having an oxide semiconductor with a small off-current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

[0387] [Memory device 2] An example of a semiconductor device (memory device) using a transistor, which is one aspect of the present invention, is shown in FIG. 24. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor 200B described in the previous embodiment can be used.

[0388] Note that, in the semiconductor device (memory device) shown in [Memory device 2], the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor device (memory device) shown in [Memory device 1]. Also, regarding the details of the configuration, materials, etc. of the semiconductor device (memory device) shown in [Memory device 2], which are common to the configuration, materials, etc. of the semiconductor device (memory device) shown in [Memory device 1], and the details of the structures, materials, etc. to which the same reference numerals are added, the previous description can be referred to.

[0389] [Memory device 3] An example of a memory device using a semiconductor device, which is one aspect of the present invention, is shown in FIG. 25. The memory device shown in FIG. 25 has a transistor 400 in addition to the semiconductor device having the transistors 200, 300, and the capacitor element 100 shown in FIG. 23.

[0390] Transistor 400 can control the second gate voltage of transistor 200. For example, the first gate and the second gate of transistor 400 are diode-connected to the source, and the source of transistor 400 is connected to the second gate of transistor 200. When the negative potential of the second gate of transistor 200 is held in this configuration, the voltage between the first gate and the source and the voltage between the second gate and the source of transistor 400 become 0V. In transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the negative potential of the second gate of transistor 200 can be maintained for a long time without supplying power to transistor 200 and transistor 400. As a result, the memory device having transistor 200 and transistor 400 can retain the stored content for a long time.

[0391] Therefore, in FIG. 25, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Also, wiring 1003 is electrically connected to one of the source and the drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Then, the gate of transistor 300 and the other of the source and the drain of transistor 200 are electrically connected to one of the electrodes of capacitor element 100, and wiring 1005 is electrically connected to the other of the electrodes of capacitor element 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0392] In addition, similar to the memory device shown in FIG. 23, the memory device shown in FIG. 25 can form a memory cell array by arranging it in a matrix. Note that one transistor 400 can control the second gate voltages of a plurality of transistors 200. Therefore, the number of transistors 400 provided may be smaller than that of transistors 200.

[0393] <Transistor 400> Transistor 400 is a transistor formed in the same layer as transistor 200 and can be fabricated in parallel. Transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, a conductor 405 (conductor 405a and conductor 405b) that functions as a second gate electrode, insulators 222, 424a, 424b, and 450 that function as gate insulators, an oxide 430c in which a channel is formed, conductors 442a, oxides 431a, and oxides 431b that function as one of a source or a drain, conductors 442b, oxides 432a, and oxides 432b that function as the other of the source or the drain, and conductors 440 (conductor 440a and conductor 440b).

[0394] In transistor 400, conductor 405 is formed in the same layer as conductor 205. Insulators 424a and 424b are formed in the same layer as insulator 224. Oxides 431a and 432a are formed in the same layer as oxide 230a, and oxides 431b and 432b are formed in the same layer as oxide 230b. Conductor 442 is formed in the same layer as conductor 242. Oxide 430c is formed in the same layer as oxide 230c. Insulator 450 is formed in the same layer as insulator 250. Conductor 460 is formed in the same layer as conductor 260.

[0395] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that becomes oxide 230c.

[0396] The oxide 430c that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as water and hydrogen, similar to the oxide 230 and the like. As a result, the threshold voltage of the transistor 400 can be increased, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0397] <<Dicing line>> Hereinafter, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate for each semiconductor element will be described. As a dividing method, for example, first, a groove (dicing line) for dividing the semiconductor element is formed in the substrate, and then cutting is performed at the dicing line to divide (split) into a plurality of semiconductor devices.

[0398] At the outer edges of the transistor 200 described in the previous embodiment and the transistor 400 shown in this embodiment, as shown in FIG. 25, the insulator 254 and the insulator 222 are in contact. Therefore, when designing the region where the insulator 254 and the insulator 222 are in contact to be the dicing line, the degree of freedom in designing the dicing line can be increased. At this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide.

[0399] With this structure, the insulator 222 and the insulator 254 can enclose the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into a plurality of chips by dividing the substrate for each circuit region in which the semiconductor element shown in this embodiment is formed, impurities such as water and hydrogen can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400.

[0400] In addition, with this structure, it is possible to prevent the excess oxygen of the insulator 224 from diffusing to the outside of the insulator 254 and the insulator 222. Therefore, the excess oxygen of the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200 or the transistor 400. By this oxygen, the oxygen deficiency of the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be reduced. Thereby, the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed and the reliability can be improved.

[0401] [Memory device 4] An example of a memory device using the semiconductor device which is one aspect of the present invention is shown in FIG. 26. The memory device shown in FIG. 26 has a transistor 400 in addition to the semiconductor device having the transistors 200, 300, and the capacitor element 100 shown in FIG. 24.

[0402] Note that, in the memory device shown in [Memory device 4], the same reference numerals are given to the structures having the same functions as the structures constituting the memory device shown in [Memory device 3]. In addition, regarding the details of the configuration, materials, etc. of the memory device shown in [Memory device 4] that are common to the configuration, materials, etc. of the memory device shown in [Memory device 3], and the details of the structures, materials, etc. to which the same reference numerals are given, the previous description can be referred to.

[0403] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and can be fabricated in parallel. Transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, a conductor 405 (conductor 405a and conductor 405b) that functions as a second gate electrode, insulators 222, 424a, 424b, and 450 that function as a gate insulator, an oxide 430c (oxide 430c1 and oxide 430c2) having a region where a channel is formed, regions 443a, oxide 431a, and oxide 431b that function as one of a source or a drain, regions 443b, oxide 432a, and oxide 432b that function as the other of the source or the drain, and a conductor 440 (conductor 440a and conductor 440b).

[0404] In transistor 400, conductor 405 and conductor 205 are formed in the same layer. Insulators 424a and 424b and insulator 224 are formed in the same layer. Oxides 431a and 432a and oxide 230a are formed in the same layer, and oxides 431b and 432b and oxide 230b are formed in the same layer. Regions 443a and 443b and regions 243a and 243b are formed in the same process. Oxides 430c1 and 430c2 and oxides 230c1 and 230c2 are formed in the same layer respectively. Insulator 450 and insulator 250 are formed in the same layer. Conductor 460 and conductor 260 are formed in the same layer.

[0405] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0406] (Embodiment 4) In this embodiment, with reference to FIGS. 27 and 28, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) according to one aspect of the present invention, and a storage device (hereinafter sometimes referred to as an OS memory device) to which a capacitor element is applied will be described. The OS memory device is a storage device having at least a capacitor element and an OS transistor that controls charging and discharging of the capacitor element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

[0407] <Configuration Example of Storage Device> FIG. 27(A) shows an example of the configuration of the OS memory device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0408] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above-mentioned wiring is the wiring connected to the memory cells included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0409] A low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0410] The control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0411] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cells MC in a column, and the like. Also, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in a row, and the like.

[0412] In FIG. 27(A), an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is shown, but the present embodiment is not limited to this. For example, as shown in FIG. 27(B), the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

[0413] A configuration example of a memory cell applicable to the above-described memory cell MC will be described with reference to FIG. 28.

[0414] [DOSRAM] Circuit configuration examples of DRAM memory cells are shown in FIGS. 28(A) to (C). In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell may be referred to as a DOSRAM. The memory cell 1471 shown in FIG. 28(A) has a transistor M1 and a capacitor element CA. Note that the transistor M1 has a gate (which may be called a top gate) and a back gate.

[0415] The first terminal of transistor M1 is connected to the first terminal of capacitor element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor element CA is connected to wiring CAL.

[0416] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor element CA. It is preferable to apply a low-level potential to wiring CAL during data writing and reading. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0417] Also, memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. For example, memory cell MC may have a configuration in which the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, like memory cell 1472 shown in FIG. 28(B). Further, for example, memory cell MC may be a memory cell composed of a transistor having a single-gate structure, that is, transistor M1 without a back gate, like memory cell 1473 shown in FIG. 28(C).

[0418] When the semiconductor device shown in the above embodiment is used for a memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor element 100 can be used as the capacitor element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very small, multi-valued data or analog data can be held for the memory cells 1471, 1472, and 1473.

[0419] Also, in DOSRAM, as described above, if the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened. Thereby, the bit line capacitance is reduced, and the holding capacitance of the memory cell can be reduced.

[0420] [NOSRAM] Figures 28(D) to (G) show circuit configuration examples of a gain cell type memory cell of 2 transistors and 1 capacitor element. The memory cell 1474 shown in Figure 28(D) has a transistor M2, a transistor M3, and a capacitor element CB. Note that the transistor M2 has a top gate (which may simply be called a gate in some cases) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor for the transistor M2 may be called a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0421] The first terminal of transistor M2 is connected to the first terminal of capacitor element CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor element CB.

[0422] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor element CB. It is preferable to apply a low-level potential to wiring CAL during data writing, during data holding, and during data reading. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0423] Also, memory cell MC is not limited to memory cell 1474, and the circuit configuration can be appropriately changed. For example, memory cell MC may be configured such that the back gate of transistor M2 is connected to wiring WOL instead of wiring BGL, as in memory cell 1475 shown in FIG. 28(E). Further, for example, memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, transistor M2 having no back gate, as in memory cell 1476 shown in FIG. 28(F). Further, for example, memory cell MC may have a configuration in which wiring WBL and wiring RBL are combined into a single wiring BIL, as in memory cell 1477 shown in FIG. 28(G).

[0424] When the semiconductor device shown in the above embodiment is used for a memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very small. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0425] Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor. Therefore, an Si transistor may be used as the transistor M3 that functions as a read transistor. Also, by using an Si transistor for the transistor M3, the transistor M2 can be provided laminated on the transistor M3, so that the occupied area of the memory cell can be reduced and high integration of the storage device can be achieved.

[0426] Also, the transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M2 and the transistor M3, the memory cell array 1470 can be configured with a circuit using only n-type transistors.

[0427] Further, FIG. 28(H) shows an example of a gain cell type memory cell of a three-transistor one-capacitor element. The memory cell 1478 shown in FIG. 28(H) includes transistors M4 to M6 and a capacitor element CC. The capacitor element CC is provided as appropriate. The memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring that supplies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of the wiring BIL.

[0428] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

[0429] Note that each of the transistors M5 and M6 may be an n-channel type Si transistor or a p-channel type Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured with only n-type transistors.

[0430] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor element 100 can be used as the capacitor element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small.

[0431] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment are not limited to the above. The arrangement or function of these circuits, the wirings connected to the circuits, circuit elements, etc. may be changed, deleted, or added as necessary.

[0432] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0433] (Embodiment 5) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using FIG. 29. A plurality of circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating a plurality of circuits (systems) on one chip is sometimes called a System on Chip (SoC).

[0434] As shown in FIG. 29(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0435] Bumps (not shown) are provided on the chip 1200 and are connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 29(B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

[0436] Storage devices such as a DRAM 1221 and a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0437] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. For this memory, the aforementioned NOSRAM or DOSRAM can be used. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. By providing an image processing circuit or a multiplication-accumulation operation circuit using the oxide semiconductor of the present invention in the GPU 1212, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption.

[0438] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after the calculation in the GPU 1212 can be performed at high speed.

[0439] The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the multiplication-accumulation operation circuit may be provided in the analog operation unit 1213.

[0440] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0441] The interface 1215 has an interface circuit for external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0442] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a network security circuit.

[0443] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0444] The PCB 1201 provided with the chip 1200 having the GPU 1212, the motherboard 1203 provided with the DRAM 1221 and the flash memory 1222 can be called a GPU module 1204.

[0445] Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is preferably used in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. Further, by the multiplication and accumulation circuit using the GPU 1212, methods such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), and a deep belief network (DBN) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0446] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0447] (Embodiment 6) In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIG. 30 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0448] FIG. 30(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 and the like.

[0449] Figure 30(B) is a schematic diagram of the appearance of an SD card, and Figure 30(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, reading and writing of data in the memory chip 1114 are enabled by wireless communication between the host device and the SD card 1110. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 or the like.

[0450] Figure 30(D) is a schematic diagram of the appearance of an SSD, and Figure 30(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing a memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 or the like.

[0451] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0452] (Embodiment 7) A semiconductor device according to an aspect of the present invention can be used for a processor such as a CPU or a GPU, or a chip. Figure 31 shows a specific example of an electronic device including a processor such as a CPU or a GPU, or a chip according to an aspect of the present invention.

[0453] <Electronic Device / System> The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include television sets, desktop or notebook personal computers, monitors for computers, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens. In addition, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, and the like can also be mentioned. Further, by providing an integrated circuit or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

[0454] The electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, it is possible to display video, information, etc. on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0455] The electronic device according to one aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0456] The electronic device according to one aspect of the present invention can have various functions. For example, it can have a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, and the like. Figure 31 shows an example of an electronic device.

[0457] [Mobile phone] FIG. 31(A) shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0458] By applying the chip of an aspect of the present invention, the information terminal 5500 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprint and voiceprint.

[0459] [Information Terminal] FIG. 31(B) shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0460] Similar to the aforementioned information terminal 5500, the desktop information terminal 5300 can execute applications using artificial intelligence by applying the chip of an aspect of the present invention. Examples of applications using artificial intelligence include, for example, design support software, text proofreading software, and automatic menu generation software. Also, by using the desktop information terminal 5300, new artificial intelligence can be developed.

[0461] In the above description, a smartphone and a desktop information terminal are taken as examples of electronic devices and are illustrated in FIGS. 31(A) and (B), respectively. However, information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0462] [Household Appliance] FIG. 31(C) shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0463] By applying the chip of one aspect of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can have functions such as automatically generating a menu based on the food ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of those food ingredients, and automatically adjusting the temperature according to the food ingredients stored in the electric refrigerator-freezer 5800.

[0464] In this example, an electric refrigerator-freezer is described as a household appliance. Other household appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual devices, and the like.

[0465] [Game Machine] FIG. 31(D) shows a portable game machine 5200, which is an example of a game machine. The portable game machine includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0466] By applying the GPU or chip according to one aspect of the present invention to the portable game machine 5200, a portable game machine 5200 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence of the heat on the circuit itself, the peripheral circuits, and the modules can be minimized.

[0467] Furthermore, by applying the GPU or chip according to one aspect of the present invention to the portable game machine 5200, a portable game machine 5200 having artificial intelligence can be realized.

[0468] Originally, the expressions such as the progress of the game, the speech and actions of the creatures appearing in the game, and the phenomena occurring in the game are defined by the program of the game. However, by applying artificial intelligence to the portable game machine 5200, expressions not limited to the game program become possible. For example, expressions such as the content asked by the player, the progress of the game, the time, and the change in the speech and actions of the characters appearing in the game become possible.

[0469] In addition, when a game that requires a plurality of players is played on the portable game machine 5200, since the game player can be anthropomorphically configured by artificial intelligence, the game can be played even by one person by using the game player by artificial intelligence as the opponent.

[0470] In FIG. 31(D), a portable game machine is illustrated as an example of a game machine. However, the game machine to which the GPU or chip according to one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip according to one aspect of the present invention is applied include, for example, a home stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0471] [Mobile body] The GPU or chip according to one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile.

[0472] FIG. 31(E1) shows an automobile 5700 which is an example of a moving body, and FIG. 31(E2) is a view showing the periphery of the windshield inside the automobile. In FIG. 31(E2), in addition to the display panels 5701, 5702, and 5703 attached to the dashboard, a display panel 5704 attached to the pillar is illustrated.

[0473] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items and layouts displayed on the display panel can be appropriately changed according to the user's preference, and the designability can be enhanced. The display panels 5701 to 5703 can also be used as lighting devices.

[0474] The display panel 5704 can complement the visual field (blind spot) blocked by the pillar by projecting an image from an imaging device (not shown) provided in the automobile 5700. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be compensated and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally without a sense of incongruity. The display panel 5704 can also be used as a lighting device.

[0475] Since the GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of the automobile 5700. In addition, the chip can be used in a system for performing road guidance, danger prediction, and the like. The display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.

[0476] In the above description, an automobile has been described as an example of a moving body. However, the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. The chip according to one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0477] [Broadcast system] The GPU or chip according to one aspect of the present invention can be applied to a broadcast system.

[0478] FIG. 31(F) schematically shows data transmission in a broadcast system. Specifically, FIG. 31(F) shows the path until the radio wave (broadcast signal) transmitted from the broadcasting station 5680 reaches the television receiving apparatus (TV) 5600 of each household. The TV 5600 includes a receiving apparatus (not shown). The broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving apparatus.

[0479] In FIG. 31(F), the antenna 5650 is illustrated as a UHF (Ultra High Frequency) antenna. However, as the antenna 5650, a BS·110°CS antenna, a CS antenna, etc. can also be applied.

[0480] The radio waves 5675A and 5675B are broadcast signals for terrestrial digital television broadcasting. The radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. In each household, by receiving the radio wave 5675B with the antenna 5650, terrestrial digital television broadcasting can be viewed on the TV 5600. Note that the broadcast system is not limited to the terrestrial digital television broadcasting shown in FIG. 31(F), and may be satellite broadcasting using artificial satellites, data broadcasting using optical fibers, etc.

[0481] The above-described broadcast system may be a broadcast system utilizing artificial intelligence by applying the chip of one aspect of the present invention. When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving device included in the TV 5600 restores the broadcast data. By utilizing artificial intelligence, for example, in motion compensation prediction which is one of the compression methods of the encoder, it is possible to recognize the display pattern included in the display image. Also, in-frame prediction using artificial intelligence can be performed. Further, for example, when receiving broadcast data with low resolution and displaying the broadcast data on the TV 5600 with high resolution, in the restoration of the broadcast data by the decoder, interpolation processing of an image such as up-conversion can be performed.

[0482] The above-described broadcast system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasts in which the amount of broadcast data increases.

[0483] Also, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. By adopting such a configuration, by having the recording device learn the user's preferences by artificial intelligence, it is possible to automatically record programs according to the user's preferences.

[0484] The electronic device, the functions of the electronic device, application examples of artificial intelligence, and the effects thereof described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0485] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments and the like.

Description of Reference Numerals

[0486] 100 Capacitive element, 110 Conductor, 112 Conductor, 120 Conductor, 130 Insulator, 140 Insulator, 150 Insulator, 200 Transistor, 200A Transistor, 200B Transistor, 205 Conductor, 210 Insulator, 212 Insulator, 214 Insulator, 216 Insulator, 218 Conductor, 222 Insulator, 224 Insulator, 224A Insulating film, 230 Oxide, 230a Oxide, 230A Oxide film, 230b Oxide, 230B Oxide film, 230c Oxide, 230c1 Oxide, 230c2 Oxide, 230C Oxide film, 230C1 Oxide film, 230C2 Oxide film, 231 Region, 231a Region, 231b Region, 232 Region, 232a Region, 232b Region, 234 Region, 240 Conductor, 240a Conductor, 240b Conductor, 241 Insulator, 241a Insulator, 241b Insulator, 242 Conductor, 242a Conductor, 242A Conductive film, 242b Conductor, 242B Conductive layer, 243 Region, 243a Region, 243b Region, 250 Insulator, 250A Insulating film, 254 Insulator, 254a Insulator, 254A Insulating film, 254b Insulator, 254B Insulating film, 254c Insulator, 260 Conductor, 260a Conductor, 260A Conductive film, 260B Conductive film, 260b Conductor, 262Dummy gate, 262A Dummy gate layer, 274 Insulator, 280 Insulator, 280a Insulator, 280A Insulating film, 280b Insulator, 281 Insulator, 282 Insulator, 300 Transistor, 311 Substrate, 313 Semiconductor region, 314a Low-resistance region, 314b Low-resistance region, 315 Insulator, 316 Conductor, 320 Insulator, 322 Insulator, 324 Insulator, 326 Insulator, 328 Conductor, 330 Conductor, 350 Insulator, 352 Insulator, 354 Insulator, 356 Conductor, 400 Transistor, 405 Conductor, 405a Conductor, 405b Conductor, 424a Insulator, 424b Insulator, 430c Oxide, 430c1 Oxide, 430c2 Oxide, 431a Oxide, 431b Oxide, 432a Oxide, 432b Oxide, 440 Conductor, 440a Conductor, 440b Conductor, 442 Conductor, 442a Conductor, 442b Conductor, 443a Region, 443b Region, 450 Insulator, 460 Conductor, 460a Conductor, 460bConductor, Wiring 1001, Wiring 1002, Wiring 1003, Wiring 1004, Wiring 1005, Wiring 1006, Wiring 1007, Wiring 1008, Wiring 1009, Wiring 1010, USB Memory 1100, Housing 1101, Cap 1102, USB Connector 1103, Substrate 1104, Memory Chip 1105, Controller Chip 1106, SD Card 1110, Housing 1111, Connector 1112, Substrate 1113, Memory Chip 1114, Controller Chip 1115, SSD 1150, Housing 1151, Connector 1152, Substrate 1153, Memory Chip 1154, Memory Chip 1155, Controller Chip 1156, Chip 1200, PCB 1201, Bump 1202, Motherboard 1203, GPU Module 1204, CPU 1211, GPU 1212, Analog Arithmetic Unit 1213, Memory Controller 1214, Interface 1215, Network Circuit 1216, DRAM 1221, Flash Memory 1222, Storage Device 1400, Peripheral Circuit 1411, Row Circuit 1420, Column Circuit 1430, Output Circuit 1440, Control Logic Circuit 1460, Memory Cell Array 1470, Memory Cell 1471, Memory Cell 1472, Memory Cell 1473, Memory Cell 1474, Memory Cell 1475, Memory Cell 1476, Memory Cell 1477, Memory Cell 1478, Portable Game Console 5200, Housing 5201, Display Unit 5202, Button 5203, Desktop Information Terminal 5300, Main Body 5301, Display 5302, Keyboard 5303, Information Terminal 5500, Housing 5510, Display Unit 5511, TV 5600, Antenna 5650, Radio Tower 5670, Radio Wave 5675A, Radio Wave 5675B, Broadcasting Station 5680, Automobile 5700, Display Panel 5701, Display Panel 5702, Display Panel 5703, Display Panel 5704, Electric Refrigerator-Freezer 5800, Housing 5801, Refrigerator Door 5802, Freezer Door 5803

Claims

1. A semiconductor device having a transistor, comprising: a first insulator; a second insulator having a region on the first insulator; a first oxide having a region on the second insulator; a second oxide having a region on the first oxide; a third oxide having a region on the second oxide; a first conductor having a region on the second oxide; a second conductor having a region on the second oxide; a third insulator having a region on the third oxide; a third conductor having a region on the third insulator; a fourth insulator having regions on the first conductor and the second conductor; a fifth insulator having a region on the fourth insulator; a sixth insulator having a region on the fifth insulator; a seventh insulator having a region on the first conductor or the second conductor; a fourth conductor having a region on the first conductor or the second conductor; a fifth conductor having a region on the fourth conductor, and at least a part of a first opening is provided in the fourth insulator and the fifth insulator; the third oxide is disposed to cover an inner wall of the first opening; the third insulator is disposed to cover the inner wall of the first opening via the third oxide; the third conductor is disposed to fill the first opening via the third oxide and the third insulator; at least a part of a second opening is provided in the fourth insulator, the fifth insulator and the sixth insulator; the fourth conductor is in contact with the first conductor or the second conductor at a bottom of the second opening; the seventh insulator is provided in contact with a side wall of the second opening; the fifth conductor has a region in contact with an upper surface of the fourth conductor and a region in contact with an upper surface of the sixth insulator; the transistor has a channel formation region in a region where the first oxide, the second oxide and the third oxide overlap; in a region that does not overlap with the first opening and in a region where the first insulator and the second insulator do not overlap, the fourth insulator has a region in contact with the first insulator. In a region overlapping with the first opening, with reference to the height of the bottom surface of the first insulator, the height of the bottom surface of the third conductor in a region where the third conductor and the second oxide do not overlap is lower than the height of the bottom surface of the second oxide. In a region overlapping with the first opening, the third oxide is in contact with at least a part of the upper surface of the second oxide, at least a part of the side surface of the second oxide, at least a part of the side surface of the first oxide, and at least a part of the side surface of the second insulator. In a region overlapping with the first opening and where the first insulator and the second insulator do not overlap, the third oxide has a region in contact with the first insulator. The first insulator has lower hydrogen or oxygen permeability than the second insulator. The fourth insulator has lower hydrogen permeability than the second insulator. The semiconductor device, wherein the seventh insulator has lower hydrogen permeability than the second insulator.

2. In claim 1, The semiconductor device, wherein at least one of the first oxide to the third oxide contains In.

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